Driver for the DSMIF peripheral on RA MCUs. This module implements the ADC Interface.
Overview
The Delta-Sigma Modulator interface (DSMIF) functions similarly to a normal ADC, however, instead of sampling an analog signal directly, DSMIF samples a PDM signal that is generated by an externally connected 1-bit Delta-Sigma Modulator.
DSMIF Overview
Every instance of the DSMIF peripheral has 3 separate channels that can sample independent PDM signals. Each channel has a pair of sinc filters. One sinc filter is used for normal measurements, and the other sinc filter is used for detecting error conditions. The sinc filter configuration will determine the sample resolution, and the final sample rate for each channel. There are three primary configuration settings for the sinc filters:
Sample Rate - The frequency that the PDM signal is sampled.
Decimation Count - Number of samples that are removed between the integration stage and the differentiation stage of the sinc filter.
Filter order - The filter order of the sinc filter: [1st, 2nd, 3rd] order.
Features
The DSMIF module supports the following features:
Two independent units (3 channels per unit for a total of 6 channels)
Configurable sinc filter (1st, 2nd, 3rd order)
Configurable decimation count in the range (4,256)
Support for master and slave modes
Channel synchronization
Trigger data capture via ELC events
Trigger reset of decimation counter via ELC events
Configurable error detection
Overcurrent error detection (Can trigger common error interrupt)
Overcurrent sum error detection (Can trigger common error interrupt)
Short-circuit detection (Can trigger common error interrupt)
The following build time configurations are defined in fsp_cfg/r_dsmif_cfg.h:
Configuration
Options
Default
Description
Parameter Checking
Default (BSP)
Enabled
Disabled
Default (BSP)
If selected code for parameter checking is included in the build.
Error Detection Support
Enabled
Disabled
Enabled
If selected code for parameter checking is included in the build.
Configurations for Analog > DSMIF (r_dsmif)
This module can be added to the Stacks tab via New Stack > Analog > DSMIF (r_dsmif). Non-secure callable guard functions can be generated for this module by right clicking the module in the RA Configuration tool and checking the "Non-secure Callable" box.
Configuration
Options
Default
Description
General
Name
Name must be a valid C symbol
g_dsmif0
Module name
Clock Selection
PCLKA
DSMIFCLK
GPTCLK
PCLKA
Select the DSMIF Core Clock.
Unit
Unit 0
Unit 1
Unit 0
DSMIF unit number.
Alignment
Left Justified
Right Justified
Right Justified
Select if the conversion result is aligned to the left or right of the channel data registers.
Callback
Name must be a valid C symbol
NULL
Callback for handling DSMIF interrupts.
Overcurrent Sum Error
Overcurrent Sum Error > Upper Limit
Detection
Disabled
Enabled
Disabled
Enable or disable overcurrent sum error upper limit detection.
Threshold
Must be an integer in the range [0,0x3FFFF].
0
Overcurrent sum error detection upper limit.
Overcurrent Sum Error > Lower Limit
Detection
Disabled
Enabled
Disabled
Enable or disable overcurrent sum error lower limit detection.
Threshold
Must be an integer in the range [0,0x3FFFF].
0
Overcurrent sum error detection lower limit.
Channel Selection
Channels 0, 1 and 2
Channels 0 and 1
Channel 0
Channel 1
Channel 2
Channels 0, 1 and 2
Specify the channel(s) used for detecting overcurrent sum errors.
Interrupts
Channel Synchronization
Channels are not synchronized
Channels 0 and 1 are synchronized
Channels 0, 1 and 2 are synchronized
Channels are not synchronized
Select the channel synchronization mode. Two or three channels that share the same configuration may optionaly configure a common interrupts instead of channel specific interrupts.
Common Data Update Interrupt Priority (CDUPD_COM)
MCU Specific Options
The Common Data Update Interrupt occurs when a conversion is completed on all synchronized channels.
Common Capture A Data Update Interrupt Priority (CDACUPD_COM)
MCU Specific Options
The Common Capture A Interrupt occurs when a Capture A conversion is completed on all synchronized channels.
Common Capture B Data Update Interrupt Priority (CDBCUPD_COM)
MCU Specific Options
The Common Capture B Interrupt occurs when a Capture B conversion is completed on all synchronized channels.
Error Interrupt Priority
MCU Specific Options
The Error Interrupt occurs when a short-cicuit, overcurrent, overcurrent sum, or window notification error occurs on any channel.
Configurations for Analog > DSMIF Channel Configuration (r_dsmif)
Configuration
Options
Default
Description
General
Name
Name must be a valid C symbol
g_dsmif_channel0
Module name
Clock
Clock Direction
Slave Mode
Master Mode
Slave Mode
Select the conversion clock mode for the DSMIF channel. In master mode the clock is output from the DSMIF channel. In slave mode the clock is input to the DSMIF channel.
Clock Edge
Negative Edge
Positive Edge
Negative Edge
Select the sampling edge of DSMCLKn for this channel.
CKDIV Setting (Master Mode Only)
Must be an integer in the range [2,63].
2
Set the A/D conversion clock division ratio. The clock division ratio is equal to 2 x (CKDIV + 1). This setting is only used in master mode.
DSMCLK Frequency (Slave Mode Only)
Must be an integer in the range [0,25000000].
25000000
If slave mode is selected, then manually enter the DSMCLK frequency. This setting is used to calculate the settling time of the DSMIF sinc filters.
Filter
Filter Order
First Order
Second Order
Third Order
Third Order
Select 1st, 2nd, or 3rd order sinc filter for current data.
Decimation Count
Must be an integer in the range [4,256].
256
Decimation ratio of the current data sinc filter.
Trigger
Trigger > Filter Initialization
Trigger
No Trigger
Trigger 0 (ELC_DSMIFm_CNT0)
Trigger 1 (ELC_DSMIFm_CNT1)
Trigger 2 (ELC_DSMIFm_CNT2)
No Trigger
Select filter initialization trigger. The filter initialization trigger resets the sinc filter's decimation clock via ELC event.
Edge
Negative
Positive
Positive
Select either a positive or negative edge for the filter initialization trigger.
Capture Trigger A
No Trigger
Trigger 0 (ELC_DSMIFm_CAP0)
Trigger 1 (ELC_DSMIFm_CAP1)
Trigger 2 (ELC_DSMIFm_CAP2)
Trigger 3 (ELC_DSMIFm_CAP3)
Trigger 4 (ELC_DSMIFm_CAP4)
Trigger 5 (ELC_DSMIFm_CAP5)
No Trigger
Current capture trigger A selection.
Capture Trigger B
No Trigger
Trigger 0 (ELC_DSMIFm_CAP0)
Trigger 1 (ELC_DSMIFm_CAP1)
Trigger 2 (ELC_DSMIFm_CAP2)
Trigger 3 (ELC_DSMIFm_CAP3)
Trigger 4 (ELC_DSMIFm_CAP4)
Trigger 5 (ELC_DSMIFm_CAP5)
No Trigger
Current capture trigger B selection.
Error Detection
Error Detection > Filter
Filter Order
First Order
Second Order
Third Order
Third Order
Select 1st, 2nd, or 3rd order sinc filter for overcurrent detection.
Decimation Count
Must be an integer in the range [4,256].
256
Decimation ratio of the overcurrent detection filter.
Enable or disable overcurrent window notification 3.
Mode
Refer to the RA Configuration tool for available options.
Window notification 0
Select overcurrent window notification 3 mode.
Error Detection > Short Circuit
Detection
Disabled
Enabled
Disabled
Enable or disable short circuit detection.
Low Count
Must be an integer in the range [0,8191].
0
Short circuit detection low count.
High Count
Must be an integer in the range [0,8191].
0
Short circuit detection high count.
Interrupts
Current Data Update Interrupt Priority (CDUPD)
MCU Specific Options
The Current Data Update Interrupt occurs when a conversion is completed.
Capture A Data Update Interrupt Priority (CDAUPD)
MCU Specific Options
The Capture A Data Update Interrupt occurs when a capture A conversion is completed.
Capture B Data Update Interrupt Priority (CDBUPD)
MCU Specific Options
The Capture B Data Update Interrupt occurs when a capture B conversion is completed.
Clock Configuration
The DSMIF conversion rate is determined by the DSMIF Core Clock, A/D Conversion Division Ratio (CKDIV), and the configured sinc filter's decimation count.
The DSMIF Core Clock is common to all channels and may be configured to the following settings:
PCLKA - Peripheral Clock A
DSMIFCLK - Dedicated DSMIF Clock
GPTCLK - Dedicated GPT Clock
The A/D Conversion Division Ratio (CKDIV) is a channel specific setting that further divides the core clock by the following formula:
A/D Conversion Division Ratio = (2 x (CKDIV + 1))
Note
1. CKDIV is set in the range [2,63].
2. CKDIV is only valid in master mode.
The decimation count is a channel specific sinc filter setting that will determine the final conversion rate of a DSMIF channel.
Note
1. The decimation count is set in the range [4,256].
DSMIF Recommended Clock Configuration:
DSMIF Core Clock (Mhz)
CKDIV
DSMCLKn (Mhz)
300
0x05
25
0x08
16.67
0x09
15
0x0E
10
0x1D
5
200
0x03
25
0x04
20
0x07
12.5
0x09
10
0x0F
6.25
0x13
5
Note
1. If settings other than the recommended are used, there is an additional clock constraint: DSMIF Core Clock/5 ≤ PCLKA
Pin Configuration
Each DSMIF channel has two pins:
DSMmCLKn - DSMIF Clock Input/Output. In Master mode the clock pin is an output, in slave mode, the clock is an input.
DSMmDATn - DSMIF Data Input.
Usage Notes
Channel Synchronization
Multiple channels may be optionally synchronized in order to generate common interrupts in response to the following events:
The following sets of channels may be synchronized:
Channel 0 and Channel 1
Channel 0, Channel 1, and Channel 2
When synchronizing channels, each channel must use the same 'Clock', 'Filter', and 'Trigger' configuration settings. For convenience, channel configurations can be reused between channels of a DSMIF instance instead of creating new channel configurations for each channel.
Note
1. Channel configurations cannot be reused between different DSMIF instances.
2. Channel configurations can only be reused between channels that are synchronized.
Filter Settling Time
The filter settling time is the time required for the filter results to be valid after the DSMIF channels have been started. The settling time is determined by the DSMCLK period, Decimation Ratio, Filter Order, DSMIF Core Clock period, and Peripheral Clock period.
The following macros are generated by the tooling in order to assist with determining the required settling time:
/* Calculated settling time required for DSMIF filters (See "Settling Time" section in the MCU user manual). */
1. For more information on how to calculate the settling time refer to the MCU user manual.
Error Detection
There are four different types of error interrupts generated by the DSMIF peripheral:
Overcurrent error detection - Triggered when a conversion result exceeds a configured upper/lower limit on a particular channel.
Overcurrent sum error detection - Triggered when the sum of conversion results from a set of channels exceeds a configured upper/lower limit.
Window Notification error detection - Triggered when a conversion result falls within a set of configurable ranges.
Short-circuit detection - Triggered when a configured number of consecutive '1's or '0's are input on a DSMmDATn pin.
In order to enable error detection, the application must call R_DSMIF_ErrorDetectionEnable after waiting for all DSMIF channel filters to stabilize. The amount of time required for a filter to stabilize is dependent on the filter parameters, and clock settings. Refer to the MCU user manual for determining the filter stabilization time.
Once error detection is enabled, R_DSMIF_ErrorStatusGet can be called to read the error status.
Note
1. Error detection is disabled when channel operation is stopped via R_DSMIF_ScanStop. When starting channel operation again, the same settling time is required before reenabling error detection.
Error Interrupt
If the error interrupt is enabled, the following configured error flags will generate an interrupt request:
Overcurrent error detection
Overcurrent sum error detection
Short-circuit detection
Note
1. Since the error interrupt is a level interrupt, R_DSMIF_ErrorStatusGet must be called from the user callback in order to clear the associated error status flags.
2. Window Notification error detection does not generate an interrupt request.
Limitations
Developers should be aware of the following limitations when using DSMIF:
The DSMIF peripheral must be stopped prior to entering software standby mode.
Examples
Basic Example
This is a basic example of minimal use of the ADC in an application.
Applies power to the DSMIF and initializes the hardware based on the user configuration. As part of this initialization, set interrupts, set DSMIF error interrupt registers, etc.
Return values
FSP_SUCCESS
Configuration successful.
FSP_ERR_ASSERTION
An input pointer is NULL or an input parameter is invalid.
FSP_ERR_ALREADY_OPEN
Control block is already open.
FSP_ERR_IRQ_BSP_DISABLED
A required interrupt is disabled
FSP_ERR_IP_UNIT_NOT_PRESENT
The Unit requested in the p_cfg parameter is not available on this device.