The Ethernet PHY module (r_ether_phy) provides an API for standard Ethernet PHY communications applications that use the ETHERC peripheral. It implements the Ethernet PHY Interface.
Overview
The Ethernet PHY module is used to setup and manage an external Ethernet PHY device for use with the on-chip Ethernet Controller (ETHERC) peripheral. It performs auto-negotiation to determine the optimal connection parameters between link partners. Once initialized the connection between the external PHY and the onboard controller is automatically managed in hardware.
Features
The Ethernet PHY module supports the following features:
- Auto negotiation support
- Flow control support
- Link status check support
Configuration
Build Time Configurations for r_ether_phy
The following build time configurations are defined in fsp_cfg/r_ether_phy_cfg.h:
| Configuration | Options | Default | Description |
| Parameter Checking |
-
Default (BSP)
-
Enabled
-
Disabled
| Default (BSP) | If selected code for parameter checking is included in the build. |
| KSZ8091RNB Target |
| Disabled | Select whether to use KSZ8091RNB Phy LSI or not. |
| KSZ8041 Target |
| Disabled | Select whether to use KSZ8041 Phy LSI or not. |
| DP83620 Target |
| Disabled | Select whether to use DP83620 Phy LSI or not. |
| ICS1894 Target |
| Disabled | Select whether to use ICS1894 Phy LSI or not. |
| User Own Target |
| Disabled | Select whether to use User own Phy LSI or not. |
| Reference Clock |
| Default | Select whether to use the RMII reference clock. Selecting 'Default' will automatically choose the correct option when using a Renesas development board. |
| Reference Clock |
| Default | Select whether to use the RMII reference clock. Selecting 'Default' will automatically choose the correct option when using a Renesas development board. |
| Automatic Phy LSI Initialization |
| Enabled | Select whether to initialize the Ethernet Phy LSI in the open function. |
Configurations for Networking > Ethernet (r_ether_phy)
This module can be added to the Stacks tab via New Stack > Networking > Ethernet (r_ether_phy). Non-secure callable guard functions can be generated for this module by right clicking the module in the RA Configuration tool and checking the "Non-secure Callable" box.
| Configuration | Options | Default | Description |
| Name | Name must be a valid C symbol | g_ether_phy0 | Module name. |
| Channel |
| 0 | Select the Ethernet controller channel number. |
| PHY-LSI Address | Specify a value between 0 and 31. | 0 | Specify the address of the PHY-LSI used. |
| PHY-LSI Reset Completion Timeout | Specify a value between 0x1 and 0xFFFFFFFF. | 0x00020000 | Specify the number of times to read the PHY-LSI control register while waiting for reset completion. This value should be adjusted experimentally based on the PHY-LSI used. |
| Select MII type |
| RMII | Specify whether to use MII or RMII. |
| Phy LSI type |
-
Kit Component
-
DEFAULT
-
KSZ8091RNB
-
KSZ8041
-
DP83620
-
ICS1894
-
User own PHY
| Kit Component | Select the Phy LSI target. Selecting 'Kit Component' will automatically choose the correct option when using a Renesas development board. |
| Port Custom Init Function | Name must be a valid C symbol | NULL | Set the initial function of the PHY-LSI, When using your own PHY-LSI. |
| Port Custom Link Partner Ability Get Function | Name must be a valid C symbol | NULL | Set the link partner ability get function of the PHY-LSI, When using your own PHY-LSI. |
| MII/RMII Register Access Wait-time | Specify a value between 0x1 and 0x7FFFFFFF. | 8 | Specify the bit timing for MII/RMII register accesses during PHY initialization. This value should be adjusted experimentally based on the PHY-LSI used. |
| Flow Control |
| Disable | Select whether to enable or disable flow control. |
Usage Notes
- Note
- See the example below for details on how to initialize the Ethernet PHY module.
Accessing the MII and RMII Registers
Use the PIR register to access the MII and RMII registers in the PHY-LSI. Serial data in the MII and RMII management frame format is transmitted and received through the ET0_MDC and ET0_MDIO pins controlled by software.
MII and RMII management frame format
The below table lists the MII and RMII management frame formats.
| Access type | MII and RMII management frame |
| Item | PRE | ST | OP | PHYAD | REGAD | TA | DATA | IDLE |
| Number of bits | 32 | 2 | 2 | 5 | 5 | 2 | 16 | 1 |
| Read | 1...1 | 01 | 10 | 00001 | RRRRR | Z0 | DDDDDDDDDDDDDDDD | Z |
| Write | 1...1 | 01 | 01 | 00001 | RRRRR | 10 | DDDDDDDDDDDDDDDD | Z |
- Note
- - PRE (preamble): Send 32 consecutive 1s.
-
- ST (start of frame): Send 01b.
-
- OP (operation code): Send 10b for read or 01b for write.
-
- PHYAD (PHY address): Up to 32 PHY-LSIs can be connected to one MAC. PHY-LSIs are selected with these 5 bits. When the PHY-LSI address is 1, send 00001b.
-
- REGAD (register address): One register is selected from up to 32 registers in the PHY-LSI. When the register address is 1, send 00001b.
-
- TA (turnaround): Use 2-bit turnaround time to avoid contention between the register address and data during a read operation.
-
Send 10b during a write operation. Release the bus for 1 bit during a read operation (Z is output).
-
(This is indicated as Z0 because 0 is output from the PHY-LSI on the next clock cycle.)
-
- DATA (data): 16-bit data. Sequentially send or receive starting from the MSB.
-
- IDLE (IDLE condition): Wait time before inputting the next MII or RMII management format. Release the bus during a write
-
operation (Z is output). No control is required, because a bus was already released during a read operation.
Limitations
- The r_ether_phy module may need to be customized for PHY devices other than the ones currently supported. Use the existing code as a starting point for creating a custom implementation. Supported PHY devices are as follows.
- KSZ8091RNB
- KSZ8041
- DP83620
- ICS1894
Examples
ETHER PHY Basic Example
This is a basic example of minimal use of the ETHER PHY in an application.
void ether_phy_basic_example (void)
{
g_ether_phy0_ctrl.open = 0U;
g_ether_phy0_cfg.channel = 0;
assert(FSP_SUCCESS == err);
assert(FSP_SUCCESS == err);
{
}
&g_ether_phy0_line_speed_duplex,
&g_ether_phy0_local_pause,
&g_ether_phy0_partner_pause);
assert(FSP_SUCCESS == err);
assert(FSP_SUCCESS == err);
}
◆ ether_phy_instance_ctrl_t
| struct ether_phy_instance_ctrl_t |
ETHER PHY control block. DO NOT INITIALIZE. Initialization occurs when ether_phy_api_t::open is called.
| Data Fields |
|---|
|
uint32_t |
open |
Used to determine if the channel is configured. |
|
ether_phy_cfg_t const * |
p_ether_phy_cfg |
Pointer to initial configurations. |
|
volatile uint32_t * |
p_reg_pir |
Pointer to ETHERC peripheral registers. |
|
uint32_t |
local_advertise |
Capabilities bitmap for local advertising. |
|
ether_phy_interface_status_t |
interface_status |
Initialized status of ETHER PHY interface. |
◆ ether_phy_extended_cfg_t
| struct ether_phy_extended_cfg_t |
ETHER PHY extended configuration.
◆ ether_phy_interface_status_t
Initialization state for read/write
| Enumerator |
|---|
| ETHER_PHY_INTERFACE_STATUS_UNINITIALIZED | ETHER PHY interface is uninitialized.
|
| ETHER_PHY_INTERFACE_STATUS_INITIALIZED | ETHER PHY interface is initialized.
|
◆ R_ETHER_PHY_Open()
Resets Ethernet PHY device. Implements ether_phy_api_t::open.
- Return values
-
| FSP_SUCCESS | Channel opened successfully. |
| FSP_ERR_ASSERTION | Pointer to ETHER_PHY control block or configuration structure is NULL. |
| FSP_ERR_ALREADY_OPEN | Control block has already been opened or channel is being used by another instance. Call close() then open() to reconfigure. |
| FSP_ERR_INVALID_CHANNEL | Invalid channel number is given. |
| FSP_ERR_INVALID_POINTER | Pointer to p_cfg is NULL. |
| FSP_ERR_TIMEOUT | PHY-LSI Reset wait timeout. |
| FSP_ERR_INVALID_ARGUMENT | Register address is incorrect |
| FSP_ERR_NOT_INITIALIZED | The control block has not been initialized. |
◆ R_ETHER_PHY_Close()
Close Ethernet PHY device. Implements ether_phy_api_t::close.
- Return values
-
| FSP_SUCCESS | Channel successfully closed. |
| FSP_ERR_ASSERTION | Pointer to ETHER_PHY control block is NULL. |
| FSP_ERR_NOT_OPEN | The control block has not been opened |
◆ R_ETHER_PHY_StartAutoNegotiate()
Starts auto-negotiate. Implements ether_phy_api_t::startAutoNegotiate.
- Return values
-
| FSP_SUCCESS | ETHER_PHY successfully starts auto-negotiate. |
| FSP_ERR_ASSERTION | Pointer to ETHER_PHY control block is NULL. |
| FSP_ERR_NOT_OPEN | The control block has not been opened |
| FSP_ERR_INVALID_ARGUMENT | Register address is incorrect |
| FSP_ERR_INVALID_POINTER | Pointer to read buffer is NULL. |
| FSP_ERR_NOT_INITIALIZED | The control block has not been initialized |
◆ R_ETHER_PHY_LinkPartnerAbilityGet()
| fsp_err_t R_ETHER_PHY_LinkPartnerAbilityGet |
( |
ether_phy_ctrl_t *const |
p_ctrl, |
|
|
uint32_t *const |
p_line_speed_duplex, |
|
|
uint32_t *const |
p_local_pause, |
|
|
uint32_t *const |
p_partner_pause |
|
) |
| |
Reports the other side's physical capability. Implements ether_phy_api_t::linkPartnerAbilityGet.
- Return values
-
| FSP_SUCCESS | ETHER_PHY successfully get link partner ability. |
| FSP_ERR_ASSERTION | Pointer to ETHER_PHY control block is NULL. |
| FSP_ERR_INVALID_POINTER | Pointer to arguments are NULL. |
| FSP_ERR_NOT_OPEN | The control block has not been opened |
| FSP_ERR_ETHER_PHY_ERROR_LINK | PHY-LSI is not link up. |
| FSP_ERR_ETHER_PHY_NOT_READY | The auto-negotiation isn't completed |
| FSP_ERR_INVALID_ARGUMENT | Status register address is incorrect |
| FSP_ERR_NOT_INITIALIZED | The control block has not been initialized |
◆ R_ETHER_PHY_LinkStatusGet()
Returns the status of the physical link. Implements ether_phy_api_t::linkStatusGet.
- Return values
-
| FSP_SUCCESS | ETHER_PHY successfully get link partner ability. |
| FSP_ERR_ASSERTION | Pointer to ETHER_PHY control block is NULL. |
| FSP_ERR_NOT_OPEN | The control block has not been opened |
| FSP_ERR_ETHER_PHY_ERROR_LINK | PHY-LSI is not link up. |
| FSP_ERR_INVALID_ARGUMENT | Status register address is incorrect |
| FSP_ERR_INVALID_POINTER | Pointer to read buffer is NULL. |
| FSP_ERR_NOT_INITIALIZED | The control block has not been initialized |
◆ R_ETHER_PHY_ChipInit()
Initialize Ethernet PHY device. Implements ether_phy_api_t::chipInit.
- Return values
-
| FSP_SUCCESS | PHY device initialized successfully. |
| FSP_ERR_ASSERTION | Pointer to ETHER_PHY control block or configuration structure is NULL. |
| FSP_ERR_INVALID_ARGUMENT | Address or data is not a valid size. |
| FSP_ERR_INVALID_POINTER | Pointer to p_cfg is NULL. |
| FSP_ERR_NOT_INITIALIZED | The control block has not been initialized. |
| FSP_ERR_NOT_OPEN | The control block has not been opened. |
| FSP_ERR_TIMEOUT | PHY-LSI Reset wait timeout. |
◆ R_ETHER_PHY_Read()
Read data from register of PHY-LSI . Implements ether_phy_api_t::read.
- Return values
-
| FSP_SUCCESS | ETHER_PHY successfully read data. |
| FSP_ERR_ASSERTION | Pointer to ETHER_PHY control block is NULL. |
| FSP_ERR_INVALID_POINTER | Pointer to read buffer is NULL. |
| FSP_ERR_INVALID_ARGUMENT | Address is not a valid size |
| FSP_ERR_NOT_INITIALIZED | The control block has not been initialized |
◆ R_ETHER_PHY_Write()
Write data to register of PHY-LSI . Implements ether_phy_api_t::write.
- Return values
-
| FSP_SUCCESS | ETHER_PHY successfully write data. |
| FSP_ERR_ASSERTION | Pointer to ETHER_PHY control block is NULL. |
| FSP_ERR_INVALID_ARGUMENT | Address or data is not a valid size |
| FSP_ERR_NOT_INITIALIZED | The control block has not been initialized |
