OSPI Flash (r_ospi_b)

Functions
fsp_err_t	R_OSPI_B_Open (spi_flash_ctrl_t *const p_ctrl, spi_flash_cfg_t const *const p_cfg)
fsp_err_t	R_OSPI_B_DirectWrite (spi_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint32_t const bytes, bool const read_after_write)
fsp_err_t	R_OSPI_B_DirectRead (spi_flash_ctrl_t *p_ctrl, uint8_t *const p_dest, uint32_t const bytes)
fsp_err_t	R_OSPI_B_DirectTransfer (spi_flash_ctrl_t *p_ctrl, spi_flash_direct_transfer_t *const p_transfer, spi_flash_direct_transfer_dir_t direction)
fsp_err_t	R_OSPI_B_XipEnter (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_OSPI_B_XipExit (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_OSPI_B_Write (spi_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint8_t *const p_dest, uint32_t byte_count)
fsp_err_t	R_OSPI_B_Erase (spi_flash_ctrl_t *p_ctrl, uint8_t *const p_device_address, uint32_t byte_count)
fsp_err_t	R_OSPI_B_StatusGet (spi_flash_ctrl_t *p_ctrl, spi_flash_status_t *const p_status)
fsp_err_t	R_OSPI_B_BankSet (spi_flash_ctrl_t *p_ctrl, uint32_t bank)
fsp_err_t	R_OSPI_B_SpiProtocolSet (spi_flash_ctrl_t *p_ctrl, spi_flash_protocol_t spi_protocol)
fsp_err_t	R_OSPI_B_Close (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_OSPI_B_AutoCalibrate (spi_flash_ctrl_t *const p_ctrl)
fsp_err_t	R_OSPI_B_RowLoad (spi_flash_ctrl_t *const p_ctrl, uint32_t row_index)
fsp_err_t	R_OSPI_B_RowStore (spi_flash_ctrl_t *const p_ctrl, uint32_t row_index)
fsp_err_t	R_OSPI_B_DOTF_Configure (spi_flash_ctrl_t *const p_ctrl, ospi_b_dotf_cfg_t *const p_dotf_cfg)

Detailed Description

Driver for the OSPI_B peripheral on RA MCUs. This module implements the SPI Flash Interface.

Overview

The OSPI_B peripheral supports xSPI (or OSPI) compatible external memory devices, and it interfaces with these devices to perform data I/O Operations. The OSPI_B peripheral does not support addressable devices, so all connected memory devices must be connected to an individual chip-select pin. Please note that this document will reference the xSPI protocol to which OSPI is a subset. The OSPI_B peripheral is compatible with a variety of xSPI protocol operating modes.

Features

The OSPI_B driver has the following key features to support the xSPI device:

• Perform data I/O Operation
• Direct memory-mapped access to the xSPI device memory up to 256 MB.
• Can be configured with xSPI devices on either of the 2 channels
• Programming the xSPI device using combination write (up to 64 bytes)
• Erasing the xSPI device
• Sending device specific commands and reading back responses of up to 8 bytes
• 1- and 2-byte addressing intended for row-column memories
• 3 byte addressing
• 4 byte addressing
• Auto-calibration
• Decryption-on-the-fly
• Support for standard SPI frames, xSPI Protocol 1.0, xSPI Protocol 2.0, and xSPI Protocol 2.0 Extended frames.

Additional build-time features:

• Optional (build-time) DMAC support for data transmission when used with OSPI_B.
• Optional (build-time) XiP support for entering/exiting XiP mode of the target device.
• Optional (build-time) Data-strobe (DS) auto-calibration support for target devices using the DS signal.
• Optional (build-time) Decryption on the fly (DOTF)
• Optional (build-time) Support for memory which use row-column addressing.

Note

For OSPI_B, use of DMAC for data transmission is strongly recommended. Without the use of DMAC, due to the high-speed hardware design of the OSPI peripheral, data transmission can be sensitive to timing variance, which could cause software-based memory-mapped operations to fail unexpectedly.

Configuration

OSPI_B Flash:

Build Time Configurations for r_ospi_b

The following build time configurations are defined in fsp_cfg/r_ospi_b_cfg.h:

Configuration	Options	Default	Description
Memory-mapping Support
Prefetch Function	Enable Disable	Enable	Enable prefetch function on memory-mapped reads.
Combination Function	Refer to the RA Configuration tool for available options.	64 Bytes	Enable combination function on memory-mapped writes.
XiP Support	Enable Disable	Disable	Enable the use of XiP enter and exit codes.
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
DMAC Support	Enable Disable	Disable	Enable DMAC support for the OSPI module.
Autocalibration Support	Enable Disable	Disable	Enable DS autocalibration for dual-data-rate modes.
DOTF Support	Enable (Protected Mode) Enable (Compatibility Mode) Disable	Disable	Enable DOTF support for the OSPI module.
Row Addressing Support	Enable Disable	Disable	Enable support for xSPI devices which utilize row-column addressing of the memory array.

Configurations for Storage > OSPI (r_ospi_b)

This module can be added to the Stacks tab via New Stack > Storage > OSPI (r_ospi_b).

Configuration	Options	Default	Description
General
Name	Name must be a valid C symbol	g_ospi0	Module name.
Unit	MCU Specific Options		Specify the OSPI peripheral to use.
Chip Select	CS0 CS1	CS1	Specify the OSPI chip select line to use.
Write Status Bit	b0 b1 b2 b3 b4 b5 b6 b7	b0	Which bit contains the write in progress status returned from the Write Status Command.
Write Enable Bit	b0 b1 b2 b3 b4 b5 b6 b7	b1	Which bit contains the write enable status returned from the Write Enable Command.
DS Auto-calibration Pattern Address	Must be a valid pointer address	0	Address to the auto-calibration pattern in the target flash memory's address space.
Command Sets
Command Sets > Custom Table
Table Pointer	Must be a vaild C symbol		Specify the custom command set table (ospi_b_xspi_command_set_t[]) to use. If provided, all other command set settings are ignored.
Table Length	Length must be an integer greater than or equal to zero.	0	Length of the custom command set table.
Command Sets > Erase Sizes
Sector Erase	Erase size must be an integer greater-than or equal-to zero and less than 4,294,967,296 (0xFFFF_FFFF).	4096	Size of the memory region erased by Sector Erase
Block Erase	Erase size must be an integer greater-than or equal-to zero and less than 4,294,967,296 (0xFFFF_FFFF).	262144	Size of the memory region erased by Block Erase
Command Sets > Initial Mode
Command Sets > Initial Mode > Read
Command Code	Command codes must be positive and fit in the selected command byte length.	0x13	Read command code. Set to 0x00 to disable.
Dummy Cycles	Dummy cycle counts must be an integer between 0 and 31.	0	Dummy cycles to use between the address and data phase for Read commands. Set to 0 to disable dummy cycles.
Command Sets > Initial Mode > Program
Command Code	Command codes must be positive and fit in the selected command byte length.	0x12	Program command code. Set to 0x00 to disable.
Dummy Cycles	Dummy cycle counts must be an integer between 0 and 31.	0	Dummy cycles to use between the address and data phase for Program commands. Set to 0 to disable dummy cycles.
Command Sets > Initial Mode > Row Load
Command Code	Command codes must be positive and fit in the selected command byte length.	0x00	Row Load command code. Set to 0x00 to disable.
Dummy Cycles	Dummy cycle counts must be an integer between 0 and 31.	0	Dummy cycles to use between the address and data phase for Row Load commands. Set to 0 to disable dummy cycles.
Command Sets > Initial Mode > Row Store
Command Code	Command codes must be positive and fit in the selected command byte length.	0x00	Row Store command code. Set to 0x00 to disable.
Dummy Cycles	Dummy cycle counts must be an integer between 0 and 31.	0	Dummy cycles to use between the address and data phase for Row Store commands. Set to 0 to disable dummy cycles.
Command Sets > Initial Mode > Write Enable
Command Code	Command codes must be positive and fit in the selected command byte length.	0x06	Write Enable command code. Set to 0x00 to disable.
Command Sets > Initial Mode > Status Read
Command Code	Command codes must be positive and fit in the selected command byte length.	0x05	Status Read command code. Set to 0x00 to disable.
Dummy Cycles	Dummy cycle counts must be an integer between 0 and 31.	0	Dummy cycles to use between the address and data phase for Status Read commands. Set to 0 to disable dummy cycles.
Command Sets > Initial Mode > Sector Erase
Command Code	Command codes must be positive and fit in the selected command byte length.	0x21	Sector Erase command code. Set to 0x00 to disable.
Command Sets > Initial Mode > Block Erase
Command Code	Command codes must be positive and fit in the selected command byte length.	0xDC	Block Erase command code. Set to 0x00 to disable.
Command Sets > Initial Mode > Chip Erase
Command Code	Command codes must be positive and fit in the selected command byte length.	0x60	Chip Erase command code. Set to 0x00 to disable.
Protocol Mode	SPI (1S-1S-1S) DSPI (1S-2S-2S) DSPI (2S-2S-2S) QSPI (1S-4S-4S) QSPI (4S-4S-4S) QSPI (4S-4D-4D) Dual data rate OPI (8D-8D-8D)	SPI (1S-1S-1S)	Signal protocol mode to use for this command set.
Frame Format	Standard xSPI Profile 1.0 xSPI Profile 2.0 xSPI Profile 2.0 Extended	Standard	Frame format to use with this command set.
Latency Mode	Fixed Variable (DQS)	Fixed	Latency mode to use with this command set.
Address Length	1 byte 2 bytes 3 bytes 4 bytes	3 bytes	Number of bytes used to address data in a memory page or row.
Address MSB Mask	Address mask must be between 0x00 and 0xFF.	0xF0	Mask of bits to zero for the most-significant byte of the address stage during memory-mapped operations
Command Code Length	1 byte 2 bytes	1 byte
Status Register Address Length	No address 1 byte 2 bytes 3 bytes 4 bytes	No address	Number of bytes used for addressing the status register.
Status Register Address	Status register address must be between 0x00 and 0xFFFF_FFFF, inclusive.	0x00	Address of the status register that reports Write-in-Progress and Write-Enable flags.
Command Sets > High-speed Mode
Command Sets > High-speed Mode > Read
Command Code	Command codes must be positive and fit in the selected command byte length.	0xEEEE	Read command code. Set to 0x00 to disable.
Dummy Cycles	Dummy cycle counts must be an integer between 0 and 31.	20	Dummy cycles to use between the address and data phase for Read commands. Set to 0 to disable dummy cycles.
Command Sets > High-speed Mode > Program
Command Code	Command codes must be positive and fit in the selected command byte length.	0x1212	Program command code. Set to 0x00 to disable.
Dummy Cycles	Dummy cycle counts must be an integer between 0 and 31.	0	Dummy cycles to use between the address and data phase for Program commands. Set to 0 to disable dummy cycles.
Command Sets > High-speed Mode > Row Load
Command Code	Command codes must be positive and fit in the selected command byte length.	0x00	Row Load command code. Set to 0x00 to disable.
Dummy Cycles	Dummy cycle counts must be an integer between 0 and 31.	0	Dummy cycles to use between the address and data phase for Row Load commands. Set to 0 to disable dummy cycles.
Command Sets > High-speed Mode > Row Store
Command Code	Command codes must be positive and fit in the selected command byte length.	0x00	Row Store command code. Set to 0x00 to disable.
Dummy Cycles	Dummy cycle counts must be an integer between 0 and 31.	0	Dummy cycles to use between the address and data phase for Row Store commands. Set to 0 to disable dummy cycles.
Command Sets > High-speed Mode > Write Enable
Command Code	Command codes must be positive and fit in the selected command byte length.	0x0606	Write Enable command code. Set to 0x00 to disable.
Command Sets > High-speed Mode > Status Read
Command Code	Command codes must be positive and fit in the selected command byte length.	0x0505	Status Read command code. Set to 0x00 to disable.
Dummy Cycles	Dummy cycle counts must be an integer between 0 and 31.	3	Dummy cycles to use between the address and data phase for Status Read commands. Set to 0 to disable dummy cycles.
Command Sets > High-speed Mode > Sector Erase
Command Code	Command codes must be positive and fit in the selected command byte length.	0x2121	Sector Erase command code. Set to 0x00 to disable.
Command Sets > High-speed Mode > Block Erase
Command Code	Command codes must be positive and fit in the selected command byte length.	0xDCDC	Block Erase command code. Set to 0x00 to disable.
Command Sets > High-speed Mode > Chip Erase
Command Code	Command codes must be positive and fit in the selected command byte length.	0x6060	Chip Erase command code. Set to 0x00 to disable.
Protocol Mode	SPI (1S-1S-1S) DSPI (1S-2S-2S) DSPI (2S-2S-2S) QSPI (1S-4S-4S) QSPI (4S-4S-4S) QSPI (4S-4D-4D) Dual data rate OPI (8D-8D-8D)	Dual data rate OPI (8D-8D-8D)	Signal protocol mode to use for this command set.
Frame Format	Standard xSPI Profile 1.0 xSPI Profile 2.0 xSPI Profile 2.0 Extended	xSPI Profile 1.0	Frame format to use with this command set.
Latency Mode	Fixed Variable (DQS)	Fixed	Latency mode to use with this command set.
Address Length	1 byte 2 bytes 3 bytes 4 bytes	4 bytes	Number of bytes used to address data in a memory page or row.
Address MSB Mask	Address mask must be between 0x00 and 0xFF.	0xF0	Mask of bits to zero for the most-significant byte of the address stage during memory-mapped operations
Command Code Length	1 byte 2 bytes	2 bytes
Status Register Address Length	No address 1 byte 2 bytes 3 bytes 4 bytes	4 bytes	Number of bytes used for addressing the status register.
Status Register Address	Status register address must be between 0x00 and 0xFFFF_FFFF, inclusive.	0x00	Address of the status register that reports Write-in-Progress and Write-Enable flags.
Timing Settings
Timing Settings > Chip Select
Command Interval	Refer to the RA Configuration tool for available options.	2 cycles	Minimum clock cycles between two consecutive xSPI frames (CS idle time).
Pull-up Timing	No Extension 1 Cycle	No Extension	Signal pull-up timing (CS asserting extension) setting in OCTACLK units
Pull-down Timing	No Extension 1 Cycle	No Extension	Signal pull-down timing (CS negating extension) setting in OCTACLK units
Timing Settings > SDR
Drive Timing	Drive 1/2 cycle before CK Drive at CK	Drive 1/2 cycle before CK	Data signal timing relative to the rising-edge of the CK signal.
CK Sampling Edge	Falling edge Rising edge	Falling edge	Selects the clock edge to sample the data signal.
Sampling Delay	None 1 cycle 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles	None	Number of cycles to delay before sampling the data signal.
Timing Settings > DDR
Sampling Window Extension	None 1 cycle 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles	None	Number of cycles to extending the data sampling window in DDR mode.
DS Latching Delay	Refer to the RA Configuration tool for available options.	Auto-calibrate	Number of delay cells for the data strobe signal. This value must be set to zero if auto-calibration is used.
XiP Mode
XiP Enter Code	Must be an integer between 0 and 255	0	XiP enter code.
XiP Exit Code	Must be an integer between 0 and 255	0	XiP exit code.
DOTF
Name	Name must be a valid C symbol	g_ospi_dotf	DOTF Configuration name.
AES Key	Name must be a valid C symbol	g_ospi_dotf_key	Name of Key variable.
AES IV	Name must be a valid C symbol	g_ospi_dotf_iv	Name of IV variable
AES Key Length	MCU Specific Options		Select AES key length
Key Format	MCU Specific Options		Select key format
Decryption start address	Value must be an integer between 0x80000000 and 0x9FFFF000	0x90000000	OSPI decryption start address
Decryption end address	Value must be an integer between 0x80000FFF and 0x9FFFFFFF	0x90001FFF	OSPI decryption end address
Row Addressing
Row Address Length	No address 1 byte 2 bytes 3 bytes 4 bytes	No address	Number of bytes used for addressing the row index.

Note

The user is expected to modify the command definitions based on the xSPI chip and SPI communication mode. The default mode is SPI mode and default erase commands are set for DOPI mode based on Infineon S28HS256.

Clock Configuration

The signals to the xSPI target device are derived from OCTACLK. OCTACLK must be set to twice the desired OMSCLK signal frequency. This allows data to be latched on either clock edge for Dual-Data-Rate modes (4S-4D-4D or 8D-8D-8D).

Please refer to the Hardware User Manual for the clocks which control the OSPI_B registers. These along with OCTACLK can be set on the Clocks tab of the RA Configuration editor.

Pin Configuration

The following pins are available to connect to an external OSPI device:

• OMSCLK: OSPI clock output (OCTACLK / 2)
• OMDQS: OSPI data strobe signal
• OMCS0: OSPI device 0 select
• OMCS1: OSPI device 1 select
• OMSIO0: Data 0 I/O
• OMSIO1: Data 1 I/O
• OMSIO2: Data 2 I/O
• OMSIO3: Data 3 I/O
• OMSIO4: Data 4 I/O
• OMSIO5: Data 5 I/O
• OMSIO6: Data 6 I/O
• OMSIO7: Data 7 I/O

Note

Data pins must be configured with IOPORT_CFG_DRIVE_HS_HIGH.

Chip Select pins should be configured with at least IOPORT_CFG_DRIVE_MEDIUM.

Usage Notes

Usage Notes for xSPI support

After R_OSPI_B_Open() completes successfully, the xSPI device contents are mapped to the appropriate external memory regions for each OSPI_B unit. For example, on the RA8M1, R_OSPI_B0 maps the CS0 device to address 0x80000000 and the CS1 device to address 0x90000000. After opening, the addresses can be accessed like on-chip flash.

Bank CS0 and CS1 support up to 256 MB of address space each depending on the platform.

Auto-calibration

If support is enabled, auto-calibration procedures are triggered automatically when the 'Data latching delay' field in the configurator properties is set to 0. The user application is responsible for setting the appropriate preamble pattern before calling R_OSPI_B_Open() when using a data strobe (DS) mode or changing the SPI protocol to a DS mode using the R_OSPI_B_SpiProtocolSet() API. The appropriate preamble pattern can be written to the desired address using the R_OSPI_B_Write() API while in simple SPI mode (recommended), or a non-DS mode. Ensure that the same address is passed through the configurator. If the xSPI device is already in a DS mode, the preamble pattern must be programmed using the debugger before calling R_OSPI_B_Open().

The preamble pattern is expected to be { 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x08, 0x00, 0x00, 0xF7, 0xFF, 0x00, 0x08, 0xF7, 0x00, 0xF7 }.

Chip Select Latencies

Chip select latencies can be set through the configurator. The default settings support SPI at minimum latency. In case the driver is opened in SPI mode and will be switched to DOPI mode later using R_OSPI_B_SpiProtocolSet(), please select latencies required for DOPI before calling R_OSPI_B_Open().

XiP Support

OSPI_B supports eXecute in Place (XiP) modes of operation. This can be used for read-only memory-mapped accesses to reduce overall read latency by skipping the command sequence in the xSPI transaction. Separate XiP enter and exit codes may be specified for either attached target device. Upon calling R_OSPI_B_XipEnter(), the associated memory region for the target device is switched to read-only mode and the enter code sent to the device. Calling R_OSPI_B_XipExit() will transmit the exit code and transition the memory region back to read-write access.

Only one flash device should be used after entering XiP mode. Once entered, XiP codes will be transmitted to all attached devices.

xSPI Commands

Command sets and erase commands may be specified individually for each supported protocol mode. By default, the configurator only supports an alternative command set for "High-Speed Mode" (DOPI 8D-8D-8D) mode. The command sets cannot be changed during run-time, but the appropriate command set will be selected when changing protocol modes. If a command set is not found, an FSP_ERR_INVALID_MODE error code will be returned.

If custom DOPI erase commands are not specified, ensure the erase commands are the appropriate 2-byte DOPI commands. The lower byte will be used for 1-byte command protocols.

DOTF Support

Decryption-On-The-Fly is configurable for OSPI Flash and is disabled from the build by default.

Using the DOTF feature requires first creating the encrypted blob on the PC and then configuring the DOTF module with the appropriate parameters to allow decryption of the blob once it is programmed into OSPI. Use the Security Key Management Tool (https://www.renesas.com/us/en/software-tool/security-key-management-tool) to create the encrypted blob.

Example: To encrypt a 4096 byte area in a input srec file from 0x90000000 to 0x90000FFF using a 128 AES encryption key FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF and IV 00000000000000000000000000000000 use SKMT with the following arguments:

skmt.exe /encdotf /keytype "AES-128" /enckey "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" /nonce "00000000000000000000000000000000" /startaddr "90000000" /endaddr "90000FFF" /prg "input.srec" /incplain /output "encrypted_output.srec"

The values for key, iv and decryption area start and end addresses that were used to create the blob using SKMT must be set in the DOTF configuration in FSP.

Make sure that the Key and IV passed into DOTF configuration are 4 byte aligned. This can be done using a compiler alignment attribute as shown below:

uint8_t aes_key[] __attribute__((aligned(4))) =
{
    0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
    0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f
};

Supported Key Formats

• When the Compatibility Mode stack is added for the crypto engine, the user can provide either a wrapped or plaintext AES key to the DOTF module.
• When the Protected Mode stack is used, only wrapped keys are supported.

When configuring the DOTF options, make sure that the key format is specified.

Note

For a detailed description of the Crypto Engine operating modes, refer to Application Note R11AN0498.

Limitations

Developers should be aware of the following limitations when using the OSPI_B driver:

OSPI_B

• The R_OSPI_B driver expects memory devices to have uniform sector sizes. If a design requires using a memory with non-uniform sectors, the end-user application must appropriately manage sectors.
• Prefetch and combination support for memory-mapped access is applied globally to all slave devices per OSPI_B unit.
• Combination writes are limited to a maximum of 64 bytes. The user should verify the write has completed before attempting to write more bytes.
• Writing to the memory-mapped regions with the CPU is restricted to 64-bit accesses with 8-byte destination alignments. This restriction is not applicable to other bus masters (e.g. DTC or DMAC).
• When using Arm LLVM ensure any read-only (const) data used with R_OSPI_B_Write() is word (4-byte) aligned if the DMAC is not being used. If parameter checking is enabled, the source pointer alignment will be verified for calls to R_OSPI_B_Write().
• Take care to restrict concurrent accesses of the OSPI memory area. Collisions on the bus can occur if other bus masters attempt to write to the OSPI memory area while another master is reading the OSPI memory area.
• When using 8D-8D-8D mode, care should be taken to access on even-aligned addresses. Problems may occur if odd address alignment is used. This restriction applies to all bus masters using OSPI_B.
• DOTF: AES-192 is not supported when the Protected Mode stack is used.
• When using the IAR compiler, OSPI data must be const qualified to be downloaded by the debugger.
• Memories which use row-column addressing must be managed by the end-user application to ensure the appropriate memory row is loaded and stored.

Examples

OSPI Flash:

The following definitions are used across various example snippets below.

#define OSPI_B_COMMAND_WRITE_ENABLE_SPI_MODE     (0x06U)
#define OSPI_B_COMMAND_WRITE_DISABLE_SPI_MODE    (0x04U)
#define OSPI_B_COMMAND_READ_STATUS_SPI_MODE      (0x05U)
#define OSPI_B_COMMAND_READ_REGISTER_SPI_MODE    (0x65U)

#define OSPI_B_COMMAND_READ_QSPI_MODE            (0x0BU)
#define OSPI_B_COMMAND_PROGRAM_QSPI_MODE         (0x12U)
#define OSPI_B_COMMAND_WRITE_ENABLE_QSPI_MODE    (0x06U)
#define OSPI_B_COMMAND_STATUS_QSPI_MODE          (0x05U)

#define OSPI_B_COMMAND_BLOCK_ERASE_DOPI_MODE     (0x21DEU)
#define OSPI_B_COMMAND_SECTOR_ERASE_DOPI_MODE    (0xDC23U)
#define OSPI_B_COMMAND_CHIP_ERASE_DOPI_MODE      (0x609FU)
#define OSPI_B_COMMAND_READ_DOPI_MODE            (0xEE11U)
#define OSPI_B_COMMAND_PROGRAM_DOPI_MODE         (0x12EDU)
#define OSPI_B_COMMAND_WRITE_ENABLE_DOPI_MODE    (0x06F9U)
#define OSPI_B_COMMAND_STATUS_DOPI_MODE          (0x05FAU)

#define OSPI_B_WEN_BIT_MASK                      (0x02U)
#define OSPI_B_WIP_BIT_MASK                      (0x01U)

#define OSPI_B_BLOCK_ERASE_SIZE                  (4096U)
#define OSPI_B_SECTOR_ERASE_SIZE                 (262144U)

#define OSPI_B_EXAMPLE_DESTINATION_ADDRESS       ((void *) 0x90000000U) /* Device on CS1 */

static void ospi_b_change_mode (spi_flash_protocol_t new_protocol)
{
    /* Step 1. Identify current device configuration and reconfigure as needed... */

    /* Step 2. Update clocks... */

    /* Step 3. Transition driver to the new protocol. */
    fsp_err_t err = R_OSPI_B_SpiProtocolSet(&g_ospi0_ctrl, new_protocol);
    assert(FSP_SUCCESS == err);

    /* Step 4. Verify mode change... */
}

Basic Example

This is a basic example of minimal use of the OSPI in an application with OctaFlash.

#define OSPI_B_EXAMPLE_DATA_LENGTH    (1024)

uint8_t g_dest[OSPI_B_EXAMPLE_DATA_LENGTH];

/* Place data in the .ospi_flash section to flash it during programming. */
const uint8_t g_src[OSPI_B_EXAMPLE_DATA_LENGTH] BSP_PLACE_IN_SECTION(".ospi0_cs1") = "ABCDEFGHIJKLMNOPQRSTUVWXYZ";

/* Place code in the .ospi0_cs1_code section to flash it during programming. */
void r_ospi_b_example_function(void) BSP_PLACE_IN_SECTION(".ospi0_cs1_code") __attribute__((noinline));

void r_ospi_b_example_function (void)
{
    /* Add code here. */
}

void r_ospi_b_basic_example (void)
{

    /* Open the OSPI instance. */
    fsp_err_t err = R_OSPI_B_Open(&g_ospi0_ctrl, &g_ospi0_cfg);

    assert(FSP_SUCCESS == err);

    /* (Optional) Change SPI to DOPI mode */
    ospi_b_change_mode(SPI_FLASH_PROTOCOL_8D_8D_8D);

    /* After R_OSPI_B_Open() and any required device specific initialization, data can be read directly from the OSPI flash. */
    memcpy(&g_dest[0], &g_src[0], OSPI_B_EXAMPLE_DATA_LENGTH);

    /* After R_OSPI_B_Open() and any required device specific initialization, functions in the OSPI flash can be called. */
    r_ospi_b_example_function();
}

Reading Status Register Example (R_OSPI_B_DirectTransfer)

This is an example of using R_OSPI_B_DirectWrite followed by R_OSPI_B_DirectRead to send the read status register command and read back the status register from the device.

#define OSPI_B_COMMAND_READ_STATUS_REGISTER    (0x05U)

void r_ospi_b_direct_example (void)
{
    spi_flash_direct_transfer_t ospi_b_test_direct_transfer =
    {
        .command        = OSPI_B_COMMAND_READ_STATUS_SPI_MODE,
        .address        = 0U,
        .data           = 0U,
        .command_length = 1U,
        .address_length = 0U,
        .data_length    = 0U,
        .dummy_cycles   = 0U
    };

    /* Open the OSPI instance. */
    fsp_err_t err = R_OSPI_B_Open(&g_ospi0_ctrl, &g_ospi0_cfg);
    assert(FSP_SUCCESS == err);


    /* Write Enable */
    err = R_OSPI_B_DirectTransfer(&g_ospi0_ctrl, &ospi_b_test_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE);
    assert(FSP_SUCCESS == err);


    /* Read Status Register */
    ospi_b_test_direct_transfer.command     = OSPI_B_COMMAND_READ_STATUS_SPI_MODE;
    ospi_b_test_direct_transfer.data_length = 1U;
    err = R_OSPI_B_DirectTransfer(&g_ospi0_ctrl, &ospi_b_test_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    assert(FSP_SUCCESS == err);

    /* Check if Write Enable is set */
    if (OSPI_B_WEN_BIT_MASK != (ospi_b_test_direct_transfer.data & OSPI_B_WEN_BIT_MASK))
    {
        __BKPT(0);
    }
}

Auto-calibration Example (R_OSPI_B_DirectTransfer, R_OSPI_B_Write, R_OSPI_B_SpiProtocolSet)

This is an example of using R_OSPI_B_SpiProtocolSet to change the operating mode from SPI to DOPI and allow the driver to initiate auto-calibration.

#define OSPI_B_DOPI_PREAMBLE_PATTERN_LENGTH_BYTES    (16U)
#define OSPI_B_EXAMPLE_PREAMBLE_ADDRESS              (0x90000000U) /* Device connected to CS1 */
const uint8_t g_preamble_bytes[OSPI_B_DOPI_PREAMBLE_PATTERN_LENGTH_BYTES] =
{
    0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x08, 0x00, 0x00, 0xF7, 0xFF, 0x00, 0x08, 0xF7, 0x00, 0xF7
};

static void ospi_b_wait_until_wip (void)
{
    fsp_err_t          err = FSP_SUCCESS;
    spi_flash_status_t status;
    status.write_in_progress = true;
    uint32_t timeout = UINT32_MAX;
    while ((status.write_in_progress) && (--timeout))
    {

        err = R_OSPI_B_StatusGet(&g_ospi0_ctrl, &status);
        assert(FSP_SUCCESS == err);

    }

    if (0 == timeout)
    {
        assert(FSP_SUCCESS == err);
    }
}

void r_ospi_b_auto_calibrate_example (void)
{
    /* Open the OSPI instance. */
    /* Set data_latch_delay_clocks to 0x0 to enable auto-calibration */
    fsp_err_t err = R_OSPI_B_Open(&g_ospi0_ctrl, &g_ospi0_cfg);
    assert(FSP_SUCCESS == err);

    uint8_t * preamble_pattern_addr = (uint8_t *) OSPI_B_EXAMPLE_PREAMBLE_ADDRESS;


    err = R_OSPI_B_Write(&g_ospi0_ctrl, g_preamble_bytes, preamble_pattern_addr, OSPI_B_EXAMPLE_PREAMBLE_ADDRESS);
    assert(FSP_SUCCESS == err);


    /* Wait until write has been completed */
    ospi_b_wait_until_wip();

    /* Change from SPI to DOPI mode */
    ospi_b_change_mode(SPI_FLASH_PROTOCOL_8D_8D_8D);
}

Octaclk Update Example (R_OSPI_B_SpiProtocolSet)

This is an example of using R_BSP_OctaclkUpdate to change the Octal-SPI clock frequency during run time. The OCTACLK frequency must be updated before calling the R_OSPI_B_SpiProtocolSet with appropriate clock source and divider settings required to be set for the new SPI protocol mode. Ensure that the clock source selected is started.

/*
 * Changes the OCTACLK divider; assumes PLL2 is being used as the source for OCTACLK.
 * @param divider New clock divider to switch to.
 */
static void ospi_b_change_omclk (bsp_clocks_octaclk_div_t divider)
{
    /* Ensure clock source (PLL2 in this example) is running before changing the OCTACLK frequency */
    bsp_octaclk_settings_t octaclk_settings;
    octaclk_settings.source_clock = BSP_CLOCKS_CLOCK_PLL2;
    octaclk_settings.divider      = divider;
    R_BSP_OctaclkUpdate(&octaclk_settings);
}

Using a Custom xSPI Command Set Example

This is an example of using custom command sets for 8D-8D-8D and 4S-4S-4S protocol modes.

/* Custom two-byte erase commands. */
spi_flash_erase_command_t g_2B_erase_commands[] =
{
    {.command = OSPI_B_COMMAND_BLOCK_ERASE_DOPI_MODE,  .size = OSPI_B_BLOCK_ERASE_SIZE        },
    {.command = OSPI_B_COMMAND_SECTOR_ERASE_DOPI_MODE, .size = OSPI_B_SECTOR_ERASE_SIZE       },
    {.command = OSPI_B_COMMAND_CHIP_ERASE_DOPI_MODE,   .size = SPI_FLASH_ERASE_SIZE_CHIP_ERASE},
};

ospi_b_table_t g_2B_erase_table =
{
    .p_table = g_2B_erase_commands,
    .length  = (uint8_t) (sizeof(g_2B_erase_commands) / sizeof(g_2B_erase_commands[0])),
};

/* Custom command sets. */
ospi_b_xspi_command_set_t g_command_sets[] =
{
    /* 8D-8D-8D example with inverted lower command byte. */
    {
        .protocol             = SPI_FLASH_PROTOCOL_8D_8D_8D,
        .command_bytes        = OSPI_B_COMMAND_BYTES_2,
        .read_command         = OSPI_B_COMMAND_READ_DOPI_MODE,
        .program_command      = OSPI_B_COMMAND_PROGRAM_DOPI_MODE,
        .write_enable_command = OSPI_B_COMMAND_WRITE_ENABLE_DOPI_MODE,
        .status_command       = OSPI_B_COMMAND_STATUS_DOPI_MODE,
        .read_dummy_cycles    = 20U,
        .program_dummy_cycles = 0U,
        .status_dummy_cycles  = 3U,
        .p_erase_commands     = &g_2B_erase_table
    },

    /* 4S-4S-4S example with different .read_command and dummy cycles. */
    {
        .protocol             = SPI_FLASH_PROTOCOL_4S_4S_4S,
        .command_bytes        = OSPI_B_COMMAND_BYTES_1,
        .read_command         = OSPI_B_COMMAND_READ_QSPI_MODE,
        .program_command      = OSPI_B_COMMAND_PROGRAM_QSPI_MODE,
        .write_enable_command = OSPI_B_COMMAND_WRITE_ENABLE_QSPI_MODE,
        .status_command       = OSPI_B_COMMAND_STATUS_QSPI_MODE,
        .read_dummy_cycles    = 10U,
        .program_dummy_cycles = 0U,
        .status_dummy_cycles  = 1U,
        .p_erase_commands     = NULL,  // Use the common erase definitions.
    },
};

void r_ospi_command_table_example (void)
{
    /* Open the OSPI instance.
     * Specify `g_command_sets` using the configurator. */
    fsp_err_t err = R_OSPI_B_Open(&g_ospi0_ctrl, &g_ospi0_cfg);
    assert(FSP_SUCCESS == err);

    /* Change SPI to DOPI mode */
    ospi_b_change_mode(SPI_FLASH_PROTOCOL_8D_8D_8D);

    /* After R_OSPI_B_Open() and any required device specific initialization, data can be read directly from the OSPI flash. */
    memcpy(&g_dest[0], &g_src[0], OSPI_B_EXAMPLE_DATA_LENGTH);

    /* After R_OSPI_B_Open() and any required device specific initialization, functions in the OSPI flash can be called. */
    r_ospi_b_example_function();

    /* Change SPI to QSPI mode */
    ospi_b_change_mode(SPI_FLASH_PROTOCOL_4S_4S_4S);

    /* Read data from an external device, this time in QSPI mode. */
    memcpy(&g_dest[0], &g_src[0], OSPI_B_EXAMPLE_DATA_LENGTH);

    /* Run the example function again in QSPI mode. */
    r_ospi_b_example_function();
}

Change Protocol Mode Example (R_OSPI_B_DirectTransfer, R_OSPI_B_SpiProtocolSet)

This is an example of using R_OSPI_B_DirectTransfer to change the attached flash device to a new protocol mode during run time.

/*
 * This example file is only intended for use with Infineon S28HS256 flash devices and is non-exhaustive.
 * Other flash devices will require modification of command codes, addresses, and/or command sequences.
 */

#include "r_ospi_b.h"

/***********************************************************************************************************************
 * Macro definitions
 **********************************************************************************************************************/

/* Command code for enabling write operations. */
#define OSPI_B_COMMAND_WRITE_ENABLE_SPI_MODE      (0x06U)

/* Command code to query the status register. */
#define OSPI_B_COMMAND_READ_STATUS_SPI_MODE       (0x05U)

/* Command code to read a configuration register. */
#define OSPI_B_COMMAND_READ_REGISTER_SPI_MODE     (0x65U)

/* Command code to write to a configuration register. */
#define OSPI_B_COMMAND_WRITE_REGISTER_SPI_MODE    (0x71U)

/* Location of the write-enable bit in the status register. */
#define OSPI_B_WEN_BIT_MASK                       (0x02U)

/* Register setting for CFR5 of the Infineon S28HS256 to enable 8D-8D-8D mode. */
#define OSPI_B_DOPI_REGISTER_SETTING              (0x43U)

/* Register setting for CFR3 of the Infineon S28HS256 to support faster clock rates (up to 166 MHz DOPI). */
#define OSPI_B_FAST_CLOCK_REGISTER_SETTING        (0x80U)

/* Address of the CFR3 volatile register for the Infineon S28HS256. */
#define OSPI_B_CFR3V_ADDRESS                      (0x800004)

/* Address of the CFR5 volatile register for the Infineon S28HS256. */
#define OSPI_B_CFR5V_ADDRESS                      (0x800006)

/***********************************************************************************************************************
 * Function prototypes
 **********************************************************************************************************************/
void r_ospi_b_example_spi_to_dopi(ospi_b_instance_ctrl_t * const p_ctrl);

static void ospi_b_write_enable_and_verify(ospi_b_instance_ctrl_t * const p_ctrl, bool is_8d);
static void ospi_b_change_omclk(bsp_clocks_octaclk_div_t divider);


/*
 * Enables write operations on the target flash and verifies the change by reading the status register.
 * @param [in] p_ctrl Pointer to the OSPI_B control struct.
 * @param is_8d Indicates the target is currently configured for 8D-8D-8D protocol mode.
 */
static void ospi_b_write_enable_and_verify (ospi_b_instance_ctrl_t * const p_ctrl, bool is_8d)
{
    spi_flash_direct_transfer_t ospi_b_test_direct_transfer =
    {
        .command        = OSPI_B_COMMAND_WRITE_ENABLE_SPI_MODE,
        .address        = 0U,
        .data           = 0U,
        .command_length = 1U,
        .address_length = 0U,
        .data_length    = 0U,
        .dummy_cycles   = 0U
    };

    /* Write Enable */
    fsp_err_t err = R_OSPI_B_DirectTransfer(p_ctrl, &ospi_b_test_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE);
    assert(FSP_SUCCESS == err);

    ospi_b_test_direct_transfer.command     = OSPI_B_COMMAND_READ_STATUS_SPI_MODE;
    ospi_b_test_direct_transfer.data_length = 1U;

    /* Adjust the dummy cycles if currently operating in 8D-8D-8D mode. */
    if (is_8d)
    {
        ospi_b_test_direct_transfer.dummy_cycles = 5U;
    }

    /* Read Status Register */
    err = R_OSPI_B_DirectTransfer(p_ctrl, &ospi_b_test_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    assert(FSP_SUCCESS == err);

    if (OSPI_B_WEN_BIT_MASK != (ospi_b_test_direct_transfer.data & OSPI_B_WEN_BIT_MASK))
    {
        /* Verification of the write enable status failed. */
        __BKPT(0);
    }
}



/*
 * Changes the OCTACLK divider; assumes PLL2 is being used as the source for OCTACLK.
 * @param divider New clock divider to switch to.
 */
static void ospi_b_change_omclk (bsp_clocks_octaclk_div_t divider)
{
    /* Ensure clock source (PLL2 in this example) is running before changing the OCTACLK frequency */
    bsp_octaclk_settings_t octaclk_settings;
    octaclk_settings.source_clock = BSP_CLOCKS_CLOCK_PLL2;
    octaclk_settings.divider      = divider;
    R_BSP_OctaclkUpdate(&octaclk_settings);
}


/*
 * Example function to change from 1S-1S-1S (SPI) to 8D-8D-8D (DOPI) protocol mode.
 *
 * This assumes S28HS256 is in default factory configuration:
 *  - 3-byte address lengths
 *  - Memory read latency of 8/20 (1S/8S) up to 166 MHz DOPI
 *  - Register read latency of 0/3 up to 25 MHz DPOI
 *
 * @param [in] p_ctrl Pointer to the OSPI_B control struct.
 *
 * The OCTACLK source must be within range to support this example as written. Clocks are intended to be configured
 * as follows to obtain a PLL2P frequency of 240 MHz and OCTACLK starting frequency of 60 MHz.
 * HOCO (48 MHz) -> PLL2 -> /3 -> x60.0 {960 MHz} -> PLL2P /4 {240 MHz} -> OCTACLK -> /4 -> {60 MHz}.
 */
void r_ospi_b_example_spi_to_dopi (ospi_b_instance_ctrl_t * const p_ctrl)
{
    fsp_err_t err = FSP_SUCCESS;

    /* Step 1: Enable write access to the registers. */
    ospi_b_write_enable_and_verify(p_ctrl, false);

    /* Step 2: Adjust the dummy cycles for a faster clock later.
     * Changes the dummy cycles for register commands to 1 for SPI and 5 for OSPI.
     */
    spi_flash_direct_transfer_t xfer_adjust_cfr3 =
    {
        .command        = OSPI_B_COMMAND_WRITE_REGISTER_SPI_MODE,
        .address        = OSPI_B_CFR3V_ADDRESS,
        .data           = OSPI_B_FAST_CLOCK_REGISTER_SETTING,
        .command_length = 1U,
        .address_length = 3U,
        .data_length    = 1U,
        .dummy_cycles   = 0U
    };
    err = R_OSPI_B_DirectTransfer(p_ctrl, &xfer_adjust_cfr3, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE);
    assert(FSP_SUCCESS == err);

    /* Step 3: Change the target flash's configuration to use 8D-8D-8D mode. */
    spi_flash_direct_transfer_t xfer_change_mode =
    {
        .command        = OSPI_B_COMMAND_WRITE_REGISTER_SPI_MODE,
        .address        = OSPI_B_CFR5V_ADDRESS,
        .data           = OSPI_B_DOPI_REGISTER_SETTING,
        .command_length = 1U,
        .address_length = 3U,
        .data_length    = 1U,
        .dummy_cycles   = 0U
    };
    err = R_OSPI_B_DirectTransfer(p_ctrl, &xfer_change_mode, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE);
    assert(FSP_SUCCESS == err);

    /* Step 4: Speed up the bus by lowering the input divider.
     * If using the suggested clock settings this will increase the bus speed from 60 MHz to 120 MHz. */
    ospi_b_change_omclk(BSP_CLOCKS_OCTACLK_DIV_2);

    /* Step 5: Transition the OSPI peripheral to DOPI mode. This will initiate auto calibration as MDTR is 0.
     * This must happen after the device has been re-configured to the new mode. Otherwise, communications will be
     * lost as both MCU and flash device will be in different modes. */
    err = R_OSPI_B_SpiProtocolSet(p_ctrl, SPI_FLASH_PROTOCOL_DOPI);
    assert(FSP_SUCCESS == err);

    /* Step 6: Verify that the chip is in requested DOPI mode. */
    spi_flash_direct_transfer_t xfer_read_register =
    {
        .command        = OSPI_B_COMMAND_READ_REGISTER_SPI_MODE,
        .address        = OSPI_B_CFR5V_ADDRESS,
        .data           = 0,
        .command_length = 1U,
        .address_length = 4U,
        .data_length    = 1U,
        .dummy_cycles   = 5U,
    };
    err = R_OSPI_B_DirectTransfer(p_ctrl, &xfer_read_register, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    assert(FSP_SUCCESS == err);

    if (OSPI_B_DOPI_REGISTER_SETTING != xfer_read_register.data)
    {
        __BKPT(0);
    }
}

Data Structures
struct	ospi_b_table_t
struct	ospi_b_timing_setting_t
struct	ospi_b_xspi_command_set_t
struct	ospi_b_dotf_cfg_t
struct	ospi_b_extended_cfg_t
struct	ospi_b_instance_ctrl_t

Macros
#define	OSPI_B_MAX_WRITE_ENABLE_POLLING_LOOPS

Enumerations
enum	ospi_b_device_number_t
enum	ospi_b_command_bytes_t
enum	ospi_b_command_interval_clocks_t
enum	ospi_b_command_cs_pullup_clocks_t
enum	ospi_b_command_cs_pulldown_clocks_t
enum	ospi_b_ds_timing_delay_t
enum	ospi_b_sdr_drive_timing_t
enum	ospi_b_ck_edge_t
enum	ospi_b_sdr_sampling_delay_t
enum	ospi_b_ddr_sampling_extension_t
enum	ospi_b_frame_format_t
enum	ospi_b_latency_mode_t
enum	ospi_b_prefetch_function_t
enum	ospi_b_combination_function_t
enum	ospi_b_dotf_aes_key_length_words_t
enum	ospi_b_dotf_aes_key_type_t
enum	ospi_b_dotf_key_format_t

---

Data Structure Documentation

ospi_b_table_t

struct ospi_b_table_t

Simple array length table structure.

Data Fields
void *	p_table	Pointer to the table array.
uint8_t	length	Number of entries in the table.

ospi_b_timing_setting_t

struct ospi_b_timing_setting_t

Fixed timing configuration for bus signals.

Data Fields
ospi_b_command_interval_clocks_t	command_to_command_interval	Interval between 2 consecutive commands.
ospi_b_command_cs_pullup_clocks_t	cs_pullup_lag	Duration to de-assert CS line after the last command.
ospi_b_command_cs_pulldown_clocks_t	cs_pulldown_lead	Duration to assert CS line before the first command.
ospi_b_sdr_drive_timing_t	sdr_drive_timing	Data signal timing relative to the rising-edge of the CK signal.
ospi_b_ck_edge_t	sdr_sampling_edge	Selects the clock edge to sample the data signal.
ospi_b_sdr_sampling_delay_t	sdr_sampling_delay	Number of cycles to delay before sampling the data signal.
ospi_b_ddr_sampling_extension_t	ddr_sampling_extension	Number of cycles to extending the data sampling window in DDR mode.

ospi_b_xspi_command_set_t

struct ospi_b_xspi_command_set_t

Command set used for a protocol mode.

Data Fields
spi_flash_protocol_t	protocol	Protocol mode associated with this command set.
ospi_b_frame_format_t	frame_format	Frame format to use for this command set.
ospi_b_latency_mode_t	latency_mode	Configurable or variable latency, only valid for OSPI_B_FRAME_FORMAT_XSPI_PROFILE_2 and OSPI_B_FRAME_FORMAT_XSPI_PROFILE_2_EXTENDED.
ospi_b_command_bytes_t	command_bytes	Number of command bytes for each command code.
spi_flash_address_bytes_t	address_bytes	Number of bytes used during the address phase.
uint16_t	read_command	Read command.
uint16_t	program_command	Memory program/write command.
uint16_t	write_enable_command	Command to enable write or erase, set to 0x00 to ignore.
uint16_t	status_command	Command to read the write status, set to 0x00 to ignore.
uint16_t	row_load_command	Load a page into the device's internal buffer, set to 0x00 to ignore.
uint16_t	row_store_command	Stores the device's internal buffer to the memory page, set to 0x00 to ignore.
uint8_t	read_dummy_cycles	Dummy cycles to be inserted for read commands.
uint8_t	program_dummy_cycles	Dummy cycles to be inserted for page program commands.
uint8_t	status_dummy_cycles	Dummy cycles to be inserted for status read commands.
uint8_t	row_load_dummy_cycles	Dummy cycles to be inserted for the page load command.
uint8_t	row_store_dummy_cycles	Dummy cycles to be inserted for the page store command.
uint8_t	address_msb_mask	Mask of bits to zero when using memory-mapped operations; only applies to the most-significant byte.
bool	status_needs_address	Indicates that reading the status register requires an address stage.
uint32_t	status_address	Address to use for reading the status register with "busy" and "write-enable" flags.
spi_flash_address_bytes_t	status_address_bytes	Number of bytes used for status register addressing.
ospi_b_table_t const *	p_erase_commands	List of all erase commands and associated sizes.

ospi_b_dotf_cfg_t

struct ospi_b_dotf_cfg_t

This structure is used to hold all the DOTF related configuration.

ospi_b_extended_cfg_t

struct ospi_b_extended_cfg_t

OSPI_B Extended configuration.

Data Fields
uint8_t	ospi_b_unit	The OSPI_B unit corresponding to the selected channel.
ospi_b_device_number_t	channel	Device number to be used for memory device.
ospi_b_timing_setting_t const *	p_timing_settings	Fixed protocol timing settings.
ospi_b_table_t const *	p_xspi_command_set	Additional protocol command sets; if additional protocol commands set are not used set this to NULL.
ospi_b_ds_timing_delay_t	data_latch_delay_clocks	Delay after assertion of the DS signal where data should be latched.
uint8_t *	p_autocalibration_preamble_pattern_addr	OctaFlash memory address holding the preamble pattern.
transfer_instance_t const *	p_lower_lvl_transfer	DMA Transfer instance used for data transmission.

ospi_b_instance_ctrl_t

struct ospi_b_instance_ctrl_t

Instance control block. DO NOT INITIALIZE. Initialization occurs when spi_flash_api_t::open is called

Data Fields
spi_flash_cfg_t const *	p_cfg	Pointer to initial configuration.
uint32_t	open	Whether or not driver is open.
spi_flash_protocol_t	spi_protocol	Current OSPI protocol selected.
ospi_b_device_number_t	channel	Device number to be used for memory device.
uint8_t	ospi_b_unit	OSPI_B instance number.
ospi_b_xspi_command_set_t const *	p_cmd_set	Command set for the active protocol mode.
R_XSPI0_Type *	p_reg	Address for the OSPI peripheral associated with this channel.

Macro Definition Documentation

OSPI_B_MAX_WRITE_ENABLE_POLLING_LOOPS

#define OSPI_B_MAX_WRITE_ENABLE_POLLING_LOOPS

Maximum number of status polling checks after enabling memory writes.

Enumeration Type Documentation

ospi_b_device_number_t

enum ospi_b_device_number_t

OSPI Flash chip select

Enumerator
OSPI_B_DEVICE_NUMBER_0	Device connected to Chip-Select 0.
OSPI_B_DEVICE_NUMBER_1	Device connected to Chip-Select 1.

ospi_b_command_bytes_t

enum ospi_b_command_bytes_t

OSPI flash number of command code bytes.

Enumerator
OSPI_B_COMMAND_BYTES_1	Command codes are 1 byte long.
OSPI_B_COMMAND_BYTES_2	Command codes are 2 bytes long.

ospi_b_command_interval_clocks_t

enum ospi_b_command_interval_clocks_t

OSPI frame to frame interval

Enumerator
OSPI_B_COMMAND_INTERVAL_CLOCKS_1	1 interval clocks
OSPI_B_COMMAND_INTERVAL_CLOCKS_2	2 interval clocks
OSPI_B_COMMAND_INTERVAL_CLOCKS_3	3 interval clocks
OSPI_B_COMMAND_INTERVAL_CLOCKS_4	4 interval clocks
OSPI_B_COMMAND_INTERVAL_CLOCKS_5	5 interval clocks
OSPI_B_COMMAND_INTERVAL_CLOCKS_6	6 interval clocks
OSPI_B_COMMAND_INTERVAL_CLOCKS_7	7 interval clocks
OSPI_B_COMMAND_INTERVAL_CLOCKS_8	8 interval clocks
OSPI_B_COMMAND_INTERVAL_CLOCKS_9	9 interval clocks
OSPI_B_COMMAND_INTERVAL_CLOCKS_10	10 interval clocks
OSPI_B_COMMAND_INTERVAL_CLOCKS_11	11 interval clocks
OSPI_B_COMMAND_INTERVAL_CLOCKS_12	12 interval clocks
OSPI_B_COMMAND_INTERVAL_CLOCKS_13	13 interval clocks
OSPI_B_COMMAND_INTERVAL_CLOCKS_14	14 interval clocks
OSPI_B_COMMAND_INTERVAL_CLOCKS_15	15 interval clocks
OSPI_B_COMMAND_INTERVAL_CLOCKS_16	16 interval clocks

ospi_b_command_cs_pullup_clocks_t

enum ospi_b_command_cs_pullup_clocks_t

OSPI chip select de-assertion duration

Enumerator
OSPI_B_COMMAND_CS_PULLUP_CLOCKS_NO_EXTENSION	CS asserting No extension.
OSPI_B_COMMAND_CS_PULLUP_CLOCKS_1	CS asserting Extend 1 cycle.

ospi_b_command_cs_pulldown_clocks_t

enum ospi_b_command_cs_pulldown_clocks_t

OSPI chip select assertion duration

Enumerator
OSPI_B_COMMAND_CS_PULLDOWN_CLOCKS_NO_EXTENSION	CS negating No extension.
OSPI_B_COMMAND_CS_PULLDOWN_CLOCKS_1	CS negating Extend 1 cycle.

ospi_b_ds_timing_delay_t

enum ospi_b_ds_timing_delay_t

OSPI data strobe delay.

Enumerator
OSPI_B_DS_TIMING_DELAY_NONE	Sample without delay.
OSPI_B_DS_TIMING_DELAY_1	Delay sampling by 1 clock cell.
OSPI_B_DS_TIMING_DELAY_2	Delay sampling by 2 clock cells.
OSPI_B_DS_TIMING_DELAY_3	Delay sampling by 3 clock cells.
OSPI_B_DS_TIMING_DELAY_4	Delay sampling by 4 clock cells.
OSPI_B_DS_TIMING_DELAY_5	Delay sampling by 5 clock cells.
OSPI_B_DS_TIMING_DELAY_6	Delay sampling by 6 clock cells.
OSPI_B_DS_TIMING_DELAY_7	Delay sampling by 7 clock cells.
OSPI_B_DS_TIMING_DELAY_8	Delay sampling by 8 clock cells.
OSPI_B_DS_TIMING_DELAY_9	Delay sampling by 9 clock cells.
OSPI_B_DS_TIMING_DELAY_10	Delay sampling by 10 clock cells.
OSPI_B_DS_TIMING_DELAY_11	Delay sampling by 11 clock cells.
OSPI_B_DS_TIMING_DELAY_12	Delay sampling by 12 clock cells.
OSPI_B_DS_TIMING_DELAY_13	Delay sampling by 13 clock cells.
OSPI_B_DS_TIMING_DELAY_14	Delay sampling by 14 clock cells.
OSPI_B_DS_TIMING_DELAY_15	Delay sampling by 15 clock cells.
OSPI_B_DS_TIMING_DELAY_16	Delay sampling by 16 clock cells.
OSPI_B_DS_TIMING_DELAY_17	Delay sampling by 17 clock cells.
OSPI_B_DS_TIMING_DELAY_18	Delay sampling by 18 clock cells.
OSPI_B_DS_TIMING_DELAY_19	Delay sampling by 19 clock cells.
OSPI_B_DS_TIMING_DELAY_20	Delay sampling by 20 clock cells.
OSPI_B_DS_TIMING_DELAY_21	Delay sampling by 21 clock cells.
OSPI_B_DS_TIMING_DELAY_22	Delay sampling by 22 clock cells.
OSPI_B_DS_TIMING_DELAY_23	Delay sampling by 23 clock cells.
OSPI_B_DS_TIMING_DELAY_24	Delay sampling by 24 clock cells.
OSPI_B_DS_TIMING_DELAY_25	Delay sampling by 25 clock cells.
OSPI_B_DS_TIMING_DELAY_26	Delay sampling by 26 clock cells.
OSPI_B_DS_TIMING_DELAY_27	Delay sampling by 27 clock cells.
OSPI_B_DS_TIMING_DELAY_28	Delay sampling by 28 clock cells.
OSPI_B_DS_TIMING_DELAY_29	Delay sampling by 29 clock cells.
OSPI_B_DS_TIMING_DELAY_30	Delay sampling by 30 clock cells.
OSPI_B_DS_TIMING_DELAY_31	Delay sampling by 31 clock cells.

ospi_b_sdr_drive_timing_t

enum ospi_b_sdr_drive_timing_t

OSPI SDR signal drive timing.

Enumerator
OSPI_B_SDR_DRIVE_TIMING_BEFORE_CK	SDR is asserted 1/2 cycle before the rising-edge of CK.
OSPI_B_SDR_DRIVE_TIMING_AT_CK	SDR is asserted at the rising-edge of CK.

ospi_b_ck_edge_t

enum ospi_b_ck_edge_t

Clock edge useed to sample data in SDR mode.

Enumerator
OSPI_B_CK_EDGE_FALLING	Falling-edge of CK signal.
OSPI_B_CK_EDGE_RISING	Rising-edge of CK signal.

ospi_b_sdr_sampling_delay_t

enum ospi_b_sdr_sampling_delay_t

SDR sampling window delay.

Enumerator
OSPI_B_SDR_SAMPLING_DELAY_NONE	No sampling delay.
OSPI_B_SDR_SAMPLING_DELAY_1	Delay sampling by 1 cycle.
OSPI_B_SDR_SAMPLING_DELAY_2	Delay sampling by 2 cycles.
OSPI_B_SDR_SAMPLING_DELAY_3	Delay sampling by 3 cycles.
OSPI_B_SDR_SAMPLING_DELAY_4	Delay sampling by 4 cycles.
OSPI_B_SDR_SAMPLING_DELAY_5	Delay sampling by 5 cycles.
OSPI_B_SDR_SAMPLING_DELAY_6	Delay sampling by 6 cycles.
OSPI_B_SDR_SAMPLING_DELAY_7	Delay sampling by 7 cycles.

ospi_b_ddr_sampling_extension_t

enum ospi_b_ddr_sampling_extension_t

DDR sampling window extension.

Enumerator
OSPI_B_DDR_SAMPLING_EXTENSION_NONE	No sampling extension.
OSPI_B_DDR_SAMPLING_EXTENSION_1	Sampling extended by 1 cycle.
OSPI_B_DDR_SAMPLING_EXTENSION_2	Sampling extended by 2 cycles.
OSPI_B_DDR_SAMPLING_EXTENSION_3	Sampling extended by 3 cycles.
OSPI_B_DDR_SAMPLING_EXTENSION_4	Sampling extended by 4 cycles.
OSPI_B_DDR_SAMPLING_EXTENSION_5	Sampling extended by 5 cycles.
OSPI_B_DDR_SAMPLING_EXTENSION_6	Sampling extended by 6 cycles.
OSPI_B_DDR_SAMPLING_EXTENSION_7	Sampling extended by 7 cycles.

ospi_b_frame_format_t

enum ospi_b_frame_format_t

Format of data frames used for communicating with the target device.

Enumerator
OSPI_B_FRAME_FORMAT_STANDARD	Standard frame with command, address, and data phases.
OSPI_B_FRAME_FORMAT_XSPI_PROFILE_1	JEDEC XSPI 8D-8D-8D Profile 1.0 frame.
OSPI_B_FRAME_FORMAT_XSPI_PROFILE_2	JEDEC XSPI 8D-8D-8D Profile 2.0 frame.
OSPI_B_FRAME_FORMAT_XSPI_PROFILE_2_EXTENDED	JEDEC XSPI 8D-8D-8D Profile 2.0 extended 6-byte command-address frame, used with HyperRAM.

ospi_b_latency_mode_t

enum ospi_b_latency_mode_t

Variable or fixed latency selection for flash devices which can notify the host of requiring additional time.

Enumerator
OSPI_B_LATENCY_MODE_FIXED	Latency is fixed to the number of dummy cycles for the command.
OSPI_B_LATENCY_MODE_VARIABLE	The flash target signifies additional latency (2x dummy cycles) by asserting the DQS line during the address phase.

ospi_b_prefetch_function_t

enum ospi_b_prefetch_function_t

Prefetch function settings

Enumerator
OSPI_B_PREFETCH_FUNCTION_DISABLE	Prefetch function disable.
OSPI_B_PREFETCH_FUNCTION_ENABLE	Prefetch function enable.

ospi_b_combination_function_t

enum ospi_b_combination_function_t

Combination function settings

Enumerator
OSPI_B_COMBINATION_FUNCTION_DISABLE	Combination function disable.
OSPI_B_COMBINATION_FUNCTION_4BYTE	Combine up to 4 bytes.
OSPI_B_COMBINATION_FUNCTION_8BYTE	Combine up to 8 bytes.
OSPI_B_COMBINATION_FUNCTION_12BYTE	Combine up to 12 bytes.
OSPI_B_COMBINATION_FUNCTION_16BYTE	Combine up to 16 bytes.
OSPI_B_COMBINATION_FUNCTION_20BYTE	Combine up to 20 bytes.
OSPI_B_COMBINATION_FUNCTION_24BYTE	Combine up to 24 bytes.
OSPI_B_COMBINATION_FUNCTION_28BYTE	Combine up to 28 bytes.
OSPI_B_COMBINATION_FUNCTION_32BYTE	Combine up to 32 bytes.
OSPI_B_COMBINATION_FUNCTION_36BYTE	Combine up to 36 bytes.
OSPI_B_COMBINATION_FUNCTION_40BYTE	Combine up to 40 bytes.
OSPI_B_COMBINATION_FUNCTION_44BYTE	Combine up to 44 bytes.
OSPI_B_COMBINATION_FUNCTION_48BYTE	Combine up to 48 bytes.
OSPI_B_COMBINATION_FUNCTION_52BYTE	Combine up to 52 bytes.
OSPI_B_COMBINATION_FUNCTION_56BYTE	Combine up to 56 bytes.
OSPI_B_COMBINATION_FUNCTION_60BYTE	Combine up to 60 bytes.
OSPI_B_COMBINATION_FUNCTION_64BYTE	Combine up to 64 bytes.
OSPI_B_COMBINATION_FUNCTION_2BYTE	Combine up to 2 bytes.

ospi_b_dotf_aes_key_length_words_t

enum ospi_b_dotf_aes_key_length_words_t

OSPI DOTF AES Key Lengths.

ospi_b_dotf_aes_key_type_t

enum ospi_b_dotf_aes_key_type_t

PSPI DOTF AES Type.

ospi_b_dotf_key_format_t

enum ospi_b_dotf_key_format_t

OSPI DOTF key Type.

Function Documentation

R_OSPI_B_Open()

fsp_err_t R_OSPI_B_Open	(	spi_flash_ctrl_t *const	p_ctrl,
		spi_flash_cfg_t const *const	p_cfg
	)

Open the xSPI device. After the driver is open, the xSPI device can be accessed like internal flash memory.

Implements spi_flash_api_t::open.

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	The parameter p_ctrl or p_cfg is NULL.
FSP_ERR_ALREADY_OPEN	Driver has already been opened with the same p_ctrl.
FSP_ERR_CALIBRATE_FAILED	Failed to perform auto-calibrate.

R_OSPI_B_DirectWrite()

fsp_err_t R_OSPI_B_DirectWrite	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t const *const	p_src,
		uint32_t const	bytes,
		bool const	read_after_write
	)

Writes raw data directly to the OctaFlash. API not supported. Use R_OSPI_B_DirectTransfer

Implements spi_flash_api_t::directWrite.

Return values

FSP_ERR_UNSUPPORTED

API not supported by OSPI.

R_OSPI_B_DirectRead()

fsp_err_t R_OSPI_B_DirectRead	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t *const	p_dest,
		uint32_t const	bytes
	)

Reads raw data directly from the OctaFlash. API not supported. Use R_OSPI_B_DirectTransfer.

Implements spi_flash_api_t::directRead.

Return values

FSP_ERR_UNSUPPORTED

API not supported by OSPI.

R_OSPI_B_DirectTransfer()

fsp_err_t R_OSPI_B_DirectTransfer	(	spi_flash_ctrl_t *	p_ctrl,
		spi_flash_direct_transfer_t *const	p_transfer,
		spi_flash_direct_transfer_dir_t	direction
	)

Read/Write raw data directly with the OctaFlash.

Implements spi_flash_api_t::directTransfer.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_OSPI_B_XipEnter()

fsp_err_t R_OSPI_B_XipEnter

(

spi_flash_ctrl_t *

p_ctrl

)

Enters XIP (execute in place) mode.

Implements spi_flash_api_t::xipEnter.

Return values

FSP_SUCCESS	XiP mode was entered successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_UNSUPPORTED	XiP support is not enabled.

R_OSPI_B_XipExit()

fsp_err_t R_OSPI_B_XipExit

(

spi_flash_ctrl_t *

p_ctrl

)

Exits XIP (execute in place) mode.

Implements spi_flash_api_t::xipExit.

Return values

FSP_SUCCESS	XiP mode was entered successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_UNSUPPORTED	XiP support is not enabled.

R_OSPI_B_Write()

fsp_err_t R_OSPI_B_Write	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t const *const	p_src,
		uint8_t *const	p_dest,
		uint32_t	byte_count
	)

Program a page of data to the flash.

Implements spi_flash_api_t::write.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	p_instance_ctrl, p_dest or p_src is NULL, or byte_count crosses a page boundary.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_SIZE	Insufficient space remaining in page or write length is not a multiple of CPU access size when not using the DMAC.
FSP_ERR_DEVICE_BUSY	Another Write/Erase transaction is in progress.
FSP_ERR_WRITE_FAILED	Write operation failed.
FSP_ERR_INVALID_ADDRESS	Destination or source is not aligned to CPU access alignment when not using the DMAC.

R_OSPI_B_Erase()

fsp_err_t R_OSPI_B_Erase	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t *const	p_device_address,
		uint32_t	byte_count
	)

Erase a block or sector of flash. The byte_count must exactly match one of the erase sizes defined in spi_flash_cfg_t. For chip erase, byte_count must be SPI_FLASH_ERASE_SIZE_CHIP_ERASE.

Implements spi_flash_api_t::erase.

Return values

FSP_SUCCESS	The command to erase the flash was executed successfully.
FSP_ERR_ASSERTION	p_instance_ctrl or p_device_address is NULL, byte_count doesn't match an erase size defined in spi_flash_cfg_t, or byte_count is set to 0.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_DEVICE_BUSY	The device is busy.
FSP_ERR_WRITE_FAILED	Write operation failed.

R_OSPI_B_StatusGet()

fsp_err_t R_OSPI_B_StatusGet	(	spi_flash_ctrl_t *	p_ctrl,
		spi_flash_status_t *const	p_status
	)

Gets the write or erase status of the flash.

Implements spi_flash_api_t::statusGet.

Return values

FSP_SUCCESS	The write status is in p_status.
FSP_ERR_ASSERTION	p_instance_ctrl or p_status is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_OSPI_B_BankSet()

fsp_err_t R_OSPI_B_BankSet	(	spi_flash_ctrl_t *	p_ctrl,
		uint32_t	bank
	)

Selects the bank to access. Use ospi_b_bank_select_t as the bank value.

Implements spi_flash_api_t::bankSet.

Return values

FSP_ERR_UNSUPPORTED

This function is unsupported.

R_OSPI_B_SpiProtocolSet()

fsp_err_t R_OSPI_B_SpiProtocolSet	(	spi_flash_ctrl_t *	p_ctrl,
		spi_flash_protocol_t	spi_protocol
	)

Sets the SPI protocol.

Implements spi_flash_api_t::spiProtocolSet.

Return values

FSP_SUCCESS	SPI protocol updated on MPU peripheral.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_CALIBRATE_FAILED	Failed to perform auto-calibrate.

R_OSPI_B_Close()

fsp_err_t R_OSPI_B_Close

(

spi_flash_ctrl_t *

p_ctrl

)

Close the OSPI driver module.

Implements spi_flash_api_t::close.

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	p_instance_ctrl is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_OSPI_B_AutoCalibrate()

fsp_err_t R_OSPI_B_AutoCalibrate

(

spi_flash_ctrl_t *const

p_ctrl

)

AutoCalibrate the OSPI_B DS signal.

Implements spi_flash_api_t::autoCalibrate.

Return values

FSP_SUCCESS	Autocalibration completed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_UNSUPPORTED	Autocalibration support is not enabled.
FSP_ERR_CALIBRATE_FAILED	Failed to perform auto-calibrate.

R_OSPI_B_RowLoad()

fsp_err_t R_OSPI_B_RowLoad	(	spi_flash_ctrl_t *const	p_ctrl,
		uint32_t	row_index
	)

Loads a row into the page buffer on devices which support row addressing.

Parameters

[in]	p_ctrl	Pointer to a driver handle.
	row_index	Index of the row in the OSPI device.

Return values

FSP_SUCCESS	Page transaction succeeded.
FSP_ERR_INVALID_ARGUMENT	Invalid argument.
FSP_ERR_NOT_OPEN	Driver has not been opened.
FSP_ERR_UNSUPPORTED	Row addressing support is not enabled
FSP_ERR_DEVICE_BUSY	On going asynchronous operation or the device in in XiP mode.

R_OSPI_B_RowStore()

fsp_err_t R_OSPI_B_RowStore	(	spi_flash_ctrl_t *const	p_ctrl,
		uint32_t	row_index
	)

Stores (programs) the page buffer to a row on devices which support row addressing.

Parameters

[in]	p_ctrl	Pointer to a driver handle.
	row_index	Index of the row in the OSPI device.

Return values

FSP_SUCCESS	Page transaction succeeded.
FSP_ERR_INVALID_ARGUMENT	Invalid argument.
FSP_ERR_NOT_OPEN	Driver has not been opened.
FSP_ERR_UNSUPPORTED	Row addressing support is not enabled
FSP_ERR_DEVICE_BUSY	On going asynchronous operation or the device in in XiP mode.

R_OSPI_B_DOTF_Configure()

fsp_err_t R_OSPI_B_DOTF_Configure	(	spi_flash_ctrl_t *const	p_ctrl,
		ospi_b_dotf_cfg_t *const	p_dotf_cfg
	)

Configure DOTF

Parameters

[in]	p_ctrl	Pointer to OSPI specific control structure
[in]	p_dotf_cfg	Pointer to DOTF configuration structure

Return values

FSP_SUCCESS	DOTF enabled successfully
FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL	Key initialization failed.
FSP_ERR_CRYPTO_SCE_FAIL	Key wrapping failed.
FSP_ERR_INVALID_ARGUMENT	Invalid key type argument.
FSP_ERR_UNSUPPORTED	DOTF support is not enabled