QSPI (r_qspi)

Functions
fsp_err_t	R_QSPI_Open (spi_flash_ctrl_t *p_ctrl, spi_flash_cfg_t const *const p_cfg)
fsp_err_t	R_QSPI_DirectWrite (spi_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint32_t const bytes, bool const read_after_write)
fsp_err_t	R_QSPI_DirectRead (spi_flash_ctrl_t *p_ctrl, uint8_t *const p_dest, uint32_t const bytes)
fsp_err_t	R_QSPI_DirectTransfer (spi_flash_ctrl_t *p_ctrl, spi_flash_direct_transfer_t *const p_transfer, spi_flash_direct_transfer_dir_t direction)
fsp_err_t	R_QSPI_XipEnter (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_QSPI_XipExit (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_QSPI_Write (spi_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint8_t *const p_dest, uint32_t byte_count)
fsp_err_t	R_QSPI_Erase (spi_flash_ctrl_t *p_ctrl, uint8_t *const p_device_address, uint32_t byte_count)
fsp_err_t	R_QSPI_StatusGet (spi_flash_ctrl_t *p_ctrl, spi_flash_status_t *const p_status)
fsp_err_t	R_QSPI_BankSet (spi_flash_ctrl_t *p_ctrl, uint32_t bank)
fsp_err_t	R_QSPI_SpiProtocolSet (spi_flash_ctrl_t *p_ctrl, spi_flash_protocol_t spi_protocol)
fsp_err_t	R_QSPI_AutoCalibrate (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_QSPI_Close (spi_flash_ctrl_t *p_ctrl)

Detailed Description

Driver for the QSPI peripheral on RA MCUs. This module implements the SPI Flash Interface.

Overview

Features

The QSPI driver has the following key features:

• Memory mapped read access to the QSPI flash
• Programming the QSPI flash device
• Erasing the QSPI flash device
• Sending device specific commands and reading back responses
• Entering and exiting QPI mode
• Entering and exiting XIP mode
• 3 or 4 byte addressing

Configuration

Build Time Configurations for r_qspi

The following build time configurations are defined in driver/r_qspi_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Support Multiple Line Program in Extended SPI Mode	Enabled Disabled	Disabled	If selected code for programming on multiple lines in extended SPI mode is included in the build.

Configurations for Storage > QSPI (r_qspi)

This module can be added to the Stacks tab via New Stack > Storage > QSPI (r_qspi).

Configuration	Options	Default	Description
General
Name	Name must be a valid C symbol	g_qspi0	Module name.
SPI Protocol	Extended SPI QPI	Extended SPI	Select the initial SPI protocol. SPI protocol can be changed in R_QSPI_Direct().
Address Bytes	3 4 4 with 4-byte read code	3	Select the number of address bytes. Selecting '4 with 4-byte read code' converts the default read code determined in Read Mode to the 4-byte version. If 4-byte mode is selected without using 4-byte commands, the application must issue the EN4B command using R_QSPI_Direct().
Read Mode	Standard Read Fast Read Fast Read Dual Output Fast Read Dual I/O Fast Read Quad Output Fast Read Quad I/O	Fast Read Quad I/O	Select the read mode for memory mapped access.
Dummy Clocks for Fast Read	Refer to the RA Configuration tool for available options.	Default	Select the number of dummy clocks for fast read operations. Default is 6 clocks for Fast Read Quad I/O, 4 clocks for Fast Read Dual I/O, and 8 clocks for other fast read instructions including Fast Read Quad Output, Fast Read Dual Output, and Fast Read
Page Size Bytes	Must be an integer greater than 0	256	The maximum number of bytes allowed for a single write.
Command Definitions
Page Program Command	Must be an 8-bit QSPI Page Program Command under Command Definitions	0x02	The command to program a page. If 'Support Multiple Line Program in Extended SPI Mode' is Enabled, this command must use the same number of data lines as the selected read mode.
Page Program Address Lines	1 2 4	1	Select the number of lines to use for the address bytes during write operations. This can be determined by referencing the datasheet for the external QSPI. It should either be 1 or match the number of data lines used for memory mapped fast read operations.
Write Enable Command	Must be an 8-bit QSPI Write Enable Command under Command Definitions	0x06	The command to enable write.
Status Command	Must be an 8-bit QSPI Status Command under Command Definitions	0x05	The command to query the status of a write or erase command.
Write Status Bit	Must be an integer between 0 and 7	0	Which bit contains the write in progress status returned from the Write Status Command.
Sector Erase Command	Must be an 8-bit QSPI Sector Erase Command under Command Definitions	0x20	The command to erase a sector. Set Sector Erase Size to 0 if unused.
Sector Erase Size	Must be an integer greater than or equal to 0	4096	The sector erase size. Set Sector Erase Size to 0 if Sector Erase is not supported.
Block Erase Command	Must be an 8-bit QSPI Block Erase Command under Command Definitions	0xD8	The command to erase a block. Set Block Erase Size to 0 if unused.
Block Erase Size	Must be an integer greater than or equal to 0	65536	The block erase size. Set Block Erase Size to 0 if Block Erase is not supported.
Block Erase 32KB Command	Must be an 8-bit QSPI Block Erase 32KB Command under Command Definitions	0x52	The command to erase a 32KB block. Set Block Erase Size to 0 if unused.
Block Erase 32KB Size	Must be an integer greater than or equal to 0	32768	The block erase 32KB size. Set Block Erase 32KB Size to 0 if Block Erase 32KB is not supported.
Chip Erase Command	Must be an 8-bit QSPI Chip Erase Command under Command Definitions	0xC7	The command to erase the entire chip. Set Chip Erase Command to 0 if unused.
XIP Enter M7-M0	Must be an 8-bit QSPI XIP Enter M7-M0 command under Command Definitions	0x20	How to set M7-M0 to enter XIP mode.
XIP Exit M7-M0	Must be an 8-bit QSPI XIP Exit M7-M0 command under Command Definitions	0xFF	How to set M7-M0 exit XIP mode.
Bus Timing
QSPKCLK Divisor	Refer to the RA Configuration tool for available options.	2	Select the divisor to apply to PCLK to get QSPCLK.
Minimum QSSL Deselect Cycles	Refer to the RA Configuration tool for available options.	4 QSPCLK	Define the minimum number of QSPCLK cycles for QSSL to remain high beween operations.

Clock Configuration

The QSPI clock is derived from PCLKA.

Pin Configuration

The following pins are available to connect to an external QSPI device:

• QSPCLK: QSPI clock output
• QSSL: QSPI slave select
• QIO0: Data 0 I/O
• QIO1: Data 1 I/O
• QIO2: Data 2 I/O
• QIO3: Data 3 I/O

Note

It is recommended to configure the pins with IOPORT_CFG_DRIVE_HIGH.

Usage Notes

QSPI Memory Mapped Access

After R_QSPI_Open() completes successfully, the QSPI flash device contents are mapped to address 0x60000000 and can be read like on-chip flash.

Limitations

Developers should be aware of the following limitations when using the QSPI driver:

• Only P305-P310 are currently supported by the J-Link driver to flash the QSPI.
• The default J-Link downloader requires the device to be in extended SPI mode (not QPI mode).

Examples

Basic Example

This is a basic example of minimal use of the QSPI in an application.

#define QSPI_EXAMPLE_DATA_LENGTH    (1024)

uint8_t g_dest[QSPI_EXAMPLE_DATA_LENGTH];

/* Place data in the .qspi_flash section to flash it during programming. */
const uint8_t g_src[QSPI_EXAMPLE_DATA_LENGTH] BSP_PLACE_IN_SECTION(".qspi_flash") = "ABCDEFGHIJKLMNOPQRSTUVWXYZ";

/* Place code in the .code_in_qspi section to flash it during programming. */
void r_qspi_example_function(void) BSP_PLACE_IN_SECTION(".code_in_qspi") __attribute__((noinline));

void r_qspi_example_function (void)
{
    /* Add code here. */
}

void r_qspi_basic_example (void)
{

    /* Open the QSPI instance. */
    fsp_err_t err = R_QSPI_Open(&g_qspi0_ctrl, &g_qspi0_cfg);

    assert(FSP_SUCCESS == err);

    /* (Optional) Send device specific initialization commands. */
    r_qspi_example_init();

    /* After R_QSPI_Open() and any required device specific intiialization, data can be read directly from the QSPI flash. */
    memcpy(&g_dest[0], &g_src[0], QSPI_EXAMPLE_DATA_LENGTH);

    /* After R_QSPI_Open() and any required device specific intiialization, functions in the QSPI flash can be called. */
    r_qspi_example_function();
}

Initialization Command Structure Example

This is an example of the types of commands that can be used to initialize the QSPI.

#define QSPI_COMMAND_WRITE_ENABLE             (0x06U)
#define QSPI_COMMAND_WRITE_STATUS_REGISTER    (0x01U)
#define QSPI_COMMAND_ENTER_QPI_MODE           (0x38U)

#define QSPI_EXAMPLE_STATUS_REGISTER_1        (0x40)
#define QSPI_EXAMPLE_STATUS_REGISTER_2        (0x00)

static void r_qspi_example_init (void)
{
    /* Write status registers */
    /* Write one byte to enable writing to the status register, then deassert QSSL. */
    uint8_t   data[4];
    fsp_err_t err;
    data[0] = QSPI_COMMAND_WRITE_ENABLE;
    err     = R_QSPI_DirectWrite(&g_qspi0_ctrl, &data[0], 1, false);
    assert(FSP_SUCCESS == err);

    /* Write 3 bytes, including the write status register command followed by values for both status registers. In the
     * status registers, set QE to 1 and other bits to their default setting. After all data is written, deassert the
     * QSSL line. */
    data[0] = QSPI_COMMAND_WRITE_STATUS_REGISTER;
    data[1] = QSPI_EXAMPLE_STATUS_REGISTER_1;
    data[2] = QSPI_EXAMPLE_STATUS_REGISTER_2;
    err     = R_QSPI_DirectWrite(&g_qspi0_ctrl, &data[0], 3, false);
    assert(FSP_SUCCESS == err);

    /* Wait for status register to update. */
    spi_flash_status_t status;
    do
    {
        (void) R_QSPI_StatusGet(&g_qspi0_ctrl, &status);
    } while (true == status.write_in_progress);

    /* Write one byte to enter QSPI mode, then deassert QSSL. After entering QPI mode on the device, change the SPI
     * protocol to QPI mode on the MCU peripheral. */
    data[0] = QSPI_COMMAND_ENTER_QPI_MODE;
    err     = R_QSPI_DirectWrite(&g_qspi0_ctrl, &data[0], 1, false);
    assert(FSP_SUCCESS == err);

    (void) R_QSPI_SpiProtocolSet(&g_qspi0_ctrl, SPI_FLASH_PROTOCOL_QPI);
}

Reading Status Register Example (R_QSPI_DirectWrite, R_QSPI_DirectRead)

This is an example of using R_QSPI_DirectWrite followed by R_QSPI_DirectRead to send the read status register command and read back the status register from the device.

#define QSPI_COMMAND_READ_STATUS_REGISTER    (0x05U)

void r_qspi_direct_example (void)
{
    /* Read a status register. */

    /* Write one byte to read the status register. Do not deassert QSSL. */
    uint8_t   data;
    fsp_err_t err;
    data = QSPI_COMMAND_READ_STATUS_REGISTER;
    err  = R_QSPI_DirectWrite(&g_qspi0_ctrl, &data, 1, true);
    assert(FSP_SUCCESS == err);

    /* Read one byte. After all data is read, deassert the QSSL line. */
    err = R_QSPI_DirectRead(&g_qspi0_ctrl, &data, 1);
    assert(FSP_SUCCESS == err);

    /* Status register contents are available in variable 'data'. */
}

Querying Device Size Example (R_QSPI_DirectWrite, R_QSPI_DirectRead)

This is an example of using R_QSPI_DirectWrite followed by R_QSPI_DirectRead to query the device size.

#define QSPI_EXAMPLE_COMMAND_READ_ID      (0x9F)
#define QSPI_EXAMPLE_COMMAND_READ_SFDP    (0x5A)

void r_qspi_size_example (void)
{
    /* Many QSPI devices support more than one way to query the device size. Consult the datasheet for your
     * QSPI device to determine which of these methods are supported (if any). */
    uint32_t  device_size_bytes;
    fsp_err_t err;

#ifdef QSPI_EXAMPLE_COMMAND_READ_ID

    /* This example shows how to get the device size by reading the manufacturer ID. */
    uint8_t data[4];
    data[0] = QSPI_EXAMPLE_COMMAND_READ_ID;
    err     = R_QSPI_DirectWrite(&g_qspi0_ctrl, &data[0], 1, true);
    assert(FSP_SUCCESS == err);

    /* Read 3 bytes. The third byte often represents the size of the QSPI, where the size of the QSPI = 2 ^ N. */
    err = R_QSPI_DirectRead(&g_qspi0_ctrl, &data[0], 3);
    assert(FSP_SUCCESS == err);
    device_size_bytes = 1U << data[2];
    FSP_PARAMETER_NOT_USED(device_size_bytes);
#endif

#ifdef QSPI_EXAMPLE_COMMAND_READ_SFDP

    /* Read the JEDEC SFDP header to locate the JEDEC flash parameters table. Reference JESD216 "Serial Flash
     * Discoverable Parameters (SFDP)". */

    /* Send the standard 0x5A command followed by 3 address bytes (SFDP header is at address 0). */
    uint8_t buffer[16];
    memset(&buffer[0], 0, sizeof(buffer));
    buffer[0] = QSPI_EXAMPLE_COMMAND_READ_SFDP;
    err       = R_QSPI_DirectWrite(&g_qspi0_ctrl, &buffer[0], 4, true);
    assert(FSP_SUCCESS == err);

    /* Read out 16 bytes (1 dummy byte followed by 15 data bytes). */
    err = R_QSPI_DirectRead(&g_qspi0_ctrl, &buffer[0], 16);
    assert(FSP_SUCCESS == err);

    /* Read the JEDEC flash parameters to locate the memory size. */

    /* Send the standard 0x5A command followed by 3 address bytes (located in big endian order at offset 0xC-0xE).
     * These bytes are accessed at 0xD-0xF because the first byte read is a dummy byte. */
    buffer[0] = QSPI_EXAMPLE_COMMAND_READ_SFDP;
    buffer[1] = buffer[0xF];
    buffer[2] = buffer[0xE];
    buffer[3] = buffer[0xD];
    err       = R_QSPI_DirectWrite(&g_qspi0_ctrl, &buffer[0], 4, true);
    assert(FSP_SUCCESS == err);

    /* Read out 9 bytes (1 dummy byte followed by 8 data bytes). */
    err = R_QSPI_DirectRead(&g_qspi0_ctrl, &buffer[0], 9);
    assert(FSP_SUCCESS == err);

    /* Read the memory density (located in big endian order at offset 0x4-0x7). These bytes are accessed at 0x5-0x8
     * because the first byte read is a dummy byte. */
    uint32_t memory_density = (uint32_t) ((buffer[8] << 24) | (buffer[7] << 16) | (buffer[6] << 8) | buffer[5]);
    if ((1U << 31) & memory_density)
    {
        /* For densities 4 gigabits and above, bit-31 is set to 1b.  The field 30:0 defines ‘N’ where the density is
         * computed as 2^N bits (N must be >= 32). This code subtracts 3 from N to divide by 8 to get the size in
         * bytes instead of bits. */
        device_size_bytes = 1U << ((memory_density & ~(1U << 31)) - 3U);
    }
    else
    {
        /* For densities 2 gigabits or less, bit-31 is set to 0b.  The field 30:0 defines the size in bits. This
         * code divides the memory density by 8 to get the size in bytes instead of bits. */
        device_size_bytes = (memory_density / 8) + 1;
    }
    FSP_PARAMETER_NOT_USED(device_size_bytes);
#endif
}

Data Structures
struct	qspi_instance_ctrl_t

Enumerations
enum	qspi_qssl_min_high_level_t
enum	qspi_qspclk_div_t

---

Data Structure Documentation

qspi_instance_ctrl_t

struct qspi_instance_ctrl_t

Instance control block. DO NOT INITIALIZE. Initialization occurs when spi_flash_api_t::open is called

Enumeration Type Documentation

qspi_qssl_min_high_level_t

enum qspi_qssl_min_high_level_t

Enumerator
QSPI_QSSL_MIN_HIGH_LEVEL_1_QSPCLK	QSSL deselected for at least 1 QSPCLK.
QSPI_QSSL_MIN_HIGH_LEVEL_2_QSPCLK	QSSL deselected for at least 2 QSPCLK.
QSPI_QSSL_MIN_HIGH_LEVEL_3_QSPCLK	QSSL deselected for at least 3 QSPCLK.
QSPI_QSSL_MIN_HIGH_LEVEL_4_QSPCLK	QSSL deselected for at least 4 QSPCLK.
QSPI_QSSL_MIN_HIGH_LEVEL_5_QSPCLK	QSSL deselected for at least 5 QSPCLK.
QSPI_QSSL_MIN_HIGH_LEVEL_6_QSPCLK	QSSL deselected for at least 6 QSPCLK.
QSPI_QSSL_MIN_HIGH_LEVEL_7_QSPCLK	QSSL deselected for at least 7 QSPCLK.
QSPI_QSSL_MIN_HIGH_LEVEL_8_QSPCLK	QSSL deselected for at least 8 QSPCLK.
QSPI_QSSL_MIN_HIGH_LEVEL_9_QSPCLK	QSSL deselected for at least 9 QSPCLK.
QSPI_QSSL_MIN_HIGH_LEVEL_10_QSPCLK	QSSL deselected for at least 10 QSPCLK.
QSPI_QSSL_MIN_HIGH_LEVEL_11_QSPCLK	QSSL deselected for at least 11 QSPCLK.
QSPI_QSSL_MIN_HIGH_LEVEL_12_QSPCLK	QSSL deselected for at least 12 QSPCLK.
QSPI_QSSL_MIN_HIGH_LEVEL_13_QSPCLK	QSSL deselected for at least 13 QSPCLK.
QSPI_QSSL_MIN_HIGH_LEVEL_14_QSPCLK	QSSL deselected for at least 14 QSPCLK.
QSPI_QSSL_MIN_HIGH_LEVEL_15_QSPCLK	QSSL deselected for at least 15 QSPCLK.
QSPI_QSSL_MIN_HIGH_LEVEL_16_QSPCLK	QSSL deselected for at least 16 QSPCLK.

qspi_qspclk_div_t

enum qspi_qspclk_div_t

Enumerator
QSPI_QSPCLK_DIV_2	QSPCLK = PCLK / 2.
QSPI_QSPCLK_DIV_3	QSPCLK = PCLK / 3.
QSPI_QSPCLK_DIV_4	QSPCLK = PCLK / 4.
QSPI_QSPCLK_DIV_5	QSPCLK = PCLK / 5.
QSPI_QSPCLK_DIV_6	QSPCLK = PCLK / 6.
QSPI_QSPCLK_DIV_7	QSPCLK = PCLK / 7.
QSPI_QSPCLK_DIV_8	QSPCLK = PCLK / 8.
QSPI_QSPCLK_DIV_9	QSPCLK = PCLK / 9.
QSPI_QSPCLK_DIV_10	QSPCLK = PCLK / 10.
QSPI_QSPCLK_DIV_11	QSPCLK = PCLK / 11.
QSPI_QSPCLK_DIV_12	QSPCLK = PCLK / 12.
QSPI_QSPCLK_DIV_13	QSPCLK = PCLK / 13.
QSPI_QSPCLK_DIV_14	QSPCLK = PCLK / 14.
QSPI_QSPCLK_DIV_15	QSPCLK = PCLK / 15.
QSPI_QSPCLK_DIV_16	QSPCLK = PCLK / 16.
QSPI_QSPCLK_DIV_17	QSPCLK = PCLK / 17.
QSPI_QSPCLK_DIV_18	QSPCLK = PCLK / 18.
QSPI_QSPCLK_DIV_20	QSPCLK = PCLK / 20.
QSPI_QSPCLK_DIV_22	QSPCLK = PCLK / 22.
QSPI_QSPCLK_DIV_24	QSPCLK = PCLK / 24.
QSPI_QSPCLK_DIV_26	QSPCLK = PCLK / 26.
QSPI_QSPCLK_DIV_28	QSPCLK = PCLK / 28.
QSPI_QSPCLK_DIV_30	QSPCLK = PCLK / 30.
QSPI_QSPCLK_DIV_32	QSPCLK = PCLK / 32.
QSPI_QSPCLK_DIV_34	QSPCLK = PCLK / 34.
QSPI_QSPCLK_DIV_36	QSPCLK = PCLK / 36.
QSPI_QSPCLK_DIV_38	QSPCLK = PCLK / 38.
QSPI_QSPCLK_DIV_40	QSPCLK = PCLK / 40.
QSPI_QSPCLK_DIV_42	QSPCLK = PCLK / 42.
QSPI_QSPCLK_DIV_44	QSPCLK = PCLK / 44.
QSPI_QSPCLK_DIV_46	QSPCLK = PCLK / 46.
QSPI_QSPCLK_DIV_48	QSPCLK = PCLK / 48.

Function Documentation

R_QSPI_Open()

fsp_err_t R_QSPI_Open	(	spi_flash_ctrl_t *	p_ctrl,
		spi_flash_cfg_t const *const	p_cfg
	)

Open the QSPI driver module. After the driver is open, the QSPI can be accessed like internal flash memory starting at address 0x60000000.

Implements spi_flash_api_t::open.

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	The parameter p_instance_ctrl or p_cfg is NULL.
FSP_ERR_ALREADY_OPEN	Driver has already been opened with the same p_instance_ctrl.

R_QSPI_DirectWrite()

fsp_err_t R_QSPI_DirectWrite	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t const *const	p_src,
		uint32_t const	bytes,
		bool const	read_after_write
	)

Writes raw data directly to the QSPI.

Implements spi_flash_api_t::directWrite.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_MODE	This function can't be called when XIP mode is enabled.
FSP_ERR_DEVICE_BUSY	The device is busy.

R_QSPI_DirectRead()

fsp_err_t R_QSPI_DirectRead	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t *const	p_dest,
		uint32_t const	bytes
	)

Reads raw data directly from the QSPI. This API can only be called after R_QSPI_DirectWrite with read_after_write set to true.

Implements spi_flash_api_t::directRead.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_MODE	This function must be called after R_QSPI_DirectWrite with read_after_write set to true.

R_QSPI_DirectTransfer()

fsp_err_t R_QSPI_DirectTransfer	(	spi_flash_ctrl_t *	p_ctrl,
		spi_flash_direct_transfer_t *const	p_transfer,
		spi_flash_direct_transfer_dir_t	direction
	)

Read/Write raw data directly with the OctaFlash/OctaRAM device. Unsupported by QSPI.

Implements spi_flash_api_t::directTransfer.

Return values

FSP_ERR_UNSUPPORTED

API not supported by QSPI.

R_QSPI_XipEnter()

fsp_err_t R_QSPI_XipEnter

(

spi_flash_ctrl_t *

p_ctrl

)

Enters XIP (execute in place) mode.

Implements spi_flash_api_t::xipEnter.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_QSPI_XipExit()

fsp_err_t R_QSPI_XipExit

(

spi_flash_ctrl_t *

p_ctrl

)

Exits XIP (execute in place) mode.

Implements spi_flash_api_t::xipExit.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_QSPI_Write()

fsp_err_t R_QSPI_Write	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t const *const	p_src,
		uint8_t *const	p_dest,
		uint32_t	byte_count
	)

Program a page of data to the flash.

Implements spi_flash_api_t::write.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	p_instance_ctrl, p_dest or p_src is NULL, or byte_count crosses a page boundary.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_MODE	This function can't be called when XIP mode is enabled.
FSP_ERR_DEVICE_BUSY	The device is busy.

R_QSPI_Erase()

fsp_err_t R_QSPI_Erase	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t *const	p_device_address,
		uint32_t	byte_count
	)

Erase a block or sector of flash. The byte_count must exactly match one of the erase sizes defined in spi_flash_cfg_t. For chip erase, byte_count must be SPI_FLASH_ERASE_SIZE_CHIP_ERASE.

Implements spi_flash_api_t::erase.

Return values

FSP_SUCCESS	The command to erase the flash was executed successfully.
FSP_ERR_ASSERTION	p_instance_ctrl or p_device_address is NULL, or byte_count doesn't match an erase size defined in spi_flash_cfg_t, or device is in XIP mode.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_MODE	This function can't be called when XIP mode is enabled.
FSP_ERR_DEVICE_BUSY	The device is busy.

R_QSPI_StatusGet()

fsp_err_t R_QSPI_StatusGet	(	spi_flash_ctrl_t *	p_ctrl,
		spi_flash_status_t *const	p_status
	)

Gets the write or erase status of the flash.

Implements spi_flash_api_t::statusGet.

Return values

FSP_SUCCESS	The write status is in p_status.
FSP_ERR_ASSERTION	p_instance_ctrl or p_status is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_MODE	This function can't be called when XIP mode is enabled.

R_QSPI_BankSet()

fsp_err_t R_QSPI_BankSet	(	spi_flash_ctrl_t *	p_ctrl,
		uint32_t	bank
	)

Selects the bank to access. A bank is a 64MB sliding access window into the QSPI device flash memory space. To access chip address 0x4000000, select bank 1, then read from internal flash address 0x60000000. To access chip address 0x8001000, select bank 2, then read from internal flash address 0x60001000.

This function is not required for memory devices less than or equal to 512 Mb (64MB).

Implements spi_flash_api_t::bankSet.

Return values

FSP_SUCCESS	Bank successfully selected.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_QSPI_SpiProtocolSet()

fsp_err_t R_QSPI_SpiProtocolSet	(	spi_flash_ctrl_t *	p_ctrl,
		spi_flash_protocol_t	spi_protocol
	)

Sets the SPI protocol.

Implements spi_flash_api_t::spiProtocolSet.

Return values

FSP_SUCCESS	SPI protocol updated on MCU peripheral.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_ARGUMENT	Invalid SPI protocol requested.

R_QSPI_AutoCalibrate()

fsp_err_t R_QSPI_AutoCalibrate

(

spi_flash_ctrl_t *

p_ctrl

)

Auto-calibrate the OctaRAM device using the preamble pattern. Unsupported by QSPI. Implements spi_flash_api_t::autoCalibrate.

Return values

FSP_ERR_UNSUPPORTED

API not supported by QSPI

R_QSPI_Close()

fsp_err_t R_QSPI_Close

(

spi_flash_ctrl_t *

p_ctrl

)

Close the QSPI driver module.

Implements spi_flash_api_t::close.

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	p_instance_ctrl is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.