Functions
fsp_err_t	R_RMAC_PHY_Open (ether_phy_ctrl_t const p_ctrl, ether_phy_cfg_t const const p_cfg)
	Resets Ethernet PHY device. Implements ether_phy_api_t::open. More...

fsp_err_t	R_RMAC_PHY_Close (ether_phy_ctrl_t *const p_ctrl)
	Close Ethernet PHY device. Implements ether_phy_api_t::close. More...

fsp_err_t	R_RMAC_PHY_StartAutoNegotiate (ether_phy_ctrl_t *const p_ctrl)
	Starts auto-negotiate. Implements ether_phy_api_t::startAutoNegotiate. More...

fsp_err_t	R_RMAC_PHY_LinkPartnerAbilityGet (ether_phy_ctrl_t const p_ctrl, uint32_t const p_line_speed_duplex, uint32_t const p_local_pause, uint32_t const p_partner_pause)
	Reports the other side's physical capability. Implements ether_phy_api_t::linkPartnerAbilityGet. More...

fsp_err_t	R_RMAC_PHY_LinkStatusGet (ether_phy_ctrl_t *const p_ctrl)
	Returns the status of the physical link. Implements ether_phy_api_t::linkStatusGet. More...

fsp_err_t	R_RMAC_PHY_ChipInit (ether_phy_ctrl_t const p_ctrl, ether_phy_cfg_t const const p_cfg)
	Initialize Ethernet PHY device. Implements ether_phy_api_t::chipInit. More...

fsp_err_t	R_RMAC_PHY_Read (ether_phy_ctrl_t const p_ctrl, uint32_t reg_addr, uint32_t const p_data)
	Read data from register of PHY-LSI . Implements ether_phy_api_t::read. More...

fsp_err_t	R_RMAC_PHY_Write (ether_phy_ctrl_t *const p_ctrl, uint32_t reg_addr, uint32_t data)
	Write data to register of PHY-LSI . Implements ether_phy_api_t::write. More...

fsp_err_t	R_RMAC_PHY_ChipSelect (ether_phy_ctrl_t *const p_ctrl, uint8_t port)
	Update the target PHY LSI of this driver. More...

Detailed Description

The RMAC PHY module (r_rmac_phy) provides an API for standard Ethernet PHY communications applications that use the RMAC peripheral. It implements the Ethernet PHY Interface.

Overview

The RMAC PHY module is used to setup and manage an external Ethernet PHY device. r_rmac_phy use the on-chip MAC layer peripheral(RMAC), which is part of Ethernet Switch Module(ESWM). It performs auto-negotiation to determine the optimal connection parameters between link partners. Once initialized the connection between the external PHY and the onboard controller is automatically managed in hardware.

Features

The RMAC PHY module supports the following features:

Auto negotiation support
Flow control support
Link status check support
Gigabit Ethernet support

Following features are not supported:

Extensions to management frame format defined in IEEE802.3 clause 45

Configuration

Build Time Configurations for r_rmac_phy

The following build time configurations are defined in fsp_cfg/r_rmac_phy_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
KSZ8091RNB Target	Disabled Enabled	Disabled	Select whether to use KSZ8091RNB PHY-LSI or not.
KSZ8041 Target	Disabled Enabled	Disabled	Select whether to use KSZ8041 PHY-LSI or not.
DP83620 Target	Disabled Enabled	Disabled	Select whether to use DP83620 PHY-LSI or not.
ICS1894 Target	Disabled Enabled	Disabled	Select whether to use ICS1894 PHY-LSI or not.
GPY111 Target	Disabled Enabled	Disabled	Select whether to use GPY111 PHY-LSI or not.
User Own Target	Disabled Enabled	Disabled	Select whether to use User own PHY-LSI or not.
Reference Clock	Default Enabled Disabled	Default	Select whether to use the RMII reference clock. Selecting 'Default' will automatically choose the correct option when using a Renesas development board.
Reference Clock	Default Enabled Disabled	Default	Select whether to use the RMII reference clock. Selecting 'Default' will automatically choose the correct option when using a Renesas development board.

Configurations for Networking > Ethernet (r_rmac_phy)

This module can be added to the Stacks tab via New Stack > Networking > Ethernet (r_rmac_phy). Non-secure callable guard functions can be generated for this module by right clicking the module in the RA Configuration tool and checking the "Non-secure Callable" box.

Configuration	Options	Default	Description
Name	Name must be a valid C symbol	g_rmac_phy0	Module name.
Channel	0 1	0	Select the Ethernet controller channel number.
Default PHY-LSI port	0 1	0	Specify the default port for PHY-LSI configuration.
PHY-LSI Reset Completion Timeout	Specify a value between 0x1 and 0xFFFFFFFF.	0x00020000	Specify the number of times to read the PHY-LSI control register while waiting for reset completion. This value should be adjusted experimentally based on the PHY-LSI used.
Select MII type	MII RMII GMII RGMII	RMII	Specify whether to use MII or RMII.
Port Custom Init Function	Name must be a valid C symbol	NULL	Set the initial function of the PHY-LSI, When using your own PHY-LSI.
Port Custom Link Partner Ability Get Function	Name must be a valid C symbol	NULL	Set the link partner ability get function of the PHY-LSI, When using your own PHY-LSI.
Flow Control	Disable Enable	Disable	Select whether to enable or disable flow control.
Management frame format	Clause 22 frame format	Clause 22 frame format	Select the management frame format used to access the PHY-LSI.
MDC clock rate (Hz)	Value must be a non-negative number	2500000	Specify the MDC clock frequency
MDIO hold timing adjustment	Value must be a non-negative integer less than 8	0	Specify the clock cycle for hold timing.
MDIO capture timing adjustment	Value must be a non-negative integer less than 8	0	Specify the clock cycle for capture timing.

Usage Notes

Accessing the Registers in PHY-LSI

Use the RMAC peripheral to access the registers in the PHY-LSI. Management frame is transmitted and received through the ETn_MDC and ETn_MDIO pins controlled by hardware.

This HW supports two management frame format.

Normal management frame format defined in Clause 22 of IEEE802.3 (Describe “MDIO” in this document)
Extension management frame format defined in Clause 45 of IEEE802.3 (Describe “eMDIO” in this document)

Management frame format of MDIO (Clause 22)

The below table lists the management frame formats of MDIO.

Access type		MII and RMII management frame
	Item	PRE	ST	OP	PHYAD	REGAD	TA	DATA	IDLE
	Number of bits	32	2	2	5	5	2	16	1
Read		1...1	01	10	00001	RRRRR	Z0	DDDDDDDDDDDDDDDD	Z
Write		1...1	01	01	00001	RRRRR	10	DDDDDDDDDDDDDDDD	Z

Note: - PRE (preamble): Send 32 consecutive 1s.; - ST (start of frame): Send 01b.; - OP (operation code): Send 10b for read or 01b for write.; - PHYAD (PHY address): Up to 32 PHY-LSIs can be connected to one MAC. PHY-LSIs are selected with these 5 bits. When the PHY-LSI address is 1, send 00001b.; - REGAD (register address): One register is selected from up to 32 registers in the PHY-LSI. When the register address is 1, send 00001b.; - TA (turnaround): Use 2-bit turnaround time to avoid contention between the register address and data during a read operation.; Send 10b during a write operation. Release the bus for 1 bit during a read operation (Z is output).; (This is indicated as Z0 because 0 is output from the PHY-LSI on the next clock cycle.); - DATA (data): 16-bit data. Sequentially send or receive starting from the MSB.; - IDLE (IDLE condition): Wait time before inputting the next MII or RMII management format. Release the bus during a write; operation (Z is output). No control is required, because a bus was already released during a read operation.

Management frame format of eMDIO (Clause 45)

The below table lists the management frame formats of eMDIO(Clause 45).

Access type		MII and RMII management frame
	Item	PRE	ST	OP	PRTAD	DEVAD	TA	DATA	IDLE
	Number of bits	32	2	2	5	5	2	16	1
Address		1...1	00	00	PPPPP	EEEEE	10	AAAAAAAAAAAAAAAA	Z
Write		1...1	00	01	PPPPP	EEEEE	10	DDDDDDDDDDDDDDDD	Z
Read		1...1	00	11	PPPPP	EEEEE	Z0	DDDDDDDDDDDDDDDD	Z
Read Increment		1...1	00	10	PPPPP	EEEEE	Z0	DDDDDDDDDDDDDDDD	Z

Note: - PRE (preamble): Send 32 consecutive 1s.; - ST (start of frame): Send 00b.; - OP (operation code): Send 00b for register address, 10b for read operation, 11b for write operation, or 10b for post-read-increment-address operation.; - PRTAD (port address): Up to 32 PHY-LSIs can be connected to one MAC. PHY-LSIs are selected with these 5 bits port address. When the port address is 1, send 00001b.; - DEVAD (device address): Up to 32 MDIO Manageable Devices(MMD) are contained in a PHY-LSI. MMD are selected with these 5 bits device address.; - TA (turnaround): Use 2-bit turnaround time to avoid contention between the register address and data during a read operation.; Send 10b during a write operation. Release the bus for 1 bit during a read operation (Z is output).; (This is indicated as Z0 because 0 is output from the PHY-LSI on the next clock cycle.); - DATA (data): 16-bit data. Sequentially send or receive starting from the MSB.; - IDLE (IDLE condition): Wait time before inputting the next MII or RMII management format. Release the bus during a write; operation (Z is output). No control is required, because a bus was already released during a read operation.

Limitations

The r_rmac_phy module may need to be customized for PHY devices other than the ones currently supported. Use the existing code as a starting point for creating a custom implementation. Supported PHY devices are as follows.
- KSZ8091RNB
- KSZ8041
- DP83620
- ICS1894
- GPY111

Examples

RMAC PHY Basic Example

This is a basic example of minimal use of the RMAC PHY in an application.

void rmac_phy_basic_example (void)
{
    fsp_err_t err = FSP_SUCCESS;
    g_rmac_phy0_ctrl.open   = 0U;
    g_rmac_phy0_cfg.channel = 0;
    /* Initializes the module. */
    err = R_RMAC_PHY_Open(&g_rmac_phy0_ctrl, &g_rmac_phy0_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
    /* Start auto negotiation. */
    err = R_RMAC_PHY_StartAutoNegotiate(&g_rmac_phy0_ctrl);
    assert(FSP_SUCCESS == err);
    /* Polling until link is established. */
    while (FSP_SUCCESS != R_RMAC_PHY_LinkStatusGet(&g_rmac_phy0_ctrl))
    {
        /* Do nothing */
    }
    /* Get link partner ability from phy interface. */
    err = R_RMAC_PHY_LinkPartnerAbilityGet(&g_rmac_phy0_ctrl,
                                           &g_rmac_phy0_line_speed_duplex,
                                           &g_rmac_phy0_local_pause,
                                           &g_rmac_phy0_partner_pause);
    assert(FSP_SUCCESS == err);
    /* Check current link status. */
    err = R_RMAC_PHY_LinkStatusGet(&g_rmac_phy0_ctrl);
    assert(FSP_SUCCESS == err);
}

Data Structures
struct	rmac_phy_instance_ctrl_t

struct	rmac_phy_extended_cfg_t

Enumerations
enum	rmac_phy_interface_status_t

enum	rmac_phy_frame_format_t

Data Structure Documentation

◆ rmac_phy_instance_ctrl_t

struct rmac_phy_instance_ctrl_t

RMAC PHY control block. DO NOT INITIALIZE. Initialization occurs when ether_phy_api_t::open is called.

Data Fields
uint32_t	open	Used to determine if the channel is configured.
ether_phy_cfg_t const *	p_ether_phy_cfg	Pointer to initial configurations.
R_RMAC0_Type *	p_reg_rmac	Pointer to RMAC peripheral registers.
uint32_t	local_advertise	Capabilities bitmap for local advertising.
rmac_phy_interface_status_t	interface_status	Initialized status of ETHER PHY interface.
uint8_t	phy_lsi_cfg_index	Index of the PHY LSI that is currently the target of operation.

◆ rmac_phy_extended_cfg_t

struct rmac_phy_extended_cfg_t

RMAC PHY extended configuration.

Data Fields
void(*	p_target_init )(rmac_phy_instance_ctrl_t *p_instance_ctrl)
	Pointer to callback that is called to initialize the target.

bool(*	p_target_link_partner_ability_get )(rmac_phy_instance_ctrl_t *p_instance_ctrl, uint32_t line_speed_duplex)
	Pointer to callback that is called to get the link partner ability.

rmac_phy_frame_format_t	frame_format
	Whether the management frame format is MDIO or eMDIO.

uint32_t	mdc_clock_rate
	MDC frequency division.

uint8_t	mdio_hold_time
	MDIO hold time adjustment.

uint8_t	mdio_capture_time
	MDIO capture time adjustment.

ether_phy_lsi_cfg_t const *	p_phy_lsi_cfg_list [BSP_FEATURE_ETHER_MAX_CHANNELS]
	Pointer list of PHY LSI configurations.

uint8_t	default_phy_lsi_cfg_index
	Index of the default PHY LSI condiguration.

Enumeration Type Documentation

◆ rmac_phy_interface_status_t

enum rmac_phy_interface_status_t

Initialization state for read/write

Enumerator
RMAC_PHY_INTERFACE_STATUS_UNINITIALIZED	ETHER PHY interface is uninitialized.
RMAC_PHY_INTERFACE_STATUS_INITIALIZED	ETHER PHY interface is initialized.

◆ rmac_phy_frame_format_t

enum rmac_phy_frame_format_t

Enumerator
RMAC_PHY_FRAME_FORMAT_MDIO	Normal management frame format defined in clause 22.
RMAC_PHY_FRAME_FORMAT_EMDIO	Extension management frame format defined in clause 45.

Function Documentation

◆ R_RMAC_PHY_Open()

fsp_err_t R_RMAC_PHY_Open	(	ether_phy_ctrl_t *const	p_ctrl,
		ether_phy_cfg_t const *const	p_cfg
	)

Resets Ethernet PHY device. Implements ether_phy_api_t::open.

Return values

FSP_SUCCESS	Channel opened successfully.
FSP_ERR_ASSERTION	Pointer to RMAC_PHY control block is NULL.
FSP_ERR_ALREADY_OPEN	Control block has already been opened or channel is being used by another instance. Call close() then open() to reconfigure.
FSP_ERR_INVALID_CHANNEL	Invalid channel number is given.
FSP_ERR_INVALID_POINTER	Pointer to p_cfg is NULL.
FSP_ERR_INVALID_MODE	Function is called when not in CONFIG mode.

◆ R_RMAC_PHY_Close()

fsp_err_t R_RMAC_PHY_Close ( ether_phy_ctrl_t *const p_ctrl )

Close Ethernet PHY device. Implements ether_phy_api_t::close.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to RMAC_PHY control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened
FSP_ERR_INVALID_MODE	Function is called when not in DISABLE mode.

◆ R_RMAC_PHY_StartAutoNegotiate()

fsp_err_t R_RMAC_PHY_StartAutoNegotiate ( ether_phy_ctrl_t *const p_ctrl )

Starts auto-negotiate. Implements ether_phy_api_t::startAutoNegotiate.

Return values

FSP_SUCCESS	RMAC_PHY successfully starts auto-negotiate.
FSP_ERR_ASSERTION	Pointer to RMAC_PHY control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened
FSP_ERR_NOT_INITIALIZED	The control block has not been initialized
FSP_ERR_INVALID_MODE	Function is called when not in OPERATION mode.

◆ R_RMAC_PHY_LinkPartnerAbilityGet()

fsp_err_t R_RMAC_PHY_LinkPartnerAbilityGet	(	ether_phy_ctrl_t *const	p_ctrl,
		uint32_t *const	p_line_speed_duplex,
		uint32_t *const	p_local_pause,
		uint32_t *const	p_partner_pause
	)

Reports the other side's physical capability. Implements ether_phy_api_t::linkPartnerAbilityGet.

Return values

FSP_SUCCESS	RMAC_PHY successfully get link partner ability.
FSP_ERR_ASSERTION	Pointer to RMAC_PHY control block is NULL.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened
FSP_ERR_ETHER_PHY_ERROR_LINK	PHY-LSI is not link up.
FSP_ERR_ETHER_PHY_NOT_READY	The auto-negotiation isn't completed
FSP_ERR_NOT_INITIALIZED	The control block has not been initialized
FSP_ERR_INVALID_MODE	Function is called when not in OPERATION mode.

◆ R_RMAC_PHY_LinkStatusGet()

fsp_err_t R_RMAC_PHY_LinkStatusGet ( ether_phy_ctrl_t *const p_ctrl )

Returns the status of the physical link. Implements ether_phy_api_t::linkStatusGet.

Return values

FSP_SUCCESS	RMAC_PHY successfully get link partner ability.
FSP_ERR_ASSERTION	Pointer to RMAC_PHY control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened
FSP_ERR_ETHER_PHY_ERROR_LINK	PHY-LSI is not link up.
FSP_ERR_NOT_INITIALIZED	The control block has not been initialized
FSP_ERR_INVALID_MODE	Function is called when not in OPERATION mode.

◆ R_RMAC_PHY_ChipInit()

fsp_err_t R_RMAC_PHY_ChipInit	(	ether_phy_ctrl_t *const	p_ctrl,
		ether_phy_cfg_t const *const	p_cfg
	)

Initialize Ethernet PHY device. Implements ether_phy_api_t::chipInit.

Return values

FSP_SUCCESS	PHY device initialized successfully.
FSP_ERR_ASSERTION	Pointer to RMAC_PHY control block or configuration structure is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_TIMEOUT	PHY-LSI Reset wait timeout.
FSP_ERR_INVALID_MODE	Function is called when not in OPERATION mode.

◆ R_RMAC_PHY_Read()

fsp_err_t R_RMAC_PHY_Read	(	ether_phy_ctrl_t *const	p_ctrl,
		uint32_t	reg_addr,
		uint32_t *const	p_data
	)

Read data from register of PHY-LSI . Implements ether_phy_api_t::read.

Return values

FSP_SUCCESS	RMAC_PHY successfully read data.
FSP_ERR_ASSERTION	Pointer to RMAC_PHY control block is NULL.
FSP_ERR_INVALID_POINTER	Pointer to read buffer is NULL.
FSP_ERR_INVALID_ARGUMENT	Address is not a valid size
FSP_ERR_NOT_INITIALIZED	The control block has not been initialized
FSP_ERR_INVALID_MODE	Function is called when not in OPERATION mode.

◆ R_RMAC_PHY_Write()

fsp_err_t R_RMAC_PHY_Write	(	ether_phy_ctrl_t *const	p_ctrl,
		uint32_t	reg_addr,
		uint32_t	data
	)

Write data to register of PHY-LSI . Implements ether_phy_api_t::write.

Return values

FSP_SUCCESS	RMAC_PHY successfully write data.
FSP_ERR_ASSERTION	Pointer to RMAC_PHY control block is NULL.
FSP_ERR_INVALID_ARGUMENT	Address or data is not a valid size
FSP_ERR_NOT_INITIALIZED	The control block has not been initialized
FSP_ERR_INVALID_MODE	Function is called when not in OPERATION mode.

◆ R_RMAC_PHY_ChipSelect()

fsp_err_t R_RMAC_PHY_ChipSelect	(	ether_phy_ctrl_t *const	p_ctrl,
		uint8_t	port
	)

Update the target PHY LSI of this driver.

Return values

FSP_SUCCESS	PHY device initialized successfully.
FSP_ERR_ASSERTION	Pointer to RMAC_PHY control block or configuration structure is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid PHY LSI is selected.

Functions

Detailed Description

Overview

Features

Configuration

Build Time Configurations for r_rmac_phy

Configurations for Networking > Ethernet (r_rmac_phy)

Usage Notes

Accessing the Registers in PHY-LSI

Management frame format of MDIO (Clause 22)

Management frame format of eMDIO (Clause 45)

Limitations

Examples

RMAC PHY Basic Example

Data Structures

Enumerations

Data Structure Documentation

◆ rmac_phy_instance_ctrl_t

◆ rmac_phy_extended_cfg_t

Data Fields

Enumeration Type Documentation

◆ rmac_phy_interface_status_t

◆ rmac_phy_frame_format_t

Function Documentation

◆ R_RMAC_PHY_Open()

◆ R_RMAC_PHY_Close()

◆ R_RMAC_PHY_StartAutoNegotiate()

◆ R_RMAC_PHY_LinkPartnerAbilityGet()

◆ R_RMAC_PHY_LinkStatusGet()

◆ R_RMAC_PHY_ChipInit()

◆ R_RMAC_PHY_Read()

◆ R_RMAC_PHY_Write()

◆ R_RMAC_PHY_ChipSelect()