The Delta-Sigma Modulator interface (DSMIF) functions similarly to a normal ADC, however, instead of sampling an analog signal directly, DSMIF samples a PDM signal that is generated by an externally connected 1-bit Delta-Sigma Modulator.
Every instance of the DSMIF peripheral has 3 separate channels that can sample independent PDM signals. Each channel has a pair of sinc filters. One sinc filter is used for normal measurements, and the other sinc filter is used for detecting error conditions. The sinc filter configuration will determine the sample resolution, and the final sample rate for each channel. There are three primary configuration settings for the sinc filters:
This module can be added to the Stacks tab via New Stack > Analog > DSMIF (r_dsmif).
| Configuration | Options | Default | Description |
| General > Name | Name must be a valid C symbol | g_dsmif0 | Module name |
| General > Clock Selection |
| PCLKA | Select the DSMIF Core Clock. |
| General > Unit |
| Unit 0 | DSMIF unit number. |
| General > Alignment |
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Left Justified
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Right Justified
| Right Justified | Select if the conversion result is aligned to the left or right of the channel data registers. |
| General > Callback | Name must be a valid C symbol | NULL | Callback for handling DSMIF interrupts. |
| Overcurrent Sum Error > Upper Limit > Detection |
| Disabled | Enable or disable overcurrent sum error upper limit detection. |
| Overcurrent Sum Error > Upper Limit > Threshold | Must be an integer in the range [0,0x3FFFF]. | 0 | Overcurrent sum error detection upper limit. |
| Overcurrent Sum Error > Lower Limit > Detection |
| Disabled | Enable or disable overcurrent sum error lower limit detection. |
| Overcurrent Sum Error > Lower Limit > Threshold | Must be an integer in the range [0,0x3FFFF]. | 0 | Overcurrent sum error detection lower limit. |
| Overcurrent Sum Error > Channel Selection |
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Channels 0, 1 and 2
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Channels 0 and 1
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Channel 0
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Channel 1
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Channel 2
| Channels 0, 1 and 2 | Specify the channel(s) used for detecting overcurrent sum errors. |
| Interrupts > Channel Synchronization |
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Channels are not synchronized
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Channels 0 and 1 are synchronized
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Channels 0, 1 and 2 are synchronized
| Channels are not synchronized | Select the channel synchronization mode. Two or three channels that share the same configuration may optionaly configure a common interrupts instead of channel specific interrupts. |
| Interrupts > Common Data Update Interrupt Priority (CDUPD_COM) | MCU Specific Options | | The Common Data Update Interrupt occurs when a conversion is completed on all synchronized channels. |
| Interrupts > Common Capture A Data Update Interrupt Priority (CDACUPD_COM) | MCU Specific Options | | The Common Capture A Interrupt occurs when a Capture A conversion is completed on all synchronized channels. |
| Interrupts > Common Capture B Data Update Interrupt Priority (CDBCUPD_COM) | MCU Specific Options | | The Common Capture B Interrupt occurs when a Capture B conversion is completed on all synchronized channels. |
| Interrupts > Error Interrupt Priority | MCU Specific Options | | The Error Interrupt occurs when a short-cicuit, overcurrent, overcurrent sum, or window notification error occurs on any channel. |
| Configuration | Options | Default | Description |
| General > Name | Name must be a valid C symbol | g_dsmif_channel0 | Module name |
| Clock > Clock Direction |
| Slave Mode | Select the conversion clock mode for the DSMIF channel. In master mode the clock is output from the DSMIF channel. In slave mode the clock is input to the DSMIF channel. |
| Clock > Clock Edge |
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Negative Edge
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Positive Edge
| Negative Edge | Select the sampling edge of DSMCLKn for this channel. |
| Clock > CKDIV Setting (Master Mode Only) | Must be an integer in the range [2,63]. | 2 | Set the A/D conversion clock division ratio. The clock division ratio is equal to 2 x (CKDIV + 1). This setting is only used in master mode. |
| Clock > DSMCLK Frequency (Slave Mode Only) | Must be an integer in the range [0,25000000]. | 25000000 | If slave mode is selected, then manually enter the DSMCLK frequency. This setting is used to calculate the settling time of the DSMIF sinc filters. |
| Filter > Filter Order |
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First Order
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Second Order
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Third Order
| Third Order | Select 1st, 2nd, or 3rd order sinc filter for current data. |
| Filter > Decimation Count | Must be an integer in the range [4,256]. | 256 | Decimation ratio of the current data sinc filter. |
| Trigger > Filter Initialization > Trigger |
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No Trigger
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Trigger 0 (ELC_DSMIFm_CNT0)
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Trigger 1 (ELC_DSMIFm_CNT1)
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Trigger 2 (ELC_DSMIFm_CNT2)
| No Trigger | Select filter initialization trigger. The filter initialization trigger resets the sinc filter's decimation clock via ELC event. |
| Trigger > Filter Initialization > Edge |
| Positive | Select either a positive or negative edge for the filter initialization trigger. |
| Trigger > Capture Trigger A |
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No Trigger
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Trigger 0 (ELC_DSMIFm_CAP0)
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Trigger 1 (ELC_DSMIFm_CAP1)
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Trigger 2 (ELC_DSMIFm_CAP2)
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Trigger 3 (ELC_DSMIFm_CAP3)
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Trigger 4 (ELC_DSMIFm_CAP4)
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Trigger 5 (ELC_DSMIFm_CAP5)
| No Trigger | Current capture trigger A selection. |
| Trigger > Capture Trigger B |
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No Trigger
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Trigger 0 (ELC_DSMIFm_CAP0)
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Trigger 1 (ELC_DSMIFm_CAP1)
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Trigger 2 (ELC_DSMIFm_CAP2)
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Trigger 3 (ELC_DSMIFm_CAP3)
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Trigger 4 (ELC_DSMIFm_CAP4)
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Trigger 5 (ELC_DSMIFm_CAP5)
| No Trigger | Current capture trigger B selection. |
| Error Detection > Filter > Filter Order |
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First Order
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Second Order
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Third Order
| Third Order | Select 1st, 2nd, or 3rd order sinc filter for overcurrent detection. |
| Error Detection > Filter > Decimation Count | Must be an integer in the range [4,256]. | 256 | Decimation ratio of the overcurrent detection filter. |
| Error Detection > Overcurrent Detection 0 > Upper Limit > Detection |
| Disabled | Enable or disable overcurrent 0 upper limit. |
| Error Detection > Overcurrent Detection 0 > Upper Limit > Threshold | Must be an integer in the range [0,65535]. | 0xFFFF | Configure the overcurrent 0 upper limit. Valid settings are in the range [0,65535]. |
| Error Detection > Overcurrent Detection 0 > Lower Limit > Detection |
| Disabled | Enable or disable overcurrent 0 lower limit. |
| Error Detection > Overcurrent Detection 0 > Lower Limit > Threshold | Must be an integer in the range [0,65535]. | 0 | Configure the overcurrent 0 lower limit. Valid settings are in the range [0,65535]. |
| Error Detection > Overcurrent Detection 1 > Upper Limit > Detection |
| Disabled | Enable or disable overcurrent 1 upper limit. |
| Error Detection > Overcurrent Detection 1 > Upper Limit > Threshold | Must be an integer in the range [0,65535]. | 0xFFFF | Configure the overcurrent 1 upper limit. Valid settings are in the range [0,65535]. |
| Error Detection > Overcurrent Detection 1 > Lower Limit > Detection |
| Disabled | Enable or disable overcurrent 1 lower limit. |
| Error Detection > Overcurrent Detection 1 > Lower Limit > Threshold | Must be an integer in the range [0,65535]. | 0 | Configure the overcurrent 1 lower limit. Valid settings are in the range [0,65535]. |
| Error Detection > Overcurrent Detection 2 > Upper Limit > Detection |
| Disabled | Enable or disable overcurrent 2 upper limit. |
| Error Detection > Overcurrent Detection 2 > Upper Limit > Threshold | Must be an integer in the range [0,65535]. | 0xFFFF | Configure the overcurrent 2 upper limit. Valid settings are in the range [0,65535]. |
| Error Detection > Overcurrent Detection 2 > Lower Limit > Detection |
| Disabled | Enable or disable overcurrent 2 lower limit. |
| Error Detection > Overcurrent Detection 2 > Lower Limit > Threshold | Must be an integer in the range [0,65535]. | 0 | Configure the overcurrent 2 lower limit. Valid settings are in the range [0,65535]. |
| Error Detection > Overcurrent Window Notifcation 0 > Notification |
| Disabled | Enable or disable overcurrent window notification 0. |
| Error Detection > Overcurrent Window Notifcation 0 > Mode |
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Overcurrent Data < Lower Limit 0 or Upper Limit 0 < Overcurrent Data
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Lower Limit 0 <= Overcurrent Data <= Upper Limit 0
| Overcurrent Data < Lower Limit 0 or Upper Limit 0 < Overcurrent Data | Select overcurrent window notification 0 mode. |
| Error Detection > Overcurrent Window Notifcation 1 > Notification |
| Disabled | Enable or disable overcurrent window notification 1. |
| Error Detection > Overcurrent Window Notifcation 1 > Mode |
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Overcurrent Data < Lower Limit 1 or Upper Limit 1 < Overcurrent Data
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Lower Limit 1 <= Overcurrent Data <= Upper Limit 1
| Overcurrent Data < Lower Limit 1 or Upper Limit 1 < Overcurrent Data | Select overcurrent window notification 1 mode. |
| Error Detection > Overcurrent Window Notifcation 2 > Notification |
| Disabled | Enable or disable overcurrent window notification 2. |
| Error Detection > Overcurrent Window Notifcation 2 > Mode |
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Overcurrent Data < Lower Limit 2 or Upper Limit 2 < Overcurrent Data
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Lower Limit 2 <= Overcurrent Data <= Upper Limit 2
| Overcurrent Data < Lower Limit 2 or Upper Limit 2 < Overcurrent Data | Select overcurrent window notification 2 mode. |
| Error Detection > Overcurrent Window Notifcation 3 > Notification |
| Disabled | Enable or disable overcurrent window notification 3. |
| Error Detection > Overcurrent Window Notifcation 3 > Mode | Refer to the RX Configuration tool for available options. | Window notification 0 | Select overcurrent window notification 3 mode. |
| Error Detection > Short Circuit > Detection |
| Disabled | Enable or disable short circuit detection. |
| Error Detection > Short Circuit > Low Count | Must be an integer in the range [0,8191]. | 0 | Short circuit detection low count. |
| Error Detection > Short Circuit > High Count | Must be an integer in the range [0,8191]. | 0 | Short circuit detection high count. |
| Interrupts > Current Data Update Interrupt Priority (CDUPD) | MCU Specific Options | | The Current Data Update Interrupt occurs when a conversion is completed. |
| Interrupts > Capture A Data Update Interrupt Priority (CDAUPD) | MCU Specific Options | | The Capture A Data Update Interrupt occurs when a capture A conversion is completed. |
| Interrupts > Capture B Data Update Interrupt Priority (CDBUPD) | MCU Specific Options | | The Capture B Data Update Interrupt occurs when a capture B conversion is completed. |
When synchronizing channels, each channel must use the same 'Clock', 'Filter', and 'Trigger' configuration settings. For convenience, channel configurations can be reused between channels of a DSMIF instance instead of creating new channel configurations for each channel.
The filter settling time is the time required for the filter results to be valid after the DSMIF channels have been started. The settling time is determined by the DSMCLK period, Decimation Ratio, Filter Order, DSMIF Core Clock period, and Peripheral Clock period.
The following macros are generated by the tooling in order to assist with determining the required settling time:
If the error interrupt is enabled, the following configured error flags will generate an interrupt request:
This is a basic example of minimal use of the ADC in an application.
This is a basic example of how to read the following types of data by OR'ing the appropriate channel mask: