Functions
fsp_err_t	R_FSP_VersionGet (fsp_pack_version_t *const p_version)

void	Reset_Handler_NS (void)

void	Default_Handler (void)

void	NMI_Handler_NS (void)

void	SVC_Handler_NS (void)
	SVC Handler.

void	PendSV_Handler_NS (void)
	PendSV Exception handler.

void	Reset_Handler_S (void)

void	Default_Handler_S (void)

void	NMI_Handler_S (void)

void	SecureFault_Handler (void)

void	SystemInit (void)

void	R_BSP_WarmStart (bsp_warm_start_event_t event)

void	SystemInit_S (void)

void	Warm_Reset_S (void)

void	Entry_Function_S (void)

void	XSPI_Boot_Entry (void)

uint32_t	R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)

fsp_err_t	R_BSP_ClockSelectorSet (fsp_priv_clock_selector_t selector, uint32_t clock_sel)

fsp_err_t	R_BSP_ClockDividerSet (fsp_priv_clock_divider_t divider, uint32_t clock_div)

__STATIC_INLINE IRQn_Type	R_FSP_CurrentIrqGet (void)

__STATIC_INLINE bsp_unique_id_t const *	R_BSP_UniqueIdGet ()

void	R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units)

fsp_err_t	R_BSP_GroupIrqWrite (bsp_grp_irq_t irq, void(*p_callback)(bsp_grp_irq_t irq))

void	R_BSP_IrqStatusClear (IRQn_Type irq)

void	R_BSP_IrqClearPending (IRQn_Type irq)

void	R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void *p_context)

void	R_BSP_IrqEnableNoClear (IRQn_Type const irq)

void	R_BSP_IrqEnable (IRQn_Type const irq)

void	R_BSP_IrqDisable (IRQn_Type const irq)

void	R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void *p_context)

uint32_t	R_BSP_SlaveAddressConversion (uint32_t original_address)

void	R_BSP_SystemResetStatusGet (void)

void	R_BSP_NonSecureEnter (void)

uint32_t	R_BSP_IntStatusControlGet (fsp_ip_t ip, uint8_t channel, IRQn_Type irq)

fsp_err_t	R_BSP_IntStatusControlClear (fsp_ip_t ip, uint8_t channel, IRQn_Type irq, uint32_t int_source)

Detailed Description

The BSP is responsible for getting the MPU from reset to the user's application. Before reaching the user's application, the BSP sets up the stacks, heap, clocks, interrupts, and C runtime environment.

BSP Features
BSP Clock Configuration
System Interrupts
Group Interrupts
External and Peripheral Interrupts
Error Logging
BSP Weak Symbols
Warm Start Callbacks
C Runtime Initialization
Register Protection
ID Codes
Software Delay
Octal-SPI Clock Update
Board Specific Features
Configuration

Overview

BSP Features

BSP Clock Configuration

All system clocks are set up during BSP initialization based on the settings in bsp_clock_cfg.h. These settings are derived from clock configuration information provided from the Configuration editor Clocks tab.

Clock configuration is performed prior to initializing the C runtime environment to speed up the startup process.
The BSP implements the required delays to allow the selected clock to stabilize.
The BSP will configure the CMSIS SystemCoreClock variable after clock initialization with the current system clock frequency.

System Interrupts

As RZ MPUs are based on the Cortex-M ARM architecture, the NVIC Nested Vectored Interrupt Controller (NVIC) handles exceptions and interrupt configuration, prioritization and interrupt masking. In the ARM architecture, the NVIC handles exceptions. Some exceptions are known as System Exceptions. System exceptions are statically located at the "top" of the vector table and occupy vector numbers 1 to 15. Vector zero is reserved for the MSP Main Stack Pointer (MSP). The remaining 15 system exceptions are shown below:

Reset
NMI
Hard Fault Handler
MPU Fault Handler
Bus Fault Handler
Usage Fault Handler
Reserved
Reserved
Reserved
Reserved
SVCall Handler
Debug Monitor Handler
Reserved
PendSV Handler
SysTick Handler

NMI and Hard Fault exceptions are enabled out of reset and have fixed priorities. Other exceptions have configurable priorities and some can be disabled.

Note1: In RZ MPU, NMI occurs as an external interrupt (SPI No.0) instead of Coretex-M Core's System Interrupt. Note2: RZ MPU does not support MPU (Memory Protection Unit).

Group Interrupts

Group Interrupts are not supported in this device.

External and Peripheral Interrupts

RZ MPU supports 480 interrupts by NVIC, and any factor can be registered in the vector table from the Interrupts tab of the Configuration editor.

BSP Weak Symbols

You might wonder how the BSP is able to place ISR addresses in the NVIC table without the user having explicitly defined one. All that is required by the BSP is that the interrupt event be given a priority.

This is accomplished through the use of the 'weak' attribute. The weak attribute causes the declaration to be emitted as a weak symbol rather than a global. A weak symbol is one that can be overridden by an accompanying strong reference with the same name. When the BSP declares a function as weak, user code can define the same function and it will be used in place of the BSP function. By defining all possible interrupt sources as weak, the vector table can be built at compile time and any user declarations (strong references) will be used at runtime.

Weak symbols are supported for ELF targets and also for a.out targets when using the GNU assembler and linker.

Note that in CMSIS system.c, there is also a weak definition (and a function body) for the Warm Start callback function R_BSP_WarmStart(). Because this function is defined in the same file as the weak declaration, it will be called as the 'default' implementation. The function may be overridden by the user by copying the body into their user application and modifying it as necessary. The linker identifies this as the 'strong' reference and uses it.

Warm Start Callbacks

As the BSP is in the process of bringing up the board out of reset, there are three points where the user can request a callback. These are defined as the 'Pre Clock Init', 'Post Clock Init' and 'Post C' warm start callbacks.

As described above, this function is already weakly defined as R_BSP_WarmStart(), so it is a simple matter of redefining the function or copying the existing body from CMSIS system.c into the application code to get a callback. R_BSP_WarmStart() takes an event parameter of type bsp_warm_start_event_t which describes the type of warm start callback being made.

This function is not enabled/disabled and is always called for both events as part of the BSP startup. Therefore it needs a function body, which will not be called if the user is overriding it. The function body is located in system.c. To use this function just copy this function into your own code and modify it to meet your needs.

C Runtime Initialization

This BSP configuration allows the user to skip the FSP C runtime initialization code by setting the "C Runtime Initialization" to "Disabled" on the BSP tab of the Configuration editor. Disabling this option is useful in cases where a non-standard linker script is being used or other modifications to the runtime initialization are desired. If this macro is disabled, the user must use the 'Post Clock Init' event from the warm start (described above) to run their own runtime initialization code.

Heap Allocation

The relatively low amount of on-chip SRAM available and lack of memory protection in an MPU means that heap use must be very carefully controlled to avoid memory leaks, overruns and attempted overallocation. Further, many RTOSes provide their own dynamic memory allocation system. For these reasons the default heap size is set at 0 bytes, effectively disabling dynamic memory. If it is required for an application setting a positive value to the "Heap size (bytes)" option in the Common configurations on the BSP tab will allocate a heap.

Note: When using printf/sprintf (and other variants) to output floating point numbers a heap is required. A minimum size of 0x1000 (4096) bytes is recommended when starting development in this case.

Error Logging

When error logging is enabled, the error logging function can be redefined on the command line by defining FSP_ERROR_LOG(err) to the desired function call. The default function implementation is FSP_ERROR_LOG(err)=fsp_error_log(err, FILE, LINE). This implementation uses the predefined macros FILE and LINE to help identify the location where the error occurred. Removing the line from the function call can reduce code size when error logging is enabled. Some compilers may support other predefined macros like FUNCTION, which could be helpful for customizing the error logger.

Register Protection

This feature is not supported on this device.

ID Codes

This feature is not supported on this device.

Software Delay

Implements a blocking software delay. A delay can be specified in microseconds, milliseconds or seconds. The delay is implemented based on the system clock rate.

    /* Delay at least 1 second. Depending on the number of wait states required for the region of memory
     * that the software_delay_loop has been linked in this could take longer. The default is 4 cycles per loop.
     * This can be modified by redefining DELAY_LOOP_CYCLES. BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS,
     * and BSP_DELAY_UNITS_MICROSECONDS can all be used with R_BSP_SoftwareDelay. */
    R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_SECONDS);

Critical Section Macros

Implements a critical section. Some MPUs (MPUs with the BASEPRI register) support allowing high priority interrupts to execute during critical sections. On these MPUs, interrupts with priority less than or equal to BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION are not serviced in critical sections. Interrupts with higher priority than BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION still execute in critical sections.

    FSP_CRITICAL_SECTION_DEFINE;
    /* Store the current interrupt posture. */
    FSP_CRITICAL_SECTION_ENTER;
    /* Interrupts cannot run in this section unless their priority is less than BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION. */
    /* Restore saved interrupt posture. */
    FSP_CRITICAL_SECTION_EXIT;

OctaClock Update

This feature is not supported on this device.

Board Specific Features

The BSP will call the board's initialization function (bsp_init) which can initialize board specific features.

Configuration

The BSP is heavily data driven with most features and functionality being configured based on the content from configuration files. Configuration files represent the settings specified by the user and are generated when the project is built and/or when the Generate Project Content button is clicked in the Configuration editor.

Build Time Configurations for fsp_common

The following build time configurations are defined in fsp_cfg/bsp/bsp_cfg.h:

Configuration	Options	Default	Description
Secure stack size (bytes)	Value must be an integer multiple of 8 and between 8 and 0xFFFFFFFF	0x200	Set the size of the secure program stack. NOTE: This entry is for the secure stack.
Main stack size (bytes)	Value must be an integer multiple of 8 and between 8 and 0xFFFFFFFF	0x400	Set the size of the main program stack. NOTE: This entry is for the main stack. When using an RTOS, thread stacks can be configured in the properties for each thread.
Heap size (bytes)	Value must be 0 or an integer multiple of 8 between 8 and 0xFFFFFFFF.	0	The main heap is disabled by default. Set the heap size to a positive integer divisible by 8 to enable it. A minimum of 4K (0x1000) is recommended if standard library functions are to be used.
MPU Vcc (mV)	Value must between 0 and 5500 (5.5V)	3300	Some peripherals require different settings based on the supplied voltage. Entering Vcc here (in mV) allows the relevant driver modules to configure the associated peripherals accordingly.
Parameter checking	Enabled Disabled	Disabled	When enabled, parameter checking for the BSP is turned on. In addition, any modules whose parameter checking configuration is set to 'Default (BSP)' will perform parameter checking as well.
Assert Failures	Return FSP_ERR_ASSERTION Call fsp_error_log then Return FSP_ERR_ASSERTION Use assert() to Halt Execution Disable checks that would return FSP_ERR_ASSERTION	Return FSP_ERR_ASSERTION	Define the behavior of the FSP_ASSERT() macro.
PFS Protect	Disabled Enabled	Enabled	Keep the PFS registers locked when they are not being modified. If disabled they will be unlocked during startup.
C Runtime Initialization	Enabled Disabled	Enabled	Select if the C runtime initialization in the BSP is to be used. If disabled, use the BSP_WARM_START_POST_CLOCK event to run user defined equivalent.
Early BSP Initialization	Enabled Disabled	Disabled	Enable this option to use BSP functions before C runtime initialization (BSP_WARM_START_RESET or BSP_WARM_START_POST_CLOCK).

Modules
	RZG2L

	RZG2UL

	RZG3E

	RZG3L

	RZG3S

Macros
#define	R_BSP_MODULE_START(ip, ch)

#define	R_BSP_MODULE_STOP(ip, ch)

#define	BSP_IRQ_DISABLED

#define	FSP_LOG_PRINT(X)

#define	FSP_RETURN(err)

#define	FSP_ERROR_LOG(err)

#define	FSP_ASSERT(a)

#define	FSP_ERROR_RETURN(a, err)

#define	FSP_CRITICAL_SECTION_ENTER

#define	FSP_CRITICAL_SECTION_EXIT

#define	FSP_INVALID_VECTOR

#define	BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x)

#define	BSP_STACK_ALIGNMENT

#define	R_BSP_MSTP_START(ip, channel)

#define	R_BSP_MSTP_STOP(ip, channel)

Enumerations
enum	fsp_ip_t

enum	bsp_warm_start_event_t

enum	bsp_delay_units_t

enum	bsp_grp_irq_t

enum	intsel_cause_t

Variables
uint32_t SystemCoreClock	BSP_SECTION_EARLY_INIT

Macro Definition Documentation

◆ R_BSP_MODULE_START

#define R_BSP_MODULE_START	(	ip,
		ch
	)

Cancels the module stop state.

Parameters

ip	fsp_ip_t enum value for the module to be started
ch	The channel. Use channel 0 for modules without channels.

◆ R_BSP_MODULE_STOP

#define R_BSP_MODULE_STOP	(	ip,
		ch
	)

Enables the module stop state.

Parameters

ip	fsp_ip_t enum value for the module to be stopped
ch	The channel. Use channel 0 for modules without channels.

◆ BSP_IRQ_DISABLED

#define BSP_IRQ_DISABLED

Used to signify that an interrupt factor is not available.

◆ FSP_LOG_PRINT

#define FSP_LOG_PRINT ( X )

Macro that can be defined in order to enable logging in FSP modules.

◆ FSP_RETURN

#define FSP_RETURN ( err )

Macro to log and return error without an assertion.

◆ FSP_ERROR_LOG

#define FSP_ERROR_LOG ( err )

This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in user code and do required debugging (breakpoints, stack dump, etc) in this function.

◆ FSP_ASSERT

#define FSP_ASSERT ( a )

Default assertion calls FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP functions.

◆ FSP_ERROR_RETURN

#define FSP_ERROR_RETURN	(	a,
		err
	)

All FSP error codes are returned using this macro. Calls FSP_ERROR_LOG function if condition "a" is false. Used to identify runtime errors in FSP functions.

◆ FSP_CRITICAL_SECTION_ENTER

#define FSP_CRITICAL_SECTION_ENTER

This macro temporarily saves the current interrupt state and disables interrupts.

◆ FSP_CRITICAL_SECTION_EXIT

#define FSP_CRITICAL_SECTION_EXIT

This macro restores the previously saved interrupt state, reenabling interrupts.

◆ FSP_INVALID_VECTOR

#define FSP_INVALID_VECTOR

Used to signify that the requested IRQ vector is not defined in this system.

◆ BSP_CFG_HANDLE_UNRECOVERABLE_ERROR

#define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR ( x )

In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will alert the user of the error. The user can override this default behavior by defining their own BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro.

◆ BSP_STACK_ALIGNMENT

#define BSP_STACK_ALIGNMENT

Stacks (and heap) must be sized and aligned to an integer multiple of this number.

◆ R_BSP_MSTP_START

#define R_BSP_MSTP_START	(	ip,
		channel
	)

Cancels the module stop state.

Parameters

ip	fsp_ip_t enum value for the module to be started.
channel	The channel. Use ch 0 for modules without channels.

◆ R_BSP_MSTP_STOP

#define R_BSP_MSTP_STOP	(	ip,
		channel
	)

Enables the module stop state.

Parameters

ip	fsp_ip_t enum value for the module to be stopped.
channel	The channel. Use ch 0 for modules without channels.

Enumeration Type Documentation

◆ fsp_ip_t

enum fsp_ip_t

Available modules.

Enumerator
FSP_IP_GTM	General Timer.
FSP_IP_GPT	General PWM Timer.
FSP_IP_POEG	Port Output Enable for GPT.
FSP_IP_PORT	I/O Ports.
FSP_IP_IM33	IM33 (Interrupt controller)
FSP_IP_SCIF	Serial Communications Interface with FIFO.
FSP_IP_RIIC	I2C Bus Interface.
FSP_IP_RSPI	Renesas Serial Peripheral Interface.
FSP_IP_MHU	Message Handling Unit.
FSP_IP_DMAC	Direct Memory Access Controller.
FSP_IP_DMAC_s	Direct Memory Access Controller.
FSP_IP_SSI	Serial Sound Interface.
FSP_IP_CANFD	CANFD Interface (RS-CANFD)
FSP_IP_ADC	A/D Converter.
FSP_IP_TSU	Thermal Sensor Unit.
FSP_IP_WDT	Watchdog Timer.
FSP_IP_SCI	Serial Communications Interface.
FSP_IP_MTU3	Multi-Function Timer Pulse Unit 3.
FSP_IP_XSPI	Expanded Serial Peripheral Interface.
FSP_IP_GTM	General Timer.
FSP_IP_GPT	General PWM Timer.
FSP_IP_POEG	Port Output Enable for GPT.
FSP_IP_PORT	I/O Ports.
FSP_IP_IM33	IM33 (Interrupt controller)
FSP_IP_SCIF	Serial Communications Interface with FIFO.
FSP_IP_RIIC	I2C Bus Interface.
FSP_IP_RSPI	Renesas Serial Peripheral Interface.
FSP_IP_MHU	Message Handling Unit.
FSP_IP_DMAC	Direct Memory Access Controller.
FSP_IP_DMAC_s	Direct Memory Access Controller.
FSP_IP_SSI	Serial Sound Interface.
FSP_IP_CANFD	CANFD Interface (RS-CANFD)
FSP_IP_ADC	A/D Converter.
FSP_IP_TSU	Thermal Sensor Unit.
FSP_IP_WDT	Watchdog Timer.
FSP_IP_SCI	Serial Communications Interface.
FSP_IP_CMTW	Compare Match Timer W.
FSP_IP_XSPI	Expanded Serial Peripheral Interface.
FSP_IP_CRC	Cyclic redundancy check (CRC) operation units.
FSP_IP_I3C	I3C Bus Interface.
FSP_IP_RTC	Realtime Clock.
FSP_IP_SYC	System counter.
FSP_IP_GTM	General Timer.
FSP_IP_GPT	General PWM Timer.
FSP_IP_POEG	Port Output Enable for GPT.
FSP_IP_PORT	I/O Ports.
FSP_IP_IM33	IM33 (Interrupt controller)
FSP_IP_SCIF	Serial Communications Interface with FIFO.
FSP_IP_RIIC	I2C Bus Interface.
FSP_IP_RSPI	Renesas Serial Peripheral Interface.
FSP_IP_MHU	Message Handling Unit.
FSP_IP_DMAC	Direct Memory Access Controller.
FSP_IP_DMAC_s	Direct Memory Access Controller.
FSP_IP_SSI	Serial Sound Interface.
FSP_IP_CANFD	CANFD Interface (RS-CANFD)
FSP_IP_ADC	A/D Converter.
FSP_IP_TSU	Thermal Sensor Unit.
FSP_IP_WDT	Watchdog Timer.
FSP_IP_SCI	Serial Communications Interface.
FSP_IP_MTU3	Multi-Function Timer Pulse Unit 3.
FSP_IP_XSPI	Expanded Serial Peripheral Interface.
FSP_IP_IRQ	External interrupt from IRQ pin.
FSP_IP_TINT	External interrupt from GPIO pin.
FSP_IP_RTC	Realtime Clock.
FSP_IP_LCDC	LCD Controller.
FSP_IP_MIPI_DSI	MIPI-DSI Tx module.
FSP_IP_VBATT	Battery Backup Function.
FSP_IP_I3C	I3C Bus Interface.

◆ bsp_warm_start_event_t

enum bsp_warm_start_event_t

Different warm start entry locations in the BSP.

Enumerator
BSP_WARM_START_RESET	Called almost immediately after reset. No C runtime environment, clocks, or IRQs.
BSP_WARM_START_POST_CLOCK	Called after clock initialization. No C runtime environment or IRQs.
BSP_WARM_START_POST_C	Called after clocks and C runtime environment have been set up.

◆ bsp_delay_units_t

enum bsp_delay_units_t

Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds

Enumerator
BSP_DELAY_UNITS_SECONDS	Requested delay amount is in seconds.
BSP_DELAY_UNITS_MILLISECONDS	Requested delay amount is in milliseconds.
BSP_DELAY_UNITS_MICROSECONDS	Requested delay amount is in microseconds.

◆ bsp_grp_irq_t

enum bsp_grp_irq_t

Which interrupts can have callbacks registered.

Enumerator
BSP_GRP_IRQ_UNSUPPORTED	NMI Group IRQ are not supported in this device.

◆ intsel_cause_t

enum intsel_cause_t

Cause of Interrupt used to change the setting of the INTPMSEL register.

Enumerator
INTSEL_CAUSE_GPT_CMPE	GTCCRE compare match.
INTSEL_CAUSE_GPT_CMPF	GTCCRF compare match.
INTSEL_CAUSE_GPT_ADTRGA	GTADTRA compare match.
INTSEL_CAUSE_GPT_ADTRGB	GTADTRB compare match.
INTSEL_CAUSE_GPT_OVF	GTCNT overflow (GTPR compare match)
INTSEL_CAUSE_GPT_UNF	GTCNT underflow.
INTSEL_CAUSE_GPT_CAUSE_NUM	The number of cause of interrupt of GPT.
INTSEL_CAUSE_MTU3_TGIA	TGRA input capture/compare match.
INTSEL_CAUSE_MTU3_TGIB	TGRB input capture/compare match.
INTSEL_CAUSE_MTU3_TGIC	TGRC input capture/compare match.
INTSEL_CAUSE_MTU3_TGID	TGRD input capture/compare match.
INTSEL_CAUSE_MTU3_TGIE	TGRE compare match.
INTSEL_CAUSE_MTU3_TGIF	TGRF compare match.
INTSEL_CAUSE_MTU3_TGIU	TGRU input capture/compare match.
INTSEL_CAUSE_MTU3_TGIV	TGRV input capture/compare match.
INTSEL_CAUSE_MTU3_TGIW	TGRW input capture/compare match.
INTSEL_CAUSE_MTU3_TCIU	TCNT underflow.
INTSEL_CAUSE_MTU3_TCIV	TCNT overflow.
INTSEL_CAUSE_MTU3_CAUSE_NUM	The number of cause of interrupt of MTU3.
INTSEL_CAUSE_TINT	TINT's cause of interrupt (interrupt signal from GPIO pin)
INTSEL_CAUSE_TINT_CAUSE_NUM	The number of cause of interrupt of TINT.
INTSEL_CAUSE_IRQ	IRQ's cause of interrupt (interrupt signal from IRQ pin)
INTSEL_CAUSE_IRQ_CAUSE_NUM	The number of cause of interrupt of IRQ.

Function Documentation

◆ R_FSP_VersionGet()

fsp_err_t R_FSP_VersionGet ( fsp_pack_version_t *const p_version )

Get the FSP version based on compile time macros.

Parameters

[out] p_version Memory address to return version information to.

Return values

FSP_SUCCESS	Version information stored.
FSP_ERR_ASSERTION	The parameter p_version is NULL.

◆ Reset_Handler_NS()

void Reset_Handler_NS ( void )

MPU starts executing here out of reset. Main stack pointer is set up already.

◆ Default_Handler()

void Default_Handler ( void )

Default exception handler.

◆ NMI_Handler_NS()

void NMI_Handler_NS ( void )

Non-maskable interrupt handler.

◆ Reset_Handler_S()

void Reset_Handler_S ( void )

MPU starts executing here out of reset. Main stack pointer is set up already.

◆ Default_Handler_S()

void Default_Handler_S ( void )

Default exception handler.

◆ NMI_Handler_S()

void NMI_Handler_S ( void )

Non-maskable interrupt handler.

◆ SecureFault_Handler()

void SecureFault_Handler ( void )

SecureFault_Handler

◆ SystemInit()

void RZG::SystemInit ( void )

Initialize the MPU and the runtime environment.

◆ R_BSP_WarmStart()

void RZG::R_BSP_WarmStart ( bsp_warm_start_event_t event )

This function is called at various points during the startup process. This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user implemented version. One of the main uses for this function is to call functional safety code during the startup process. To use this function just copy this function into your own code and modify it to meet your needs.

Parameters

[in] event Where the code currently is in the start up process

◆ SystemInit_S()

void RZG::SystemInit_S ( void )

Initialize the MPU and the runtime environment.

◆ Warm_Reset_S()

void RZG::Warm_Reset_S ( void )

In the Cortex-M33 CPU core of this device, the secure vector address must be set to SYS_CM33_CFG2 before WarmReset is executed. Also, the non-secure vector address must be set to SYS_CM33_CFG3 before WarmReset is executed. The Cortex-M33's program works on the assumption that the appropriate vector address values have been set in SYS_CM33_CFG2 and SYS_CM33_CFG3 in the Cortex-A55 program.

◆ Entry_Function_S()

void RZG::Entry_Function_S ( void )

Entry function when debugging RAM load using a debugger

◆ XSPI_Boot_Entry()

void RZG::XSPI_Boot_Entry ( void )

Same function as Warm_Reset_S. Used as an entry function at XSPI boot.

◆ R_FSP_SystemClockHzGet()

uint32_t R_FSP_SystemClockHzGet ( fsp_priv_clock_t clock )

Get the system clock frequency.

Parameters

[in] clock Element number of the array that defines the frequency of the bus clock.

Return values

g_clock_freq[clock] System clock frequency.

◆ R_BSP_ClockSelectorSet()

fsp_err_t R_BSP_ClockSelectorSet	(	fsp_priv_clock_selector_t	selector,
		uint32_t	clock_sel
	)

Set a clock selector.

Parameters

[in]	selector	Element number of the array that defines the clock selector.
[in]	clock_sel	Value to set in Mux Control register.

Return values

FSP_SUCCESS	Selector configuration changes completed.
FSP_ERR_INVALID_ARGUMENT	Undefined selector specified.
FSP_ERR_PLL_SRC_INACTIVE	Clock source PLL is reset state.

Note: This function assumes that a source clock is supplied. If the source clock is not supplied, the selector setting process cannot be completed successfully.

◆ R_BSP_ClockDividerSet()

fsp_err_t R_BSP_ClockDividerSet	(	fsp_priv_clock_divider_t	divider,
		uint32_t	clock_div
	)

Set a clock division ratio.

Parameters

[in]	divider	Element number of the array that defines the clock divider.
[in]	clock_div	Value to set in Gear Control register.

Return values

FSP_SUCCESS	Divider configuration changes completed.
FSP_ERR_INVALID_ARGUMENT	Undefined divider specified.
FSP_ERR_PLL_SRC_INACTIVE	Clock source PLL is reset state.

Note: This function assumes that a source clock is supplied. If the source clock is not supplied, the divider setting process cannot be completed successfully.

◆ R_FSP_CurrentIrqGet()

__STATIC_INLINE IRQn_Type RZG::R_FSP_CurrentIrqGet ( void )

Return active interrupt vector number value

Returns: Active interrupt vector number value

◆ R_BSP_UniqueIdGet()

__STATIC_INLINE bsp_unique_id_t const* RZG::R_BSP_UniqueIdGet ( )

Get unique ID is not supported in this device.

Returns: A pointer to the unique identifier structure

◆ R_BSP_SoftwareDelay()

void R_BSP_SoftwareDelay	(	uint32_t	delay,
		bsp_delay_units_t	units
	)

Delay for at least the specified duration in units and return. This function shouldn't be used to generate an accurate delay time. A running time of the function is depending on the region of memory where the function is excuted on and a frequency of the CPU clock.

The funcion calls bsp_prv_software_delay_loop() which loops over the requested delay time. One loop time through bsp_prv_software_delay_loop() takes roughly 500ns. This value is based on the actual measured time in the condition that a frequency of the CPU clock is 200MHz and the code is excuted on DDR3L-1333 DRAM(133MHz). One loop running time of software_delay_loop() can be modified by redefining BSP_FEATURE_BSP_DELAY_LOOP_CYCLES.

Parameters

[in]	delay	The number of 'units' to delay.
[in]	units	The 'base' (bsp_delay_units_t) for the units specified. Valid values are: BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS, BSP_DELAY_UNITS_MICROSECONDS. For example: One run through bsp_prv_software_delay_loop() takes roughly 500ns. A delay of 100 us therefore requires 100000ns/500ns -> 200 loops.

The 'theoretical' maximum delay that may be obtained is determined by a full 32 bit loop count and the system clock rate. @200MHz: ((0xFFFFFFFF loops * 500ns) = 2147 seconds.

Note that requests for very large delays will be affected by rounding in the calculations and the actual delay achieved may be slightly off of a setting time.

Note also that if the calculations result in a loop_cnt of zero, the bsp_prv_software_delay_loop() function is not called at all. In this case the requested delay is too small (nanoseconds) to be carried out by the loop itself, and the overhead associated with executing the code to just get to this point has certainly satisfied the requested delay.

Note: This function uses SystemCoreClock and therefore requires that the BSP has already initialized the variable (which it does as part of the SystemInit). Care should be taken to ensure this remains the case if in the future this function were to be called as part of the BSP initialization.

◆ R_BSP_GroupIrqWrite()

fsp_err_t R_BSP_GroupIrqWrite	(	bsp_grp_irq_t	irq,
		void(*)(bsp_grp_irq_t irq)	p_callback
	)

Register a callback function for supported interrupts. If NULL is passed for the callback argument then any previously registered callbacks are unregistered.

Parameters

[in]	irq	Interrupt for which to register a callback.
[in]	p_callback	Pointer to function to call when interrupt occurs.

Return values

FSP_ERR_UNSUPPORTED NMI Group IRQ are not supported in this device.

◆ R_BSP_IrqStatusClear()

void RZG::R_BSP_IrqStatusClear ( IRQn_Type irq )

Clear the interrupt status flag for a given interrupt.

Note: This function does not implement processing on this device.

Parameters

[in] irq Not used

◆ R_BSP_IrqClearPending()

void RZG::R_BSP_IrqClearPending ( IRQn_Type irq )

Clear the interrupt status flag for a given interrupt and clear the NVIC pending interrupt.

Parameters

[in] irq Interrupt for which to clear the status flag. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.

Warning: Do not call this function for system exceptions where the IRQn_Type value is < 0.

◆ R_BSP_IrqCfg()

void RZG::R_BSP_IrqCfg	(	IRQn_Type const	irq,
		uint32_t	priority,
		void *	p_context
	)

Sets the interrupt priority and context.

Parameters

[in]	irq	The IRQ to configure.
[in]	priority	NVIC priority of the interrupt
[in]	p_context	The interrupt context is a pointer to data required in the ISR.

Warning: Do not call this function for system exceptions where the IRQn_Type value is < 0.

◆ R_BSP_IrqEnableNoClear()

void RZG::R_BSP_IrqEnableNoClear ( IRQn_Type const irq )

Enable the IRQ in the NVIC (Without clearing the pending bit).

Parameters

[in] irq The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.

Warning: Do not call this function for system exceptions where the IRQn_Type value is < 0.

◆ R_BSP_IrqEnable()

void RZG::R_BSP_IrqEnable ( IRQn_Type const irq )

Clears pending interrupts in both IM33 and NVIC, then enables the interrupt.

Parameters

[in] irq Interrupt for which to clear status flag and enable in the NVIC. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.

Warning: Do not call this function for system exceptions where the IRQn_Type value is < 0.

◆ R_BSP_IrqDisable()

void RZG::R_BSP_IrqDisable ( IRQn_Type const irq )

Disables interrupts in the NVIC.

Parameters

[in] irq The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.

Warning: Do not call this function for system exceptions where the IRQn_Type value is < 0.

◆ R_BSP_IrqCfgEnable()

void RZG::R_BSP_IrqCfgEnable	(	IRQn_Type const	irq,
		uint32_t	priority,
		void *	p_context
	)

Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt.

Parameters

[in]	irq	Interrupt number.
[in]	priority	NVIC priority of the interrupt
[in]	p_context	The interrupt context is a pointer to data required in the ISR.

Warning: Do not call this function for system exceptions where the IRQn_Type value is < 0.

◆ R_BSP_SlaveAddressConversion()

uint32_t RZG::R_BSP_SlaveAddressConversion ( uint32_t original_address )

Converts the cpu address specified in the argument to the bus address. If an address that does not exist in the external-bus is specified, it will not be converted.

Parameters

[in] original_address Address that CPU access to slave.

Return values

converted_address Address that Bus-master device access to slave.

◆ R_BSP_SystemResetStatusGet()

void RZG::R_BSP_SystemResetStatusGet ( void )

Store the status of system reset signals to g_bsp_system_reset_status_table.

◆ R_BSP_NonSecureEnter()

void RZG::R_BSP_NonSecureEnter ( void )

Enter the non-secure code environment.

This function configures the non-secure MSP and vector table then jumps to the non-secure project's Reset_Handler.

Note: This function (and therefore the non-secure code) should not return.

◆ R_BSP_IntStatusControlGet()

uint32_t R_BSP_IntStatusControlGet	(	fsp_ip_t	ip,
		uint8_t	channel,
		IRQn_Type	irq
	)

Gets the status that is represent which interrupt signal is active.

Parameters

[in]	ip	Specifies which module to read status.
[in]	channel	Specifies the channel number. If multiple channel interrupt factors are bundled together as a single interrupt factor, this argument is not used.
[in]	irq	Specifies the irq number. If the interrupt factor is separated for each channel, this argument is not used.

Return values

int_status Returns the value of the Interrupt Status Control register by offsetting the data relative to the position of bit0. If a channel number is specified, returns the status of all interrupts for that channel. If an interrupt factor is specified, it returns the status for all channels of that interrupt factor.

◆ R_BSP_IntStatusControlClear()

fsp_err_t R_BSP_IntStatusControlClear	(	fsp_ip_t	ip,
		uint8_t	channel,
		IRQn_Type	irq,
		uint32_t	int_source
	)

Clears the status of the specified interrupt source.

Parameters

[in]	ip	Specifies which module to read status.
[in]	channel	Specifies the channel number.
[in]	irq	Specifies the irq number.
[in]	int_source	Specify the source of the interrupt to be cleared. It does not include the channel number.

Return values

FSP_SUCCESS	Interrupt status clear was successful.
FSP_ERR_INVALID_MODE	Specified module is not eligible for the Interrupt Selection feature.
FSP_ERR_INVALID_ARGUMENT	An invalid source of interrupt was specified.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	Requested channel number is not available.

Variable Documentation

◆ BSP_SECTION_EARLY_INIT

uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT

System Clock Frequency (Core Clock)

Functions

Detailed Description

Overview

BSP Features

BSP Clock Configuration

System Interrupts

Group Interrupts

External and Peripheral Interrupts

BSP Weak Symbols

Warm Start Callbacks

C Runtime Initialization

Heap Allocation

Error Logging

Register Protection

ID Codes

Software Delay

Critical Section Macros

OctaClock Update

Board Specific Features

Configuration

Build Time Configurations for fsp_common

Modules

Macros

Enumerations

Variables

Macro Definition Documentation

◆ R_BSP_MODULE_START

◆ R_BSP_MODULE_STOP

◆ BSP_IRQ_DISABLED

◆ FSP_LOG_PRINT

◆ FSP_RETURN

◆ FSP_ERROR_LOG

◆ FSP_ASSERT

◆ FSP_ERROR_RETURN

◆ FSP_CRITICAL_SECTION_ENTER

◆ FSP_CRITICAL_SECTION_EXIT

◆ FSP_INVALID_VECTOR

◆ BSP_CFG_HANDLE_UNRECOVERABLE_ERROR

◆ BSP_STACK_ALIGNMENT

◆ R_BSP_MSTP_START

◆ R_BSP_MSTP_STOP

Enumeration Type Documentation

◆ fsp_ip_t

◆ bsp_warm_start_event_t

◆ bsp_delay_units_t

◆ bsp_grp_irq_t

◆ intsel_cause_t

Function Documentation

◆ R_FSP_VersionGet()

◆ Reset_Handler_NS()

◆ Default_Handler()

◆ NMI_Handler_NS()

◆ Reset_Handler_S()

◆ Default_Handler_S()

◆ NMI_Handler_S()

◆ SecureFault_Handler()

◆ SystemInit()

◆ R_BSP_WarmStart()

◆ SystemInit_S()

◆ Warm_Reset_S()

◆ Entry_Function_S()

◆ XSPI_Boot_Entry()

◆ R_FSP_SystemClockHzGet()

◆ R_BSP_ClockSelectorSet()

◆ R_BSP_ClockDividerSet()

◆ R_FSP_CurrentIrqGet()

◆ R_BSP_UniqueIdGet()

◆ R_BSP_SoftwareDelay()

◆ R_BSP_GroupIrqWrite()

◆ R_BSP_IrqStatusClear()

◆ R_BSP_IrqClearPending()

◆ R_BSP_IrqCfg()

◆ R_BSP_IrqEnableNoClear()

◆ R_BSP_IrqEnable()

◆ R_BSP_IrqDisable()

◆ R_BSP_IrqCfgEnable()

◆ R_BSP_SlaveAddressConversion()

◆ R_BSP_SystemResetStatusGet()

◆ R_BSP_NonSecureEnter()

◆ R_BSP_IntStatusControlGet()