NAND Flash (r_nandc)

Functions
fsp_err_t	R_NANDC_Open (nand_flash_ctrl_t *const p_ctrl, nand_flash_cfg_t const *const p_cfg)
fsp_err_t	R_NANDC_Close (nand_flash_ctrl_t *const p_ctrl)
fsp_err_t	R_NANDC_Read (nand_flash_ctrl_t *const p_ctrl, nand_flash_device_page_t const *const p_src_page, nand_flash_data_buffer_t *const p_dest_buffer, uint32_t const chip_select)
fsp_err_t	R_NANDC_Write (nand_flash_ctrl_t *const p_ctrl, nand_flash_data_buffer_t const *const p_src_buffer, nand_flash_device_page_t const *const p_dest_page, uint32_t const chip_select)
fsp_err_t	R_NANDC_Erase (nand_flash_ctrl_t *const p_ctrl, uint32_t const block, uint32_t const block_count, uint32_t const chip_select)
fsp_err_t	R_NANDC_FeatureSet (nand_flash_ctrl_t *const p_ctrl, uint32_t const feature_address, uint32_t const feature_value, uint32_t const chip_select)
fsp_err_t	R_NANDC_DeviceReset (nand_flash_ctrl_t *const p_ctrl, uint32_t const chip_select)
fsp_err_t	R_NANDC_StatusGet (nand_flash_ctrl_t *const p_ctrl, uint32_t const chip_select, nand_flash_status_t *const p_status)
fsp_err_t	R_NANDC_CallbackSet (nand_flash_ctrl_t *const p_ctrl, void(*p_callback)(nand_flash_callback_args_t *), void const *const p_context, nand_flash_callback_args_t *const p_callback_memory)
fsp_err_t	R_NANDC_InfoGet (nand_flash_ctrl_t *const p_ctrl, nand_flash_device_info_t *const p_info)
fsp_err_t	R_NANDC_Copyback (nand_flash_ctrl_t *const p_ctrl, nand_flash_device_page_t const *const p_src_page, nand_flash_device_page_t const *const p_dest_page, uint32_t const chip_select)
fsp_err_t	R_NANDC_RawRead (nand_flash_ctrl_t *const p_ctrl, nand_flash_device_page_t const *const p_src_page, uint8_t *const p_dest, uint32_t const chip_select)
fsp_err_t	R_NANDC_RawWrite (nand_flash_ctrl_t *const p_ctrl, uint8_t const *const p_src, nand_flash_device_page_t const *const p_dest_page, uint32_t const chip_select)
fsp_err_t	R_NANDC_RemapSet (nand_flash_ctrl_t *const p_ctrl, uint32_t const logical_address, uint32_t const physical_address)
fsp_err_t	R_NANDC_RemapClear (nand_flash_ctrl_t *const p_ctrl)
fsp_err_t	R_NANDC_WriteProtectEnable (nand_flash_ctrl_t *const p_ctrl, uint32_t const start_address, uint32_t const size, uint32_t const index)
fsp_err_t	R_NANDC_WriteProtectDisable (nand_flash_ctrl_t *const p_ctrl, uint32_t const index)
fsp_err_t	R_NANDC_ControllerStatusGet (nand_flash_ctrl_t *const p_ctrl, nandc_controller_status_t *const p_status)

Detailed Description

Driver for the NAND Controller (NANDC) peripheral on RZ microprocessor. This module implements the NAND Flash Interface.

Overview

The NAND Controller (NANDC) supports ONFI-compliant external NAND Flash devices, and it interfaces with these devices to perform data I/O Operations.

Features

• Supports ONFI-compliant NAND Flash.
  • Supports reading, programming and erasing NAND Flash devices.
  • Supports copy-back in NAND Flash devices.
  • Supports reseting NAND Flash devices.
  • Supports acquiring NAND Flash parameter page data.
  • Supports cache operation in NAND Flash devices.
  • Supports multi-plane operation in NAND Flash devices.
• Supports configuring signal timings and changing transmission rates.
• Supports notifying the following events via callbacks: Command operation completion, Command error condition, Command timeout condition.
• Supports error detection by CRC.
• Supports error correction by BCH code.
• Supports scrambling processing.
• Supports address translation for NAND Flash array.
• Supports write protection for NAND Flash array.
• Supports skipping access of specific bytes.

  Note

  The NANDC driver supports ONFI v1.0. Features added in later versions are not supported.

Configuration

Build Time Configurations for r_nandc

The following build time configurations are defined in fsp_cfg/r_nandc_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Nested Interrupt (Multiplex Interrupt)	Enabled Disabled	Disabled	Enable nested interrupt for a single driver.

Configurations for Storage > NAND Flash (r_nandc)

This module can be added to the Stacks tab via New Stack > Storage > NAND Flash (r_nandc).

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_nand_flash0	Module name.
General > Scrambling	Enabled Disabled	Disabled	Select if data scrambling function in NANDC should be enabled. Scrambling the data helps in reducing the chances of read or program disturbs that cause data corruption in the page.
Data Size Configuration per Page > Main Data > Sector Number per Page	Must be an interger between 1 and 255	1	Sector number per page.
Data Size Configuration per Page > Main Data > Sector Bytes	Must be an interger between 1 and 65535	8192	Sector size. The stored data size per page is calculated as Sector Number per Page * Sector Bytes.
Data Size Configuration per Page > OOB Data Bytes	Must be an interger between 0 and 65535	0	OOB data size per page.
Signal Timings > Controller Signal Timings > RE# signal > RE# signal timing configuration	Disabled Enabled	Enabled	Select if the RE# signal timing configuration should be enabled.
Signal Timings > Controller Signal Timings > RE# signal > RE# pulse width (NF_CLK cycles)	Value must be an integer between 1 and 32	25	RE# pulse width cycles. (tRP in ONFI)
Signal Timings > Controller Signal Timings > RE# signal > RE# hold time (NF_CLK cycles)	Value must be an integer between 1 and 32	25	RE# hold time cycles. (tREH in ONFI)
Signal Timings > Controller Signal Timings > WE# signal > WE# signal timing configuration	Disabled Enabled	Enabled	Select if the WE# signal timing configuration should be enabled.
Signal Timings > Controller Signal Timings > WE# signal > WE# pulse width (NF_CLK cycles)	Value must be an integer between 1 and 32	25	WE# pulse width cycles. (tWP in ONFI)
Signal Timings > Controller Signal Timings > WE# signal > WE# hold time (NF_CLK cycles)	Value must be an integer between 1 and 32	25	WE# hold time cycles. (tWH in ONFI)
Signal Timings > Controller Signal Timings > RE# high to WE# low (NF_CLK cycles)	Value must be an integer between 157 and 256	256	RE# high to WE# low cycles. (tRHW in ONFI)
Signal Timings > Controller Signal Timings > WE# high to RE# low (NF_CLK cycles)	Value must be an integer between 12 and 257	257	WE# high to RE# low cycles. (tWHR in ONFI)
Signal Timings > Controller Signal Timings > ALE to data loading time (NF_CLK cycles)	Value must be an integar between 57 and 312	312	ALE data loading time cycles. (tADL in ONFI)
Signal Timings > Controller Signal Timings > Command end to SR[6] low (NF_CLK cycles)	Value must be an integer between 52 and 266	266	Command end to SR[6] low cycles. (Similar to tWB in ONFI)
Signal Timings > Controller Signal Timings > RE# high to output hi-Z (NF_CLK cycles)	Value must be an integer between 28 and 257	257	RE# high to output Hi-Z cycles. (tRHZ in ONFI)
Signal Timings > Controller Signal Timings > CE# setup time (NF_CLK cycles)	Value must be an integer between 11 and 74	74	CE# setup time. (tCS in ONFI)
Signal Timings > Controller Signal Timings > CE# high hold time (NF_CLK cycles)	Value must be an integer between 1 and 64	64	CE# high hold time. (tCH in ONFI)
Signal Timings > Controller Signal Timings > Interface and Timing Mode Change time (NF_CLK cycles)	Value must be an integer between 318 and 1341	1341	Interface and Timing Mode Change time cycles. (tITC in ONFI)
Signal Timings > NAND Flash Timing Mode	Timing Mode 0 Timing Mode 1 Timing Mode 2 Timing Mode 3	Timing Mode 0	Set timing mode of NAND Flash.
Interrupts > Source > Command Complete	Enabled Disabled	Enabled	Trigger NANDC interrupt when command complete occur.
Interrupts > Source > Command Error	Enabled Disabled	Enabled	Trigger NANDC interrupt when command error occur.
Interrupts > Source > Command Timeout	Enabled Disabled	Enabled	Trigger NANDC interrupt when command timeout occur.
Interrupts > NANDC Interrupt Priority	MCU Specific Options		NANDC interrupt priority.
Interrupts > Callback	Name must be a valid C symbol	NULL	A user callback function. If this callback function is provided, it is called from the interrupt service routine (ISR) of NAND Controller.
Ready Status Detection Method > Ready Status Detection	NAND_RY_BY# pin check Status polling	NAND_RY_BY# pin check	Select the method to detect device ready status. NAND_RY_BY# pin check: Get device status by RY_BY# pin level. Status polling: Get device status by polling read status command.
Ready Status Detection Method > Cycles of long polling time (Status polling only)	Must be an integer between 1 and 65535	1000	Number of system clock cycles after issue of erase/write/read operation before the controller starts to poll for status. Should be significantly larger than the short polling value.
Ready Status Detection Method > Cycles of short polling time (Status polling only)	Must be an integer between 1 and 65535	500	Subsequent read status polling interval cycles.
Command Specifications > Erased Page Detection > Enable Erased Page Flag	Enabled Disabled	Disabled	Enable erased page flag in command status
Command Specifications > Erased Page Detection > Permissible Number of Zeros inside the Transferred Sector	Must be an interger between 0 and 255	0	The number of zeros inside the transferred sector that is still considered as Erased when ECC is disabled. When ECC is enabled, permissible number of zeros depends on correction ability setting.
Command Specifications > Skip Bytes for Marker Preservation > Skip Bytes Offset	Must be an interger between 0x0 and 0xFFFFFF	0x0	Set marker position in a page. NANDC skips the marker from read or write.
Command Specifications > Skip Bytes for Marker Preservation > Skip Bytes Size	Must be an interger between 0 and 255	0	Set marker size in a page. NANDC skips the marker from read or write. When set to 0, no bytes are skipped.
Command Specifications > Skip Bytes for Marker Preservation > Skip Bytes Marker Value	Must be an interger between 0x0 and 0xFF	0xFF	Marker value to program. Skipped bytes are filled with the marker value.
Command Specifications > Multi-plane > Send Multi-plane Operation in Read Operation	Enabled Disabled	Disabled	Use multi-plane command when read operation.
Command Specifications > Multi-plane > Send Multi-plane Operation in Write and Erase Operation	Enabled Disabled	Disabled	Use multi-plane command when write and erase operation.
Command Specifications > Multi-plane > Number of Planes	1 2 4 6 8	1	Select the number of plane of connected NAND Flash.
Command Specifications > Remap > Remap Enable	Enabled Disabled	Disabled	Use address translation when access to NAND Flash array.
Command Specifications > Remap > Remap Target Address Bits	Must be an interger between 0x00000000 and 0xFFFFFFFF	0xFFFFFFFF	Select the target bits of address translation.
Command Specifications > Command Timeout Cycles	Must be an interger between 0 and 4294967295	0	Command execution timeout cycles of NF_CLK. When set to 0, timeout function is disabled. Otherwise, command timeout interrupt source is triggered if the setting cycles are counted while command execution.
Error Detection > CRC > Detect Error in Controller Data Path by CRC	Enabled (8 bytes CRC checksum added) Disabled	Disabled	Use CRC error detection. When enabled, 8 bytes of checksum added to the data stream.
Error Detection > ECC > ECC Enable	Enabled Disabled	Disabled	Use ECC error correction. Checksum bits are added to the data stream.
Error Detection > ECC > Correction Ability per Sector	8 bits (16 bytes check-bit added) 16 bits (30 bytes check-bit added) 32 bits (60 bytes check-bit added) 64 bits (120 bytes check-bit added) 72 bits (136 bytes check-bit added)	8 bits (16 bytes check-bit added)	ECC error correction ability per sector. Size of check bits is determined by this setting.
Device Discovery Process > R/B# valid wait time configuration > R/B# valid wait time (PCLKAM cycles)	Value must be an integer between 0 and 65535	0	Wait time before device discovery process (PCLKAM cycles). Used to avoid communication during the undefined period of the R/B# pin following power-up. If you want to wait for 10 us, you need to set the value to 2000, which is calculated as 10 [us] * 200 [MHz] (PCLKAM).
Device Discovery Process > R/B# valid wait time configuration	Disabled Enabled	Disabled	Configure whether to wait for the R/B pin to become active in device discovery process. You may set to disabled if there is sufficient time between power-on and NANDC open.

Clock Configuration

The NANDC peripheral uses NF_CLK for its clock source.

NF_CLK frequencies can be set on the Clocks tab of the FSP Configuration editor.

Pin Configuration

The NANDC driver supports the following pins :

• NAND_CE0#
• NAND_IO[7:0]
• NAND_CLE
• NAND_ALE
• NAND_RE#
• NAND_WE#
• NAND_WP#
• NAND_RY_BY0#

Note

Due to Chip Select limitation, this driver does not support NAND_CE1#, NAND_CE2#, NAND_CE3#, NAND_RY_BY1#, NAND_RY_BY2#, NAND_RY_BY3#. For details, please refer to the chip select section.

Usage Notes

Page Definition

Size of the data stored on each page is managed in units called sector. Sector is the unit of error correction and detection for the ECC and CRC functions provided by the NANDC peripheral. The number of bytes per sector is configured in 'Sector Bytes', and the number of sectors per page is configured in 'Sector Number per Page' in the configuration properties.

In addition to the main data stored in the sectors, you can specify OOB (Out of Band) data separately from the main data. You can store any information that can be used by your software, such as data related to FTL (Flash Translation Layer). The OOB data is inserted after the last sector.

In addition to the main data configured by sector and OOB data, the following code is stored on each page depending on the configuration settings.

• ECC code: Codes for Detection and Correction of multiple errors in the data stream read from the NAND flash device. Inserted between each sector.
• CRC code: Codes for Detection of controller data path errors. Inserted between each sector.

The diagram below illustrates the data structure on a page.

NANDC Data Structure on a Page

In addition, you can configure the 'Skip bytes' feature, which skips access to specific bytes in each page. This feature allows you to retain the bad block markers complianted with ONFI Factory Defect Mapping requirements. The following items are configured in configuration properties:

• Skip Bytes Offset: Configure the offset bytes of the bad block marker in the page.
• Skip Bytes Size: Configure the size of the bad block marker.
• Skip Bytes Marker Value: Configure the byte pattern to be written to the skipped bytes in write operation.

The diagram below illustrates the skipped bytes position in a page.

NANDC Skip Bytes Region Example

Note

Please configure 'Sector Bytes' and 'Sector Number per Page' considering skipped bytes configured in 'Skip Bytes Size' in the configuration properties, OOB data size bytes configured in 'OOB Data Bytes', and check-bits inserted between sectors when ECC or CRC is enabled.

Read Data Bytes per Page = (Sector Bytes) * (Sector Number per Page) /* Stored in main data buffer */
Read OOB Data Bytes per Page = (OOB Data Bytes) /* Stored in OOB data buffer */

Programmed Data Bytes per Page = (Sector Bytes) * ((Sector Number per Page) + (ECC check-bits) + (CRC check-bits)) + (Skip Bytes Size) + (OOB Data Bytes)

Example of One Page

This section shows an example of one page data structure.

Table below shows an example of configuration that affect page structure.

Configuration	Value
General > Scrambling	Disabled
Data Size Configuration per Page > Main Data > Sector Number per Page	4
Data Size Configuration per Page > Main Data > Sector Bytes	1024
Data Size Configuration per Page > OOB Data Bytes	64
Command Specifications > Skip Bytes for Marker Preservation > Skip Bytes Offset	4096
Command Specifications > Skip Bytes for Marker Preservation > Skip Bytes Size	2
Error Detection > CRC > Detect Error in Controller Data Path by CRC	Enabled (8 byte checkbits added)
Error Detection > ECC > ECC Enable	Enabled
Error Detection > ECC > Corrction Ability per Sector	16 bits (30 bytes check-bit added)

For the above table, NANDC peripheral writes a page of data as shown in the following table. In this example, a flash memory of 4096 + 224 bytes per page is assumed to be connected.

Bytes in Page	Stored Data	Data Size
0 - 1023	Sector 0	1024
1024 - 1061	ECC + CRC	30 + 8
1062 - 2085	Sector 1	1024
2086 - 2123	ECC + CRC	30 + 8
2124 - 3147	Sector 2	1024
3148 - 3185	ECC + CRC	30 + 8
3186 - 4125	Sector 3	940
4126 - 4127	Skipped	2
4128 - 4211	Sector 3	84
4212 - 4275	OOB Data	64
4276 - 4313	ECC + CRC	30 + 8
4314 - 4319	No Data	6

Read and Write

R_NANDC_Write() and R_NANDC_Read() access data in NAND Flash according to the configuration properties below.

• OOB Data Bytes: Selected size of OOB data is inserted just after the main data in the last sector.
• ECC: Check-bits corresponding to the correction ability are inserted between sectors. Error correction applies to the data in each sector and the OOB data.
• CRC: 8-byte check-bits are inserted between sectors.
• Scrambling: Scrambling is applied to the written data, and the scrambled data is decoded when read.
• Skip Bytes: The region configured in 'Skip Bytes Offset' and 'Skip Bytes Size' is skipped when read and write. In write operation, 'Skip Bytes Marker value' pattern is written in the skipped bytes.

If these features are enabled, R_NANDC_Write() and R_NANDC_Read() perform as follows.

• Write operation : Program the main data (stored in each sector) and the OOB data (just after the last sector). ECC/CRC codes for these data are automatically inserted. This block of data is scrambled before being written. The data is not placed at the locations specified by the skip bytes; instead, 'Skip Bytes Marker Value' pattern is written there.
• Read operation : The main data stored in each sector and the OOB data are returned. The scrambled data is decoded, and error correction and detection by ECC/CRC codes are performed automatically. The Skipped bytes are ignored.

To access raw data in NAND Flash array while ignoring configuration, call R_NANDC_RawWrite() and R_NANDC_RawRead().

Cache Command

If the connected NAND Flash supports ONFI cache commands, this driver operates as follows:

• When accessing a single page of data, NANDC peripheral issues a normal command sequence.
• When accessing multiple pages, NANDC peripheral issues a cache command sequence.

Remap Address Translation

Remap function allows the NANDC peripheral to automatically translate row addresses according to the translation table. Using it, NANDC peripheral can access a different page when trying to a page registered in the table. This is useful when avoiding access to bad blocks.

In the configuration properties, 'Remap Enable' should be set to 'Enabled' to use remap function. In addition, 'Remap Target Address Bits' allows you to specify the bit positions of the row address to which address translation is applied.

The pair of the logical address (the address of translation target) and the physical address (the address after translation) is registered in the translation table using R_NANDC_RemapSet(). Up to 1024 pairs of addresses can be registered to the table by calling R_NANDC_RemapSet() multiple times.

Examples of the translation rules and target bits for each 'Remap Target Address Bit' are as follows:

• Remap Target Address Bits = 0xFFFFFFFF : If all bits of the Logical Address match, it is translated to a Physical Address.
• Remap Target Address Bits = 0xFFFFFF00 : If the upper 24 bits of the Logical Address match, only the upper 24 bits are translated to the same value as the Physical Address.
• Remap Target Address Bits = 0xFFFF0000 : If the upper 16 bits of the Logical Address match, only the upper 16 bits are translated to the same value as the Physical Address.

The pair of the logical address (the address of translation target) and the physical address (the address after translation) is registered in the translation table using R_NANDC_RemapSet(). Up to 1024 pairs of addresses can be registered to the table by calling R_NANDC_RemapSet() multiple times.

Table below shows an example of address translation table entries.

Logical Address	Physical Address
0x00000104	0x00000204
0x0000100A	0x0000201E
0x0010A000	0x0030E010

The entries in the address translation table can be updated as follows:

/* Set the entry examples in the table above. */
R_NANDC_RemapSet(&g_nand_flash_ctrl, 0x00000104, 0x00000204);
R_NANDC_RemapSet(&g_nand_flash_ctrl, 0x0000100A, 0x0000201E);
R_NANDC_RemapSet(&g_nand_flash_ctrl, 0x0010A000, 0x0030E010);

For the above table, NANDC peripheral performs address translation as shown in the following table.

Translation Target Address Example (Logical Address)	Translated Address (Remap Target Address Bits = 0xFFFFFFFF)	Translated Address (Remap Target Address Bits = 0xFFFFFF00)	Translated Address (Remap Target Address Bits = 0xFFFF0000)
0x00000104	0x00000204 (Translated)	0x00000204 (Translated)	0x00000104 (Translated)
0x00000106	0x00000106	0x00000206 (Translated)	0x00000106 (Translated)
0x0000100A	0x0000201E (Translated)	0x0000200A (Translated)	0x0000100A (Translated)
0x0000100C	0x0000100C	0x0000200C (Translated)	0x0000100C (Translated)
0x0010A000	0x0030E010 (Translated)	0x0030E000 (Translated)	0x0030A000 (Translated)
0x0010A014	0x0010A014	0x0030E014 (Translated)	0x0030A014 (Translated)
0x0010C018	0x0010C018	0x0010C018	0x0030C018 (Translated)

Write Protect

This driver can protect pages within a specified row address area of NAND Flash from write access. Protection areas are specified by calling R_NANDC_WriteProtectEnable(). Up to two protection areas can be registered.

When attempting write access to a protected area, the access is not executed, and an interrupt occurs due to a command error condition.

Limitations

Developers should be aware of the following limitations when using the NANDC driver:

Chip Select Limitations

This driver always accesses the target to which CE0# is connected. Therefore, the following limitations are applied.

• The chip select value set in the argument of R_NANDC_Write(), R_NANDC_Read(), R_NANDC_Erase(), R_NANDC_Copyback(), R_NANDC_DeviceReset(), R_NANDC_FeatureSet(), R_NANDC_RawWrite() and R_NANDC_RawRead() is ignored.
• The pins for Chip Select 1, 2 and 3 (CS1NAND_CE1#, NAND_CE2#, NAND_CE3#, NAND_RY_BY1#, NAND_RY_BY2# and NAND_RY_BY3#) are not supported in this driver.

Data Buffer Placement Limitations

The data read by R_NANDC_Read() or R_NANDC_RawRead(), and the data programmed by R_NANDC_Write() or R_NANDC_RawWrite() are transferred to the data buffer via the NANDC peripheral's internal DMA. Therefore, it is necessary to use an uncached area for data buffer to read data to or data buffer to program data from.

Multi-plane Limitations

When multi-plane mode is enabled, the region accessed by R_NANDC_Write(), R_NANDC_Read() and R_NANDC_Copyback() are restricted as below.

• The number of pages must be a multiple of the number of planes.
• The row address of the first page to be accessed must belong to a block in plane 0.

In addition, the accessed pages change to take full advantage of the functionality. The following example shows the actual pages accessed when accessing 6 pages starting at row address 0x00000000 (block 0 page 0).

plane number	1st page data	2nd page data	3rd page data	4th page data	5th page data	6th page data
1 (same as multi-plane disabled)	block 0 page 0	block 0 page 1	block 0 page 2	block 0 page 3	block 0 page 4	block 0 page 5
2	block 0 page 0	block 1 page 0	block 0 page 1	block 1 page 1	block 0 page 2	block 1 page 2
4	block 0 page 0	block 1 page 0	block 2 page 0	block 3 page 0	block 0 page 1	block 1 page 1

The region accessed by R_NANDC_Erase() is similarly restricted.

• The number of blocks must be a multiple of the number of planes.
• The block number must be a block belonging to plane 0.

Limitation on Interrupts for Raw Access Functions

When calling R_NANDC_RawWrite() and R_NANDC_RawRead(), the command complete interrupt source must be enabled.

In addition, R_NANDC_Write(), R_NANDC_Read(), R_NANDC_Erase(), R_NANDC_Copyback(), and R_NANDC_DeviceReset() cannot be called until the command complete interrupt has completed.

Configurable Timings Limitation

Configurable timings are restricted by NF_CLK cycle time and NANDC peripheral. The user must configure timing that satisfies both Timing Mode specifications in ONFI and the limitations of the controller. The table below shows the timings configurable in the configuration editor.

nand_flash_timing_info_t	Timing in ONFI	Min NF_CLK cycles	Max NF_CLK cycles
we_pulse_width	tWP	1	32
we_high_hold_time	tWH	1	32
re_pulse_width	tRP	1	32
re_high_hold_time	tREH	1	32
re_high_to_we_low_time	tRHW	157	256
we_high_to_re_low_time	tWHR	12	257
ale_to_data_loading_time	tADL	57	312
command_end_to_sr6_low	tWB	52	266
re_high_to_output_hiz	tRHZ	28	257
ce_setup_time	tCS	11	74
ce_high_hold_time	tCEH	1	64
interface_and_timing_mode_change_time	tITC	318	1341

Note

If 'RE# signal timing configuration' is set to 'Disabled' in the configuration properties, the settings of following items are not used. Instead, NANDC peripheral operates according to the timing in Electrical Characteristics. For details, see "Electrical Characteristics" in the RZ microprocessor manual.

- RE# pulse width

- RE# hold

Similarly, if 'WE# signal timing configuration' is set to 'Disabled' in the configuration properties, the settings of following items are not used. Instead, NANDC peripheral operates according to the timing in Electrical Characteristics. For details, see "Electrical Characteristics" in the RZ microprocessor manual.

- WE# pulse width

- WE# hold

Due to NANDC peripheral does not support EDO data output cycle timings, this driver supports up to Timing Mode 3. For detail, see Open NAND Flash Interface Specification.

Blocking call

NANDC peripheral automatically accesses the NAND Flash device to acquire the device information immediately after module stop is released. R_NANDC_Open() blocks execution until the access completes.

Note

With ONFI-compliant NAND flash, the R/B# pin remains inactive for up to 10 us after power-on. Therefore, sufficient time must elapse between power-on and the start of NAND Flash access in R_NANDC_Open().

If you can't make a sufficient amount of time, you can delay the start of NAND Flash access in R_NANDC_Open() by setting 'R/B# valid wait time (PCLKAM cycles)' in the configurator properties. Please note that the blocking period increases if you use the function.

Examples

Basic Example

This is a basic example of minimal use of the r_nandc in an application.

#define NAND_FLASH_DATA_BYTES            (8192)
#define NAND_FLASH_SPARE_BYTES           (448)
#define NAND_FLASH_PAGE_BYTES            (NAND_FLASH_DATA_BYTES + NAND_FLASH_SPARE_BYTES)
#define NAND_FLASH_OOB_DATA_BYTES        (64)
#define NAND_FLASH_CHIP_SELECT           (0)
#define NAND_FLASH_ACCESS_ROW_ADDRESS    (0x00000085)
#define NAND_FLASH_ACCESS_BLOCK          (1)

uint8_t g_dest[NAND_FLASH_PAGE_BYTES] BSP_PLACE_IN_SECTION(".noncache_buffer");
uint8_t g_src[NAND_FLASH_PAGE_BYTES] BSP_PLACE_IN_SECTION(".noncache_buffer");
uint8_t g_dest_spare[NAND_FLASH_OOB_DATA_BYTES] BSP_PLACE_IN_SECTION(".noncache_buffer");
uint8_t g_src_spare[NAND_FLASH_OOB_DATA_BYTES] BSP_PLACE_IN_SECTION(".noncache_buffer");
uint8_t g_command_complete = 0;

void r_nandc_basic_example (void)
{
    /* Configure device page information to access. */
    nand_flash_device_page_t flash_page =
    {
        .row_address = NAND_FLASH_ACCESS_ROW_ADDRESS,
        .page_count  = 1,
    };

    /* Configure write source buffer address information. */
    nand_flash_data_buffer_t data_buffer =
    {
        .p_main_data_buffer = g_src,
        .p_oob_data_buffer  = g_src_spare, // Set control data if needed.
    };

    /* Configure read destination buffer address information. */
    nand_flash_data_buffer_t result_buffer =
    {
        .p_main_data_buffer = g_dest,
        .p_oob_data_buffer  = g_dest_spare, // Set buffer for control data if needed.
    };

    /* Initialize g_src to known data */
    for (uint32_t i = 0; i < NAND_FLASH_PAGE_BYTES; i++)
    {
        g_src[i] = (uint8_t) ('A' + (i % 26));
    }


    /* Open the NANDC driver. */
    fsp_err_t err = R_NANDC_Open(&g_nand_flash_ctrl, &g_nand_flash_cfg);

    assert(FSP_SUCCESS == err);


    /* Erase a block to access. */
    err = R_NANDC_Erase(&g_nand_flash_ctrl, NAND_FLASH_ACCESS_BLOCK, 1, NAND_FLASH_CHIP_SELECT);

    assert(FSP_SUCCESS == err);

    while (!g_command_complete)
    {
        /* Wait for command completion. */
    }

    /* Reset command complete flag. */
    g_command_complete = 0;


    /* Write a page of data. */
    err = R_NANDC_Write(&g_nand_flash_ctrl, &data_buffer, &flash_page, NAND_FLASH_CHIP_SELECT);

    assert(FSP_SUCCESS == err);

    while (!g_command_complete)
    {
        /* Wait for command completion. */
    }

    /* Reset command complete flag. */
    g_command_complete = 0;


    /* Read a page of data. */
    err = R_NANDC_Read(&g_nand_flash_ctrl, &flash_page, &result_buffer, NAND_FLASH_CHIP_SELECT);

    assert(FSP_SUCCESS == err);

    while (!g_command_complete)
    {
        /* Wait for command completion. */
    }
}

/* The callback is called when a command completes. */
void r_nandc_example_callback (nand_flash_callback_args_t * p_args)
{
    if ((NAND_FLASH_EVENT_ERASE_COMPLETE == p_args->event) ||
        (NAND_FLASH_EVENT_WRITE_COMPLETE == p_args->event) ||
        (NAND_FLASH_EVENT_READ_COMPLETE == p_args->event))
    {
        g_command_complete = 1;
    }
}

Raw Data Access example

This is an example of using R_NANDC_RawRead() to access raw data and extracting spare bytes in NAND Flash.

uint8_t spare_bytes[NAND_FLASH_SPARE_BYTES];
uint8_t g_raw_access_read_complete;

void r_nandc_raw_data_access_example (void)
{
    /* Configure device page information to access. */
    nand_flash_device_page_t flash_page =
    {
        .row_address = NAND_FLASH_ACCESS_ROW_ADDRESS,
        .page_count  = 1,
    };


    /* Open the NANDC driver. */
    fsp_err_t err = R_NANDC_Open(&g_nand_flash_ctrl, &g_nand_flash_cfg);

    assert(FSP_SUCCESS == err);

    /* Wait for the controller to get ready before raw access. */
    nandc_controller_status_t ctrl_status;
    do
    {

        err = R_NANDC_ControllerStatusGet(&g_nand_flash_ctrl, &ctrl_status);

        assert(FSP_SUCCESS == err);
    } while (ctrl_status.status == NANDC_CONTROLLER_STATE_BUSY);


    /* Read all a page of raw data. */
    err = R_NANDC_RawRead(&g_nand_flash_ctrl, &flash_page, g_dest, NAND_FLASH_CHIP_SELECT);

    assert(FSP_SUCCESS == err);

    while (!g_raw_access_read_complete)
    {
        /* Wait for command completion. */
    }

    /* Extract spare bytes from a page of data in buffer. */
    memcpy(spare_bytes, &g_dest[NAND_FLASH_DATA_BYTES], NAND_FLASH_SPARE_BYTES);
}

Remap example

This example demonstrates the sequence of address translation by NANDC remap function.

#define NAND_FLASH_ACCESS_LOGICAL_ADDRESS     (0x00000085)
#define NAND_FLASH_ACCESS_PHYSICAL_ADDRESS    (0x00000105)

uint8_t g_remap_read_complete = 0;

/* This example assumes that the Remap Enable is set to "Enabled", and Remap Target Address Bits is set to "0xFFFFFFFF" in the configuration editor. */
void r_nandc_remap_example (void)
{
    /* Configure device page information to access. */
    nand_flash_device_page_t flash_page =
    {
        .row_address = NAND_FLASH_ACCESS_LOGICAL_ADDRESS,
        .page_count  = 1,
    };

    /* Configure read destination buffer address information. */
    nand_flash_data_buffer_t result_buffer =
    {
        .p_main_data_buffer = g_dest,
        .p_oob_data_buffer  = g_dest_spare, // Set buffer for control data if needed.
    };


    /* Open the NANDC driver. */
    fsp_err_t err = R_NANDC_Open(&g_nand_flash_ctrl, &g_nand_flash_cfg);

    assert(FSP_SUCCESS == err);

    /* Wait for the controller to get ready before re-map configuration. */
    nandc_controller_status_t ctrl_status;
    do
    {

        err = R_NANDC_ControllerStatusGet(&g_nand_flash_ctrl, &ctrl_status);

        assert(FSP_SUCCESS == err);
    } while (ctrl_status.status == NANDC_CONTROLLER_STATE_BUSY);


    /* Set the translation table to access to NAND_FLASH_ACCESS_PHYSICAL_ADDRESS when the user tries to access NAND_FLASH_ACCESS_LOGICAL_ADDRESS. */
    err = R_NANDC_RemapSet(&g_nand_flash_ctrl, NAND_FLASH_ACCESS_LOGICAL_ADDRESS, NAND_FLASH_ACCESS_PHYSICAL_ADDRESS);

    assert(FSP_SUCCESS == err);


    /* Read a page of data. Though NAND_FLASH_ACCESS_LOGICAL_ADDRESS is set as an argument,
     * the NANDC peripheral actually reads the pages start from NAND_FLASH_ACCESS_PHYSICAL_ADDRESS. */
    err = R_NANDC_Read(&g_nand_flash_ctrl, &flash_page, &result_buffer, NAND_FLASH_CHIP_SELECT);

    assert(FSP_SUCCESS == err);

    while (!g_remap_read_complete)
    {
        /* Wait for command completion. */
    }


    /* Clear all the contents of the translation table. */
    err = R_NANDC_RemapClear(&g_nand_flash_ctrl);

    assert(FSP_SUCCESS == err);
}

void r_nandc_remap_read_callback (nand_flash_callback_args_t * p_args)
{
    if (NAND_FLASH_EVENT_READ_COMPLETE == p_args->event)
    {
        g_remap_read_complete = 1;
    }
}

Write Protect example

This example demonstrates the configuration of write protection.

#define NAND_FLASH_WRITE_PROTECT_START_ADDRESS    (NAND_FLASH_ACCESS_ROW_ADDRESS - 0x10)
#define NAND_FLASH_WRITE_PROTECT_REGION_SIZE      (0x20)
#define NANDC_EXAMPLE_WRITE_PROTECT_INDEX_0       (0)

uint8_t                g_write_protect_command_complete = 0;
uint8_t                g_write_protect_command_error    = 0;
nandc_command_status_t g_command_error_status;

void r_nandc_write_protect_example (void)
{
    /* Configure device page information to access. */
    nand_flash_device_page_t flash_page =
    {
        .row_address = NAND_FLASH_ACCESS_ROW_ADDRESS,
        .page_count  = 1,
    };

    /* Configure write source buffer address information. */
    nand_flash_data_buffer_t data_buffer =
    {
        .p_main_data_buffer = g_src,
        .p_oob_data_buffer  = g_src_spare, // Set control data if needed.
    };


    /* Open the NANDC driver. */
    fsp_err_t err = R_NANDC_Open(&g_nand_flash_ctrl, &g_nand_flash_cfg);

    assert(FSP_SUCCESS == err);

    /* Wait for the controller to get ready before re-map configuration. */
    nandc_controller_status_t ctrl_status;
    do
    {

        err = R_NANDC_ControllerStatusGet(&g_nand_flash_ctrl, &ctrl_status);

        assert(FSP_SUCCESS == err);
    } while (ctrl_status.status == NANDC_CONTROLLER_STATE_BUSY);


    /* Set write protect region that includes flash_page region.*/
    err = R_NANDC_WriteProtectEnable(&g_nand_flash_ctrl,
                                     NAND_FLASH_WRITE_PROTECT_START_ADDRESS,
                                     NAND_FLASH_WRITE_PROTECT_REGION_SIZE,
                                     NANDC_EXAMPLE_WRITE_PROTECT_INDEX_0);

    assert(FSP_SUCCESS == err);


    /* Write a page of data. An error will occur due to accessing the write-protected area. */
    err = R_NANDC_Write(&g_nand_flash_ctrl, &data_buffer, &flash_page, NAND_FLASH_CHIP_SELECT);

    assert(FSP_SUCCESS == err);

    while (!g_write_protect_command_error)
    {
        /* Wait for command error. */
    }

    /* Assert the protection error occurs.*/
    assert(g_command_error_status.nandc_command_status_bit.prot_err);


    /* Disable write protect region settings.*/
    err = R_NANDC_WriteProtectDisable(&g_nand_flash_ctrl, NANDC_EXAMPLE_WRITE_PROTECT_INDEX_0);

    assert(FSP_SUCCESS == err);

    /* Write a page of data. Data will be successfully written.*/
    err = R_NANDC_Write(&g_nand_flash_ctrl, &data_buffer, &flash_page, NAND_FLASH_CHIP_SELECT);

    assert(FSP_SUCCESS == err);

    while (!g_write_protect_command_complete)
    {
        /* Wait for command completion. */
    }
}

/* The callback is called when a command completes. */
void r_nandc_write_protect_example_callback (nand_flash_callback_args_t * p_args)
{
    if (NAND_FLASH_EVENT_WRITE_ERROR == p_args->event)
    {
        g_write_protect_command_error         = 1;
        g_command_error_status.command_status = p_args->error;
    }
    else if (NAND_FLASH_EVENT_WRITE_COMPLETE == p_args->event)
    {
        g_write_protect_command_complete = 1;
    }
    else
    {
        /* Do nothing. */
    }
}

Timeout example

This example demonstrates the sequence when timeout occurred.

nand_flash_event_t timeout_example_event;
uint8_t            g_command_end;

/* This example assumes that the Command Timeout Cycles is set to a value other than 0 in the configuration editor. */
void r_nandc_timeout_example (void)
{

    /* Open the NANDC driver. */
    fsp_err_t err = R_NANDC_Open(&g_nand_flash_ctrl, &g_nand_flash_cfg);

    assert(FSP_SUCCESS == err);


    /* Erase a block to access. */
    err = R_NANDC_Erase(&g_nand_flash_ctrl, NAND_FLASH_ACCESS_BLOCK, 1, NAND_FLASH_CHIP_SELECT);

    assert(FSP_SUCCESS == err);

    while (!g_command_end)
    {
        /* Wait for the command ends with completion, error, or timeout. */
    }

    if (NAND_FLASH_EVENT_ERASE_TIMEOUT == timeout_example_event)
    {

        /* When command timeout occurred, the controller and the NAND Flash should reset. */
        err = R_NANDC_DeviceReset(&g_nand_flash_ctrl, NAND_FLASH_CHIP_SELECT);

        assert(FSP_SUCCESS == err);
    }
}

void r_nandc_timeout_example_callback (nand_flash_callback_args_t * p_args)
{
    timeout_example_event = p_args->event;
    g_command_end         = 1;
}

Classes
struct	st_nandc_timing_info
struct	st_nandc_comnand_status
struct	st_nandc_controller_status
struct	st_nandc_instance_ctrl
struct	st_nandc_extended_cfg

Typedefs
typedef struct st_nandc_timing_info	nandc_timing_info_t
typedef struct st_nandc_comnand_status	nandc_command_status_t
typedef struct st_nandc_controller_status	nandc_controller_status_t
typedef struct st_nandc_instance_ctrl	nandc_instance_ctrl_t
typedef struct st_nandc_extended_cfg	nandc_extended_cfg_t

Enumerations
enum	nandc_timing_mode_t
enum	nandc_device_status_detection_t
enum	nandc_ecc_t
enum	nandc_ecc_correction_ability_t
enum	nandc_crc_t
enum	nandc_data_scrambling_t
enum	nandc_erased_page_flag_t
enum	nandc_multiplane_command_t
enum	nandc_multiplane_number_t
enum	nandc_remap_t
enum	nandc_int_t
enum	nandc_controller_state_t
enum	nandc_flash_timing_mode_t

---

Class Documentation

RZT::st_nandc_timing_info

struct RZT::st_nandc_timing_info

Timing information during communication with the NAND Flash

Class Members
uint32_t	we_pulse_width	WE_n pulse width cycles.
uint32_t	we_high_hold_time	WE_n high hold time cycles.
uint32_t	re_pulse_width	RE_n pulse width cycles.
uint32_t	re_high_hold_time	RE_n high hold time cycles.
uint32_t	re_high_to_we_low_time	RE_n high to WE_n low time cycles.
uint32_t	we_high_to_re_low_time	WE_n high to RE_n low time cycles.
uint32_t	ale_to_data_loading_time	ALE to data loading time cycles.
uint32_t	command_end_to_sr6_low	Command end timing to SR[6] low cycles.
uint32_t	re_high_to_output_hiz	RE_n high to output hi-Z cycles.
uint32_t	ce_setup_time	CE_n setup time cycles.
uint32_t	ce_high_hold_time	CE_n high hold time cycles.
uint32_t	interface_and_timing_mode_change_time	Interface and Timing Mode Change time cycles.

RZT::st_nandc_comnand_status

struct RZT::st_nandc_comnand_status

Command error status

RZT::st_nandc_controller_status

struct RZT::st_nandc_controller_status

Controller status

Class Members
nandc_controller_state_t	status	NANDC controller status is stored.

RZT::st_nandc_instance_ctrl

struct RZT::st_nandc_instance_ctrl

NAND_FLASH Instance Control Block. This is private to the FSP and should not be used or modified by the application

Public Attributes
uint32_t	open
	Boolean to verify that the Unit has been initialized.
nand_flash_cfg_t const *	p_cfg
	Pointer to initial configurations.
R_NANDC_Type *	p_reg
	Base register for this channel.
void(*	p_callback )(nand_flash_callback_args_t *)
	Pointer to callback.
nand_flash_callback_args_t *	p_callback_memory
	Pointer to optional callback argument memory.
void const *	p_context
	Pointer to context to be passed into callback function.

RZT::st_nandc_extended_cfg

struct RZT::st_nandc_extended_cfg

Optional NANDC extension data structure

Class Members
nandc_timing_mode_t	read_enable_signal_timing_mode	RE# timing mode.
nandc_timing_mode_t	write_enable_signal_timing_mode	WE# timing mode.
nandc_timing_info_t *	p_signal_timing_info	Settings of signal timing.
nandc_flash_timing_mode_t	flash_timing_mode	Timing Mode of NAND Flash defined in ONFI.
nandc_device_status_detection_t	ready_status_detection_method	Device status detection method.
uint32_t	long_polling_time	System clock cycles after issue of erase/write/read operation before the controller starts to poll for status.
uint32_t	short_polling_time	Subsequent status polling interval cycles.
uint32_t	sector_bytes	Sector size.
uint8_t	sector_number	Sector number per page.
uint32_t	oob_data_size	Size of Out-of-Band data handled by NANDC control data function.
nandc_ecc_t	ecc_enable	ECC setting.
nandc_ecc_correction_ability_t	ecc_correction_ability	Error correction ability for ECC.
nandc_crc_t	crc_enable	CRC setting.
uint32_t	command_timeout_count	Timeout cycles of NANDC thread operation.
nandc_data_scrambling_t	data_scrambling_enable	Scrambling setting.
nandc_erased_page_flag_t	erased_page_detection	Erased page detection setting.
uint8_t	erase_detection_level	Permissible number of 0 bits for erased page detection.
nandc_multiplane_command_t	multiplane_read_enable	Multi-plane read operation setting.
nandc_multiplane_command_t	multiplane_write_enable	Multi-plane write and erase operation setting.
nandc_multiplane_number_t	plane_number	Number of Planes in NAND Flash.
uint32_t	skip_bytes_offset	Offset of skipped bytes.
uint32_t	skip_bytes_size	Number of skipped bytes.
uint32_t	skip_bytes_marker_value	Byte pattern written in skipped bytes.
nandc_remap_t	remap_enable	Address translation setting.
uint32_t	remap_valid_bits	Row address bits that address translation is applied to.
nandc_int_t	command_complete_interrupt	Command complete interrupt source setting.
nandc_int_t	command_error_interrupt	Command error interrupt source setting.
nandc_int_t	command_timeout_interrupt	Command timeout interrupt source setting.
uint32_t	rb_valid_time_cycles	Time to wait for the R/B pin to become valid before device discovery (SYS_CLK cycles)
void *	p_reg	Base register.

Typedef Documentation

nandc_timing_info_t

typedef struct st_nandc_timing_info nandc_timing_info_t

Timing information during communication with the NAND Flash Please refer to the struct st_nandc_timing_info.

nandc_command_status_t

typedef struct st_nandc_comnand_status nandc_command_status_t

Command error status Please refer to the struct st_nandc_comnand_status.

nandc_controller_status_t

typedef struct st_nandc_controller_status nandc_controller_status_t

Controller status Please refer to the struct st_nandc_controller_status.

nandc_instance_ctrl_t

typedef struct st_nandc_instance_ctrl nandc_instance_ctrl_t

NAND_FLASH Instance Control Block. This is private to the FSP and should not be used or modified by the application Please refer to the struct st_nandc_instance_ctrl.

nandc_extended_cfg_t

typedef struct st_nandc_extended_cfg nandc_extended_cfg_t

Optional NANDC extension data structure Please refer to the struct st_nandc_extended_cfg.

Enumeration Type Documentation

nandc_timing_mode_t

enum nandc_timing_mode_t

Timing Mode

Enumerator
NANDC_TIMING_MODE_PERFORMANCE	Drive RE# / WE# signals in performance mode.
NANDC_TIMING_MODE_EXTEND	Drive RE# / WE# signals in extended mode.

nandc_device_status_detection_t

enum nandc_device_status_detection_t

Device status detection method

Enumerator
NANDC_DEVICE_STATUS_DETECTION_POLLING	Get NAND Flash device status by polling read status command.
NANDC_DEVICE_STATUS_DETECTION_RY_BY_PIN	Get NAND Flash device status by RY_BY# pin level.

nandc_ecc_t

enum nandc_ecc_t

ECC setting

Enumerator
NANDC_ECC_DISABLE	ECC disabled.
NANDC_ECC_ENABLE	ECC enabled.

nandc_ecc_correction_ability_t

enum nandc_ecc_correction_ability_t

Error correction ability for ECC

Enumerator
NANDC_ECC_CORRECTION_8_BITS	Insert ECC check-bits to enable correction of 8 bits per sector.
NANDC_ECC_CORRECTION_16_BITS	Insert ECC check-bits to enable correction of 16 bits per sector.
NANDC_ECC_CORRECTION_32_BITS	Insert ECC check-bits to enable correction of 32 bits per sector.
NANDC_ECC_CORRECTION_64_BITS	Insert ECC check-bits to enable correction of 64 bits per sector.
NANDC_ECC_CORRECTION_72_BITS	Insert ECC check-bits to enable correction of 72 bits per sector.

nandc_crc_t

enum nandc_crc_t

CRC setting

Enumerator
NANDC_CRC_DISABLE	CRC disabled.
NANDC_CRC_ENABLE	CRC enabled.

nandc_data_scrambling_t

enum nandc_data_scrambling_t

Scrambling function setting

Enumerator
NANDC_DATA_SCRAMBLING_DISABLE	Scrambling disabled.
NANDC_DATA_SCRAMBLING_ENABLE	Scrambling enabled.

nandc_erased_page_flag_t

enum nandc_erased_page_flag_t

Erased page detection setting

Enumerator
NANDC_ERASED_PAGE_FLAG_DISABLE	Erased page detection flag disabled.
NANDC_ERASED_PAGE_FLAG_ENABLE	Erased page detection flag enabled.

nandc_multiplane_command_t

enum nandc_multiplane_command_t

Multi-plane command setting

Enumerator
NANDC_MULTIPLANE_COMMAND_DISABLE	Multi-plane command sequence disabled.
NANDC_MULTIPLANE_COMMAND_ENABLE	multi-plane command sequence enabled

nandc_multiplane_number_t

enum nandc_multiplane_number_t

Number of planes of connected NAND Flash

Enumerator
NANDC_MULTIPLANE_NUMBER_1	Connected NAND Flash has 1 plane.
NANDC_MULTIPLANE_NUMBER_2	Connected NAND Flash has 2 planes.
NANDC_MULTIPLANE_NUMBER_4	Connected NAND Flash has 4 planes.
NANDC_MULTIPLANE_NUMBER_6	Connected NAND Flash has 6 planes.
NANDC_MULTIPLANE_NUMBER_8	Connected NAND Flash has 8 planes.

nandc_remap_t

enum nandc_remap_t

Address translation setting

Enumerator
NANDC_REMAP_DISABLE	Address translation for NAND Flash is disabled.
NANDC_REMAP_ENABLE	Address translation for NAND Flash is enabled.

nandc_int_t

enum nandc_int_t

NANDC interrupt source setting

Enumerator
NANDC_INT_DISABLE	The event is not used as NANDC interrupt source.
NANDC_INT_ENABLE	The event is used as NANDC interrupt source.

nandc_controller_state_t

enum nandc_controller_state_t

Controller status

Enumerator
NANDC_CONTROLLER_STATE_READY	The controller is in ready state.
NANDC_CONTROLLER_STATE_BUSY	The controller is in busy state.

nandc_flash_timing_mode_t

enum nandc_flash_timing_mode_t

Timing mode setting of connected NAND Flash

Enumerator
NANDC_FLASH_TIMING_MODE_0	Set timing configuration of connected NAND Flash to Timing Mode 0.
NANDC_FLASH_TIMING_MODE_1	Set timing configuration of connected NAND Flash to Timing Mode 1.
NANDC_FLASH_TIMING_MODE_2	Set timing configuration of connected NAND Flash to Timing Mode 2.
NANDC_FLASH_TIMING_MODE_3	Set timing configuration of connected NAND Flash to Timing Mode 3.

Function Documentation

R_NANDC_Open()

fsp_err_t R_NANDC_Open	(	nand_flash_ctrl_t *const	p_ctrl,
		nand_flash_cfg_t const *const	p_cfg
	)

Initialize the NANDC module and enables interrupts. Implements nand_flash_api_t::open.

Return values

FSP_SUCCESS	Initializes the NANDC module.
FSP_ERR_ALREADY_OPEN	NANDC module is open already.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_ABORTED	Failed Device Discovery process.

R_NANDC_Close()

fsp_err_t R_NANDC_Close

(

nand_flash_ctrl_t *const

p_ctrl

)

Close the NANDC module. Implements nand_flash_api_t::close.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver has not been initialized.

R_NANDC_Read()

fsp_err_t R_NANDC_Read	(	nand_flash_ctrl_t *const	p_ctrl,
		nand_flash_device_page_t const *const	p_src_page,
		nand_flash_data_buffer_t *const	p_dest_buffer,
		uint32_t const	chip_select
	)

Reads data from the NAND Flash. Implements nand_flash_api_t::read.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver has not been initialized.
FSP_ERR_INVALID_ARGUMENT	Device address information is invalid.
FSP_ERR_INVALID_STATE	Configurations of the controller are changed to access raw data.
FSP_ERR_DEVICE_BUSY	The thread is in busy state.
FSP_ERR_INVALID_ADDRESS	Destination address is invalid.

R_NANDC_Write()

fsp_err_t R_NANDC_Write	(	nand_flash_ctrl_t *const	p_ctrl,
		nand_flash_data_buffer_t const *const	p_src_buffer,
		nand_flash_device_page_t const *const	p_dest_page,
		uint32_t const	chip_select
	)

Program data to the NAND Flash. Implements nand_flash_api_t::write.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver has not been initialized.
FSP_ERR_INVALID_ARGUMENT	Device address information is invalid.
FSP_ERR_INVALID_STATE	Configurations of the controller are changed to access raw data.
FSP_ERR_DEVICE_BUSY	The thread is in busy state.
FSP_ERR_INVALID_ADDRESS	Source address is invalid.

R_NANDC_Erase()

fsp_err_t R_NANDC_Erase	(	nand_flash_ctrl_t *const	p_ctrl,
		uint32_t const	block,
		uint32_t const	block_count,
		uint32_t const	chip_select
	)

Erases block data in the NAND Flash. Implements nand_flash_api_t::erase.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver has not been initialized.
FSP_ERR_INVALID_STATE	Configurations of the controller are changed to access raw data.
FSP_ERR_INVALID_ARGUMENT	Device block information is invalid.
FSP_ERR_DEVICE_BUSY	The thread is in busy state.

R_NANDC_FeatureSet()

fsp_err_t R_NANDC_FeatureSet	(	nand_flash_ctrl_t *const	p_ctrl,
		uint32_t const	feature_address,
		uint32_t const	feature_value,
		uint32_t const	chip_select
	)

Send set feature command to the NAND Flash. Implements nand_flash_api_t::featureSet.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver has not been initialized.
FSP_ERR_DEVICE_BUSY	The thread is in busy state.

R_NANDC_DeviceReset()

fsp_err_t R_NANDC_DeviceReset	(	nand_flash_ctrl_t *const	p_ctrl,
		uint32_t const	chip_select
	)

Send reset command to the NAND Flash. Implements nand_flash_api_t::deviceReset.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver has not been initialized.
FSP_ERR_INVALID_STATE	Configurations of the controller are changed to access raw data.
FSP_ERR_DEVICE_BUSY	The thread is in busy state.

R_NANDC_StatusGet()

fsp_err_t R_NANDC_StatusGet	(	nand_flash_ctrl_t *const	p_ctrl,
		uint32_t const	chip_select,
		nand_flash_status_t *const	p_status
	)

Get the device status by checking whether the threads are ready or not. Implements nand_flash_api_t::statusGet.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver has not been initialized.

R_NANDC_CallbackSet()

fsp_err_t R_NANDC_CallbackSet	(	nand_flash_ctrl_t *const	p_ctrl,
		void(*)(nand_flash_callback_args_t *)	p_callback,
		void const *const	p_context,
		nand_flash_callback_args_t *const	p_callback_memory
	)

Updates the user callback with the option to provide memory for the callback argument structure. Implements nand_flash_api_t::callbackSet.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

R_NANDC_InfoGet()

fsp_err_t R_NANDC_InfoGet	(	nand_flash_ctrl_t *const	p_ctrl,
		nand_flash_device_info_t *const	p_info
	)

Get NAND Flash information obtained in Device Discovery process. Implements nand_flash_api_t::infoGet.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver has not been initialized.

R_NANDC_Copyback()

fsp_err_t R_NANDC_Copyback	(	nand_flash_ctrl_t *const	p_ctrl,
		nand_flash_device_page_t const *const	p_src_page,
		nand_flash_device_page_t const *const	p_dest_page,
		uint32_t const	chip_select
	)

Copy pages to another NAND Flash region. Implements nand_flash_api_t::copyback.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver has not been initialized.
FSP_ERR_INVALID_STATE	Configurations of the controller are changed to access raw data. Multi-plane configurations for read and write do not match.
FSP_ERR_INVALID_ARGUMENT	Device address information is invalid.
FSP_ERR_DEVICE_BUSY	The thread is in busy state.

R_NANDC_RawRead()

fsp_err_t R_NANDC_RawRead	(	nand_flash_ctrl_t *const	p_ctrl,
		nand_flash_device_page_t const *const	p_src_page,
		uint8_t *const	p_dest,
		uint32_t const	chip_select
	)

Reads raw data from the NAND Flash. Implements nand_flash_api_t::rawRead.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver has not been initialized.
FSP_ERR_INVALID_ARGUMENT	Device address information is invalid.
FSP_ERR_DEVICE_BUSY	The thread is in busy state.
FSP_ERR_INVALID_STATE	Command complete interrupt is disabled. This function can only be used when command complete interrupt is enabled. Another access to raw data is in progress.
FSP_ERR_INVALID_ADDRESS	Destination address is invalid.

Note

This function accesses all bytes on the selected pages, independent of sector configurations. Therefore, confirm the number of bytes per page for the connected NAND Flash, and prepare the data buffer for all bytes of the pages to be accessed.

R_NANDC_RawWrite()

fsp_err_t R_NANDC_RawWrite	(	nand_flash_ctrl_t *const	p_ctrl,
		uint8_t const *const	p_src,
		nand_flash_device_page_t const *const	p_dest_page,
		uint32_t const	chip_select
	)

Program data to the NAND Flash. Implements nand_flash_api_t::rawWrite.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver has not been initialized.
FSP_ERR_INVALID_ARGUMENT	Device address information is invalid.
FSP_ERR_DEVICE_BUSY	The thread is in busy state.
FSP_ERR_INVALID_STATE	Command complete interrupt is disabled. This function can only be used when command complete interrupt is enabled. Another access to raw data is in progress.
FSP_ERR_INVALID_ADDRESS	Source address is invalid.

Note

This function accesses all bytes on the selected pages, independent of sector configurations. Therefore, confirm the number of bytes per page for the connected NAND Flash, and prepare the source data for all bytes of the pages to be accessed.

R_NANDC_RemapSet()

fsp_err_t R_NANDC_RemapSet	(	nand_flash_ctrl_t *const	p_ctrl,
		uint32_t const	logical_address,
		uint32_t const	physical_address
	)

Set logical address to physical address mapping table in NANDC.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver has not been initialized.
FSP_ERR_INVALID_ARGUMENT	Device address information is invalid.
FSP_ERR_DEVICE_BUSY	The thread is in busy state.

R_NANDC_RemapClear()

fsp_err_t R_NANDC_RemapClear

(

nand_flash_ctrl_t *const

p_ctrl

)

Clear all data in logical address to physical address mapping table in NANDC.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver has not been initialized.
FSP_ERR_DEVICE_BUSY	The thread is in busy state.

R_NANDC_WriteProtectEnable()

fsp_err_t R_NANDC_WriteProtectEnable	(	nand_flash_ctrl_t *const	p_ctrl,
		uint32_t const	start_address,
		uint32_t const	size,
		uint32_t const	index
	)

Get the controller status by checking whether the controller is ready or not.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver has not been initialized.
FSP_ERR_INVALID_ARGUMENT	Device address information is invalid. Index exceeds the number of the write-protected address ranges that the controller can set.
FSP_ERR_DEVICE_BUSY	The thread is in busy state.

Note

NANDC can specify up to two write-protected address ranges. Therefore, index should be set to 0 or 1.

R_NANDC_WriteProtectDisable()

fsp_err_t R_NANDC_WriteProtectDisable	(	nand_flash_ctrl_t *const	p_ctrl,
		uint32_t const	index
	)

Clear the address range to protect write access.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver has not been initialized.
FSP_ERR_INVALID_ARGUMENT	Index exceeds the number of the address range that the controller can set as write protect.
FSP_ERR_DEVICE_BUSY	The thread is in busy state.

R_NANDC_ControllerStatusGet()

fsp_err_t R_NANDC_ControllerStatusGet	(	nand_flash_ctrl_t *const	p_ctrl,
		nandc_controller_status_t *const	p_status
	)

Get the device status by checking whether the controller is ready or not.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver has not been initialized.