Functions
fsp_err_t	R_DMAC_B_Open (transfer_ctrl_t const p_api_ctrl, transfer_cfg_t const const p_cfg)

fsp_err_t	R_DMAC_B_Reconfigure (transfer_ctrl_t const p_api_ctrl, transfer_info_t p_info)

fsp_err_t	R_DMAC_B_Reset (transfer_ctrl_t const p_api_ctrl, void const volatile p_src, void *volatile p_dest, uint16_t const num_transfers)

fsp_err_t	R_DMAC_B_SoftwareStart (transfer_ctrl_t *const p_api_ctrl, transfer_start_mode_t mode)

fsp_err_t	R_DMAC_B_SoftwareStop (transfer_ctrl_t *const p_api_ctrl)

fsp_err_t	R_DMAC_B_Enable (transfer_ctrl_t *const p_api_ctrl)

fsp_err_t	R_DMAC_B_Disable (transfer_ctrl_t *const p_api_ctrl)

fsp_err_t	R_DMAC_B_InfoGet (transfer_ctrl_t const p_api_ctrl, transfer_properties_t const p_info)

fsp_err_t	R_DMAC_B_Close (transfer_ctrl_t *const p_api_ctrl)

fsp_err_t	R_DMAC_B_Reload (transfer_ctrl_t const p_api_ctrl, void const p_src, void *p_dest, uint32_t const num_transfers)

fsp_err_t	R_DMAC_B_CallbackSet (transfer_ctrl_t const p_api_ctrl, void(p_callback)(dmac_b_callback_args_t ), void const p_context, dmac_b_callback_args_t *const p_callback_memory)

Detailed Description

Driver for the DMAC peripheral on RZ MPUs. This module implements the Transfer Interface.

Overview

The Direct Memory Access Controller (DMAC) transfers data from one memory location to another without using the CPU.

Features

Supports multiple transfer modes
- Normal transfer
- Block transfer
Support Register mode
Supports Next0 Register set and Next1 Register set
Address increment, fixed
Triggered by peripheral module events
- See "Table On-Chip Module Requests"¹ or "Table DMA Transfer Request Detection Operation Setting Table"² in the user's manual
Supports 1, 2, 4, 8, 16, 32, 64, 128 byte data units
Configurable DMA transfer activation request source, detection method of DMA request signal and DACK output mode
Configurable DMA transfer interval
Configurable DMAC channel priority

Note: 1. RZ/V2L; 2. RZ/V2H and RZ/V2N

Configuration

Build Time Configurations for r_dmac_b

The following build time configurations are defined in fsp_cfg/r_dmac_b_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.

Configurations for Transfer > Transfer Driver on r_dmac_b

This module can be added to the Stacks tab via New Stack > Transfer > Transfer Driver on r_dmac_b.

Configuration	Options	Default	Description
Name	Name must be a valid C symbol	g_transfer0	Module name.
Unit	MCU Specific Options		Specify the hardware unit. In a multi-core environment, it is recommended to open a separate unit for each core.
Channel	Must be a valid integer between 0 and 15.	0	Specify the hardware channel.
Mode	Normal Block	Normal	Select the transfer mode.
Source Data Size	1 Byte 2 Bytes 4 Bytes 8 Bytes 16 Bytes 32 Bytes 64 Bytes 128 Bytes	2 Bytes	Select the source data size.
Destination Data Size	1 Byte 2 Bytes 4 Bytes 8 Bytes 16 Bytes 32 Bytes 64 Bytes 128 Bytes	2 Bytes	Select the destination data size.
Destination Address Mode	Incremented Fixed	Incremented	Select the address mode for the destination.
Source Address Mode	Incremented Fixed	Incremented	Select the address mode for the source.
Activation Source	MCU Specific Options		Select the DMAC transfer start event.
DMA Activation Request Source Select	Requested by a transfer source module Requested by a transfer destination module	Requested by a transfer source module	DMA Activation Request Source Select.
DACK Output mode	MCU Specific Options		Select DACK output mode.
External DREQ Input Pin Select	MCU Specific Options		Select DREQ input signal.
External DACK Output Pin Select	MCU Specific Options		Select DACK output signal.
External TEND Output Pin Select	MCU Specific Options		Select TEND output signal.
External DREQ Detection Mode	MCU Specific Options		External DREQ detection mode select.(This cannot be set on devices that do not have an external DREQ terminal)
DMAC Mode	Register Mode	Register Mode	Select DMAC Mode.
Callback	Name must be a valid C symbol	NULL	A user callback that is called at the end of the transfer.
Context	Manual Entry	NULL	Pointer to the context structure passed through the callback argument.
Transfer End Interrupt Enable	MCU Specific Options		Enable the transfer end interrupt.
Transfer End Interrupt Priority	Value must be an integer between 0 and 255	12	Select the transfer end interrupt priority.
Transfer Interval	Value must be a non-negative integer	0	Transfer interval
Channel Priority	Fixed Round Robin	Fixed	Channel Priority
Transfer Continuation	DMA transfer only once Transfer with Setting 1 and Setting 2 alternately	DMA transfer only once	When Next0 Register Set Transfer completes, Next1 Register Set Transfer occurs
Setting 1 Destination Address	Manual Entry	NULL	Specify the transfer destination address.
Setting 1 Source Address	Manual Entry	NULL	Specify the transfer source address.
Setting 1 Total Number of Transfer Bytes	Value must be a non-negative integer	1	Specify the total number of transfer bytes.
Setting 2 Destination Address	Manual Entry	NULL	Specify the transfer destination address.(Use only when Transfer with Setting 1 and Setting 2 horizontally is selected in Transfer Continuatuion.)
Setting 2 Source Address	Manual Entry	NULL	Specify the transfer source address.(Use only when Transfer with Setting 1 and Setting 2 horizontally is selected in Transfer Continuatuion.)
Setting 2 Total Number of Transfer Bytes	Value must be a non-negative integer	1	Specify the total number of transfer bytes.(Use only when Transfer with Setting 1 and Setting 2 horizontally is selected in Transfer Continuatuion.)

Warning: "DMA Activation Request Source Select", "Low Detection Enable", "High Detection Enable", and "DACK output" must be set according to the DMAC transfer request source. For details, see 'DMA Transfer Request Detection Operation Setting Table' of the user's manual.

Clock Configuration

The clock sources for the DMAC peripheral module vary depending on the device. These clocks are shown in the table below.

MPU Group	Clock Name
RZ/V2L	P1CLK
RZ/V2H	I7CLK (for Unit 0), P7CLK (for Unit 1, 2), P11CLK (for Unit 3, 4)
RZ/V2N	I7CLK (for Unit 0), P7CLK (for Unit 1, 2), P11CLK (for Unit 3, 4)

Pin Configuration

This module can use DREQn, DACKn and TENDn pins as external pins¹ (n = 0~4).

DREQn is used for external DMA transfer request input from an external device.
DACKn is used for output of DMAC transfer request acceptance to an external device.
TENDn is used for output of transfer completion to an external device.

Note: 1. RZ/V2H and RZ/V2N only support

Usage Notes

Transfer Modes

The DMAC Module supports two modes of operation.

Normal Mode - In normal mode, a single data unit is forwarded each time a configured peripheral module event is received by the DMAC channel. The data unit can be 1 byte, 2 bytes, 4 bytes, 8 bytes, 16 bytes, 32 bytes, 64 bytes, or 128 bytes. The source and destination addresses can be fixed or incremented. The 32-bit counter decrements on every transfer. When the counter reaches 0, the peripheral module event no longer triggers the transfer and you can interrupt the CPU to signal that all transfers have finished.
Block Mode - In block mode, the amount of data units transfered by each interrupt. For one DMA request, performs transfers until a DMA transfer completes. When the counter reaches 0, transfers will no longer be triggered by the peripheral module event and the CPU can be interrupted to signal that all transfers have finished.

Limitations

This driver only supports the transfer by non-secure access. Also, DMA transfer cannot be performed to the slave area for which the security level has been set. Therefore, for slave areas with a security level set, be sure to change the slave level appropriately before performing a DMA transfer.

If CPU has built-in cache memory, the transfer source and destination should be placed to the area where the cache memory is set to disabled.

The execution of the Reload function must be completed during the transfer of Next0 or Next1. If the total number of bytes transferred is small, the next transfer may start before the function execution completes. In this case, continuous operation of DMAC transfer is not guaranteed, so when using the Reload function, it is recommended to set the number of bytes to be transferred a little longer, taking into account the bus clock frequency and interrupt processing time.

Examples

Basic Example

This is a basic example of minimal use of the DMAC in an application.

void dmac_minimal_example (void)
{
    /* Open the transfer instance with initial configuration. */
    fsp_err_t err = R_DMAC_B_Open(&g_transfer_ctrl, &g_transfer_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
    /* Enable the DMAC to handle incoming transfer requests. */
    err = R_DMAC_B_Enable(&g_transfer_ctrl);
    assert(FSP_SUCCESS == err);
}

Classes
struct	st_dmac_b_register_set_setting_t

struct	st_dmac_b_instance_ctrl

struct	st_dmac_b_extended_cfg

struct	st_dmac_b_extended_info

Typedefs
typedef struct st_dmac_b_register_set_setting_t	dmac_b_register_set_setting_t

typedef struct st_dmac_b_instance_ctrl	dmac_b_instance_ctrl_t

typedef struct st_dmac_b_extended_cfg	dmac_b_extended_cfg_t

typedef struct st_dmac_b_extended_info	dmac_b_extended_info_t

Enumerations
enum	dmac_b_transfer_size_t

enum	dmac_b_ack_mode_t

enum	dmac_b_external_detection_t

enum	dmac_b_internal_detection_t

enum	dmac_b_request_direction_t

enum	dmac_b_continuous_setting_t

enum	dmac_b_channel_scheduling_t

enum	dmac_b_mode_select_t

Class Documentation

◆ RZV::st_dmac_b_register_set_setting_t

struct RZV::st_dmac_b_register_set_setting_t

Register set settings.

Class Members
void const *	p_src	Source pointer.
void *	p_dest	Destination pointer.
uint32_t	length	Transfer byte.

◆ RZV::st_dmac_b_instance_ctrl

struct RZV::st_dmac_b_instance_ctrl

Control block used by driver. DO NOT INITIALIZE - this structure will be initialized in transfer_api_t::open.

◆ RZV::st_dmac_b_extended_cfg

struct RZV::st_dmac_b_extended_cfg

DMAC transfer configuration extension. This extension is required.

Public Attributes
uint8_t	unit
	Unit number.

uint8_t	channel
	Channel number.

IRQn_Type	dmac_int_irq
	DMAC interrupt number.

uint8_t	dmac_int_ipl
	DMAC interrupt priority.

dmac_trigger_event_t	activation_source

dmac_b_ack_mode_t	ack_mode
	DACK output mode.

dmac_b_external_input_pin_t	dreq_input_pin
	DREQ input pin name.

dmac_b_external_output_pin_t	ack_output_pin
	DACK output pin name.

dmac_b_external_output_pin_t	tend_output_pin
	TEND output pin name.

dmac_b_external_detection_t	external_detection_mode
	DMAC request detection method for external pin.

dmac_b_internal_detection_t	internal_detection_mode
	DMAC request detection method for internal pin.

dmac_b_request_direction_t	activation_request_source_select
	DMAC activation request source.

dmac_b_mode_select_t	dmac_mode
	DMAC Mode.

dmac_b_continuous_setting_t	continuous_setting
	Next register operation settings.

uint16_t	transfer_interval
	DMA transfer interval.

dmac_b_channel_scheduling_t	channel_scheduling
	DMA channel scheduling.

void(*	p_callback )(dmac_b_callback_args_t *cb_data)

void *	p_context

Member Data Documentation

◆ activation_source

dmac_trigger_event_t activation_source

Select which event will trigger the transfer.

◆ p_callback

void(* p_callback) (dmac_b_callback_args_t *cb_data)

Callback for transfer end interrupt.

◆ p_context

void* p_context

Placeholder for user data. Passed to the user p_callback in RZV::transfer_callback_args_t.

◆ RZV::st_dmac_b_extended_info

struct RZV::st_dmac_b_extended_info

DMAC transfer information configuration extension. This extension is required.

Class Members
dmac_b_transfer_size_t	src_size	Select number of source bytes to transfer at once.
dmac_b_transfer_size_t	dest_size	Select number of destination bytes to transfer at once.
dmac_b_register_set_setting_t *	p_next1_register_setting	Next1 Register set settings

Typedef Documentation

◆ dmac_b_register_set_setting_t

typedef struct st_dmac_b_register_set_setting_t dmac_b_register_set_setting_t

Register set settings. Please refer to the struct st_dmac_b_register_set_setting_t.

◆ dmac_b_instance_ctrl_t

typedef struct st_dmac_b_instance_ctrl dmac_b_instance_ctrl_t

Control block used by driver. DO NOT INITIALIZE - this structure will be initialized in transfer_api_t::open. Please refer to the struct st_dmac_b_instance_ctrl.

◆ dmac_b_extended_cfg_t

typedef struct st_dmac_b_extended_cfg dmac_b_extended_cfg_t

DMAC transfer configuration extension. This extension is required. Please refer to the struct st_dmac_b_extended_cfg.

◆ dmac_b_extended_info_t

typedef struct st_dmac_b_extended_info dmac_b_extended_info_t

DMAC transfer information configuration extension. This extension is required. Please refer to the struct st_dmac_b_extended_info.

Enumeration Type Documentation

◆ dmac_b_transfer_size_t

enum dmac_b_transfer_size_t

Transfer size specifies the size of each individual transfer.

Enumerator
DMAC_B_TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
DMAC_B_TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
DMAC_B_TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
DMAC_B_TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
DMAC_B_TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
DMAC_B_TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
DMAC_B_TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
DMAC_B_TRANSFER_SIZE_128_BYTE	Each transfer transfers a 1024-bit value.

◆ dmac_b_ack_mode_t

enum dmac_b_ack_mode_t

DACK output mode.

Enumerator
DMAC_B_ACK_MODE_LEVEL_MODE	Level mode.
DMAC_B_ACK_MODE_BUS_CYCLE_MODE	Bus cycle mode.
DMAC_B_ACK_MODE_MASK_DACK_OUTPUT	Output is masked.

◆ dmac_b_external_detection_t

enum dmac_b_external_detection_t

Detection method of the external DMA request signal.

Enumerator
DMAC_B_EXTERNAL_DETECTION_LOW_LEVEL	Low level detection.
DMAC_B_EXTERNAL_DETECTION_FALLING_EDGE	Falling edge detection.
DMAC_B_EXTERNAL_DETECTION_RISING_EDGE	Rising edge detection.
DMAC_B_EXTERNAL_DETECTION_FALLING_RISING_EDGE	Falling/Rising edge detection.
DMAC_B_EXTERNAL_DETECTION_NO_DETECTION	Not using hardware detection.

◆ dmac_b_internal_detection_t

enum dmac_b_internal_detection_t

Detection method of the internal DMA request signal.

Enumerator
DMAC_B_INTERNAL_DETECTION_NO_DETECTION	Not using hardware detection.
DMAC_B_INTERNAL_DETECTION_FALLING_EDGE	Falling edge detection.
DMAC_B_INTERNAL_DETECTION_RISING_EDGE	Rising edge detection.
DMAC_B_INTERNAL_DETECTION_LOW_LEVEL	Low level detection.
DMAC_B_INTERNAL_DETECTION_HIGH_LEVEL	High level detection.

◆ dmac_b_request_direction_t

enum dmac_b_request_direction_t

DMA activation request source select.

Enumerator
DMAC_B_REQUEST_DIRECTION_SOURCE_MODULE	Requested by a transfer source module.
DMAC_B_REQUEST_DIRECTION_DESTINATION_MODULE	Requested by a transfer destination module.

◆ dmac_b_continuous_setting_t

enum dmac_b_continuous_setting_t

Select the Next register set to be executed next.

Enumerator
DMAC_B_CONTINUOUS_SETTING_TRANSFER_ONCE	Transfer only once using the Next0 register set.
DMAC_B_CONTINUOUS_SETTING_TRANSFER_ALTERNATELY	Transfers are performed alternately with the Next0 register set and the Next1 register set.

◆ dmac_b_channel_scheduling_t

enum dmac_b_channel_scheduling_t

DMAC channel scheduling.

Enumerator
DMAC_B_CHANNEL_SCHEDULING_FIXED	Fixed priority mode.
DMAC_B_CHANNEL_SCHEDULING_ROUND_ROBIN	Round-robin mode.

◆ dmac_b_mode_select_t

enum dmac_b_mode_select_t

DMAC mode setting.

Enumerator
DMAC_B_MODE_SELECT_REGISTER	Register mode.
DMAC_B_MODE_SELECT_LINK	Link mode.

Function Documentation

◆ R_DMAC_B_Open()

fsp_err_t R_DMAC_B_Open	(	transfer_ctrl_t *const	p_api_ctrl,
		transfer_cfg_t const *const	p_cfg
	)

Configure a DMAC channel.

Return values

FSP_SUCCESS	Successful open.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	The configured channel is invalid.
FSP_ERR_IRQ_BSP_DISABLED	The IRQ associated with the activation source is not enabled in the BSP.
FSP_ERR_ALREADY_OPEN	The control structure is already opened.

◆ R_DMAC_B_Reconfigure()

fsp_err_t R_DMAC_B_Reconfigure	(	transfer_ctrl_t *const	p_api_ctrl,
		transfer_info_t *	p_info
	)

Reconfigure the transfer with new transfer info.

Return values

FSP_SUCCESS	Transfer is configured and will start when trigger occurs.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_ENABLED	DMAC is not enabled. The current configuration must not be valid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.

◆ R_DMAC_B_Reset()

fsp_err_t R_DMAC_B_Reset	(	transfer_ctrl_t *const	p_api_ctrl,
		void const *volatile	p_src,
		void *volatile	p_dest,
		uint16_t const	num_transfers
	)

Reset transfer source, destination, and number of transfers.

Return values

FSP_ERR_UNSUPPORTED API not supported.

◆ R_DMAC_B_SoftwareStart()

fsp_err_t R_DMAC_B_SoftwareStart	(	transfer_ctrl_t *const	p_api_ctrl,
		transfer_start_mode_t	mode
	)

If the mode is TRANSFER_START_MODE_SINGLE initiate a single transfer with software. If the mode is TRANSFER_START_MODE_REPEAT continue triggering transfers until all of the transfers are completed.

Return values

FSP_SUCCESS	Transfer started written successfully.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.

◆ R_DMAC_B_SoftwareStop()

fsp_err_t R_DMAC_B_SoftwareStop ( transfer_ctrl_t *const p_api_ctrl )

Stop software transfers if they were started with TRANSFER_START_MODE_REPEAT.

Return values

FSP_SUCCESS	Transfer stopped written successfully.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.

◆ R_DMAC_B_Enable()

fsp_err_t R_DMAC_B_Enable ( transfer_ctrl_t *const p_api_ctrl )

Enable transfers for the configured activation source.

Return values

FSP_SUCCESS	Counter value written successfully.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.

◆ R_DMAC_B_Disable()

fsp_err_t R_DMAC_B_Disable ( transfer_ctrl_t *const p_api_ctrl )

Disable transfers so that they are no longer triggered by the activation source.

Return values

FSP_SUCCESS	Counter value written successfully.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.

◆ R_DMAC_B_InfoGet()

fsp_err_t R_DMAC_B_InfoGet	(	transfer_ctrl_t *const	p_api_ctrl,
		transfer_properties_t *const	p_info
	)

Set driver specific information in provided pointer.

Return values

FSP_SUCCESS	Information has been written to p_info.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.
FSP_ERR_ASSERTION	An input parameter is invalid.

◆ R_DMAC_B_Close()

fsp_err_t R_DMAC_B_Close ( transfer_ctrl_t *const p_api_ctrl )

Disable transfer and clean up internal data. Implements transfer_api_t::close.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.

◆ R_DMAC_B_Reload()

fsp_err_t R_DMAC_B_Reload	(	transfer_ctrl_t *const	p_api_ctrl,
		void const *volatile	p_src,
		void *volatile	p_dest,
		uint32_t const	num_transfers
	)

Make the following transfer settings to continue the transfer.

Return values

FSP_SUCCESS	Successful continuous transfer settings.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.

◆ R_DMAC_B_CallbackSet()

fsp_err_t R_DMAC_B_CallbackSet	(	transfer_ctrl_t *const	p_api_ctrl,
		void()(dmac_b_callback_args_t )	p_callback,
		void *const	p_context,
		dmac_b_callback_args_t *const	p_callback_memory
	)

Updates the user callback with the option to provide memory for the callback argument structure. Implements transfer_api_t::callbackSet.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

Functions

Detailed Description

Overview

Features

Configuration

Build Time Configurations for r_dmac_b

Configurations for Transfer > Transfer Driver on r_dmac_b

Clock Configuration

Pin Configuration

Usage Notes

Transfer Modes

Limitations

Examples

Basic Example

Classes

Typedefs

Enumerations

Class Documentation

◆ RZV::st_dmac_b_register_set_setting_t

◆ RZV::st_dmac_b_instance_ctrl

◆ RZV::st_dmac_b_extended_cfg

Public Attributes

Member Data Documentation

◆ activation_source

◆ p_callback

◆ p_context

◆ RZV::st_dmac_b_extended_info

Typedef Documentation

◆ dmac_b_register_set_setting_t

◆ dmac_b_instance_ctrl_t

◆ dmac_b_extended_cfg_t

◆ dmac_b_extended_info_t

Enumeration Type Documentation

◆ dmac_b_transfer_size_t

◆ dmac_b_ack_mode_t

◆ dmac_b_external_detection_t

◆ dmac_b_internal_detection_t

◆ dmac_b_request_direction_t

◆ dmac_b_continuous_setting_t

◆ dmac_b_channel_scheduling_t

◆ dmac_b_mode_select_t

Function Documentation

◆ R_DMAC_B_Open()

◆ R_DMAC_B_Reconfigure()

◆ R_DMAC_B_Reset()

◆ R_DMAC_B_SoftwareStart()

◆ R_DMAC_B_SoftwareStop()

◆ R_DMAC_B_Enable()

◆ R_DMAC_B_Disable()

◆ R_DMAC_B_InfoGet()

◆ R_DMAC_B_Close()

◆ R_DMAC_B_Reload()

◆ R_DMAC_B_CallbackSet()