Controller Area Network - Flexible Data (r_canfd)

Functions
fsp_err_t	R_CANFD_Open (can_ctrl_t *const p_api_ctrl, can_cfg_t const *const p_cfg)
fsp_err_t	R_CANFD_Close (can_ctrl_t *const p_api_ctrl)
fsp_err_t	R_CANFD_Write (can_ctrl_t *const p_api_ctrl, uint32_t const buffer, can_frame_t *const p_frame)
fsp_err_t	R_CANFD_Read (can_ctrl_t *const p_api_ctrl, uint32_t const buffer, can_frame_t *const p_frame)
fsp_err_t	R_CANFD_ModeTransition (can_ctrl_t *const p_api_ctrl, can_operation_mode_t operation_mode, can_test_mode_t test_mode)
fsp_err_t	R_CANFD_InfoGet (can_ctrl_t *const p_api_ctrl, can_info_t *const p_info)
fsp_err_t	R_CANFD_CallbackSet (can_ctrl_t *const p_api_ctrl, void(*p_callback)(can_callback_args_t *), void const *const p_context, can_callback_args_t *const p_callback_memory)

Detailed Description

Driver for the CANFD peripheral on RZ MPUs. This module implements the CAN Interface.

Overview

The CANFD module can be used to communicate over CAN networks, optionally using Flexible Data (CAN-FD) to accelerate the data phase. A variety of message filtering and buffer options are available.

Features

Common Features

• Compatibility
  • Send and receive Classical CAN and CAN-FD frames on the same channel
  • Bitrate up to 1 Mbps with FD data phase speeds up to 4 Mbps
  • Supports both ISO 11898-1
• Buffers
  • 32 global receive Message Buffers (RX MBs)
  • 8 global receive FIFOs (RX FIFOs)
  • 16 transmit Message Buffers (TX MBs) per channel
• Filtering
  • Up to 128 filter rules across both channels
  • Each filter rule can be individually configured to accept messages based on:
    • ID
    • Standard or Extended ID (IDE bit)
    • Data or Remote Frame (RTR bit)
    • ID/IDE/RTR mask
    • Minimum DLC (data length) value
• Interrupts
  • Configurable Global RX FIFO Interrupt
    • Configurable per FIFO
    • Interrupt at a certain depth or on every received message
  • Channel TX Interrupt
  • Global Error
    • DLC Check
    • Message Lost
    • FD Payload Overflow
  • Channel Error
    • Bus Error
    • Error Warning
    • Error Passive
    • Bus-Off Entry
    • Bus-Off Recovery
    • Overload
    • Bus Lock
    • Arbitration Loss
    • Transmission Aborted

Per-MPU Specifications

	RZ/A3UL
Channels	2
Max nominal bitrate	1 Mbps
Max data bitrate	4 Mbps
Filter rules	128
TX message buffers	16/ch
RX message buffers	32
RX FIFOs	8
RX Buffer RAM	4864 bytes
Standards	ISO

Note

Each message buffer comprises 12 header bytes plus data length (8-64 bytes). The above buffer RAM values therefore correspond to the following capacities:

	RZ/A3UL
Max 64-byte storage	64 messages
Max 8-byte storage	243 messages

Configuration

Build Time Configurations for r_canfd

The following build time configurations are defined in fsp_cfg/r_canfd_cfg.h:

Configuration	Options	Default	Description
Global Error Interrupt > Priority	Value must be an integer between 0 and 31	24	This interrupt is fired for each of the error sources selected below.
Global Error Interrupt > Sources	MCU Specific Options		Select which errors should trigger an interrupt.
Global Error Interrupt > Callback Channel	Channel 0 Channel 1	Channel 1	Specify which channel callback should be called to handle global errors. When starting the driver this channel must be opened first.
Flexible Data (FD) > Protocol Exceptions	MCU Specific Options		Select whether to enter the protocol exception handling state when a RES bit is sampled recessive as defined in ISO 11898-1.
Flexible Data (FD) > Payload Overflow	MCU Specific Options		Configure whether received messages larger than the destination buffer should be truncated or rejected.
Reception > Message Buffers > Number of Buffers	RX Message Buffer number must be an integer between 0 and 32.	0	Number of message buffers available for reception. As there is no interrupt for message buffer reception it is recommended to use RX FIFOs instead. Set this value to 0 to disable RX Message Buffers.
Reception > Message Buffers > Payload Size	MCU Specific Options		Payload size for all RX Message Buffers.
Reception > FIFOs > FIFO 0 > Enable	Enabled Disabled	Enabled	Enable or disable RX FIFO 0.
Reception > FIFOs > FIFO 0 > Interrupt Mode	MCU Specific Options		Set the interrupt mode for RX FIFO 0. Threshold mode will only fire an interrupt each time an incoming message crosses the threshold value set below.
Reception > FIFOs > FIFO 0 > Interrupt Threshold	MCU Specific Options		Set the interrupt threshold value for RX FIFO 0. This setting is only applicable when the Interrupt Mode is set to 'At Threshold Value'.
Reception > FIFOs > FIFO 0 > Payload Size	MCU Specific Options		Select the message payload size for RX FIFO 0.
Reception > FIFOs > FIFO 0 > Depth	MCU Specific Options		Select the number of stages for RX FIFO 0.
Reception > FIFOs > FIFO 1 > Enable	Enabled Disabled	Disabled	Enable or disable RX FIFO 1.
Reception > FIFOs > FIFO 1 > Interrupt Mode	MCU Specific Options		Set the interrupt mode for RX FIFO 1. Threshold mode will only fire an interrupt each time an incoming message crosses the threshold value set below.
Reception > FIFOs > FIFO 1 > Interrupt Threshold	MCU Specific Options		Set the interrupt threshold value for RX FIFO 1. This setting is only applicable when the Interrupt Mode is set to 'At Threshold Value'.
Reception > FIFOs > FIFO 1 > Payload Size	MCU Specific Options		Select the message payload size for RX FIFO 1.
Reception > FIFOs > FIFO 1 > Depth	MCU Specific Options		Select the number of stages for RX FIFO 1.
Reception > FIFOs > FIFO 2 > Enable	Enabled Disabled	Disabled	Enable or disable RX FIFO 2.
Reception > FIFOs > FIFO 2 > Interrupt Mode	MCU Specific Options		Set the interrupt mode for RX FIFO 2. Threshold mode will only fire an interrupt each time an incoming message crosses the threshold value set below.
Reception > FIFOs > FIFO 2 > Interrupt Threshold	MCU Specific Options		Set the interrupt threshold value for RX FIFO 2. This setting is only applicable when the Interrupt Mode is set to 'At Threshold Value'.
Reception > FIFOs > FIFO 2 > Payload Size	MCU Specific Options		Select the message payload size for RX FIFO 2.
Reception > FIFOs > FIFO 2 > Depth	MCU Specific Options		Select the number of stages for RX FIFO 2.
Reception > FIFOs > FIFO 3 > Enable	Enabled Disabled	Disabled	Enable or disable RX FIFO 3.
Reception > FIFOs > FIFO 3 > Interrupt Mode	MCU Specific Options		Set the interrupt mode for RX FIFO 3. Threshold mode will only fire an interrupt each time an incoming message crosses the threshold value set below.
Reception > FIFOs > FIFO 3 > Interrupt Threshold	MCU Specific Options		Set the interrupt threshold value for RX FIFO 3. This setting is only applicable when the Interrupt Mode is set to 'At Threshold Value'.
Reception > FIFOs > FIFO 3 > Payload Size	MCU Specific Options		Select the message payload size for RX FIFO 3.
Reception > FIFOs > FIFO 3 > Depth	MCU Specific Options		Select the number of stages for RX FIFO 3.
Reception > FIFOs > FIFO 4 > Enable	Enabled Disabled	Disabled	Enable or disable RX FIFO 4.
Reception > FIFOs > FIFO 4 > Interrupt Mode	MCU Specific Options		Set the interrupt mode for RX FIFO 4. Threshold mode will only fire an interrupt each time an incoming message crosses the threshold value set below.
Reception > FIFOs > FIFO 4 > Interrupt Threshold	MCU Specific Options		Set the interrupt threshold value for RX FIFO 4. This setting is only applicable when the Interrupt Mode is set to 'At Threshold Value'.
Reception > FIFOs > FIFO 4 > Payload Size	MCU Specific Options		Select the message payload size for RX FIFO 4.
Reception > FIFOs > FIFO 4 > Depth	MCU Specific Options		Select the number of stages for RX FIFO 4.
Reception > FIFOs > FIFO 5 > Enable	Enabled Disabled	Disabled	Enable or disable RX FIFO 5.
Reception > FIFOs > FIFO 5 > Interrupt Mode	MCU Specific Options		Set the interrupt mode for RX FIFO 5. Threshold mode will only fire an interrupt each time an incoming message crosses the threshold value set below.
Reception > FIFOs > FIFO 5 > Interrupt Threshold	MCU Specific Options		Set the interrupt threshold value for RX FIFO 5. This setting is only applicable when the Interrupt Mode is set to 'At Threshold Value'.
Reception > FIFOs > FIFO 5 > Payload Size	MCU Specific Options		Select the message payload size for RX FIFO 5.
Reception > FIFOs > FIFO 5 > Depth	MCU Specific Options		Select the number of stages for RX FIFO 5.
Reception > FIFOs > FIFO 6 > Enable	Enabled Disabled	Disabled	Enable or disable RX FIFO 6.
Reception > FIFOs > FIFO 6 > Interrupt Mode	MCU Specific Options		Set the interrupt mode for RX FIFO 6. Threshold mode will only fire an interrupt each time an incoming message crosses the threshold value set below.
Reception > FIFOs > FIFO 6 > Interrupt Threshold	MCU Specific Options		Set the interrupt threshold value for RX FIFO 6. This setting is only applicable when the Interrupt Mode is set to 'At Threshold Value'.
Reception > FIFOs > FIFO 6 > Payload Size	MCU Specific Options		Select the message payload size for RX FIFO 6.
Reception > FIFOs > FIFO 6 > Depth	MCU Specific Options		Select the number of stages for RX FIFO 6.
Reception > FIFOs > FIFO 7 > Enable	Enabled Disabled	Disabled	Enable or disable RX FIFO 7.
Reception > FIFOs > FIFO 7 > Interrupt Mode	MCU Specific Options		Set the interrupt mode for RX FIFO 7. Threshold mode will only fire an interrupt each time an incoming message crosses the threshold value set below.
Reception > FIFOs > FIFO 7 > Interrupt Threshold	MCU Specific Options		Set the interrupt threshold value for RX FIFO 7. This setting is only applicable when the Interrupt Mode is set to 'At Threshold Value'.
Reception > FIFOs > FIFO 7 > Payload Size	MCU Specific Options		Select the message payload size for RX FIFO 7.
Reception > FIFOs > FIFO 7 > Depth	MCU Specific Options		Select the number of stages for RX FIFO 7.
Reception > FIFOs > Interrupt Priority	Value must be an integer between 0 and 31	24	This priority level will apply to all FIFO interrupts globally.
Reception > Acceptance Filtering > Channel 0 Rule Count	The number of AFL rules must be a positive integer.	64	Number of acceptance filter list rules dedicated to Channel 0.
Reception > Acceptance Filtering > Channel 1 Rule Count	The number of AFL rules must be a positive integer.	64	Number of acceptance filter list rules dedicated to Channel 1.
Common FIFOs > FIFO 0 > Enable	Enabled Disabled	Disabled	Enable or disable Common FIFO 0.
Common FIFOs > FIFO 0 > Mode	Receive Transmit	Receive	Select the operation mode for Common FIFO 0.
Common FIFOs > FIFO 0 > RX Interrupt Enable	Enabled Disabled	Disabled	Enable to allow interrupts on message receiption for Common FIFO 0.
Common FIFOs > FIFO 0 > TX Interrupt Enable	Enabled Disabled	Disabled	Enable to allow interrupts on message transmission for Common FIFO 0.
Common FIFOs > FIFO 0 > Interrupt Mode	At Threshold Value | Empty Buffer Every Frame	At Threshold Value | Empty Buffer	Set the interrupt mode for Common FIFO 0. Receive Mode: - Threshold mode will only generate an interrupt each time an incoming message crosses the threshold value set below. - Every Frame mode will generate an interrupt each time a message has been received. Transmit mode: - Empty buffer mode will generate an interrupt when the buffer becomes empty upon completion of message transmission. - Every Frame will generate an interrupt each time a message has been transmitted.
Common FIFOs > FIFO 0 > Interrupt Threshold	MCU Specific Options		Set the interrupt threshold value for Common FIFO 0. This setting is only applicable when the Interrupt Mode is set to 'At Threshold Value'.
Common FIFOs > FIFO 0 > Payload Size	MCU Specific Options		Select the message payload size for Common FIFO 0.
Common FIFOs > FIFO 0 > Depth	MCU Specific Options		Select the number of stages for Common FIFO 0.
Common FIFOs > FIFO 0 > TX Message Buffer	MCU Specific Options		Select the TX message buffer that participates in TX scans related to Common FIFO 0.
Common FIFOs > FIFO 0 > Interval TX Delay	TX delay must be an integer between 0 and 255.	0	Selects the delay between successive transmission for Common FIFO 0 in units of the Interval Timer Clock.
Common FIFOs > FIFO 0 > Interval Timer	Reference clock Bit time clock	Reference clock	Select the source of the interval timer clock for Common FIFO 0. The reference clock can be scaled by x10 below.
Common FIFOs > FIFO 0 > Interval Timer Reference Clock Resolution	x1 x10	x1	Selects the timer resolution if the reference clock is selected as the timer source for Common FIFO 0.
Common FIFOs > FIFO 1 > Enable	Enabled Disabled	Disabled	Enable or disable Common FIFO 1.
Common FIFOs > FIFO 1 > Mode	Receive Transmit	Receive	Select the operation mode for Common FIFO 1.
Common FIFOs > FIFO 1 > RX Interrupt Enable	Enabled Disabled	Disabled	Enable to allow interrupts on message receiption for Common FIFO 1.
Common FIFOs > FIFO 1 > TX Interrupt Enable	Enabled Disabled	Disabled	Enable to allow interrupts on message transmission for Common FIFO 1.
Common FIFOs > FIFO 1 > Interrupt Mode	At Threshold Value | Empty Buffer Every Frame	At Threshold Value | Empty Buffer	Set the interrupt mode for Common FIFO 1. Receive Mode: - Threshold mode will only generate an interrupt each time an incoming message crosses the threshold value set below. - Every Frame mode will generate an interrupt each time a message has been received. Transmit mode: - Empty buffer mode will generate an interrupt when the buffer becomes empty upon completion of message transmission. - Every Frame will generate an interrupt each time a message has been transmitted.
Common FIFOs > FIFO 1 > Interrupt Threshold	MCU Specific Options		Set the interrupt threshold value for Common FIFO 1. This setting is only applicable when the Interrupt Mode is set to 'At Threshold Value'.
Common FIFOs > FIFO 1 > Payload Size	MCU Specific Options		Select the message payload size for Common FIFO 1.
Common FIFOs > FIFO 1 > Depth	MCU Specific Options		Select the number of stages for Common FIFO 1.
Common FIFOs > FIFO 1 > TX Message Buffer	MCU Specific Options		Select the TX message buffer that participates in TX scans related to Common FIFO 1.
Common FIFOs > FIFO 1 > Interval TX Delay	TX delay must be an integer between 0 and 255.	0	Selects the delay between successive transmission for Common FIFO 1 in units of the Interval Timer Clock.
Common FIFOs > FIFO 1 > Interval Timer	Reference clock Bit time clock	Reference clock	Select the source of the interval timer clock for Common FIFO 1. The reference clock can be scaled by x10 below.
Common FIFOs > FIFO 1 > Interval Timer Reference Clock Resolution	x1 x10	x1	Selects the timer resolution if the reference clock is selected as the timer source for Common FIFO 1.
Common FIFOs > FIFO 2 > Enable	Enabled Disabled	Disabled	Enable or disable Common FIFO 2.
Common FIFOs > FIFO 2 > Mode	Receive Transmit	Receive	Select the operation mode for Common FIFO 2.
Common FIFOs > FIFO 2 > RX Interrupt Enable	Enabled Disabled	Disabled	Enable to allow interrupts on message receiption for Common FIFO 2.
Common FIFOs > FIFO 2 > TX Interrupt Enable	Enabled Disabled	Disabled	Enable to allow interrupts on message transmission for Common FIFO 2.
Common FIFOs > FIFO 2 > Interrupt Mode	At Threshold Value | Empty Buffer Every Frame	At Threshold Value | Empty Buffer	Set the interrupt mode for Common FIFO 2. Receive Mode: - Threshold mode will only generate an interrupt each time an incoming message crosses the threshold value set below. - Every Frame mode will generate an interrupt each time a message has been received. Transmit mode: - Empty buffer mode will generate an interrupt when the buffer becomes empty upon completion of message transmission. - Every Frame will generate an interrupt each time a message has been transmitted.
Common FIFOs > FIFO 2 > Interrupt Threshold	MCU Specific Options		Set the interrupt threshold value for Common FIFO 2. This setting is only applicable when the Interrupt Mode is set to 'At Threshold Value'.
Common FIFOs > FIFO 2 > Payload Size	MCU Specific Options		Select the message payload size for Common FIFO 2.
Common FIFOs > FIFO 2 > Depth	MCU Specific Options		Select the number of stages for Common FIFO 2.
Common FIFOs > FIFO 2 > TX Message Buffer	MCU Specific Options		Select the TX message buffer that participates in TX scans related to Common FIFO 2.
Common FIFOs > FIFO 2 > Interval TX Delay	TX delay must be an integer between 0 and 255.	0	Selects the delay between successive transmission for Common FIFO 2 in units of the Interval Timer Clock.
Common FIFOs > FIFO 2 > Interval Timer	Reference clock Bit time clock	Reference clock	Select the source of the interval timer clock for Common FIFO 2. The reference clock can be scaled by x10 below.
Common FIFOs > FIFO 2 > Interval Timer Reference Clock Resolution	x1 x10	x1	Selects the timer resolution if the reference clock is selected as the timer source for Common FIFO 2.
Common FIFOs > FIFO 3 > Enable	Enabled Disabled	Disabled	Enable or disable Common FIFO 3.
Common FIFOs > FIFO 3 > Mode	Receive Transmit	Receive	Select the operation mode for Common FIFO 3.
Common FIFOs > FIFO 3 > RX Interrupt Enable	Enabled Disabled	Disabled	Enable to allow interrupts on message receiption for Common FIFO 3.
Common FIFOs > FIFO 3 > TX Interrupt Enable	Enabled Disabled	Disabled	Enable to allow interrupts on message transmission for Common FIFO 3.
Common FIFOs > FIFO 3 > Interrupt Mode	At Threshold Value | Empty Buffer Every Frame	At Threshold Value | Empty Buffer	Set the interrupt mode for Common FIFO 3. Receive Mode: - Threshold mode will only generate an interrupt each time an incoming message crosses the threshold value set below. - Every Frame mode will generate an interrupt each time a message has been received. Transmit mode: - Empty buffer mode will generate an interrupt when the buffer becomes empty upon completion of message transmission. - Every Frame will generate an interrupt each time a message has been transmitted.
Common FIFOs > FIFO 3 > Interrupt Threshold	MCU Specific Options		Set the interrupt threshold value for Common FIFO 3. This setting is only applicable when the Interrupt Mode is set to 'At Threshold Value'.
Common FIFOs > FIFO 3 > Payload Size	MCU Specific Options		Select the message payload size for Common FIFO 3.
Common FIFOs > FIFO 3 > Depth	MCU Specific Options		Select the number of stages for Common FIFO 3.
Common FIFOs > FIFO 3 > TX Message Buffer	MCU Specific Options		Select the TX message buffer that participates in TX scans related to Common FIFO 3.
Common FIFOs > FIFO 3 > Interval TX Delay	TX delay must be an integer between 0 and 255.	0	Selects the delay between successive transmission for Common FIFO 3 in units of the Interval Timer Clock.
Common FIFOs > FIFO 3 > Interval Timer	Reference clock Bit time clock	Reference clock	Select the source of the interval timer clock for Common FIFO 3. The reference clock can be scaled by x10 below.
Common FIFOs > FIFO 3 > Interval Timer Reference Clock Resolution	x1 x10	x1	Selects the timer resolution if the reference clock is selected as the timer source for Common FIFO 3.
Common FIFOs > FIFO 4 > Enable	Enabled Disabled	Disabled	Enable or disable Common FIFO 4.
Common FIFOs > FIFO 4 > Mode	Receive Transmit	Receive	Select the operation mode for Common FIFO 4.
Common FIFOs > FIFO 4 > RX Interrupt Enable	Enabled Disabled	Disabled	Enable to allow interrupts on message receiption for Common FIFO 4.
Common FIFOs > FIFO 4 > TX Interrupt Enable	Enabled Disabled	Disabled	Enable to allow interrupts on message transmission for Common FIFO 4.
Common FIFOs > FIFO 4 > Interrupt Mode	At Threshold Value | Empty Buffer Every Frame	At Threshold Value | Empty Buffer	Set the interrupt mode for Common FIFO 4. Receive Mode: - Threshold mode will only generate an interrupt each time an incoming message crosses the threshold value set below. - Every Frame mode will generate an interrupt each time a message has been received. Transmit mode: - Empty buffer mode will generate an interrupt when the buffer becomes empty upon completion of message transmission. - Every Frame will generate an interrupt each time a message has been transmitted.
Common FIFOs > FIFO 4 > Interrupt Threshold	MCU Specific Options		Set the interrupt threshold value for Common FIFO 4. This setting is only applicable when the Interrupt Mode is set to 'At Threshold Value'.
Common FIFOs > FIFO 4 > Payload Size	MCU Specific Options		Select the message payload size for Common FIFO 4.
Common FIFOs > FIFO 4 > Depth	MCU Specific Options		Select the number of stages for Common FIFO 4.
Common FIFOs > FIFO 4 > TX Message Buffer	MCU Specific Options		Select the TX message buffer that participates in TX scans related to Common FIFO 4.
Common FIFOs > FIFO 4 > Interval TX Delay	TX delay must be an integer between 0 and 255.	0	Selects the delay between successive transmission for Common FIFO 4 in units of the Interval Timer Clock.
Common FIFOs > FIFO 4 > Interval Timer	Reference clock Bit time clock	Reference clock	Select the source of the interval timer clock for Common FIFO 4. The reference clock can be scaled by x10 below.
Common FIFOs > FIFO 4 > Interval Timer Reference Clock Resolution	x1 x10	x1	Selects the timer resolution if the reference clock is selected as the timer source for Common FIFO 4.
Common FIFOs > FIFO 5 > Enable	Enabled Disabled	Disabled	Enable or disable Common FIFO 5.
Common FIFOs > FIFO 5 > Mode	Receive Transmit	Receive	Select the operation mode for Common FIFO 5.
Common FIFOs > FIFO 5 > RX Interrupt Enable	Enabled Disabled	Disabled	Enable to allow interrupts on message receiption for Common FIFO 5.
Common FIFOs > FIFO 5 > TX Interrupt Enable	Enabled Disabled	Disabled	Enable to allow interrupts on message transmission for Common FIFO 5.
Common FIFOs > FIFO 5 > Interrupt Mode	At Threshold Value | Empty Buffer Every Frame	At Threshold Value | Empty Buffer	Set the interrupt mode for Common FIFO 5. Receive Mode: - Threshold mode will only generate an interrupt each time an incoming message crosses the threshold value set below. - Every Frame mode will generate an interrupt each time a message has been received. Transmit mode: - Empty buffer mode will generate an interrupt when the buffer becomes empty upon completion of message transmission. - Every Frame will generate an interrupt each time a message has been transmitted.
Common FIFOs > FIFO 5 > Interrupt Threshold	MCU Specific Options		Set the interrupt threshold value for Common FIFO 5. This setting is only applicable when the Interrupt Mode is set to 'At Threshold Value'.
Common FIFOs > FIFO 5 > Payload Size	MCU Specific Options		Select the message payload size for Common FIFO 5.
Common FIFOs > FIFO 5 > Depth	MCU Specific Options		Select the number of stages for Common FIFO 5.
Common FIFOs > FIFO 5 > TX Message Buffer	MCU Specific Options		Select the TX message buffer that participates in TX scans related to Common FIFO 5.
Common FIFOs > FIFO 5 > Interval TX Delay	TX delay must be an integer between 0 and 255.	0	Selects the delay between successive transmission for Common FIFO 5 in units of the Interval Timer Clock.
Common FIFOs > FIFO 5 > Interval Timer	Reference clock Bit time clock	Reference clock	Select the source of the interval timer clock for Common FIFO 5. The reference clock can be scaled by x10 below.
Common FIFOs > FIFO 5 > Interval Timer Reference Clock Resolution	x1 x10	x1	Selects the timer resolution if the reference clock is selected as the timer source for Common FIFO 5.
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Transmission Priority	MCU Specific Options		Select how messages should be prioritized for transmission. In either case, lower numbers indicate higher priority.
DLC Check	MCU Specific Options		When enabled received messages will be rejected if their DLC field is less than the value configured in the associated AFL rule. If 'Enabled w/truncate' is selected and a message passes the DLC check the DLC field is set to the value in the associated AFL rule and any excess data is discarded.
Clock Source	MCU Specific Options		Select the CANFD clock source.
Interval Timer Prescaler	Timer prescaler must be an integer between 0 and 65535.	0	FIFO interval timer prescaler, required for Interval TX Delay.

Configurations for Connectivity > CANFD Driver on r_canfd

This module can be added to the Stacks tab via New Stack > Connectivity > CANFD Driver on r_canfd.

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_canfd0	Module name.
General > Channel	Channel should be 0 or 1	0	Specify the CAN channel to use.
Bitrate > Automatic > Clock source frequency (Set 0 if P0CLK use)	Must be a valid integer.	0	Input clock source frequency.
Bitrate > Automatic > Nominal Rate (bps)	Must be a valid integer with a maximum of 1MHz.	500000	Specify nominal bitrate in bits per second.
Bitrate > Automatic > Data Rate (bps)	Must be a valid integer greater than 0.	2000000	Specify data bitrate in bits per second.
Bitrate > Automatic > Sample Point (%)	Must be a valid integer between 60 and 99.	75	Specify desired sample point.
Bitrate > Manual > Nominal > Prescaler (divisor)	Manual Entry	1	Specify clock divisor for nominal bitrate.
Bitrate > Manual > Nominal > Time Segment 1 (Tq)	Manual Entry	29	Select the Time Segment 1 value. Check module usage notes for how to calculate this value.
Bitrate > Manual > Nominal > Time Segment 2 (Tq)	Manual Entry	10	Select the Time Segment 2 value. Check module usage notes for how to calculate this value.
Bitrate > Manual > Nominal > Sync Jump Width (Tq)	Manual Entry	4	Select the Synchronization Jump Width value. Check module usage notes for how to calculate this value.
Bitrate > Manual > Data > Prescaler (divisor)	Manual Entry	1	Specify clock divisor for data bitrate.
Bitrate > Manual > Data > Time Segment 1 (Tq)	Manual Entry	12	Select the Time Segment 1 value. Check module usage notes for how to calculate this value.
Bitrate > Manual > Data > Time Segment 2 (Tq)	Manual Entry	4	Select the Time Segment 2 value. Check module usage notes for how to calculate this value.
Bitrate > Manual > Data > Sync Jump Width (Tq)	Manual Entry	1	Select the Synchronization Jump Width value. Check module usage notes for how to calculate this value.
Bitrate > Manual > Use manual settings	Yes No	No	Select whether or not to override automatic baudrate generation and instead use the values specified here.
Bitrate > Delay Compensation	Enable Disable	Enable	When enabled the CANFD module will automatically compensate for any transceiver or bus delay between transmitted and received bits. When manually supplying bit timing values with delay compensation enabled be sure the data prescaler is 2 or smaller for correct operation.
Interrupts > Callback	Name must be a valid C symbol	canfd0_callback	A user callback function. If this callback function is provided, it is called from the interrupt service routine (ISR) each time any interrupt occurs.
Interrupts > Channel Interrupt Priority Level	Value must be an integer between 0 and 31	24	Channel Error/Transmit interrupt priority.
Transmit Interrupts	MCU Specific Options		Select which TX Message Buffers should trigger an interrupt when transmission is complete.
Channel Error Interrupts	MCU Specific Options		Select which channel error interrupt sources to enable.
TX Buffer Merge Mode	MCU Specific Options		When enabled the CANFD module set Transmit buffer merge mode enable. TX MB0,3 are able to transmit payload with a length of more than 20 bytes.
Filter List Array	Name must be a valid C symbol	p_canfd0_afl	Acceptance Filter List (AFL) rule array symbol name.

Clock Configuration

The CANFD peripheral uses the clocks shown in the table below as its clock sources.

	RZ/A3UL
Clock Source	P0 clock/2 or External CANFD Clock[^1]

[^1]: Externally input clock to the CAN_CLK pin

To achieve an exact bitrate the CANFD source clock or divisor may need to be adjusted to meet the criteria in the formula below:

bitrate = canfd_clock_hz / ((time_segment_1 + time_segment_2 + 1) * prescalar)

For CANFD, the possible values for each element are as follows:

Element	Min	Max (Nominal)	Max (Data)
Bitrate	—	1 Mbps	4 Mbps
Time Segment 1	2 Tq	128 Tq	16 Tq
Time Segment 2	2 Tq	32 Tq	8 Tq
Sync Jump Width	1 Tq	Time Segment 2	Time Segment 2
Prescalar	1	1024	256

Note

RZ/A FSP does not support changing the frequency of the peripheral clock used in CANFD.

Pin Configuration

CANFD channels each control two pins: CRX (receive) and CTX (transmit).

Usage Notes

Buffers

The CANFD driver provides three types of buffers: Transmit Message Buffers (TX MBs), Receive Message Buffers (RX MBs) and Receive FIFOs (RX FIFOs).

TX Message Buffers

TX MBs are used for transmission only. Refer to the hardware manual for your device for information on which TX MBs are available.

Note

The CANFD peripheral continually scans TX MBs for new data. Depending on the provided clock it may be possible to write to multiple TX MBs before transmission begins. In this case, messages will be sent in the priority specified by the Transmission Priority option in the RZ Configuration editor.

RX Message Buffers

RX MBs are for reception only and may only hold one message at a time. 32 total RX MBs are available and are shared across all channels.

No interrupts are provided for RX MBs. Use R_CANFD_InfoGet and R_CANFD_Read to poll and read them, respectively.

RX FIFOs

RX FIFOs provide interrupt-driven queue functionality for receiving messages and are shared across all channels. All FIFOs have the following capabilities:

• Up to 64 byte payloads
• Up to 128 message capacity
• Interrupt events:
  • On every received frame OR when filled to a specified fraction of its capacity
  • When a message is overwritten (message received on full FIFO)

Once an interrupt is fired it will continue to fire until the FIFO is emptied and all messages have been passed to user code via the callback. When using the threshold interrupt mode a FIFO can be checked for data and read between interrupts by calling R_CANFD_InfoGet and R_CANFD_Read, respectively.

RX Buffer Pool

The CANFD peripheral has a limited amount of buffer pool RAM available for allocating RX MBs and FIFO stages. The RZ Configuration editor will provide a warning when the limit is exceeded.

The number of bytes used by RX MBs and individual FIFOs can be calculated as follows:

Total RX MB bytes used = (number of RX MBs enabled) * (RX MB payload size + 12 header bytes)

RX FIFO bytes used = (number of FIFO stages) * (FIFO payload size + 12 header bytes)

Message Filtering (Acceptance Filter List)

To filter messages to the desired message buffer or FIFO the CANFD peripheral uses an Acceptance Filter List (AFL). Each entry in the AFL provides a rule to check a message against along with destination and other filtering information. When a message is received the CANFD peripheral internally checks against every configured AFL rule for the channel. If a match is found the message is transferred to the destination(s) specified in the rule. The default template with one entry is shown below:

static const canfd_afl_entry_t p_canfd0_afl[CANFD_CFG_AFL_CH0_RULE_NUM] =
{
    {
        .id =
        {
            /* Specify the ID, ID type and frame type to accept. */
            .id         = 0x00000000,
            .frame_type = CAN_FRAME_TYPE_DATA,
            .id_mode    = CAN_ID_MODE_EXTENDED,
        },

        .mask =
        {
            /* These values mask which ID/mode bits to compare when filtering messages. */
            .mask_id         = 0x1FFFFFFF,
            .mask_frame_type = 1,
            .mask_id_mode    = 1,
        },

        .destination =
        {
            /* If DLC checking is enabled any messages shorter than the below setting will be rejected. */
            .minimum_dlc = CANFD_MINIMUM_DLC_0,

            /* Optionally specify a Receive Message Buffer (RX MB) to store accepted frames. RX MBs do not have an
             * interrupt or overwrite protection and must be checked with R_CANFD_InfoGet and R_CANFD_Read. */
            .rx_buffer   = CANFD_RX_MB_NONE,

            /* Specify which FIFO(s) to send filtered messages to. Multiple FIFOs can be OR'd together. */
            .fifo_select_flags = CANFD_RX_FIFO_0,
        }
    }
};

For an example configuration refer to the AFL Example below.

Flexible Data (FD)

Flexible Data is an extension of the CAN protocol allowing for messages up to 64 bytes and higher data bitrates, among other features. The CANFD driver supports the following:

• Sending and receiving FD messages
• Bitrate switching for data phase
• Manual and automatic setting of the error state (ESI) bit

To specify one or more of these options when transmitting set can_frame_t::options with combined values from canfd_frame_options_t. Received messages will automatically have this field filled, if applicable.

    /* Configure a frame to write 64 bytes with bitrate switching (BRS) enabled */
    g_can_tx_frame.id               = CAN_EXAMPLE_ID;
    g_can_tx_frame.id_mode          = CAN_ID_MODE_STANDARD;
    g_can_tx_frame.type             = CAN_FRAME_TYPE_DATA;
    g_can_tx_frame.data_length_code = CAN_EXAMPLE_64_BYTES;
    g_can_tx_frame.options          = CANFD_FRAME_OPTION_FD | CANFD_FRAME_OPTION_BRS;

Note

When using bitrate switching be sure to configure the Data Bitrate as desired in the RZ Configuration editor.

Bit Rate Calculation

For convenience, the baudrate of the CAN peripheral is automatically set through the RZ Configuration editor using a best effort approach. To increase compliance and reliability two extra options are provided: Link Prescalers and Delay Compensation.

When Link Prescalers is enabled the prescalers for Nominal and Data bitrates will be kept the same, improving clock tolerance in networks using FD frames. This option somewhat limits the available options for bitrate settings, so be sure to check that the automatically generated values are acceptable.

Enabling Delay Compensation instructs the CANFD peripheral to measure TX to RX tranceiver delay and automatically adjust for it, improving the reliability of high-speed FD messages. This option may severely limit available bitrate settings depending on the source clock; it is highly recommended to check the generated values when enabled.

If the auto-generated baud settings cause deviation that is not tolerable by the application the user can override the auto-generated settings and put in manually calculated values through the RZ Configuration editor. For more details on how the bitrate is calculated refer to the Clock Configuration section above.

Sync Jump Width

The Sync Jump Width option specifies the maximum number of time quanta that the sample point may be delayed by to account for differences in oscillators on the bus. It should be set to a value between 1 and the configured Time Segment 2 value depending on the maximum permissible clock error.

Error Handling

The CANFD peripheral provides two types of error interrupts: Channel and Global. As the names imply, each channel has its own Channel Error interrupt but there is only one Global Error interrupt. Only the configured channel will receive callbacks for Global Errors.

Error interrupt callbacks will pass either CAN_EVENT_ERR_CHANNEL or CAN_EVENT_ERR_GLOBAL in the can_callback_args_t::event field. A second field, can_callback_args_t::error, provides the actual error code as canfd_error_t. Cast to this enum to retrieve the error condition. See the callback in the Basic Example below for a demonstration.

DLC Checking

When DLC Checking is enabled messages are checked against the destination.minimum_dlc value of each AFL rule. If the data length of a message is less than this value the message will be rejected. When DLC checking is set to "Enabled w/truncate" in the RZ Configuration editor any data in excess of the minimum DLC setting will be truncated and the DLC value for the frame will be set to match.

FD Payload Overflow

When an FD message is received with a DLC larger than the destination buffer an FD Payload Overflow interrupt is thrown (if configured). When Payload Overflow is set to "Truncate" the message will still be accepted but only data up to the buffer capacity will be preserved. The DLC value is unchanged in this case; any data beyond this value in the can_frame_t::data array should not be used.

Test Modes

The CANFD peripheral provides three basic test modes: Listen Only, Internal Loopback and External Loopback. Use R_CANFD_ModeTransition to switch to a test mode.

On some MPUs an additional "Internal Bus" test mode is available that allows connecting both CANFD channels together on an internal bus, effectively creating an internal CAN network. See the Internal Bus example below for details.

Limitations

Developers should be aware of the following limitations when using CANFD:

• RX Message Buffers do not have an associated interrupt. To use them in an application one of the following is recommended:
  • Use R_CANFD_InfoGet to determine if any RX MBs have received data, then use R_CANFD_Read to obtain it
  • Select an RX FIFO as an additional destination for the relevant filter rules and configure the FIFO interrupt/callback as desired
• The CANFD peripheral has a limited amount of buffer pool RAM available for allocating RX MBs and FIFO stages. See the RX Buffer Pool section above for more information.
• When switching modes with R_CANFD_ModeTransition a delay of up to several CAN frames may be incurred. Consult Section "Channel Modes" in the User's Manual for details.
• Only one channel will receive callbacks for Global Errors. If a different channel is opened first these error interrupts will be suppressed until the specified handler channel is opened.

Examples

AFL Example

The below is an example Acceptance Filter List (AFL) declaration with two rules.

const canfd_afl_entry_t p_canfd0_afl[CANFD_CFG_AFL_CH1_RULE_NUM] =
{
    /* Store all data frames with at least 4 bytes from Standard IDs 0x40-0x4F in RX FIFO 0 and RX FIFO 1 */
    {
        .id =
        {
            .id         = 0x40,
            .frame_type = CAN_FRAME_TYPE_DATA,
            .id_mode    = CAN_ID_MODE_STANDARD
        },

        .mask =
        {
            .mask_id         = 0x7F0,
            .mask_frame_type = 1,
            .mask_id_mode    = 1
        },

        .destination =
        {
            .minimum_dlc       = CANFD_MINIMUM_DLC_4,
            .rx_buffer         = CANFD_RX_MB_NONE,
            .fifo_select_flags = (canfd_rx_fifo_t) (CANFD_RX_FIFO_0 | CANFD_RX_FIFO_1)
        }
    },

    /* Store all frames from Extended ID 0x1100 in RX FIFO 2 and RX MB 0 */
    {
        .id =
        {
            .id         = 0x1100,
            .frame_type = CAN_FRAME_TYPE_DATA, // This setting is ignored by the mask
            .id_mode    = CAN_ID_MODE_EXTENDED
        },

        .mask =
        {
            .mask_id         = 0x1FFFFFFF,
            .mask_frame_type = 0,
            .mask_id_mode    = 1
        },

        .destination =
        {
            .minimum_dlc       = CANFD_MINIMUM_DLC_0,
            .rx_buffer         = CANFD_RX_MB_0,
            .fifo_select_flags = CANFD_RX_FIFO_2
        }
    }
};

Basic Example

This is a basic example of minimal use of the CANFD module in an application.

Note

It is recommended to use RX FIFOs for reception as there are no interrupts for RX message buffers.

#define CAN_EXAMPLE_ID    (0x20)

can_frame_t g_can_tx_frame;
can_frame_t g_can_rx_frame;

volatile canfd_error_t g_err_status = (canfd_error_t) 0;

void canfd_callback (can_callback_args_t * p_args)
{
    switch (p_args->event)
    {
        case CAN_EVENT_RX_COMPLETE:    /* Receive complete event. */
        {
            /* Read received frame */
            memcpy(&g_can_rx_frame, &p_args->frame, sizeof(can_frame_t));

            /* Handle event */

            break;
        }

        case CAN_EVENT_TX_COMPLETE:    /* Transmit complete event. */
        {
            /* Handle event */

            break;
        }

        case CAN_EVENT_ERR_GLOBAL:                        /* Global error. */
        case CAN_EVENT_ERR_CHANNEL:                       /* Channel error. */
        {
            /* Get error status */
            g_err_status = (canfd_error_t) p_args->error; /* Check error code with canfd_error_t. */

            /* Handle event */

            break;
        }

        default:
        {
            break;
        }
    }
}

void canfd_basic_example (void)
{
    fsp_err_t err;


    /* Initialize the CAN module */
    err = R_CANFD_Open(&g_canfd0_ctrl, &g_canfd0_cfg);


    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);

    /* Setup frame to write to CAN ID 0x20 */
    g_can_tx_frame.id               = CAN_EXAMPLE_ID;
    g_can_tx_frame.id_mode          = CAN_ID_MODE_STANDARD;
    g_can_tx_frame.type             = CAN_FRAME_TYPE_DATA;
    g_can_tx_frame.data_length_code = 8;
    g_can_tx_frame.options          = 0;

    /* Write some data to the transmit frame */
    for (uint32_t i = 0; i < 8; i++)
    {
        g_can_tx_frame.data[i] = (uint8_t) i;
    }


    /* Send data on the bus */
    err = R_CANFD_Write(&g_canfd0_ctrl, CANFD_TX_MB_0, &g_can_tx_frame);
    assert(FSP_SUCCESS == err);


    /* Wait for a transmit callback event */
}

Flexible Data

This example demonstrates sending an FD message with bitrate switching over external loopback. The CTX and CRX pins must be connected when using external loopback, though if a CAN tranciever is onboard a 120 Ohm resistor should be connected across CANH and CANL instead.

#define CAN_EXAMPLE_64_BYTES    64

void canfd_fd_loopback_example (void)
{
    fsp_err_t err;

    err = R_CANFD_Open(&g_canfd0_ctrl, &g_canfd0_cfg);

    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);


    /* Switch to external loopback mode */
    err = R_CANFD_ModeTransition(&g_canfd0_ctrl, CAN_OPERATION_MODE_NORMAL, CAN_TEST_MODE_LOOPBACK_EXTERNAL);
    assert(FSP_SUCCESS == err);


    /* Configure a frame to write 64 bytes with bitrate switching (BRS) enabled */
    g_can_tx_frame.id               = CAN_EXAMPLE_ID;
    g_can_tx_frame.id_mode          = CAN_ID_MODE_STANDARD;
    g_can_tx_frame.type             = CAN_FRAME_TYPE_DATA;
    g_can_tx_frame.data_length_code = CAN_EXAMPLE_64_BYTES;
    g_can_tx_frame.options          = CANFD_FRAME_OPTION_FD | CANFD_FRAME_OPTION_BRS;


    /* Write some data to the transmit frame */
    for (uint32_t i = 0; i < CAN_DATA_BUFFER_LENGTH; i++)
    {
        g_can_tx_frame.data[i] = (uint8_t) i;
    }

    /* Send data on the bus */
    err = R_CANFD_Write(&g_canfd0_ctrl, CANFD_TX_MB_0, &g_can_tx_frame);
    assert(FSP_SUCCESS == err);

    /* Wait for a transmit and/or receive callback event */
}

Internal Bus

In this example two CANFD channels are connected to the Internal Bus test mode. API error checking has been omitted for clarity.

Note

Internal Bus mode is only available on MPUs with more than one CANFD channel. In addition, use of Global Modes for any other purpose is not recommended without consulting the device User's Manual.

Data Structures
struct	canfd_afl_entry_t
struct	canfd_global_cfg_t
struct	canfd_extended_cfg_t

Enumerations
enum	canfd_status_t
enum	canfd_error_t
enum	canfd_tx_mb_t
enum	canfd_rx_buffer_t
enum	canfd_rx_mb_t
enum	canfd_rx_fifo_t
enum	canfd_minimum_dlc_t
enum	canfd_frame_options_t
enum	canfd_txmb_merge_mode_t

---

Data Structure Documentation

canfd_afl_entry_t

struct canfd_afl_entry_t

AFL Entry (based on R_CANFD_CFDGAFL_Type in renesas.h)

canfd_global_cfg_t

struct canfd_global_cfg_t

CANFD Global Configuration

Data Fields
uint32_t	global_interrupts	Global control options (CFDGCTR register setting)
uint32_t	global_config	Global configuration options (CFDGCFG register setting)
uint32_t	rx_fifo_config[8]	RX FIFO configuration (CFDRFCCn register settings)
uint32_t	rx_mb_config	Number and size of RX Message Buffers (CFDRMNB register setting)
uint8_t	global_err_ipl	Global Error interrupt priority.
uint8_t	rx_fifo_ipl	RX FIFO interrupt priority.
uint32_t	common_fifo_config[R_CANFD_NUM_COMMON_FIFOS]	Common FIFO configurations.

canfd_extended_cfg_t

struct canfd_extended_cfg_t

CANFD Extended Configuration

Data Fields
canfd_afl_entry_t const *	p_afl	AFL rules list.
uint64_t	txmb_txi_enable	Array of TX Message Buffer enable bits.
uint32_t	error_interrupts	Error interrupt enable bits.
can_bit_timing_cfg_t *	p_data_timing	FD Data Rate (when bitrate switching is used)
uint8_t	delay_compensation	FD Transceiver Delay Compensation (enable or disable)
canfd_global_cfg_t *	p_global_cfg	Global configuration (global error callback channel only)
canfd_txmb_merge_mode_t	txmb_merge_mode_enable	TXMB buffer marge mode configuration.

Enumeration Type Documentation

canfd_status_t

enum canfd_status_t

CANFD Status

Enumerator
CANFD_STATUS_RESET_MODE	Channel in Reset mode.
CANFD_STATUS_HALT_MODE	Channel in Halt mode.
CANFD_STATUS_SLEEP_MODE	Channel in Sleep mode.
CANFD_STATUS_ERROR_PASSIVE	Channel in error-passive state.
CANFD_STATUS_BUS_OFF	Channel in bus-off state.
CANFD_STATUS_TRANSMITTING	Channel is transmitting.
CANFD_STATUS_RECEIVING	Channel is receiving.
CANFD_STATUS_READY	Channel is ready for communication.
CANFD_STATUS_ESI	At least one CAN-FD message was received with the ESI flag set.

canfd_error_t

enum canfd_error_t

CANFD Error Code

Enumerator
CANFD_ERROR_CHANNEL_BUS	Bus Error.
CANFD_ERROR_CHANNEL_WARNING	Error Warning (TX/RX error count over 0x5F)
CANFD_ERROR_CHANNEL_PASSIVE	Error Passive (TX/RX error count over 0x7F)
CANFD_ERROR_CHANNEL_BUS_OFF_ENTRY	Bus-Off State Entry.
CANFD_ERROR_CHANNEL_BUS_OFF_RECOVERY	Recovery from Bus-Off State.
CANFD_ERROR_CHANNEL_OVERLOAD	Overload.
CANFD_ERROR_CHANNEL_BUS_LOCK	Bus Locked.
CANFD_ERROR_CHANNEL_ARBITRATION_LOSS	Arbitration Lost.
CANFD_ERROR_CHANNEL_STUFF	Stuff Error.
CANFD_ERROR_CHANNEL_FORM	Form Error.
CANFD_ERROR_CHANNEL_ACK	ACK Error.
CANFD_ERROR_CHANNEL_CRC	CRC Error.
CANFD_ERROR_CHANNEL_BIT_RECESSIVE	Bit Error (recessive) Error.
CANFD_ERROR_CHANNEL_BIT_DOMINANT	Bit Error (dominant) Error.
CANFD_ERROR_CHANNEL_ACK_DELIMITER	ACK Delimiter Error.
CANFD_ERROR_GLOBAL_DLC	DLC Error.
CANFD_ERROR_GLOBAL_MESSAGE_LOST	Message Lost.
CANFD_ERROR_GLOBAL_PAYLOAD_OVERFLOW	FD Payload Overflow.
CANFD_ERROR_GLOBAL_TXQ_OVERWRITE	TX Queue Message Overwrite.
CANFD_ERROR_GLOBAL_TXQ_MESSAGE_LOST	TX Queue Message Lost.
CANFD_ERROR_GLOBAL_CH0_SCAN_FAIL	Channel 0 RX Scan Failure.
CANFD_ERROR_GLOBAL_CH1_SCAN_FAIL	Channel 1 RX Scan Failure.
CANFD_ERROR_GLOBAL_CH0_ECC	Channel 0 ECC Error.
CANFD_ERROR_GLOBAL_CH1_ECC	Channel 1 ECC Error.

canfd_tx_mb_t

enum canfd_tx_mb_t

CANFD Transmit Message Buffer (TX MB)

canfd_rx_buffer_t

enum canfd_rx_buffer_t

CANFD Receive Buffer (MB + FIFO + CFIFO)

canfd_rx_mb_t

enum canfd_rx_mb_t

CANFD Receive Message Buffer (RX MB)

canfd_rx_fifo_t

enum canfd_rx_fifo_t

CANFD Receive FIFO (RX FIFO)

canfd_minimum_dlc_t

enum canfd_minimum_dlc_t

CANFD AFL Minimum DLC settings

canfd_frame_options_t

enum canfd_frame_options_t

CANFD Frame Options

Enumerator
CANFD_FRAME_OPTION_ERROR	Error state set (ESI).
CANFD_FRAME_OPTION_BRS	Bit Rate Switching (BRS) enabled.
CANFD_FRAME_OPTION_FD	Flexible Data frame (FDF).

canfd_txmb_merge_mode_t

enum canfd_txmb_merge_mode_t

CANFD TXMB Merge mode

Function Documentation

R_CANFD_Open()

fsp_err_t R_CANFD_Open	(	can_ctrl_t *const	p_api_ctrl,
		can_cfg_t const *const	p_cfg
	)

Open and configure the CANFD channel for operation.

Example:

    /* Initialize the CAN module */
    err = R_CANFD_Open(&g_canfd0_ctrl, &g_canfd0_cfg);

Return values

FSP_SUCCESS	Channel opened successfully.
FSP_ERR_ALREADY_OPEN	Driver already open.
FSP_ERR_IN_USE	Channel is already in use.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	Channel does not exist on this MPU.
FSP_ERR_ASSERTION	A required pointer was NULL.
FSP_ERR_CAN_INIT_FAILED	The provided nominal or data bitrate is invalid.

R_CANFD_Close()

fsp_err_t R_CANFD_Close

(

can_ctrl_t *const

p_api_ctrl

)

Close the CANFD channel.

Return values

FSP_SUCCESS	Channel closed successfully.
FSP_ERR_NOT_OPEN	Control block not open.
FSP_ERR_ASSERTION	Null pointer presented.

R_CANFD_Write()

fsp_err_t R_CANFD_Write	(	can_ctrl_t *const	p_api_ctrl,
		uint32_t	buffer,
		can_frame_t *const	p_frame
	)

Write data to the CANFD channel.

Example:

    /* Send data on the bus */
    err = R_CANFD_Write(&g_canfd0_ctrl, CANFD_TX_MB_0, &g_can_tx_frame);
    assert(FSP_SUCCESS == err);

Return values

FSP_SUCCESS	Operation succeeded.
FSP_ERR_NOT_OPEN	Control block not open.
FSP_ERR_CAN_TRANSMIT_NOT_READY	Transmit in progress, cannot write data at this time.
FSP_ERR_INVALID_ARGUMENT	Data length or buffer number invalid.
FSP_ERR_INVALID_MODE	An FD option was set on a non-FD frame.
FSP_ERR_ASSERTION	One or more pointer arguments is NULL.
FSP_ERR_UNSUPPORTED	FD is not supported on this MPU.

R_CANFD_Read()

fsp_err_t R_CANFD_Read	(	can_ctrl_t *const	p_api_ctrl,
		uint32_t	buffer,
		can_frame_t *const	p_frame
	)

Read data from a CANFD Message Buffer or FIFO.

Example: snippet r_canfd_example.c R_CANFD_Read

Return values

FSP_SUCCESS	Operation succeeded.
FSP_ERR_NOT_OPEN	Control block not open.
FSP_ERR_INVALID_ARGUMENT	Buffer number invalid.
FSP_ERR_ASSERTION	p_api_ctrl or p_frame is NULL.
FSP_ERR_BUFFER_EMPTY	Buffer or FIFO is empty.

R_CANFD_ModeTransition()

fsp_err_t R_CANFD_ModeTransition	(	can_ctrl_t *const	p_api_ctrl,
		can_operation_mode_t	operation_mode,
		can_test_mode_t	test_mode
	)

Switch to a different channel, global or test mode.

Example:

    /* Switch to external loopback mode */
    err = R_CANFD_ModeTransition(&g_canfd0_ctrl, CAN_OPERATION_MODE_NORMAL, CAN_TEST_MODE_LOOPBACK_EXTERNAL);
    assert(FSP_SUCCESS == err);

Return values

FSP_SUCCESS	Operation succeeded.
FSP_ERR_NOT_OPEN	Control block not open.
FSP_ERR_ASSERTION	Null pointer presented
FSP_ERR_INVALID_MODE	Cannot change to the requested mode from the current global mode.

R_CANFD_InfoGet()

fsp_err_t R_CANFD_InfoGet	(	can_ctrl_t *const	p_api_ctrl,
		can_info_t *const	p_info
	)

Get CANFD state and status information for the channel.

Return values

FSP_SUCCESS	Operation succeeded.
FSP_ERR_NOT_OPEN	Control block not open.
FSP_ERR_ASSERTION	Null pointer presented

R_CANFD_CallbackSet()

fsp_err_t R_CANFD_CallbackSet	(	can_ctrl_t *const	p_api_ctrl,
		void(*)(can_callback_args_t *)	p_callback,
		void const *const	p_context,
		can_callback_args_t *const	p_callback_memory
	)

Updates the user callback with the option to provide memory for the callback argument structure. Implements can_api_t::callbackSet.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_NO_CALLBACK_MEMORY	p_callback is non-secure and p_callback_memory is either secure or NULL.