RZ/A Flexible Software Package Documentation  Release v3.0.0

 
Memory Managing Unit (r_mmu)

Functions

fsp_err_t R_MMU_Open (mmu_ctrl_t *const p_api_ctrl, mmu_cfg_t const *const p_cfg)
 
fsp_err_t R_MMU_Close (mmu_ctrl_t *const p_api_ctrl)
 
fsp_err_t R_MMU_AllocateTable (mmu_ctrl_t *const p_api_ctrl, uint32_t table_level, uint64_t table_base_ptr)
 
fsp_err_t R_MMU_WriteTableLink (mmu_ctrl_t *const p_api_ctrl, mmu_table_info_t *p_table_info, uint64_t vaddress, uint64_t next_table_base_ptr)
 
fsp_err_t R_MMU_WriteTable (mmu_ctrl_t *const p_api_ctrl, mmu_table_info_t *p_table_info, mmu_section_info_t *p_section_info)
 
fsp_err_t R_MMU_WriteTableFault (mmu_ctrl_t *const p_api_ctrl, mmu_table_info_t *p_table_info, mmu_section_info_t *p_section_info)
 

Detailed Description

Driver for the MMU peripheral on RZ MPUs. This module implements the Memory Managing Unit Interface.

Overview

Features

Configuration

Examples

Basic Example

This is a basic example of the MMU in an application.

When you create a new project, mmu_page_table.c with the following contents will be generated in the src folder directly under the project. If you want to change the settings for the virtual page table, please edit this file.

/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/
#define R_MMU_UNCACHE_FLASH_OFFESET 0x10000000
#define R_MMU_UNCACHE_DDR_OFFESET 0x40000000
#define R_MMU_PHYSICAL_FLASH_START 0x20000000
#define R_MMU_PHYSICAL_FLASH_END 0x2FFFFFFF
#define R_MMU_PHYSICAL_DDR_START 0x40000000
#define R_MMU_PHYSICAL_DDR_END 0x7FFFFFFF
#define R_MMU_UNCACHE_FLASH_START 0x30000000
#define R_MMU_UNCACHE_FLASH_END 0x3FFFFFFF
#define R_MMU_UNCACHE_DDR_START 0x80000000
#define R_MMU_UNCACHE_DDR_END 0xBFFFFFFF
/***********************************************************************************************************************
* Global Variables
**********************************************************************************************************************/
r_mmu_pgtbl_cfg_t const g_mmu_pagetable_array[] =
{
/* vaddress, paddress, size, attribute */
{0x00000000, 0x00000000, 0x00200000, R_MMU_PG_ATTRIBUTE_NORMAL_CACHEABLE},
{0x00200000, 0x00200000, 0x0FE00000, R_MMU_PG_ATTRIBUTE_ACCESS_FAULT },
{0x10000000, 0x10000000, 0x10000000, R_MMU_PG_ATTRIBUTE_DEVICE },
{0x20000000, 0x20000000, 0x10000000, R_MMU_PG_ATTRIBUTE_NORMAL_CACHEABLE},
{0x30000000, 0x20000000, 0x10000000, R_MMU_PG_ATTRIBUTE_NORMAL_UNCACHE },
{0x40000000, 0x40000000, 0x40000000, R_MMU_PG_ATTRIBUTE_NORMAL_CACHEABLE},
{0x80000000, 0x40000000, 0x40000000, R_MMU_PG_ATTRIBUTE_NORMAL_UNCACHE },
{0xC0000000, 0xC0000000, 0x40000000, R_MMU_PG_ATTRIBUTE_ACCESS_FAULT },
{0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF }
};
/*******************************************************************************************************************/
fsp_err_t R_MMU_VAtoPA (uint64_t vaddress, uint64_t * p_paddress)
{
fsp_err_t err = FSP_SUCCESS;
if ((R_MMU_UNCACHE_FLASH_START <= vaddress) && (vaddress <= R_MMU_UNCACHE_FLASH_END))
{
*p_paddress = vaddress - R_MMU_UNCACHE_FLASH_OFFESET;
}
else if ((R_MMU_UNCACHE_DDR_START <= vaddress) && (vaddress <= R_MMU_UNCACHE_DDR_END))
{
*p_paddress = vaddress - R_MMU_UNCACHE_DDR_OFFESET;
}
else
{
*p_paddress = vaddress;
}
return err;
}
/*******************************************************************************************************************/
fsp_err_t R_MMU_PAtoVA (uint64_t paddress, uint64_t * p_vaddress)
{
fsp_err_t err = FSP_SUCCESS;
if ((R_MMU_PHYSICAL_FLASH_START <= paddress) && (paddress <= R_MMU_PHYSICAL_FLASH_END))
{
*p_vaddress = paddress + R_MMU_UNCACHE_FLASH_OFFESET;
}
else if ((R_MMU_PHYSICAL_DDR_START <= paddress) && (paddress <= R_MMU_PHYSICAL_DDR_END))
{
*p_vaddress = paddress + R_MMU_UNCACHE_DDR_OFFESET;
}
else
{
*p_vaddress = paddress;
}
return err;
}

Memory translation rule table

g_mmu_pagetable_array contains a table of virtual to physical translation rules. In this table, please specify 2MB boundary values for address and size.

Memory address translation function

R_MMU_VAtoPA is a function that translates from a virtual address to a physical address. R_MMU_PAtoVA is a function that translates from a physical address to a virtual address.

If you have changed g_mmu_pagetable_array, please modify these functions to meet the new memory translation rules as well.

Function Documentation

◆ R_MMU_Open()

fsp_err_t R_MMU_Open ( mmu_ctrl_t *const  p_api_ctrl,
mmu_cfg_t const *const  p_cfg 
)

Initializes whole of MMU page table.

Return values
FSP_SUCCESSInitialized Page Table.
FSP_ERR_INVALID_ARGUMENTIllegal parameter.

◆ R_MMU_Close()

fsp_err_t R_MMU_Close ( mmu_ctrl_t *const  p_api_ctrl)

Close the MMU driver.

Return values
FSP_SUCCESSClose the MMU

◆ R_MMU_AllocateTable()

fsp_err_t R_MMU_AllocateTable ( mmu_ctrl_t *const  p_api_ctrl,
uint32_t  table_level,
uint64_t  table_base_ptr 
)

Initializes specified MMU page table.

Return values
FSP_ERR_UNSUPPORTEDWill be supported in a future version.

◆ R_MMU_WriteTableLink()

fsp_err_t R_MMU_WriteTableLink ( mmu_ctrl_t *const  p_api_ctrl,
mmu_table_info_t *  p_table_info,
uint64_t  vaddress,
uint64_t  next_table_base_ptr 
)

Write page table entries as next page table link.

Return values
FSP_SUCCESSSuccessfully updated page table link.
FSP_ERR_INVALID_ARGUMENTIllegal parameter.

◆ R_MMU_WriteTable()

fsp_err_t R_MMU_WriteTable ( mmu_ctrl_t *const  p_api_ctrl,
mmu_table_info_t *  p_table_info,
mmu_section_info_t *  p_section_info 
)

Fill page table entries with specified attribute.

Return values
FSP_SUCCESSSuccessfully updated page table.
FSP_ERR_INVALID_ARGUMENTIllegal parameter.

◆ R_MMU_WriteTableFault()

fsp_err_t R_MMU_WriteTableFault ( mmu_ctrl_t *const  p_api_ctrl,
mmu_table_info_t *  p_table_info,
mmu_section_info_t *  p_section_info 
)

Fill page table entries with acccess fault attribute.

Return values
FSP_SUCCESSSuccessfully updated page table.
FSP_ERR_INVALID_ARGUMENTIllegal parameter.