RZ/A Flexible Software Package Documentation  Release v3.4.0

 
mipi_phy_b_timing_t Struct Reference

#include <r_mipi_phy_b.h>

Data Fields

uint32_t t_init
 Minimum duration of the TINIT state (Units: PCLKA cycles)
 
uint8_t t_clk_prep
 Duration of the clock lane LP-00 state (immediately before entry to the HS-0 state)
 
uint8_t t_hs_prep
 Duration of the data lane LP-00 state (immediately before entry to the HS-0 state)
 
uint8_t t_clk_zero
 TCLKZERO setting.
 
uint8_t t_clk_pre
 TCLKPRE setting.
 
uint8_t t_clk_post
 TCLKPOST setting.
 
uint8_t t_clk_trail
 TCLKTRAIL setting.
 
uint8_t t_hs_zero
 THSZERO setting.
 
uint8_t t_hs_trail
 THSTRAIL setting.
 
uint8_t t_hs_exit
 THSEXIT setting.
 
uint8_t t_lp_exit
 Low-power transition time to High-Speed mode.
 

Detailed Description

MIPI PHY D-PHY power mode transition timing

Field Documentation

◆ t_init

uint32_t mipi_phy_b_timing_t::t_init

Minimum duration of the TINIT state (Units: PCLKA cycles)

◆ t_clk_prep

uint8_t mipi_phy_b_timing_t::t_clk_prep

Duration of the clock lane LP-00 state (immediately before entry to the HS-0 state)

◆ t_hs_prep

uint8_t mipi_phy_b_timing_t::t_hs_prep

Duration of the data lane LP-00 state (immediately before entry to the HS-0 state)

◆ t_clk_zero

uint8_t mipi_phy_b_timing_t::t_clk_zero

TCLKZERO setting.

◆ t_clk_pre

uint8_t mipi_phy_b_timing_t::t_clk_pre

TCLKPRE setting.

◆ t_clk_post

uint8_t mipi_phy_b_timing_t::t_clk_post

TCLKPOST setting.

◆ t_clk_trail

uint8_t mipi_phy_b_timing_t::t_clk_trail

TCLKTRAIL setting.

◆ t_hs_zero

uint8_t mipi_phy_b_timing_t::t_hs_zero

THSZERO setting.

◆ t_hs_trail

uint8_t mipi_phy_b_timing_t::t_hs_trail

THSTRAIL setting.

◆ t_hs_exit

uint8_t mipi_phy_b_timing_t::t_hs_exit

THSEXIT setting.

◆ t_lp_exit

uint8_t mipi_phy_b_timing_t::t_lp_exit

Low-power transition time to High-Speed mode.


The documentation for this struct was generated from the following file: