Transfer (r_dmac_b)

Functions
fsp_err_t	R_DMAC_B_Open (transfer_ctrl_t *const p_api_ctrl, transfer_cfg_t const *const p_cfg)
fsp_err_t	R_DMAC_B_Reconfigure (transfer_ctrl_t *const p_api_ctrl, transfer_info_t *p_info)
fsp_err_t	R_DMAC_B_Reset (transfer_ctrl_t *const p_api_ctrl, void const *volatile p_src, void *volatile p_dest, uint16_t const num_transfers)
fsp_err_t	R_DMAC_B_SoftwareStart (transfer_ctrl_t *const p_api_ctrl, transfer_start_mode_t mode)
fsp_err_t	R_DMAC_B_SoftwareStop (transfer_ctrl_t *const p_api_ctrl)
fsp_err_t	R_DMAC_B_Enable (transfer_ctrl_t *const p_api_ctrl)
fsp_err_t	R_DMAC_B_Disable (transfer_ctrl_t *const p_api_ctrl)
fsp_err_t	R_DMAC_B_InfoGet (transfer_ctrl_t *const p_api_ctrl, transfer_properties_t *const p_info)
fsp_err_t	R_DMAC_B_Close (transfer_ctrl_t *const p_api_ctrl)
fsp_err_t	R_DMAC_B_Reload (transfer_ctrl_t *const p_api_ctrl, void const *p_src, void *p_dest, uint32_t const num_transfers)
fsp_err_t	R_DMAC_B_CallbackSet (transfer_ctrl_t *const p_api_ctrl, void(*p_callback)(dmac_b_callback_args_t *), void const *const p_context, dmac_b_callback_args_t *const p_callback_memory)
fsp_err_t	R_DMAC_B_LinkDescriptorSet (transfer_ctrl_t *const p_api_ctrl, dmac_b_link_cfg_t *p_descriptor)

Detailed Description

Driver for the DMAC peripheral on RZ MPUs. This module implements the Transfer Interface.

Overview

The Direct Memory Access Controller (DMAC) transfers data from one memory location to another without using the CPU.

Features

• Supports multiple transfer modes
  • Normal transfer
  • Block transfer
• Support Register mode and Link mode
• Supports Next0 Register set and Next1 Register set (Register mode only)
• Address increment, fixed
• Triggered by peripheral module events
  • See "Table On-Chip Module Requests"¹ or "Table DMA Transfer Request Detection Operation Setting Table"² in the user's manual
• Supports 1, 2, 4, 8, 16, 32, 64, 128 byte data units
• Configurable DMA transfer activation request source, detection method of DMA request signal and DACK output mode
• Configurable DMA transfer interval
• Configurable DMAC channel priority

Note

1. RZ/G2L, RZ/G2LC, RZ/G2UL and RZ/G3S

2. RZ/G3E

Configuration

Build Time Configurations for r_dmac_b

The following build time configurations are defined in fsp_cfg/r_dmac_b_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.

Configurations for Transfer > Transfer (r_dmac_b)

This module can be added to the Stacks tab via New Stack > Transfer > Transfer (r_dmac_b).

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_transfer0	Module name.
General > Unit	MCU Specific Options		Specify the hardware unit. In a multi-core environment, it is recommended to open a separate unit for each core.
General > Channel	Must be a valid integer between 0 and 15.	0	Specify the hardware channel.
General > Activation Source	MCU Specific Options		Select the DMAC transfer start event.
General > DACK Output mode	MCU Specific Options		Select DACK output mode.
General > External DREQ Input Pin Select	MCU Specific Options		Select DREQ input signal.
General > External DACK Output Pin Select	MCU Specific Options		Select DACK output signal.
General > External TEND Output Pin Select	MCU Specific Options		Select TEND output signal.
General > External DREQ Detection Mode	MCU Specific Options		External DREQ detection mode select.(This cannot be set on devices that do not have an external DREQ terminal)
General > DMAC Mode	Register Mode Link mode	Register Mode	Select DMAC Mode.
General > Channel Priority	Fixed Round Robin	module.driver.transfer_on_dmac_b.channel_priority.fixed	Channel Priority
Register Mode > Mode	Normal Block	Normal	Select the transfer mode.
Register Mode > Source Data Size	1 Byte 2 Bytes 4 Bytes 8 Bytes 16 Bytes 32 Bytes 64 Bytes 128 Bytes	2 Bytes	Select the source data size.
Register Mode > Destination Data Size	1 Byte 2 Bytes 4 Bytes 8 Bytes 16 Bytes 32 Bytes 64 Bytes 128 Bytes	2 Bytes	Select the destination data size.
Register Mode > Destination Address Mode	Incremented Fixed	Incremented	Select the address mode for the destination.
Register Mode > Source Address Mode	Incremented Fixed	Incremented	Select the address mode for the source.
Register Mode > DMA Activation Request Source Select	Requested by a transfer source module Requested by a transfer destination module	Requested by a transfer source module	DMA Activation Request Source Select.
Register Mode > Transfer Interval	Value must be a non-negative integer	0	Transfer interval
Register Mode > Transfer Continuation	DMA transfer only once Transfer with Setting 1 and Setting 2 alternately	DMA transfer only once	When Next0 Register Set Transfer completes, Next1 Register Set Transfer occurs
Register Mode > Setting 1 Destination Address	Manual Entry	NULL	Specify the transfer destination address.
Register Mode > Setting 1 Source Address	Manual Entry	NULL	Specify the transfer source address.
Register Mode > Setting 1 Total Number of Transfer Bytes	Value must be a non-negative integer	1	Specify the total number of transfer bytes.
Register Mode > Setting 2 Destination Address	Manual Entry	NULL	Specify the transfer destination address.(Use only when Transfer with Setting 1 and Setting 2 horizontally is selected in Transfer Continuatuion.)
Register Mode > Setting 2 Source Address	Manual Entry	NULL	Specify the transfer source address.(Use only when Transfer with Setting 1 and Setting 2 horizontally is selected in Transfer Continuatuion.)
Register Mode > Setting 2 Total Number of Transfer Bytes	Value must be a non-negative integer	1	Specify the total number of transfer bytes.(Use only when Transfer with Setting 1 and Setting 2 horizontally is selected in Transfer Continuatuion.)
Link Mode > Descriptor	Name must be a valid C symbol	NULL	DMAC Link mode descriptor symbol name.
Interrupts > Callback	Name must be a valid C symbol	NULL	A user callback that is called at the end of the transfer.
Interrupts > Context	Manual Entry	NULL	Pointer to the context structure passed through the callback argument.
Interrupts > Transfer End Interrupt Enable	MCU Specific Options		Enable the transfer end interrupt.
Interrupts > Transfer End Interrupt Priority	Value must be an integer between 0 and 255	12	Select the transfer end interrupt priority.

Warning

"DMA Activation Request Source Select", "Low Detection Enable", "High Detection Enable", and "DACK output" must be set according to the DMAC transfer request source. For details, see 'DMA Transfer Request Detection Operation Setting Table' of the user's manual.

Clock Configuration

The clock sources for the DMAC peripheral module vary depending on the device. These clocks are shown in the table below.

MPU Group	Clock Name
RZ/G2L	P1CLK
RZ/G2UL	P1CLK
RZ/G3S	P3CLK
RZ/G3E	I7CLK (for Unit 0), P7CLK (for Unit 1, 2), P11CLK (for Unit 3, 4)

Pin Configuration

This module can use DREQn, DACKn and TENDn pins as external pins¹ (n = 0~4).

• DREQn is used for external DMA transfer request input from an external device.
• DACKn is used for output of DMAC transfer request acceptance to an external device.
• TENDn is used for output of transfer completion to an external device.

Note

1. RZ/G3E only support

Usage Notes

Register Mode

In Register mode, a DMA transfer is performed by setting transfer information in each register. The address information of the transfer source and destination and the number of bytes to transfer, can be set up to two register sets (Next0 register set and Next1 register set), and continuous transfers can be performed alternately according to each setting. For more information, see the "Register Mode" section of the user's manual.

Link Mode

In Link mode, a DMA transfer is performed by reading a descriptor placed in the memory as the transfer information. The descriptor is configured by dmac_b_link_cfg_t struct. For more information, including what information can be set in the descriptor, see the "Link Mode" section of the user's manual.

Note

1. The descriptor must be aligned in 4-byte boundaries.

2. To set the transfer source/destination address, see 'Area Maps' chapter in the user's manual for details. If the device supports MMU, specify the physical address for the source/destination address. (Use R_MMU_VAtoPA to convert to a physical address.)

3. dmac_b_link_cfg_t::channel_cfg and dmac_b_link_cfg_t::channel_extension_cfg have configuration restrictions same as the DMAC CHCFG_n and CHEXT_n registers. For more information see 'CHCFG_n : Channel Configuration Register n' and 'CHEXT_n : Channel Extension Register n' section in the user's manual.

4. Setting the link destination of the last descriptor to the address of the previous descriptor configures the descriptors in a loop. When set the descriptor to a loop, disable Parameter Checking of Build Time Configuration to avoid infinite loop operation.

Transfer Modes

The DMAC Module supports two modes of operation.

• Normal Mode - In normal mode, a single data unit is forwarded each time a configured peripheral module event is received by the DMAC channel. The data unit can be 1 byte, 2 bytes, 4 bytes, 8 bytes, 16 bytes, 32 bytes, 64 bytes, or 128 bytes. The source and destination addresses can be fixed or incremented. The 32-bit counter decrements on every transfer. When the counter reaches 0, the peripheral module event no longer triggers the transfer and you can interrupt the CPU to signal that all transfers have finished.
• Block Mode - In block mode, the amount of data units transfered by each interrupt. For one DMA request, performs transfers until a DMA transfer completes. When the counter reaches 0, transfers will no longer be triggered by the peripheral module event and the CPU can be interrupted to signal that all transfers have finished.

Limitations

This driver only supports the transfer by non-secure access. Therefore, for slave areas with a security level set, be sure to change the slave level appropriately before performing a DMA transfer.

If CPU has built-in cache memory, the transfer source and destination should be placed to the area where the cache memory is set to disabled.

The execution of the Reload function must be completed during the transfer of Next0 or Next1. If the total number of bytes transferred is small, the next transfer may start before the function execution completes. In this case, continuous operation of DMAC transfer is not guaranteed, so when using the Reload function, it is recommended to set the number of bytes to be transferred a little longer, taking into account the bus clock frequency and interrupt processing time.

Examples

Basic Example

This is a basic example of minimal use of the DMAC in an application.

void dmac_minimal_example (void)
{

    /* Open the transfer instance with initial configuration. */
    fsp_err_t err = R_DMAC_B_Open(&g_transfer_ctrl, &g_transfer_cfg);


    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);


    /* Enable the DMAC to handle incoming transfer requests. */
    err = R_DMAC_B_Enable(&g_transfer_ctrl);
    assert(FSP_SUCCESS == err);

}

Link Mode Example

This is an example of an application using the DMAC link mode for continuous transfers. DMAC transfer is triggered by R_DMAC_B_SoftwareStart().

In this example, if the MMU is supported, the source and destination addresses are set to non-cached areas of system RAM.

#define TRANSFER_LENGTH_0           (2048)
#define TRANSFER_LENGTH_1           (1024)
#define TRANSFER_LENGTH_2           (512)
#define DMAC_CHCFG_SETTING_VALUE    (0x80400420)
#define DMAC_CHEXT_SETTING_VALUE    (0x00)

#if (BSP_FEATURE_DMAC_B_64BIT_SYSTEM == 1)

uint8_t g_src0[TRANSFER_LENGTH_0] BSP_ALIGN_VARIABLE(64)  __attribute__((section(".noncache_buffer"))); /* Placed at System RAM Non-Cache buffer area */
uint8_t g_dest0[TRANSFER_LENGTH_0] BSP_ALIGN_VARIABLE(64) __attribute__((section(".noncache_buffer"))); /* Placed at System RAM Non-Cache buffer area */
uint8_t g_src1[TRANSFER_LENGTH_1] BSP_ALIGN_VARIABLE(64)  __attribute__((section(".noncache_buffer"))); /* Placed at System RAM Non-Cache buffer area */
uint8_t g_dest1[TRANSFER_LENGTH_1] BSP_ALIGN_VARIABLE(64) __attribute__((section(".noncache_buffer"))); /* Placed at System RAM Non-Cache buffer area */
uint8_t g_src2[TRANSFER_LENGTH_2] BSP_ALIGN_VARIABLE(64)  __attribute__((section(".noncache_buffer"))); /* Placed at System RAM Non-Cache buffer area */
uint8_t g_dest2[TRANSFER_LENGTH_2] BSP_ALIGN_VARIABLE(64) __attribute__((section(".noncache_buffer"))); /* Placed at System RAM Non-Cache buffer area */

dmac_b_link_cfg_t transfer0_descriptor BSP_ALIGN_VARIABLE (64) __attribute__((section(".noncache_buffer"))) =
{
    .header.link_valid         = DMAC_B_LINK_VALID_DESCRIPTOR_ENABLE,
    .header.link_end           = DMAC_B_LINK_END_DISABLE,
    .header.write_back_disable = DMAC_B_LINK_WRITE_BACK_DISABLE,
    .header.interrupt_mask     = DMAC_B_LINK_INTERRUPT_MASK_DISABLE,
    .src_addr              = 0x0,                      /* Source address */
    .dest_addr             = 0x0,                      /* Destination address */
    .transaction_byte      = TRANSFER_LENGTH_0,        /* Transaction byte */
    .channel_cfg           = DMAC_CHCFG_SETTING_VALUE, /* Channel configuration register setting */
    .channel_interval      = 0,                        /* Channel interval. */
    .channel_extension_cfg = 0,                        /* Channel extension register setting */
    .next_link_addr        = 0,                        /* Next link address */
};

dmac_b_link_cfg_t transfer1_descriptor BSP_ALIGN_VARIABLE (64) __attribute__((section(".noncache_buffer"))) =
{
    .header.link_valid         = DMAC_B_LINK_VALID_DESCRIPTOR_ENABLE,
    .header.link_end           = DMAC_B_LINK_END_DISABLE,
    .header.write_back_disable = DMAC_B_LINK_WRITE_BACK_DISABLE,
    .header.interrupt_mask     = DMAC_B_LINK_INTERRUPT_MASK_DISABLE,
    .src_addr              = 0x0,                      /* Source address */
    .dest_addr             = 0x0,                      /* Destination address */
    .transaction_byte      = TRANSFER_LENGTH_1,        /* Transaction byte */
    .channel_cfg           = DMAC_CHCFG_SETTING_VALUE, /* Channel configuration register setting */
    .channel_interval      = 0,                        /* Channel interval. */
    .channel_extension_cfg = 0,                        /* Channel extension register setting */
    .next_link_addr        = 0,                        /* Next link address */
};

dmac_b_link_cfg_t transfer2_descriptor BSP_ALIGN_VARIABLE (64) __attribute__((section(".noncache_buffer"))) =
{
    .header.link_valid         = DMAC_B_LINK_VALID_DESCRIPTOR_ENABLE,
    .header.link_end           = DMAC_B_LINK_END_ENABLE,
    .header.write_back_disable = DMAC_B_LINK_WRITE_BACK_DISABLE,
    .header.interrupt_mask     = DMAC_B_LINK_INTERRUPT_MASK_DISABLE,
    .src_addr              = 0x0,                      /* Source address */
    .dest_addr             = 0x0,                      /* Destination address */
    .transaction_byte      = TRANSFER_LENGTH_2,        /* Transaction byte */
    .channel_cfg           = DMAC_CHCFG_SETTING_VALUE, /* Channel configuration register setting */
    .channel_interval      = 0,                        /* Channel interval. */
    .channel_extension_cfg = 0,                        /* Channel extension register setting */
    .next_link_addr        = 0,                        /* Next link address */
};

#else

uint8_t g_src0[TRANSFER_LENGTH_0];     /* Placed at System RAM area */
uint8_t g_dest0[TRANSFER_LENGTH_0];    /* Placed at System RAM area */
uint8_t g_src1[TRANSFER_LENGTH_1];     /* Placed at System RAM area */
uint8_t g_dest1[TRANSFER_LENGTH_1];    /* Placed at System RAM area */
uint8_t g_src2[TRANSFER_LENGTH_2];     /* Placed at System RAM area */
uint8_t g_dest2[TRANSFER_LENGTH_2];    /* Placed at System RAM area */

dmac_b_link_cfg_t transfer0_descriptor BSP_ALIGN_VARIABLE (4) =
{
    .header.link_valid         = DMAC_B_LINK_VALID_DESCRIPTOR_ENABLE,
    .header.link_end           = DMAC_B_LINK_END_DISABLE,
    .header.write_back_disable = DMAC_B_LINK_WRITE_BACK_DISABLE,
    .header.interrupt_mask     = DMAC_B_LINK_INTERRUPT_MASK_DISABLE,
    .p_src                 = (void *) ((uint32_t) &g_src0[0]),  /* Source address */
    .p_dest                = (void *) ((uint32_t) &g_dest0[0]), /* Destination address */
    .transaction_byte      = TRANSFER_LENGTH_0,                 /* Transaction byte */
    .channel_cfg           = DMAC_CHCFG_SETTING_VALUE,          /* Channel configuration register setting */
    .channel_interval      = 0,                                 /* Channel interval. */
    .channel_extension_cfg = 0,                                 /* Channel extension register setting */
    .p_next_link_addr      = NULL,                              /* Next link address */
};

dmac_b_link_cfg_t transfer1_descriptor BSP_ALIGN_VARIABLE (4) =
{
    .header.link_valid         = DMAC_B_LINK_VALID_DESCRIPTOR_ENABLE,
    .header.link_end           = DMAC_B_LINK_END_DISABLE,
    .header.write_back_disable = DMAC_B_LINK_WRITE_BACK_DISABLE,
    .header.interrupt_mask     = DMAC_B_LINK_INTERRUPT_MASK_DISABLE,
    .p_src                 = (void *) ((uint32_t) &g_src1[0]),  /* Source address */
    .p_dest                = (void *) ((uint32_t) &g_dest1[0]), /* Destination address */
    .transaction_byte      = TRANSFER_LENGTH_1,                 /* Transaction byte */
    .channel_cfg           = DMAC_CHCFG_SETTING_VALUE,          /* Channel configuration register setting */
    .channel_interval      = 0,                                 /* Channel interval. */
    .channel_extension_cfg = 0,                                 /* Channel extension register setting */
    .p_next_link_addr      = NULL,                              /* Next link address */
};

dmac_b_link_cfg_t transfer2_descriptor BSP_ALIGN_VARIABLE (4) =
{
    .header.link_valid         = DMAC_B_LINK_VALID_DESCRIPTOR_ENABLE,
    .header.link_end           = DMAC_B_LINK_END_ENABLE,
    .header.write_back_disable = DMAC_B_LINK_WRITE_BACK_DISABLE,
    .header.interrupt_mask     = DMAC_B_LINK_INTERRUPT_MASK_DISABLE,
    .p_src                 = (void *) ((uint32_t) &g_src2[0]),  /* Source address */
    .p_dest                = (void *) ((uint32_t) &g_dest2[0]), /* Destination address */
    .transaction_byte      = TRANSFER_LENGTH_2,                 /* Transaction byte */
    .channel_cfg           = DMAC_CHCFG_SETTING_VALUE,          /* Channel configuration register setting */
    .channel_interval      = 0,                                 /* Channel interval. */
    .channel_extension_cfg = 0,                                 /* Channel extension register setting */
    .p_next_link_addr      = NULL,                              /* Next link address */
};

#endif

volatile bool g_transfer_complete = false;

void dmac_callback (transfer_callback_args_t * p_args)
{
    FSP_PARAMETER_NOT_USED(p_args);
    g_transfer_complete = true;
}

void dmac_link_mode_example (void)
{
    for (uint32_t i = 0; i < TRANSFER_LENGTH_0; i++)
    {
        g_src0[i] = (uint8_t) ('A' + (i % 26));
    }

    for (uint32_t i = 0; i < TRANSFER_LENGTH_1; i++)
    {
        g_src1[i] = (uint8_t) ('A' + (i % 26));
    }

    for (uint32_t i = 0; i < TRANSFER_LENGTH_2; i++)
    {
        g_src2[i] = (uint8_t) ('A' + (i % 26));
    }

#if (BSP_FEATURE_BSP_HAS_MMU_SUPPORT)

    /*  To set the physical address, use R_MMU_VAtoPA function to convert from the virtual address to the physical address. */
    uint64_t * p_src_paddress = 0;
    R_MMU_VAtoPA(NULL, (uint64_t) &g_src0[0], p_src_paddress);
    transfer0_descriptor.src_addr = (uint32_t) *p_src_paddress;

    uint64_t * p_dest_paddress = 0;
    R_MMU_VAtoPA(NULL, (uint64_t) &g_dest0[0], p_dest_paddress);
    transfer0_descriptor.dest_addr = (uint32_t) *p_dest_paddress;

    uint64_t * p_next_link_paddress = 0;
    R_MMU_VAtoPA(NULL, (uint64_t) &transfer1_descriptor, p_next_link_paddress);
    transfer0_descriptor.next_link_addr = (uint32_t) *p_next_link_paddress;

    R_MMU_VAtoPA(NULL, (uint64_t) &g_src1[0], p_src_paddress);
    transfer1_descriptor.src_addr = (uint32_t) *p_src_paddress;

    R_MMU_VAtoPA(NULL, (uint64_t) &g_dest1[0], p_dest_paddress);
    transfer1_descriptor.dest_addr = (uint32_t) *p_dest_paddress;

    R_MMU_VAtoPA(NULL, (uint64_t) &transfer2_descriptor, p_next_link_paddress);
    transfer1_descriptor.next_link_addr = (uint32_t) *p_next_link_paddress;

    R_MMU_VAtoPA(NULL, (uint64_t) &g_src2[0], p_src_paddress);
    transfer2_descriptor.src_addr = (uint32_t) *p_src_paddress;

    R_MMU_VAtoPA(NULL, (uint64_t) &g_dest2[0], p_dest_paddress);
    transfer2_descriptor.dest_addr = (uint32_t) *p_dest_paddress;
#else
    transfer0_descriptor.p_next_link_addr = &transfer1_descriptor;
    transfer1_descriptor.p_next_link_addr = &transfer2_descriptor;
#endif

    /* Open the transfer instance with initial configuration. */
    fsp_err_t err = R_DMAC_B_Open(&g_transfer_ctrl, &g_transfer_cfg);
    assert(FSP_SUCCESS == err);

    /* Reset transfer descriptor. */
    err = R_DMAC_B_LinkDescriptorSet(&g_transfer_ctrl, &transfer0_descriptor);
    assert(FSP_SUCCESS == err);

    /* Trigger the transfer using software. */
    err = R_DMAC_B_SoftwareStart(&g_transfer_ctrl, (transfer_start_mode_t) NULL);
    assert(FSP_SUCCESS == err);

    while (!g_transfer_complete)
    {
        /* Wait for the first transfer complete interrupt */
    }

    g_transfer_complete = false;

    /* Trigger the transfer using software. */
    err = R_DMAC_B_SoftwareStart(&g_transfer_ctrl, (transfer_start_mode_t) NULL);
    assert(FSP_SUCCESS == err);

    while (!g_transfer_complete)
    {
        /* Wait for the second transfer complete interrupt */
    }

    g_transfer_complete = false;

    /* Trigger the transfer using software. */
    err = R_DMAC_B_SoftwareStart(&g_transfer_ctrl, (transfer_start_mode_t) NULL);
    assert(FSP_SUCCESS == err);

    while (!g_transfer_complete)
    {
        /* Wait for the third transfer complete interrupt */
    }
}

Data Structures
struct	dmac_b_register_set_setting_t
struct	dmac_b_link_cfg_t
struct	dmac_b_instance_ctrl_t
struct	dmac_b_extended_cfg_t
struct	dmac_b_extended_info_t

Macros
#define	DMAC_B_MAX_NORMAL_TRANSFER_LENGTH
#define	DMAC_B_MAX_BLOCK_TRANSFER_LENGTH

Enumerations
enum	dmac_b_transfer_size_t
enum	dmac_b_ack_mode_t
enum	dmac_b_external_detection_t
enum	dmac_b_internal_detection_t
enum	dmac_b_request_direction_t
enum	dmac_b_continuous_setting_t
enum	dmac_b_channel_scheduling_t
enum	dmac_b_mode_select_t
enum	dmac_b_link_valid_t
enum	dmac_b_link_end_t
enum	dmac_b_link_write_back_t
enum	dmac_b_link_interrupt_mask_t

---

Data Structure Documentation

dmac_b_register_set_setting_t

struct dmac_b_register_set_setting_t

Register set settings.

Data Fields
void const *	p_src	Source pointer.
void *	p_dest	Destination pointer.
uint32_t	length	Transfer byte.

dmac_b_link_cfg_t

struct dmac_b_link_cfg_t

Descriptor structure used in DMAC link mode, and variables of dmac_b_link_cfg_t must be allocated in the memory area.

Data Fields
union dmac_b_link_cfg_t	__unnamed__
void const *volatile	p_src	Source address.
void *volatile	p_dest	Destination address.
volatile uint32_t	transaction_byte	Transaction byte.
volatile uint32_t	channel_cfg	Channel configuration (Set value for CHCFG_n register).
volatile uint32_t	channel_interval	Channel interval (Set value for CHITVL register).
volatile uint32_t	channel_extension_cfg	Channel extension configuration (Set value for CHEXT_n register).
void *volatile	p_next_link_addr	Next link address.

dmac_b_instance_ctrl_t

struct dmac_b_instance_ctrl_t

Control block used by driver. DO NOT INITIALIZE - this structure will be initialized in transfer_api_t::open.

dmac_b_extended_cfg_t

struct dmac_b_extended_cfg_t

DMAC transfer configuration extension. This extension is required.

Data Fields
uint8_t	unit
	Unit number.
uint8_t	channel
	Channel number.
IRQn_Type	dmac_int_irq
	DMAC interrupt number.
uint8_t	dmac_int_ipl
	DMAC interrupt priority.
dmac_trigger_event_t	activation_source
dmac_b_ack_mode_t	ack_mode
	DACK output mode.
dmac_b_external_input_pin_t	dreq_input_pin
	DREQ input pin name.
dmac_b_external_output_pin_t	ack_output_pin
	DACK output pin name.
dmac_b_external_output_pin_t	tend_output_pin
	TEND output pin name.
dmac_b_external_detection_t	external_detection_mode
	DMAC request detection method for external pin.
dmac_b_internal_detection_t	internal_detection_mode
	DMAC request detection method for internal pin.
dmac_b_request_direction_t	activation_request_source_select
	DMAC activation request source.
dmac_b_mode_select_t	dmac_mode
	DMAC Mode.
dmac_b_link_cfg_t const *	p_descriptor
	The address of the descriptor (DMA Link Mode only)
dmac_b_continuous_setting_t	continuous_setting
	Next register operation settings.
uint16_t	transfer_interval
	DMA transfer interval.
dmac_b_channel_scheduling_t	channel_scheduling
	DMA channel scheduling.
void(*	p_callback )(dmac_b_callback_args_t *cb_data)
void const *	p_context
void *	p_reg
	Register base address for specified unit.

Field Documentation

activation_source

dmac_trigger_event_t dmac_b_extended_cfg_t::activation_source

Select which event will trigger the transfer.

p_callback

void(* dmac_b_extended_cfg_t::p_callback) (dmac_b_callback_args_t *cb_data)

Callback for transfer end interrupt.

p_context

void const* dmac_b_extended_cfg_t::p_context

Placeholder for user data. Passed to the user p_callback in transfer_callback_args_t.

dmac_b_extended_info_t

struct dmac_b_extended_info_t

DMAC transfer information configuration extension. This extension is required.

Data Fields
dmac_b_transfer_size_t	src_size	Select number of source bytes to transfer at once.
dmac_b_transfer_size_t	dest_size	Select number of destination bytes to transfer at once.
dmac_b_register_set_setting_t *	p_next1_register_setting	Next1 Register set settings

Macro Definition Documentation

DMAC_B_MAX_NORMAL_TRANSFER_LENGTH

#define DMAC_B_MAX_NORMAL_TRANSFER_LENGTH

Max configurable number of transfers in TRANSFER_MODE_NORMAL.

DMAC_B_MAX_BLOCK_TRANSFER_LENGTH

#define DMAC_B_MAX_BLOCK_TRANSFER_LENGTH

Max number of transfers per block in TRANSFER_MODE_BLOCK

Enumeration Type Documentation

dmac_b_transfer_size_t

enum dmac_b_transfer_size_t

Transfer size specifies the size of each individual transfer.

Enumerator
DMAC_B_TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
DMAC_B_TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
DMAC_B_TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
DMAC_B_TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
DMAC_B_TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
DMAC_B_TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
DMAC_B_TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
DMAC_B_TRANSFER_SIZE_128_BYTE	Each transfer transfers a 1024-bit value.

dmac_b_ack_mode_t

enum dmac_b_ack_mode_t

DACK output mode.

Enumerator
DMAC_B_ACK_MODE_LEVEL_MODE	Level mode.
DMAC_B_ACK_MODE_BUS_CYCLE_MODE	Bus cycle mode.
DMAC_B_ACK_MODE_MASK_DACK_OUTPUT	Output is masked.

dmac_b_external_detection_t

enum dmac_b_external_detection_t

Detection method of the external DMA request signal.

Enumerator
DMAC_B_EXTERNAL_DETECTION_LOW_LEVEL	Low level detection.
DMAC_B_EXTERNAL_DETECTION_FALLING_EDGE	Falling edge detection.
DMAC_B_EXTERNAL_DETECTION_RISING_EDGE	Rising edge detection.
DMAC_B_EXTERNAL_DETECTION_FALLING_RISING_EDGE	Falling/Rising edge detection.
DMAC_B_EXTERNAL_DETECTION_NO_DETECTION	Not using hardware detection.
DMAC_B_EXTERNAL_DETECTION_NO_DETECTION	Not using hardware detection.
DMAC_B_EXTERNAL_DETECTION_NO_DETECTION	Not using hardware detection.

dmac_b_internal_detection_t

enum dmac_b_internal_detection_t

Detection method of the internal DMA request signal.

Enumerator
DMAC_B_INTERNAL_DETECTION_NO_DETECTION	Not using hardware detection.
DMAC_B_INTERNAL_DETECTION_FALLING_EDGE	Falling edge detection.
DMAC_B_INTERNAL_DETECTION_RISING_EDGE	Rising edge detection.
DMAC_B_INTERNAL_DETECTION_LOW_LEVEL	Low level detection.
DMAC_B_INTERNAL_DETECTION_HIGH_LEVEL	High level detection.

dmac_b_request_direction_t

enum dmac_b_request_direction_t

DMA activation request source select.

Enumerator
DMAC_B_REQUEST_DIRECTION_SOURCE_MODULE	Requested by a transfer source module.
DMAC_B_REQUEST_DIRECTION_DESTINATION_MODULE	Requested by a transfer destination module.

dmac_b_continuous_setting_t

enum dmac_b_continuous_setting_t

Select the Next register set to be executed next.

Enumerator
DMAC_B_CONTINUOUS_SETTING_TRANSFER_ONCE	Transfer only once using the Next0 register set.
DMAC_B_CONTINUOUS_SETTING_TRANSFER_ALTERNATELY	Transfers are performed alternately with the Next0 register set and the Next1 register set.

dmac_b_channel_scheduling_t

enum dmac_b_channel_scheduling_t

DMAC channel scheduling.

Enumerator
DMAC_B_CHANNEL_SCHEDULING_FIXED	Fixed priority mode.
DMAC_B_CHANNEL_SCHEDULING_ROUND_ROBIN	Round-robin mode.

dmac_b_mode_select_t

enum dmac_b_mode_select_t

DMAC mode setting.

Enumerator
DMAC_B_MODE_SELECT_REGISTER	Register mode.
DMAC_B_MODE_SELECT_LINK	Link mode.

dmac_b_link_valid_t

enum dmac_b_link_valid_t

Indicates the descriptor is enabled or disabled.

Enumerator
DMAC_B_LINK_VALID_DESCRIPTOR_DISABLE	The Descriptor is disabled.
DMAC_B_LINK_VALID_DESCRIPTOR_ENABLE	The Descriptor is enabled.

dmac_b_link_end_t

enum dmac_b_link_end_t

Indicates that the link ends during DMA transfer of this descriptor.

Enumerator
DMAC_B_LINK_END_DISABLE	The link continues.
DMAC_B_LINK_END_ENABLE	The link ends.

dmac_b_link_write_back_t

enum dmac_b_link_write_back_t

Masks write back execution of the dmac_b_link_cfg_t::link_valid. When disable, DMAC does not perform write-back operation.

Enumerator
DMAC_B_LINK_WRITE_BACK_ENABLE	Set dmac_b_link_cfg_t::link_valid to disable after the DMA transfer ends.
DMAC_B_LINK_WRITE_BACK_DISABLE	Remain dmac_b_link_cfg_t::link_valid after DMA transfer ends.

dmac_b_link_interrupt_mask_t

enum dmac_b_link_interrupt_mask_t

When dmac_b_link_cfg_t::link_valid is DMAC_B_LINK_VALID_DESCRIPTOR_DISABLE at loading of header, specifies whether DMA transfer completion interrupt mask or not.

Enumerator
DMAC_B_LINK_INTERRUPT_MASK_DISABLE	DMA transfer completion interrupt is asserted.
DMAC_B_LINK_INTERRUPT_MASK_ENABLE	DMA transfer completion interrupt is masked.

Function Documentation

R_DMAC_B_Open()

fsp_err_t R_DMAC_B_Open	(	transfer_ctrl_t *const	p_api_ctrl,
		transfer_cfg_t const *const	p_cfg
	)

Configure a DMAC channel.

Return values

FSP_SUCCESS	Successful open.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	The configured channel is invalid.
FSP_ERR_IRQ_BSP_DISABLED	The IRQ associated with the activation source is not enabled in the BSP.
FSP_ERR_ALREADY_OPEN	The control structure is already opened.

R_DMAC_B_Reconfigure()

fsp_err_t R_DMAC_B_Reconfigure	(	transfer_ctrl_t *const	p_api_ctrl,
		transfer_info_t *	p_info
	)

Reconfigure the transfer with new transfer info.

Return values

FSP_SUCCESS	Transfer is configured and will start when trigger occurs.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_ENABLED	DMAC is not enabled. The current configuration must not be valid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.

R_DMAC_B_Reset()

fsp_err_t R_DMAC_B_Reset	(	transfer_ctrl_t *const	p_api_ctrl,
		void const *volatile	p_src,
		void *volatile	p_dest,
		uint16_t const	num_transfers
	)

Reset transfer source, destination, and number of transfers.

Return values

FSP_ERR_UNSUPPORTED

API not supported.

R_DMAC_B_SoftwareStart()

fsp_err_t R_DMAC_B_SoftwareStart	(	transfer_ctrl_t *const	p_api_ctrl,
		transfer_start_mode_t	mode
	)

If the mode is TRANSFER_START_MODE_SINGLE initiate a single transfer with software. If the mode is TRANSFER_START_MODE_REPEAT continue triggering transfers until all of the transfers are completed.

Return values

FSP_SUCCESS	Transfer started written successfully.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.

R_DMAC_B_SoftwareStop()

fsp_err_t R_DMAC_B_SoftwareStop

(

transfer_ctrl_t *const

p_api_ctrl

)

Stop software transfers if they were started with TRANSFER_START_MODE_REPEAT.

Return values

FSP_SUCCESS	Transfer stopped written successfully.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.

R_DMAC_B_Enable()

fsp_err_t R_DMAC_B_Enable

(

transfer_ctrl_t *const

p_api_ctrl

)

Enable transfers for the configured activation source.

Return values

FSP_SUCCESS	Counter value written successfully.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.

R_DMAC_B_Disable()

fsp_err_t R_DMAC_B_Disable

(

transfer_ctrl_t *const

p_api_ctrl

)

Disable transfers so that they are no longer triggered by the activation source.

Return values

FSP_SUCCESS	Counter value written successfully.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.

R_DMAC_B_InfoGet()

fsp_err_t R_DMAC_B_InfoGet	(	transfer_ctrl_t *const	p_api_ctrl,
		transfer_properties_t *const	p_info
	)

Set driver specific information in provided pointer.

Return values

FSP_SUCCESS	Information has been written to p_info.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.
FSP_ERR_ASSERTION	An input parameter is invalid.

R_DMAC_B_Close()

fsp_err_t R_DMAC_B_Close

(

transfer_ctrl_t *const

p_api_ctrl

)

Disable transfer and clean up internal data. Implements transfer_api_t::close.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.

R_DMAC_B_Reload()

fsp_err_t R_DMAC_B_Reload	(	transfer_ctrl_t *const	p_api_ctrl,
		void const *volatile	p_src,
		void *volatile	p_dest,
		uint32_t const	num_transfers
	)

Make the following transfer settings to continue the transfer.

Return values

FSP_SUCCESS	Successful continuous transfer settings.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.
FSP_ERR_INVALID_MODE	This API cannot be called during link mode operation or setting not to use the Next1 register.

R_DMAC_B_CallbackSet()

fsp_err_t R_DMAC_B_CallbackSet	(	transfer_ctrl_t *const	p_api_ctrl,
		void(*)(dmac_b_callback_args_t *)	p_callback,
		void const *const	p_context,
		dmac_b_callback_args_t *const	p_callback_memory
	)

Updates the user callback with the option to provide memory for the callback argument structure. Implements transfer_api_t::callbackSet.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

R_DMAC_B_LinkDescriptorSet()

fsp_err_t R_DMAC_B_LinkDescriptorSet	(	transfer_ctrl_t *const	p_api_ctrl,
		dmac_b_link_cfg_t *	p_descriptor
	)

Reconfigure the transfer descriptor information with new transfer descriptor.

Return values

FSP_SUCCESS	Transfer is configured and will start when trigger occurs.
FSP_ERR_ASSERTION	An input parameter pointer is NULL.
FSP_ERR_NOT_ENABLED	DMAC is not enabled. The current configuration must not be valid.
FSP_ERR_INVALID_MODE	DMA mode is register mode. This function can only be used when the DMA mode is link mode.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_B_Open to initialize the control block.