RZG Flexible Software Package Documentation  Release v3.1.0

 
Watchdog (r_wdt)

Functions

fsp_err_t R_WDT_Refresh (wdt_ctrl_t *const p_ctrl)
 
fsp_err_t R_WDT_Open (wdt_ctrl_t *const p_ctrl, wdt_cfg_t const *const p_cfg)
 
fsp_err_t R_WDT_StatusClear (wdt_ctrl_t *const p_ctrl, const wdt_status_t status)
 
fsp_err_t R_WDT_StatusGet (wdt_ctrl_t *const p_ctrl, wdt_status_t *const p_status)
 
fsp_err_t R_WDT_CounterGet (wdt_ctrl_t *const p_ctrl, uint32_t *const p_count)
 
fsp_err_t R_WDT_TimeoutGet (wdt_ctrl_t *const p_ctrl, wdt_timeout_values_t *const p_timeout)
 
fsp_err_t R_WDT_CallbackSet (wdt_ctrl_t *const p_ctrl, void(*p_callback)(wdt_callback_args_t *), void const *const p_context, wdt_callback_args_t *const p_callback_memory)
 

Detailed Description

Driver for the WDT peripheral on RZ MPUs. This module implements the WDT Interface.

Overview

The watchdog timer is used to recover from unexpected errors in an application. The watchdog timer must be refreshed periodically in the permitted count window by the application. If the count is allowed to timeout or refresh occurs outside of the valid refresh period, the WDT resets the device or generates an IRQ. Note: The support for window functions or interrupt request generation varies across devices.

r_wdt_operation_example.png
Watchdog Timer Operation Example

Features

RZ/G2L, RZ/G2LC, RZ/G2UL and RZ/G3S

The WDT HAL module has the following key features:

RZ/G3E

Configuration

When using register start mode, configure the watchdog timer on the Stacks tab.

Build Time Configurations for r_wdt

The following build time configurations are defined in fsp_cfg/r_wdt_cfg.h:

ConfigurationOptionsDefaultDescription
Parameter Checking
  • Default (BSP)
  • Enabled
  • Disabled
Default (BSP) If selected code for parameter checking is included in the build.

Configurations for Monitoring > Watchdog (r_wdt)

This module can be added to the Stacks tab via New Stack > Monitoring > Watchdog (r_wdt).

ConfigurationOptionsDefaultDescription
General > NameName must be a valid C symbolg_wdt0 Module name.
General > ChannelMCU Specific OptionsCheck the user's manual: Hardware to see which CPU a channel is for.
General > TimeoutValue must be non-negative between 0.04369 and 178.960 Select the time (in seconds) before the WDT counter timeouts. (A single timeout does not generate a reset.)
General > TimeoutMCU Specific OptionsSelect the watchdog timeout in cycles.
General > Clock Division RatioMCU Specific OptionsSelect the watchdog clock divisor.
General > Window Start PositionMCU Specific OptionsSelect the allowed watchdog refresh start point in %.
General > Window End PositionMCU Specific OptionsSelect the allowed watchdog refresh end point in %.
General > WDT CountingMCU Specific OptionsSelect to enable or disable WDT counting. It is recommended to set "WDT Counting" to "Disabled" to avoid unintentional WDT interrupt occurs when debugging the user program.
Reset Operation > WDT Pin AssertionMCU Specific OptionsSelect to enable or disable the pin assertion due to a request by WDT.
Reset Operation > System ResetMCU Specific OptionsSelect to enable or disable system reset due to a request by WDT.
Reset Operation > Cold ResetMCU Specific OptionsSelect to enable or disable the cold reset due to a request by WDT.
Interrupt > Interrupt EnableMCU Specific OptionsEnable the WDT interrupt.
Interrupt > Interrupt PriorityValue must be an integer between 0 and 25524 Select the interrupt priority.
Interrupt > CallbackName must be a valid C symbolNULL A user callback function can be provided.

Clock Configuration

The WDT clock is based on the OSCCLK frequency. You can not set the OSCCLK frequency using the Clocks tab of the RZ Configuration editor or by using the CGC Interface at run-time. The below table describes the maximum timeout period on each device:

Device WDT clock source Maximum timeout period
RZ/G2L OSCCLK = 24MHz 178.9 seconds
RZ/G2LC OSCCLK = 24MHz 178.9 seconds
RZ/G2UL OSCCLK = 24MHz 178.9 seconds
RZ/G3S OSCCLK = 24MHz 178.9 seconds
RZ/G3E OSCCLK = 24MHz 0.175 seconds

Pin Configuration

This WDT uses the following pin.

Device Pin name Description
RZ/G2L WDTOVF_PERROUT Watchdog timer counter overflow signal output.
RZ/G2LC WDTOVF_PERROUT Watchdog timer counter overflow signal output.
RZ/G2UL WDTOVF_PERROUT Watchdog timer counter overflow signal output.
RZ/G3S WDTOVF_PERROUT Watchdog timer counter overflow signal output.
RZ/G3E WDTUDF_PERROUT Watchdog timer counter underflow signal output.

Usage Notes

Period Calculation

On RZ/G2L, RZ/G2LC, RZ/G2UL and RZ/G3S

The configuration editor can directly enter the timeout period (seconds) until timeout. The selectable timeout time (seconds) is from 0.04369(s) to 178.9(s).

Below is an example of calculating the maximum timeout time when OSCLK is 24MHz.

OSCCLK = 24 MHz
Timeout period = 1024 * 1024 * 4096 = 4294967296 cycles
(4095 : Register Settimg Max Value)
Cycle time = 1 / 24 MHz = 41.66 ns
Timeout = 41.66 us x 4294967296 cycles = 178.9 seconds

On RZ/G3E

The WDT operates from OSCCLK. With a OSCCLK of 24 MHz, the maximum time from the last refresh to device reset or IRQ generation will be just over 0.175 seconds as detailed below.

OSCCLK = 24 MHz
Clock division ratio = OSCCLK / 256
Timeout period = 16384 cycles
WDT clock frequency = 24 MHz / 256 = 93.750 kHz
Cycle time = 1 / 93.750 kHz = 10.667 us
Timeout = 10.667 us x 16384 cycles = 0.175 seconds

Limitations

On RZ/G3E

Developers should be aware of the following limitations when using the WDT:

WDT Interrupt

WDT interrupt to CPU are prohibited in specific core.

DeviceCore WDT interrupt to CPU
RZ/G2L Cortex-M33 Not prohibited
RZ/G2LCCortex-M33 Not prohibited
RZ/G2ULCortex-M33 Not prohibited
RZ/G3S Cortex-M33 Not prohibited
RZ/G3E Cortex-M33 Prohibited

Examples

WDT Basic Example

This is a basic example of minimal use of the WDT in an application.

void wdt_basic_example (void)
{
fsp_err_t err = FSP_SUCCESS;
/* Initializes the module. */
err = R_WDT_Open(&g_wdt_ctrl, &g_wdt_cfg);
/* Handle any errors. This function should be defined by the user. */
assert(FSP_SUCCESS == err);
/* Call R_WDT_Refresh to start the watchdog. */
err = R_WDT_Refresh(&g_wdt_ctrl);
assert(FSP_SUCCESS == err);
while (true)
{
/* Application work here. */
/* Refresh before the counter timeouts. */
err = R_WDT_Refresh(&g_wdt_ctrl);
assert(FSP_SUCCESS == err);
}
}

WDT Advanced Example

This example demonstrates starting the WDT and gives an example callback to handle an interrupt generated by a timeout or refresh error.

Configuration

Configuration is different for each device to run the example.

DeviceCoreChannelTimeoutClock Division RatioWindow Start PositionWindow End PositionWDT CountingWDT Pin AssertionSystem ResetCold ResetInterrupt Enable
RZ/G2 LCortex-M33 Channel 2 60 - (not available) - (not available) - (not available) Enable Disable Enable Disable Enable
RZ/G2LCCortex-M33 Channel 2 60 - (not available) - (not available) - (not available) Enable Disable Enable Disable Enable
RZ/G2ULCortex-M33 Channel 2 60 - (not available) - (not available) - (not available) Enable Disable Enable Disable Enable
RZ/G3S Cortex-M33 Channel 1 60 - (not available) - (not available) - (not available) Enable Disable Enable Disable Enable
RZ/G3S Cortex-M33_FPUChannel 2 60 - (not available) - (not available) - (not available) Enable Disable Enable Disable Enable
RZ/G3E Cortex-M33 Channel 0 16384 cyclesPCLK/256 100 0 Enable Disable Enable Disable - (not available)
#define WDT_START_WINDOW_75 ((WDT_TIMEOUT * 3) / 4)
/* Example callback called when a watchdog NMI occurs. */
void wdt_callback (wdt_callback_args_t * p_args)
{
fsp_err_t err = FSP_SUCCESS;
/* (Optional) Determine the source of the NMI. */
err = R_WDT_StatusGet(&g_wdt_ctrl, &status);
assert(FSP_SUCCESS == err);
/* (Optional) Clear the error flags. */
err = R_WDT_StatusClear(&g_wdt_ctrl, status);
assert(FSP_SUCCESS == err);
/* Call R_WDT_Refresh() to continue using the watchdog after an error. */
err = R_WDT_Refresh(&g_wdt_ctrl);
assert(FSP_SUCCESS == err);
}
void wdt_advanced_example (void)
{
fsp_err_t err = FSP_SUCCESS;
/* (Optional) Check if the system is recovering from a WDT reset. */
R_BSP_SystemResetStatusGet();
if (BSP_SYSTEM_RESET_STATUS_GENERATED == g_bsp_system_reset_status_table[BSP_SYSTEM_RESET_SIGNAL_WDT_CM33])
{
R_BSP_SystemResetStatusClear(BSP_SYSTEM_RESET_SIGNAL_WDT_CM33);
}
/* Open the module. */
err = R_WDT_Open(&g_wdt_ctrl, &g_wdt_cfg);
/* Handle any errors. This function should be defined by the user. */
assert(FSP_SUCCESS == err);
/* Initialize other application code. */
/* Call R_WDT_Refresh() to start the WDT. */
err = R_WDT_Refresh(&g_wdt_ctrl);
assert(FSP_SUCCESS == err);
while (true)
{
/* Application work here. */
/* (Optional) If there is a chance the application takes less time than
* the start window, verify the WDT counter is past the start window
* before refreshing the WDT. */
uint32_t wdt_counter = 0U;
do
{
/* Read the current WDT counter value. */
err = R_WDT_CounterGet(&g_wdt_ctrl, &wdt_counter);
assert(FSP_SUCCESS == err);
} while (wdt_counter <= WDT_START_WINDOW_75);
/* Refresh before the counter timeouts to prevent reset. */
err = R_WDT_Refresh(&g_wdt_ctrl);
assert(FSP_SUCCESS == err);
}
}

Data Structures

struct  wdt_instance_ctrl_t
 
struct  wdt_extended_cfg_t
 

Data Structure Documentation

◆ wdt_instance_ctrl_t

struct wdt_instance_ctrl_t

WDT private control block. DO NOT MODIFY. Initialization occurs when R_WDT_Open() is called.

◆ wdt_extended_cfg_t

struct wdt_extended_cfg_t

WDT configuration extension. This extension is required.

Function Documentation

◆ R_WDT_Refresh()

fsp_err_t R_WDT_Refresh ( wdt_ctrl_t *const  p_ctrl)

Refresh the watchdog timer. Implements wdt_api_t::refresh.

In addition to refreshing the watchdog counter this function can be used to start the counter in register start mode.

Example:

/* Refresh before the counter timeouts. */
err = R_WDT_Refresh(&g_wdt_ctrl);
assert(FSP_SUCCESS == err);
Return values
FSP_SUCCESSWDT successfully refreshed.
FSP_ERR_ASSERTIONp_ctrl is NULL.
FSP_ERR_NOT_OPENInstance control block is not initialized.

◆ R_WDT_Open()

fsp_err_t R_WDT_Open ( wdt_ctrl_t *const  p_ctrl,
wdt_cfg_t const *const  p_cfg 
)

Configures the WDT driver based on the input configurations. This function sets the callback function, the timeout count value, and enables the timeout interrupt. Implements wdt_api_t::open.

This function should only be called once as WDT configuration registers can only be written to once so subsequent calls will have no effect.

Example:

/* Initializes the module. */
err = R_WDT_Open(&g_wdt_ctrl, &g_wdt_cfg);
Return values
FSP_SUCCESSWDT successfully configured.
FSP_ERR_ASSERTIONNull pointer, or one or more configuration options is invalid.
FSP_ERR_ALREADY_OPENModule is already open. This module can only be opened once.

◆ R_WDT_StatusClear()

fsp_err_t R_WDT_StatusClear ( wdt_ctrl_t *const  p_ctrl,
const wdt_status_t  status 
)

Clear the WDT status and error flags. Implements wdt_api_t::statusClear.

Example:

/* (Optional) Clear the error flags. */
err = R_WDT_StatusClear(&g_wdt_ctrl, status);
assert(FSP_SUCCESS == err);
Return values
FSP_SUCCESSWDT flag(s) successfully cleared.
FSP_ERR_ASSERTIONNull pointer as a parameter.
FSP_ERR_NOT_OPENInstance control block is not initialized.

◆ R_WDT_StatusGet()

fsp_err_t R_WDT_StatusGet ( wdt_ctrl_t *const  p_ctrl,
wdt_status_t *const  p_status 
)

Read the WDT status flags. Implements wdt_api_t::statusGet.

Indicates both status and error conditions.

Example:

/* (Optional) Determine the source of the NMI. */
err = R_WDT_StatusGet(&g_wdt_ctrl, &status);
assert(FSP_SUCCESS == err);
Return values
FSP_SUCCESSWDT status successfully read.
FSP_ERR_ASSERTIONNull pointer as a parameter.
FSP_ERR_NOT_OPENInstance control block is not initialized.

◆ R_WDT_CounterGet()

fsp_err_t R_WDT_CounterGet ( wdt_ctrl_t *const  p_ctrl,
uint32_t *const  p_count 
)

Read the current count value of the WDT. Implements wdt_api_t::counterGet.

Example:

/* Read the current WDT counter value. */
err = R_WDT_CounterGet(&g_wdt_ctrl, &wdt_counter);
assert(FSP_SUCCESS == err);
Return values
FSP_SUCCESSWDT current count successfully read.
FSP_ERR_ASSERTIONNull pointer passed as a parameter.
FSP_ERR_NOT_OPENInstance control block is not initialized.

◆ R_WDT_TimeoutGet()

fsp_err_t R_WDT_TimeoutGet ( wdt_ctrl_t *const  p_ctrl,
wdt_timeout_values_t *const  p_timeout 
)

Read timeout information for the watchdog timer. Implements wdt_api_t::timeoutGet.

Return values
FSP_SUCCESSWDT timeout information retrieved successfully.
FSP_ERR_ASSERTIONNull Pointer.
FSP_ERR_NOT_OPENInstance control block is not initialized.

◆ R_WDT_CallbackSet()

fsp_err_t R_WDT_CallbackSet ( wdt_ctrl_t *const  p_ctrl,
void(*)(wdt_callback_args_t *)  p_callback,
void const *const  p_context,
wdt_callback_args_t *const  p_callback_memory 
)

Updates the user callback and has option of providing memory for callback structure. Implements wdt_api_t::callbackSet

Return values
FSP_SUCCESSCallback updated successfully.
FSP_ERR_ASSERTIONA required pointer is NULL.
FSP_ERR_NOT_OPENThe control block has not been opened.
FSP_ERR_NO_CALLBACK_MEMORYp_callback is non-secure and p_callback_memory is either secure or NULL.