Expanded Serial Peripheral Interface (xSPI) QSPI (r_xspi_qspi)

Functions
fsp_err_t	R_XSPI_QSPI_Open (spi_flash_ctrl_t *p_ctrl, spi_flash_cfg_t const *const p_cfg)
fsp_err_t	R_XSPI_QSPI_Close (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_XSPI_QSPI_DirectWrite (spi_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint32_t const bytes, bool const read_after_write)
fsp_err_t	R_XSPI_QSPI_DirectRead (spi_flash_ctrl_t *p_ctrl, uint8_t *const p_dest, uint32_t const bytes)
fsp_err_t	R_XSPI_QSPI_SpiProtocolSet (spi_flash_ctrl_t *p_ctrl, spi_flash_protocol_t spi_protocol)
fsp_err_t	R_XSPI_QSPI_XipEnter (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_XSPI_QSPI_XipExit (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_XSPI_QSPI_Write (spi_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint8_t *const p_dest, uint32_t byte_count)
fsp_err_t	R_XSPI_QSPI_Erase (spi_flash_ctrl_t *p_ctrl, uint8_t *const p_device_address, uint32_t byte_count)
fsp_err_t	R_XSPI_QSPI_StatusGet (spi_flash_ctrl_t *p_ctrl, spi_flash_status_t *const p_status)
fsp_err_t	R_XSPI_QSPI_BankSet (spi_flash_ctrl_t *p_ctrl, uint32_t bank)
fsp_err_t	R_XSPI_QSPI_DirectTransfer (spi_flash_ctrl_t *p_ctrl, spi_flash_direct_transfer_t *const p_transfer, spi_flash_direct_transfer_dir_t direction)
fsp_err_t	R_XSPI_QSPI_AutoCalibrate (spi_flash_ctrl_t *p_ctrl)

Detailed Description

Driver for the xSPI peripheral on RZ microprocessor. This module implements the SPI Flash Interface.

Overview

Features

The xSPI QSPI driver has the following key features:

• Memory mapped read access to the QSPI flash
• Programming the QSPI flash device
• Erasing the QSPI flash device
• Sending device specific commands and reading back responses, not
• Supports each xSPI protocol
• Entering and exiting XIP mode
• 3 or 4 byte addressing
• Supports combination function during write access of memory-mapping mode
• Configurable prefetch function during read transaction in memory-mapping mode

Note

The available chip select lines may differ between devices. A full list of selectable chip select lines is available in the User's Manual for your device.

Configuration

Build Time Configurations for r_xspi_qspi

The following build time configurations are defined in driver/r_xspi_qspi_cfg.h:

Configuration	Options	Default	Description
Parameter Checking Enable	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.

Configurations for Storage > QSPI (r_xspi_qspi)

This module can be added to the Stacks tab via New Stack > Storage > QSPI (r_xspi_qspi).

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_qspi0	Module name.
General > unit	Unit should be 0	0	Specify the xSPI unit number.
General > Chip Select	Chip Select 0 Chip Select 1	Chip Select 0	Specify the XSPI chip select line to use.
General > SPI Protocol	1S-1S-1S 4S-4D-4D 1S-2S-2S 2S-2S-2S 1S-4S-4S 4S-4S-4S	1S-1S-1S	Select the initial SPI protocol. SPI protocol can be changed in R_XSPI_QSPI_SpiProtocolSet().
General > Address Bytes	3 4	3	Select the number of address bytes. If 4-byte mode is selected, the application must issue the EN4B command using R_XSPI_QSPI_DirectTransfer().
General > Dummy Clocks for Read	Refer to the RZG Configuration tool for available options.	0	Select the number of dummy clocks for read operations.
General > Prefetch Function	Disable Enable	Disable	Prefetch function settings.
Command Definitions > Page Program Command	Must be an 8-bit QSPI command	0x02	The command to program a page.
Command Definitions > Read Command	Must be an 8-bit QSPI command	0x03	The command to read.
Command Definitions > Write Enable Command	Must be an 8-bit QSPI command	0x06	The command to enable write.
Command Definitions > Status Command	Must be an 8-bit QSPI command	0x05	The command to query the status of a write or erase command.
Command Definitions > Write Status Bit	Must be an integer between 0 and 7	0	Which bit contains the write in progress status returned from the Write Status Command.
Command Definitions > Sector Erase Command	Must be an 8-bit QSPI command	0x20	The command to erase a sector. Set Sector Erase Size to 0 if unused.
Command Definitions > Sector Erase Size	Must be an integer greater than or equal to 0	4096	The sector erase size. Set Sector Erase Size to 0 if Sector Erase is not supported.
Command Definitions > Block Erase Command	Must be an 8-bit QSPI command	0xD8	The command to erase a block. Set Block Erase Size to 0 if unused.
Command Definitions > Block Erase Size	Must be an integer greater than or equal to 0	65536	The block erase size. Set Block Erase Size to 0 if Block Erase is not supported.
Command Definitions > Block Erase 32KB Command	Must be an 8-bit QSPI command	0x52	The command to erase a 32KB block. Set Block Erase Size to 0 if unused.
Command Definitions > Block Erase 32KB Size	Must be an integer greater than or equal to 0	32768	The block erase 32KB size. Set Block Erase 32KB Size to 0 if Block Erase 32KB is not supported.
Command Definitions > Chip Erase Command	Must be an 8-bit QSPI command	0xC7	The command to erase the entire chip. Set Chip Erase Command to 0 if unused.
Command Definitions > XIP Enter M7-M0	Must be an 8-bit QSPI command	0x20	How to set M7-M0 to enter XIP mode.
Command Definitions > XIP Exit M7-M0	Must be an 8-bit QSPI command	0xFF	How to set M7-M0 exit XIP mode.
Bus Timing > CS minimum idle term	Refer to the RZG Configuration tool for available options.	7 CYCLES	Define the CS minimum idle term.
Bus Timing > CS asserting extension	No Extension Extend 1 cycle	No Extension	Define the CS asserting extension
Bus Timing > CS negating extension	No Extension Extend 1 cycle	No Extension	Define the CS negating extension
Extra > Stop controller on close	True False	False	Define to stop controller on close
Extra > Pre initialize function	Name must be a valid C symbol	NULL	Function name or "NULL"
Extra > Post initialize function	Name must be a valid C symbol	NULL	Function name or "NULL"

Clock Configuration

The QSPI clock is derived from XSPI_CLKn. You can set the clock frequency using the Clocks tab of the FSP Configuration editor or by using the CGC Interface at run-time.

Pin Configuration

The following pins are available to connect to an external QSPI device:

• XSPIn_CKP: QSPI clock output
• XSPIn_CS0, XSPIn_CS1: QSPI slave select
• XSPIn_IO0: Data 0 I/O
• XSPIn_IO1: Data 1 I/O
• XSPIn_IO2: Data 2 I/O
• XSPIn_IO3: Data 3 I/O

Note

It is recommended to configure the pins with IOPORT_CFG_DRIVE_HIGH.

Usage Notes

xSPI_QSPI Memory Mapped Access

After R_XSPI_QSPI_Open() completes successfully, the QSPI flash device contents are mapped to address 0x90000000(Non-secure External address space) or 0x80000000(Secure External address space).

The address map for the external address space xSPI is as follows:

Address	Space
0x80000000 to 0x87FFFFFF	CS0 Secure space
0x88000000 to 0x8FFFFFFF	CS1 Secure space
0x90000000 to 0x97FFFFFF	CS0 Non-secure space
0x98000000 to 0x9FFFFFFF	CS1 Non-secure space

Examples

Basic Example

This is a basic example of minimal use of the QSPI in an application. When using the section definition in the example below, the user must define it separately in the linker configuration file.

#define QSPI_EXAMPLE_DATA_LENGTH    (1024)
#define QSPI_EXAMPLE_ERASE_SIZE     (4096)
#define QSPI_EXAMPLE_WRITE_SIZE     (64)

uint8_t g_dest[QSPI_EXAMPLE_DATA_LENGTH];

uint8_t * gp_src = (uint8_t *) BSP_FEATURE_XSPI_START_ADDRESS;

void r_qspi_basic_example (void)
{
    fsp_err_t err;


    /* Open the QSPI instance. */
    err = R_XSPI_QSPI_Open(&g_qspi0_ctrl, &g_qspi0_cfg);
    handle_error(err);


    /* (Optional) Send device specific initialization commands. */
    r_qspi_example_init();

    /* After R_XSPI_QSPI_Open() and any required device specific initialization, data can be read directly from the QSPI flash. */
    memcpy(&g_dest[0], gp_src, QSPI_EXAMPLE_DATA_LENGTH);


    /* After R_XSPI_QSPI_Open() and any required device specific initialization, sector can be erase from the QSPI flash.
     * The erase size must exactly match one of the settings in the configurator.
     */
    err = R_XSPI_QSPI_Erase(&g_qspi0_ctrl, gp_src, QSPI_EXAMPLE_ERASE_SIZE);
    handle_error(err);



    /* After R_XSPI_QSPI_Open() and any required device specific initialization, page can be write to the QSPI flash.
     * The write size must be less than or equal to the page size or 64 bytes, whichever is smaller.
     */
    err = R_XSPI_QSPI_Write(&g_qspi0_ctrl, &g_dest[0], gp_src, QSPI_EXAMPLE_WRITE_SIZE);
    handle_error(err);

}

Initialization Command Structure Example

This is an example of the types of commands that can be used to initialize the QSPI.

/* Example for Adesto/Dialog/Renesas AT25SL/AT25QL QSPI flash. Not suitable for AT25SF/AT25QF. */
#define QSPI_COMMAND_WRITE_ENABLE             (0x06U)
#define QSPI_COMMAND_WRITE_STATUS_REGISTER    (0x01U)
#define QSPI_COMMAND_ENTER_QPI_MODE           (0x38U)

#define QSPI_EXAMPLE_STATUS_REGISTER_1        (0x00U)
#define QSPI_EXAMPLE_STATUS_REGISTER_2        (0x02U)

static void r_qspi_example_init (void)
{
    fsp_err_t err;
    spi_flash_direct_transfer_t qspi_direct_transfer =
    {
        .command        = QSPI_COMMAND_WRITE_ENABLE,
        .address        = 0U,
        .data           = 0U,
        .command_length = 1U,
        .address_length = 0U,
        .data_length    = 0U,
        .dummy_cycles   = 0U
    };


    /* Send the Write Enable (WREN) command to enable writing to the status register */
    err = R_XSPI_QSPI_DirectTransfer(&g_qspi0_ctrl, &qspi_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE);
    handle_error(err);


    /* Example for write status register command that take two value.  Values are set in the data field.
     * For the AT25QL, set QE to 1 and other bits to their default setting.
     */
    qspi_direct_transfer.command     = QSPI_COMMAND_WRITE_STATUS_REGISTER;
    qspi_direct_transfer.data        = QSPI_EXAMPLE_STATUS_REGISTER_2 << 8 | QSPI_EXAMPLE_STATUS_REGISTER_1;
    qspi_direct_transfer.data_length = 2U;
    err = R_XSPI_QSPI_DirectTransfer(&g_qspi0_ctrl, &qspi_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE);
    handle_error(err);

    /* Wait for complete to update. */
    spi_flash_status_t status;
    do
    {
        err = R_XSPI_QSPI_StatusGet(&g_qspi0_ctrl, &status);
        handle_error(err);
    } while (true == status.write_in_progress);

    /* Execute the Enable QPI command to enter QSPI mode. After entering QPI mode on the device, change the SPI
     * protocol to QPI mode on the MCU peripheral. */
    qspi_direct_transfer.command     = QSPI_COMMAND_ENTER_QPI_MODE;
    qspi_direct_transfer.data        = 0U;
    qspi_direct_transfer.data_length = 0U;
    err = R_XSPI_QSPI_DirectTransfer(&g_qspi0_ctrl, &qspi_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE);
    handle_error(err);


    (void) R_XSPI_QSPI_SpiProtocolSet(&g_qspi0_ctrl, SPI_FLASH_PROTOCOL_4S_4S_4S);

}

Reading Status Register Example (R_XSPI_QSPI_DirectTransfer)

This is an example of using R_XSPI_QSPI_DirectTransfer to send the read status register command and read back the status register from the device.

#define QSPI_COMMAND_READ_STATUS_REGISTER    (0x05U)

void r_qspi_direct_example (void)
{
    spi_flash_direct_transfer_t qspi_direct_transfer =
    {
        .command        = QSPI_COMMAND_READ_STATUS_REGISTER,
        .address        = 0U,
        .data           = 0U,
        .command_length = 1U,
        .address_length = 0U,
        .data_length    = 1U,
        .dummy_cycles   = 0U
    };

    /* Open the QSPI instance. */
    fsp_err_t err = R_XSPI_QSPI_Open(&g_qspi0_ctrl, &g_qspi0_cfg);
    handle_error(err);

    /* Read the Status Register */
    err = R_XSPI_QSPI_DirectTransfer(&g_qspi0_ctrl, &qspi_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    handle_error(err);

    /* Status register contents are available in variable 'qspi_direct_transfer.data'. */
}

Querying Device Size Example (R_XSPI_QSPI_DirectTransfer)

This is an example of using R_XSPI_QSPI_DirectTransfer to query the device size.

#define QSPI_EXAMPLE_COMMAND_READ_ID      (0x9F)
#define QSPI_EXAMPLE_COMMAND_READ_SFDP    (0x5A)

void r_qspi_size_example (void)
{
    /* Many QSPI devices support more than one way to query the device size. Consult the datasheet for your
     * QSPI device to determine which of these methods are supported (if any). */
    uint32_t  device_size_bytes;
    fsp_err_t err;

#ifdef QSPI_EXAMPLE_COMMAND_READ_ID
    spi_flash_direct_transfer_t qspi_rdid_direct_transfer =
    {
        .command        = QSPI_EXAMPLE_COMMAND_READ_ID,
        .address        = 0U,
        .data           = 0U,
        .command_length = 1U,
        .address_length = 0U,
        .data_length    = 3U,
        .dummy_cycles   = 0U
    };

    /* This example shows how to get the device size by reading the manufacturer ID. */
    /* Read 3 bytes. The third byte often represents the size of the QSPI, where the size of the QSPI = 2 ^ N. */
    err = R_XSPI_QSPI_DirectTransfer(&g_qspi0_ctrl, &qspi_rdid_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    handle_error(err);

    device_size_bytes = 1U << (qspi_rdid_direct_transfer.data >> 16);
    FSP_PARAMETER_NOT_USED(device_size_bytes);
#endif

#ifdef QSPI_EXAMPLE_COMMAND_READ_SFDP
    spi_flash_direct_transfer_t qspi_rdsfdp_direct_transfer =
    {
        .command        = QSPI_EXAMPLE_COMMAND_READ_SFDP,
        .address        = 0x00000CU,
        .data           = 0U,
        .command_length = 1U,
        .address_length = 3U,
        .data_length    = 3U,
        .dummy_cycles   = 8U
    };

    /* Read the Parameter Table Pointer (PTP) of 1st Parameter header to locate the JEDEC flash parameters table.
     * Reference JESD216 "Serial Flash Discoverable Parameters (SFDP)". */

    /* Send the standard 0x5A command followed by 3 address bytes (1st Parameter header's PTP is at address 0xC).
     * 3 byte address of JEDEC flash parameters are read back and stored in qspi_rdsfdp_direct_transfer.data */
    err = R_XSPI_QSPI_DirectTransfer(&g_qspi0_ctrl, &qspi_rdsfdp_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    handle_error(err);

    /* Read the JEDEC flash parameters' memory density. */

    /* Send the standard 0x5A command followed by 3 address bytes of Flash memory density (offset 0x04 from JEDEC
     * flash parameters address). Read 4 bytes. */
    qspi_rdsfdp_direct_transfer.command        = QSPI_EXAMPLE_COMMAND_READ_SFDP;
    qspi_rdsfdp_direct_transfer.address        = qspi_rdsfdp_direct_transfer.data + 0x04;
    qspi_rdsfdp_direct_transfer.data           = 0U;
    qspi_rdsfdp_direct_transfer.command_length = 1U;
    qspi_rdsfdp_direct_transfer.address_length = 3U;
    qspi_rdsfdp_direct_transfer.data_length    = 4U;
    qspi_rdsfdp_direct_transfer.dummy_cycles   = 8U;
    err = R_XSPI_QSPI_DirectTransfer(&g_qspi0_ctrl, &qspi_rdsfdp_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    handle_error(err);

    /* Calculate device size based on memory density */
    uint32_t memory_density = qspi_rdsfdp_direct_transfer.data;
    if ((1U << 31) & memory_density)
    {
        /* For densities 4 gigabits and above, bit-31 is set to 1b.  The field 30:0 defines 'N' where the density is
         * computed as 2^N bits (N must be >= 32). This code subtracts 3 from N to divide by 8 to get the size in
         * bytes instead of bits. */
        device_size_bytes = 1U << ((memory_density & ~(1U << 31)) - 3U);
    }
    else
    {
        /* For densities 2 gigabits or less, bit-31 is set to 0b.  The field 30:0 defines the size in bits. This
         * code divides the memory density by 8 to get the size in bytes instead of bits. */
        device_size_bytes = (memory_density / 8) + 1;
    }
    FSP_PARAMETER_NOT_USED(device_size_bytes);
#endif
}

Data Structures
struct	xspi_qspi_instance_ctrl_t

Enumerations
enum	xspi_qspi_chip_select_t
enum	xspi_qspi_memory_size_t
enum	xspi_qspi_command_interval_clocks_t
enum	xspi_qspi_cs_pullup_clocks_t
enum	xspi_qspi_cs_pulldown_clocks_t
enum	xspi_qspi_prefetch_function_t

---

Data Structure Documentation

xspi_qspi_instance_ctrl_t

struct xspi_qspi_instance_ctrl_t

Instance control block. DO NOT INITIALIZE. Initialization occurs when spi_flash_api_t::open is called

Enumeration Type Documentation

xspi_qspi_chip_select_t

enum xspi_qspi_chip_select_t

Enumerator
XSPI_QSPI_CHIP_SELECT_0	Device connected to Chip-Select 0.
XSPI_QSPI_CHIP_SELECT_1	Device connected to Chip-Select 1.

xspi_qspi_memory_size_t

enum xspi_qspi_memory_size_t

Enumerator
XSPI_QSPI_MEMORY_SIZE_1MB	Memory size 1MB.
XSPI_QSPI_MEMORY_SIZE_2MB	Memory size 2MB.
XSPI_QSPI_MEMORY_SIZE_4MB	Memory size 4MB.
XSPI_QSPI_MEMORY_SIZE_8MB	Memory size 8MB.
XSPI_QSPI_MEMORY_SIZE_16MB	Memory size 16MB.
XSPI_QSPI_MEMORY_SIZE_32MB	Memory size 32MB.
XSPI_QSPI_MEMORY_SIZE_64MB	Memory size 64MB.

xspi_qspi_command_interval_clocks_t

enum xspi_qspi_command_interval_clocks_t

Enumerator
XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_1	1 interval clocks
XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_2	2 interval clocks
XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_3	3 interval clocks
XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_4	4 interval clocks
XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_5	5 interval clocks
XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_6	6 interval clocks
XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_7	7 interval clocks
XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_8	8 interval clocks
XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_9	9 interval clocks
XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_10	10 interval clocks
XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_11	11 interval clocks
XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_12	12 interval clocks
XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_13	13 interval clocks
XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_14	14 interval clocks
XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_15	15 interval clocks
XSPI_QSPI_COMMAND_INTERVAL_CLOCKS_16	16 interval clocks

xspi_qspi_cs_pullup_clocks_t

enum xspi_qspi_cs_pullup_clocks_t

Enumerator
XSPI_QSPI_CS_PULLUP_CLOCKS_NO_EXTENSION	CS asserting No extension.
XSPI_QSPI_CS_PULLUP_CLOCKS_1	CS asserting Extend 1 cycle.

xspi_qspi_cs_pulldown_clocks_t

enum xspi_qspi_cs_pulldown_clocks_t

Enumerator
XSPI_QSPI_CS_PULLDOWN_CLOCKS_NO_EXTENSION	CS negating No extension.
XSPI_QSPI_CS_PULLDOWN_CLOCKS_1	CS negating Extend 1 cycle.

xspi_qspi_prefetch_function_t

enum xspi_qspi_prefetch_function_t

Enumerator
XSPI_QSPI_PREFETCH_FUNCTION_DISABLE	Prefetch function disable.
XSPI_QSPI_PREFETCH_FUNCTION_ENABLE	Prefetch function enable.

Function Documentation

R_XSPI_QSPI_Open()

fsp_err_t R_XSPI_QSPI_Open	(	spi_flash_ctrl_t *	p_ctrl,
		spi_flash_cfg_t const *const	p_cfg
	)

Open the QSPI driver module. After the driver is open, the QSPI can be accessed like internal flash memory starting at address 0x60000000 or 0x40000000.

Implements spi_flash_api_t::open.

Example:

    /* Open the QSPI instance. */
    err = R_XSPI_QSPI_Open(&g_qspi0_ctrl, &g_qspi0_cfg);
    handle_error(err);

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	The parameter p_instance_ctrl or p_cfg is NULL.
FSP_ERR_ALREADY_OPEN	Driver has already been opened with the same p_instance_ctrl.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	The requested channel does not exist on this MCU.

R_XSPI_QSPI_Close()

fsp_err_t R_XSPI_QSPI_Close

(

spi_flash_ctrl_t *

p_ctrl

)

Close the QSPI driver module.

Implements spi_flash_api_t::close.

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	p_instance_ctrl is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_XSPI_QSPI_DirectWrite()

fsp_err_t R_XSPI_QSPI_DirectWrite	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t const *const	p_src,
		uint32_t const	bytes,
		bool const	read_after_write
	)

Writes raw data directly to the QSPI.

Implements spi_flash_api_t::directWrite.

Return values

FSP_ERR_UNSUPPORTED

API not supported.

R_XSPI_QSPI_DirectRead()

fsp_err_t R_XSPI_QSPI_DirectRead	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t *const	p_dest,
		uint32_t const	bytes
	)

Reads raw data directly from the QSPI.

Implements spi_flash_api_t::directRead.

Return values

FSP_ERR_UNSUPPORTED

API not supported.

R_XSPI_QSPI_SpiProtocolSet()

fsp_err_t R_XSPI_QSPI_SpiProtocolSet	(	spi_flash_ctrl_t *	p_ctrl,
		spi_flash_protocol_t	spi_protocol
	)

Sets the SPI protocol.

Implements spi_flash_api_t::spiProtocolSet.

Return values

FSP_SUCCESS	SPI protocol updated on MCU peripheral.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_ARGUMENT	Invalid SPI protocol requested.

R_XSPI_QSPI_XipEnter()

fsp_err_t R_XSPI_QSPI_XipEnter

(

spi_flash_ctrl_t *

p_ctrl

)

Enters XIP (execute in place) mode.

Implements spi_flash_api_t::xipEnter.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_XSPI_QSPI_XipExit()

fsp_err_t R_XSPI_QSPI_XipExit

(

spi_flash_ctrl_t *

p_ctrl

)

Exits XIP (execute in place) mode.

Implements spi_flash_api_t::xipExit.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_XSPI_QSPI_Write()

fsp_err_t R_XSPI_QSPI_Write	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t const *const	p_src,
		uint8_t *const	p_dest,
		uint32_t	byte_count
	)

Program a page of data to the flash.

Implements spi_flash_api_t::write.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	p_instance_ctrl, p_dest or p_src is NULL, or byte_count crosses a page boundary.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_MODE	This function can't be called when XIP mode is enabled.
FSP_ERR_DEVICE_BUSY	The device is busy.

Note

In this API, data can be written up to 64 bytes at a time.

R_XSPI_QSPI_Erase()

fsp_err_t R_XSPI_QSPI_Erase	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t *const	p_device_address,
		uint32_t	byte_count
	)

Erase a block or sector of flash. The byte_count must exactly match one of the erase sizes defined in spi_flash_cfg_t. For chip erase, byte_count must be SPI_FLASH_ERASE_SIZE_CHIP_ERASE.

Implements spi_flash_api_t::erase.

Return values

FSP_SUCCESS	The command to erase the flash was executed successfully.
FSP_ERR_ASSERTION	p_instance_ctrl or p_device_address is NULL, or byte_count doesn't match an erase size defined in spi_flash_cfg_t, or device is in XIP mode.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_MODE	This function can't be called when XIP mode is enabled.
FSP_ERR_DEVICE_BUSY	The device is busy.

R_XSPI_QSPI_StatusGet()

fsp_err_t R_XSPI_QSPI_StatusGet	(	spi_flash_ctrl_t *	p_ctrl,
		spi_flash_status_t *const	p_status
	)

Gets the write or erase status of the flash.

Implements spi_flash_api_t::statusGet.

Return values

FSP_SUCCESS	The write status is in p_status.
FSP_ERR_ASSERTION	p_instance_ctrl or p_status is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_MODE	This function can't be called when XIP mode is enabled.

R_XSPI_QSPI_BankSet()

fsp_err_t R_XSPI_QSPI_BankSet	(	spi_flash_ctrl_t *	p_ctrl,
		uint32_t	bank
	)

Selects the bank to access.

Implements spi_flash_api_t::bankSet.

Return values

FSP_ERR_UNSUPPORTED

API not supported.

R_XSPI_QSPI_DirectTransfer()

fsp_err_t R_XSPI_QSPI_DirectTransfer	(	spi_flash_ctrl_t *	p_ctrl,
		spi_flash_direct_transfer_t *const	p_transfer,
		spi_flash_direct_transfer_dir_t	direction
	)

Read/Write raw data directly with the SerialFlash.

Implements spi_flash_api_t::directTransfer.

Example:

    /* Send the Write Enable (WREN) command to enable writing to the status register */
    err = R_XSPI_QSPI_DirectTransfer(&g_qspi0_ctrl, &qspi_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE);
    handle_error(err);

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_MODE	This function must be called after R_XSPI_QSPI_DirectWrite with read_after_write set to true.

R_XSPI_QSPI_AutoCalibrate()

fsp_err_t R_XSPI_QSPI_AutoCalibrate

(

spi_flash_ctrl_t *

p_ctrl

)

AutoCalibrate the SPI flash driver module.

Implements spi_flash_api_t::autoCalibrate.

Return values

FSP_ERR_UNSUPPORTED

API not supported.