Bus State Controller (r_bsc)

Functions
fsp_err_t	R_BSC_Open (external_bus_ctrl_t *p_ctrl, external_bus_cfg_t const *const p_cfg)
fsp_err_t	R_BSC_Close (external_bus_ctrl_t *p_ctrl)
fsp_err_t	R_BSC_CallbackSet (external_bus_ctrl_t *p_ctrl, void(*p_callback)(bsc_callback_args_t *), void const *const p_context, bsc_callback_args_t *const p_callback_memory)

Detailed Description

Driver for the BSC peripheral on RZ microprocessor. This module implements the External Bus Interface.

Overview

Features

The BSC driver has the following key features:

• Memory mapped write/read access to the external memory
• Various available memory type
  • SRAM
• Data bus size : 8bit, 16bit
• Configurable idle cycle, wait state cycle

Configuration

Build Time Configurations for r_bsc

The following build time configurations are defined in fsp_cfg/r_bsc_cfg.h:

Configuration	Options	Default	Description
Parameter Checking Enable	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Multiplex Interrupt	Enabled Disabled	Disabled	Enable multiplex interrupt for a single driver.

Configurations for Storage > BSC (r_bsc)

This module can be added to the Stacks tab via New Stack > Storage > BSC (r_bsc).

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_bsc0	Module name.
General > Chip Select	Chip Select 0 Chip Select 2 Chip Select 3 Chip Select 5	Chip Select 0	Specify the BSC chip select line to use.
General > Memory Type	Normal Space (SRAM)	Normal Space (SRAM)	Select memory type.
General > Data Bus Width	8-bit 16-bit	8-bit	Select the number of BSC data bus width.
Idle Cycles > Read-Read Cycles In The Same CS Space	0 CYCLE 1 CYCLE 2 CYCLES 4 CYCLES 6 CYCLES 8 CYCLES 10 CYCLES 12 CYCLES	4 CYCLES	Idle cycle insertion between Read-Read cycles in the same CS space.
Idle Cycles > Read-Read Cycles In The Different CS Spaces	0 CYCLE 1 CYCLE 2 CYCLES 4 CYCLES 6 CYCLES 8 CYCLES 10 CYCLES 12 CYCLES	4 CYCLES	Idle cycle insertion between Read-Read cycles in different CS space.
Idle Cycles > Read-Write Cycles In The Same CS Spaces	0 CYCLE 1 CYCLE 2 CYCLES 4 CYCLES 6 CYCLES 8 CYCLES 10 CYCLES 12 CYCLES	4 CYCLES	Idle cycle insertion between Read-Write cycles in the same CS space.
Idle Cycles > Read-Write Cycles In The Different CS Spaces	0 CYCLE 1 CYCLE 2 CYCLES 4 CYCLES 6 CYCLES 8 CYCLES 10 CYCLES 12 CYCLES	4 CYCLES	Idle cycle insertion between Read-Write cycles in different CS space.
Idle Cycles > Write-Read Cycles And Write-Write Cycles	0 CYCLE 1 CYCLE 2 CYCLES 4 CYCLES 6 CYCLES 8 CYCLES 10 CYCLES 12 CYCLES	4 CYCLES	Idle cycles between Write-Read cycles and Write-Write cycles.
Chip Select Timing > CS Negate (RD#,WE# to CSn#) Delay Timing (CS0,5 only)	0.5 CYCLES 1.5 CYCLES 2.5 CYCLES 3.5 CYCLES	0.5 CYCLES	Delay States from RD#, WEn# Negation to Address, CSn# Negation.
Chip Select Timing > CS Assert (CSn# to RD#,WE#) Delay Timing (CS0,5 only)	0.5 CYCLES 1.5 CYCLES 2.5 CYCLES 3.5 CYCLES	0.5 CYCLES	Number of Delay Cycles from Address, CSn# Assertion to RD#, WE# Assertion.
Number of Access Wait > Access Wait For Read	Refer to the RZT Configuration tool for available options.	14 WAITS	The number of waits that are necessary for read access.
Number of Access Wait > Access Wait For Write	The Same As Number Of Read Access Wait (Select when use CS0,2,3) 0 WAIT 1 WAIT 2 WAITS 3 WAITS 4 WAITS 5 WAITS 6 WAITS	The Same As Number Of Read Access Wait (Select when use CS0,2,3)	The number of waits that are necessary for write access.
External WAIT# > External WAIT# input	Disable Enable	Disable	Specifies whether the external wait input is valid.
External WAIT# > External WAIT# timeout detection error	Disable Enable	Disable	Specifies enabling or disabling the detection of timeout for waiting in the CS space.
External WAIT# > External WAIT# timeout cycles (Valid only when External WAIT# timeout detection error is Enabled)	Value must be a non-negative integer between 1 and 65536.	65536	Timeout Cycle Number
External WAIT# > External WAIT# timeout Callback	Name must be a valid C symbol	NULL	A user callback function. If this callback function is provided, it is called from the interrupt service routine (ISR) each time any interrupt occurs.

Clock Configuration

The BSC clock is derived from External bus clock (BSC_CLK, CKIO). You can set the clock frequency using the Clocks tab of the FSP Configuration editor or by using the CGC Interface at run-time.

Usage Notes

BSC Memory Mapped Access

After R_BSC_Open() completes successfully, the connected BSC device contents are mapped to address 0x70000000(External address space) or 0x50000000(Mirror space of External address space) and can be read like internal memory.

When not using the cache, access the memory via the mirror space.

The address map for the external address space is as follows:

Address	Space
0x50000000 to 0x53FFFFFF	CS0 mirror space
0x54000000 to 0x57FFFFFF	CS2 mirror space
0x58000000 to 0x5BFFFFFF	CS3 mirror space
0x5C000000 to 0x5FFFFFFF	CS5 mirror space
0x70000000 to 0x73FFFFFF	CS0 space
0x74000000 to 0x77FFFFFF	CS2 space
0x78000000 to 0x7BFFFFFF	CS3 space
0x7C000000 to 0x7FFFFFFF	CS5 space

Interrupt

The BSC outputs an error signal to the ICU. ICU can output PERI_ERRn interrupt (Peripherals error event n) to GIC or cause error reset when ICU accepts error signal from BSC when external wait timeout is detected. To use PERI_ERRn interrupt or reset at BSC, Interrupt Controller Unit (ICU) ERROR (r_icu_error) need to be configured. When the PERI_ERRn interrupt is configured to use interrupt and triggered, the callback function registered during open is called.

Examples

Basic Example

This is a basic example of minimal use of the BSC module in an application.

#define CS0_BASE                   (0x50000000)
#define BSC_EXAMPLE_DATA_LENGTH    (256)
uint16_t write_data[BSC_EXAMPLE_DATA_LENGTH];
uint16_t read_data[BSC_EXAMPLE_DATA_LENGTH];

void r_bsc_basic_example (void)
{
    /* Write some data to the write buffer */
    for (uint16_t i = 0; i < BSC_EXAMPLE_DATA_LENGTH; i++)
    {
        write_data[i] = i;
    }


    /* Open the BSC instance */
    fsp_err_t err = R_BSC_Open(&g_bsc0_ctrl, &g_bsc0_cfg);
    handle_error(err);


    /* After R_BSC_Open() and any required device specific initialization, data can be write directly
     * to the SRAM connected to BSC. */
    for (uint16_t i = 0; i < BSC_EXAMPLE_DATA_LENGTH; i++)
    {
        *((volatile uint16_t *) CS0_BASE + 0x0000 + i) = write_data[i];
    }

    /* After R_BSC_Open() and any required device specific initialization, data can be read directly
     * from the SRAM connected to BSC. */
    for (uint16_t i = 0; i < BSC_EXAMPLE_DATA_LENGTH; i++)
    {
        read_data[i] = *((volatile uint16_t *) CS0_BASE + 0x0000 + i);
    }

    /* Verify the read_data. */
    for (uint16_t i = 0; i < BSC_EXAMPLE_DATA_LENGTH; i++)
    {
        if (read_data[i] != write_data[i])
        {
            /* Verify error. */
            __BKPT(0);
        }
    }

    while (1)
    {
        ;
    }
}

Data Structures
struct	bsc_callback_args_t
struct	bsc_extended_cfg_t
struct	bsc_instance_ctrl_t

Enumerations
enum	bsc_event_t
enum	bsc_memory_type_t
enum	bsc_idle_cycle_t
enum	bsc_access_wait_cycle_t
enum	bsc_cs_wait_cycle_t
enum	bsc_external_wait_timeout_t

---

Data Structure Documentation

bsc_callback_args_t

struct bsc_callback_args_t

Callback function parameter data.

Data Fields
bsc_event_t	event	BSC callback event.
void const *	p_context	Placeholder for user data.

bsc_extended_cfg_t

struct bsc_extended_cfg_t

Extended configuration.

Data Fields
bsc_memory_type_t	memory_type
	Configure memory type.
bsc_idle_cycle_t	r_r_same_space_idle_cycle
	Idle cycle between Read-Read cycles in the same CS space.
bsc_idle_cycle_t	r_r_different_space_idle_cycle
	Idle cycle between Read-Read cycles in the different CS space.
bsc_idle_cycle_t	r_w_same_space_idle_cycle
	Idle cycle between Read-Write cycles in the same CS space.
bsc_idle_cycle_t	r_w_different_space_idle_cycle
	Idle cycle between Read-Write cycles in the different CS space.
bsc_idle_cycle_t	w_r_w_w_idle_cycle
	Idle cycle between Write-Read cycles and Write-Write cycles.
bsc_access_wait_cycle_t	read_access_wait_cycle
	Number of read access cycle waits.
bsc_access_wait_cycle_t	write_access_wait_cycle
	Number of write access cycle waits.
bsc_cs_wait_cycle_t	cs_pullup_lag
	Duration to de-assert CS line after RD#,WE# de-assert.
bsc_cs_wait_cycle_t	cs_pulldown_lead
	Duration to assert CS line before RD#,WE# assert.
bsc_external_wait_timeout_t	external_wait_timeout_enable
	External wait timeout enable/disable setting.
uint32_t	external_wait_timeout_counts
	External wait timeout cycle.
void(*	p_callback )(bsc_callback_args_t *p_args)
	Callback for external wait timeout detection interrupt.
void const *	p_context
	Placeholder for user data. Passed to the user p_callback in bsc_callback_args_t.

bsc_instance_ctrl_t

struct bsc_instance_ctrl_t

Instance control block. DO NOT INITIALIZE. Initialization occurs when external_bus_api_t::open is called

Enumeration Type Documentation

bsc_event_t

enum bsc_event_t

BSC callback event definitions

Enumerator
BSC_EVENT_EXTERNAL_WAIT_TIMEOUT	External wait timeout detection.

bsc_memory_type_t

enum bsc_memory_type_t

Memory type connected to a CS space

Enumerator
BSC_MEMORY_TYPE_SRAM	Normal space (SRAM)

bsc_idle_cycle_t

enum bsc_idle_cycle_t

Number of insertion idle cycle between access cycles

Enumerator
BSC_IDLE_CYCLE_0	No idle cycle insertion.
BSC_IDLE_CYCLE_1	1 idle cycle insertion
BSC_IDLE_CYCLE_2	2 idle cycle insertion
BSC_IDLE_CYCLE_4	4 idle cycle insertion
BSC_IDLE_CYCLE_6	6 idle cycle insertion
BSC_IDLE_CYCLE_8	8 idle cycle insertion
BSC_IDLE_CYCLE_10	10 idle cycle insertion
BSC_IDLE_CYCLE_12	12 idle cycle insertion

bsc_access_wait_cycle_t

enum bsc_access_wait_cycle_t

Number of insertion access wait cycle

Enumerator
BSC_ACCESS_WAIT_CYCLE_0	No wait insertion.
BSC_ACCESS_WAIT_CYCLE_1	1 access wait cycle insertion
BSC_ACCESS_WAIT_CYCLE_2	2 access wait cycle insertion
BSC_ACCESS_WAIT_CYCLE_3	3 access wait cycle insertion
BSC_ACCESS_WAIT_CYCLE_4	4 access wait cycle insertion
BSC_ACCESS_WAIT_CYCLE_5	5 access wait cycle insertion
BSC_ACCESS_WAIT_CYCLE_6	6 access wait cycle insertion
BSC_ACCESS_WAIT_CYCLE_8	8 access wait cycle insertion
BSC_ACCESS_WAIT_CYCLE_10	10 access wait cycle insertion
BSC_ACCESS_WAIT_CYCLE_12	12 access wait cycle insertion
BSC_ACCESS_WAIT_CYCLE_14	14 access wait cycle insertion
BSC_ACCESS_WAIT_CYCLE_18	18 access wait cycle insertion
BSC_ACCESS_WAIT_CYCLE_24	24 access wait cycle insertion
BSC_ACCESS_WAIT_CYCLE_SAME_AS_READ_ACCESS	Insert the same weight cycle when read access (Used only for Write access wait settings)

bsc_cs_wait_cycle_t

enum bsc_cs_wait_cycle_t

Number of insertion CS wait cycle

Enumerator
BSC_CS_WAIT_CYCLE_0_5	CS wait 0.5 cycle insertion.
BSC_CS_WAIT_CYCLE_1_5	CS wait 1.5 cycle insertion.
BSC_CS_WAIT_CYCLE_2_5	CS wait 2.5 cycle insertion.
BSC_CS_WAIT_CYCLE_3_5	CS wait 3.5 cycle insertion.

bsc_external_wait_timeout_t

enum bsc_external_wait_timeout_t

External wait timeout detection setting

Enumerator
BSC_EXTERNAL_WAIT_TIMEOUT_DISABLE	External WAIT timeout detection disable.
BSC_EXTERNAL_WAIT_TIMEOUT_ENABLE	External WAIT timeout detection enable.

Function Documentation

R_BSC_Open()

fsp_err_t R_BSC_Open	(	external_bus_ctrl_t *	p_ctrl,
		external_bus_cfg_t const *const	p_cfg
	)

Open the BSC driver module. After the driver is open, the BSC can be accessed like internal flash memory starting at address 0x70000000 or 0x50000000.

Implements external_bus_api_t::open.

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	The parameter p_instance_ctrl or p_cfg is NULL.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	Invalid Channel.
FSP_ERR_ALREADY_OPEN	Driver has already been opened with the same p_instance_ctrl.

R_BSC_Close()

fsp_err_t R_BSC_Close

(

external_bus_ctrl_t *

p_ctrl

)

Close the BSC driver module.

Implements external_bus_api_t::close.

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	p_instance_ctrl is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_BSC_CallbackSet()

fsp_err_t R_BSC_CallbackSet	(	external_bus_ctrl_t *	p_ctrl,
		void(*)(bsc_callback_args_t *)	p_callback,
		void const *const	p_context,
		bsc_callback_args_t *const	p_callback_memory
	)

Updates the user callback with the option to provide memory for the callback argument structure.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.