MCU Board Support Package

Functions
fsp_err_t	R_FSP_VersionGet (fsp_pack_version_t *const p_version)
void	Default_Handler (void)
BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void	system_init (void)
void	SystemInit (void)
void	R_BSP_WarmStart (bsp_warm_start_event_t event)
void	R_BSP_CacheEnableInst (void)
void	R_BSP_CacheEnableData (void)
void	R_BSP_CacheEnableMemoryProtect (void)
void	R_BSP_CacheDisableInst (void)
void	R_BSP_CacheDisableData (void)
void	R_BSP_CacheDisableMemoryProtect (void)
void	R_BSP_CacheCleanAll (void)
void	R_BSP_CacheInvalidateAll (void)
void	R_BSP_CacheCleanInvalidateAll (void)
void	R_BSP_CacheCleanRange (uintptr_t base_address, uintptr_t length)
void	R_BSP_CacheInvalidateRange (uintptr_t base_address, uintptr_t length)
void	R_BSP_CacheCleanInvalidateRange (uintptr_t base_address, uintptr_t length)
void	R_BSP_CacheL3PowerCtrl (void)
__STATIC_INLINE IRQn_Type	R_FSP_CurrentIrqGet (void)
__STATIC_INLINE uint32_t	R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
void	R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units)
__STATIC_INLINE void	R_FSP_IsrContextSet (IRQn_Type const irq, void *p_context)
	Sets the ISR context associated with the requested IRQ. More...
__STATIC_INLINE void	R_BSP_IrqClearPending (IRQn_Type irq)
__STATIC_INLINE uint32_t	R_BSP_IrqPendingGet (IRQn_Type irq)
__STATIC_INLINE void	R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void *p_context)
__STATIC_INLINE void	R_BSP_IrqEnableNoClear (IRQn_Type const irq)
__STATIC_INLINE void	R_BSP_IrqEnable (IRQn_Type const irq)
__STATIC_INLINE void	R_BSP_IrqDisable (IRQn_Type const irq)
__STATIC_INLINE void	R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void *p_context)
__STATIC_INLINE void *	R_FSP_IsrContextGet (IRQn_Type const irq)
	Finds the ISR context associated with the requested IRQ. More...
__STATIC_INLINE void	R_BSP_IrqDetectTypeSet (IRQn_Type const irq, uint32_t detect_type)
__STATIC_INLINE void	R_BSP_IrqGroupSet (IRQn_Type const irq, uint32_t interrupt_group)
__STATIC_INLINE void	R_BSP_IrqMaskLevelSet (uint32_t mask_level)
__STATIC_INLINE uint32_t	R_BSP_IrqMaskLevelGet (void)
void	R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect)
void	R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect)
void	R_BSP_SystemReset (void)
void	R_BSP_CPUReset (bsp_reset_t cpu)
void	R_BSP_CPUResetAutoRelease (bsp_reset_t cpu)
void	R_BSP_CPUResetRelease (bsp_reset_t cpu)
void	R_BSP_ModuleResetEnable (bsp_module_reset_t module_to_enable)
void	R_BSP_ModuleResetDisable (bsp_module_reset_t module_to_disable)
BSP_TFU_INLINE float	__sinf (float angle)
BSP_TFU_INLINE float	__cosf (float angle)
BSP_TFU_INLINE void	__sincosf (float angle, float *sin, float *cos)
BSP_TFU_INLINE float	__atan2f (float y_cord, float x_cord)
BSP_TFU_INLINE float	__hypotf (float x_cord, float y_cord)
BSP_TFU_INLINE void	__atan2hypotf (float y_cord, float x_cord, float *atan2, float *hypot)
BSP_TFU_INLINE uint32_t	__sinfx (uint32_t angle)
BSP_TFU_INLINE uint32_t	__cosfx (uint32_t angle)
BSP_TFU_INLINE void	__sincosfx (uint32_t angle, uint32_t *sin, uint32_t *cos)
BSP_TFU_INLINE uint32_t	__atan2fx (uint32_t y_cord, uint32_t x_cord)
BSP_TFU_INLINE int32_t	__hypotfx (uint32_t x_cord, uint32_t y_cord)
BSP_TFU_INLINE void	__atan2hypotfx (uint32_t y_cord, uint32_t x_cord, uint32_t *atan2, int32_t *hypot)
BSP_ATTRIBUTE_STACKLESS void	r_bsp_software_delay_loop (__attribute__((unused)) uint32_t loop_cnt)
fsp_err_t	R_BSP_GroupIrqWrite (bsp_grp_irq_t irq, void(*p_callback)(bsp_grp_irq_t irq))
void	R_BSP_GICD_SetCtlr (bsp_gicd_ctlr_bit_t bit)
uint32_t	R_BSP_GICD_GetCtlr (void)
void	R_BSP_GICD_Enable (bsp_gicd_ctlr_bit_t bit)
void	R_BSP_GICD_Disable (bsp_gicd_ctlr_bit_t bit)
void	R_BSP_GICD_AffinityRouteEnable (bsp_gicd_ctlr_bit_t bit)
void	R_BSP_GICD_SpiEnable (IRQn_Type irq)
void	R_BSP_GICD_SpiDisable (IRQn_Type irq)
void	R_BSP_GICD_SetSpiPriority (IRQn_Type irq, uint32_t priority)
uint32_t	R_BSP_GICD_GetSpiPriority (IRQn_Type irq)
void	R_BSP_GICD_SetSpiRoute (IRQn_Type id, uint64_t route, bsp_gicd_irouter_route_t mode)
uint64_t	R_BSP_GICD_GetSpiRoute (IRQn_Type id)
void	R_BSP_GICD_SetSpiSense (IRQn_Type irq, bsp_gicd_icfgr_sense_t sense)
uint32_t	R_BSP_GICD_GetSpiSense (IRQn_Type irq)
void	R_BSP_GICD_SetSpiPending (IRQn_Type irq)
uint32_t	R_BSP_GICD_GetSpiPending (IRQn_Type irq)
void	R_BSP_GICD_SetSpiClearPending (IRQn_Type irq)
uint32_t	R_BSP_GICD_GetSpiClearPending (IRQn_Type irq)
void	R_BSP_GICD_SetSpiSecurity (IRQn_Type irq, bsp_gic_igroupr_secure_t group)
void	R_BSP_GICD_SetSpiSecurityLine (uint32_t line, bsp_gic_igroupr_secure_t group)
void	R_BSP_GICD_SetSpiSecurityAll (bsp_gic_igroupr_secure_t group)
void	R_BSP_GICD_SetSpiClass (IRQn_Type id, bsp_gicd_iclar_class_t class_group)
void	R_BSP_GICR_Enable (void)
void	R_BSP_GICR_SgiPpiEnable (IRQn_Type irq)
void	R_BSP_GICR_SgiPpiDisable (IRQn_Type irq)
void	R_BSP_GICR_SetSgiPpiPriority (IRQn_Type irq, uint32_t priority)
uint32_t	R_BSP_GICR_GetSgiPpiPriority (IRQn_Type irq)
void	R_BSP_GICR_SetSgiPpiSense (IRQn_Type irq, bsp_gicd_icfgr_sense_t sense)
uint32_t	R_BSP_GICR_GetSgiPpiSense (IRQn_Type irq)
void	R_BSP_GICR_SetSgiPpiPending (IRQn_Type irq)
uint32_t	R_BSP_GICR_GetSgiPpiPending (IRQn_Type irq)
void	R_BSP_GICR_SetSgiPpiClearPending (IRQn_Type irq)
uint32_t	R_BSP_GICR_GetSgiPpiClearPending (IRQn_Type irq)
void	R_BSP_GICR_SetSgiPpiSecurity (IRQn_Type irq, bsp_gic_igroupr_secure_t group)
void	R_BSP_GICR_SetSgiPpiSecurityLine (bsp_gic_igroupr_secure_t group)
void	R_BSP_GICR_SetClass (bsp_gicd_iclar_class_t class_group)
uint32_t	R_BSP_GICR_GetRoute (void)
void	R_BSP_GICC_SetMaskLevel (uint64_t mask_level)
uint64_t	R_BSP_GICC_GetMaskLevel (void)
void	R_BSP_GICC_SetEoiGrp0 (IRQn_Type irq)
void	R_BSP_GICC_SetEoiGrp1 (IRQn_Type irq)
uint32_t	R_BSP_GICC_Get_IntIdGrp0 (void)
uint32_t	R_BSP_GICC_Get_IntIdGrp1 (void)
fsp_err_t	R_BSP_MmuVatoPa (uint64_t vaddress, uint64_t *p_paddress)
fsp_err_t	R_BSP_MmuPatoVa (uint64_t paddress, uint64_t *p_vaddress, bsp_mmu_conversion_flag_t cache_flag)

Detailed Description

The BSP is responsible for getting the MCU from reset to the user's application. Before reaching the user's application, the BSP sets up the stacks, heap, clocks, interrupts, C runtime environment, and stack monitor.

Default initialization function.

• BSP Features
• BSP Clock Configuration
• System Interrupts
• Multiplex Interrupts
• External and Peripheral Interrupts
• Warm Start Callbacks
• C Runtime Initialization
• Register Protection
• Software Delay
• Trigonometric Function
• Critical Section Macros
• Noncache Section
• Memory Attributes
• Memory Management Unit
• TrustZone Address Space Controller (TZC-400)
• Module Reset
• Software Reset
• Configuration
• Core Comparison

Overview

BSP Features

BSP Clock Configuration

All system clocks are set up during BSP initialization based on the settings in bsp_clock_cfg.h. These settings are derived from clock configuration information provided from the Configuration editor Clocks tab.

• Clock configuration is performed prior to initializing the C runtime environment to speed up the startup process.
• The BSP implements the required delays to allow the selected clock to stabilize.
• The BSP will configure the CMSIS SystemCoreClock variable after clock initialization with the current system clock frequency.

System Interrupts

As Cortex-R ARM architecture, the Generic Interrupt Controller (GIC) handles exceptions and interrupt configuration, prioritization and interrupt masking. In the ARM architecture, the GIC handles IRQ and FIQ exceptions and receives the following interrupt types.

• Private Peripheral Interrupt (PPI)
• Shared Peripheral Interrupt (SPI)
• Software Generated Interrupt (SGI)

SGI and PPI are core-related specific interrupts, and SPI is connected to interrupts from each peripheral. GIC has interrupt number (INTID) internally. SGI uses INTID 0 to 15, PPI uses INTID 16 to 31, and SPI uses INTID 32 or later.

Multiplex Interrupts

When multiplex interrupts are enabled, another interrupt can operated while one interrupt is operating.

If an interrupt occurs, it branches to BSP common handler and then to HAL interrupt handler. The user can choose whether to allow multiple interrupts in BSP common handler or in HAL interrupt handler.

There are two ways to enable it:

• Enable in BSP properties
  • Multiplex interrupts are enabled system-wide

The behavior when multiplex interrupts are enabled in the BSP properties is as follows. Pink areas represent critical sections.

Behavior when multiplex interrupts are enabled in BSP

• Enable in HAL module properties
  • Multiplex interrupts are enabled only on set HAL modules

The behavior when multiplex interrupts are enabled for only HAL1 of the two HAL modules in the HAL module properties is as follows. Pink areas represent critical sections.

Behavior when multiplex interrupts are enabled in HAL module

Note

If you enable Multiplex interrupts in BSP properties, it will be enabled even if you disable it in HAL module

External and Peripheral Interrupts

User configurable interrupts begin with slot 32 (SPI). These may be external, or peripheral generated interrupts.

The SPI is mapped along the Event Table, and the BSP allows the user to select only the events of interest as interrupt sources.

C Runtime Initialization

If C Runtime is disabled, users must perform C runtime initialization themselves.

Register Protection

The BSP register protection functions utilize reference counters to ensure that an application which has specified a certain register and subsequently calls another function doesn't have its register protection settings inadvertently modified.

Each time R_BSP_RegisterProtectDisable() is called, the respective reference counter is incremented.

Each time R_BSP_RegisterProtectEnable() is called, the respective reference counter is decremented.

Both functions will only modify the protection state if their reference counter is zero.

    /* Enable writing to protected CGC registers */
    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC);

    /* Insert code to modify protected CGC registers. */

    /* Disable writing to protected CGC registers */
    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC);

Software Delay

Do not recommend using R_BSP_SoftwareDelay () for strict wait time processing. The reason we do not recommend using this API is that the Delay Time may change depending on the memory area where the execution program is placed.

Implements a blocking software delay. A delay can be specified in microseconds, milliseconds or seconds. The delay is implemented based on the system clock rate.

    /* Delay at least 1 second. Depending on the number of wait states required for the region of memory
     * that the software_delay_loop has been linked in this could take longer. The default is 4 cycles per loop.
     * This can be modified by redefining DELAY_LOOP_CYCLES. BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS,
     * and BSP_DELAY_UNITS_MICROSECONDS can all be used with R_BSP_SoftwareDelay. */
    R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_SECONDS);

Trigonometric Function

Implements Trigonometric math inline functions utilizing TFU hardware. These functions can calculate sine, cosine, arctangent and hypotenuse. The trigonometric library functions sinf(), cosf(), atan2f(), and hypotf() can be mapped to respective TFU functions by enabling TFU Mathlib property in FSP Configuration tool. Extended functions sincosf() and atan2hypotf() are also available when the TFU Mathlib property is enabled in the FSP Configuration editor.

TFU functions are not reentrant. Disable the TFU Mathlib property in Configuration editor if reentrant access to trigonometric library functions is required.

Note

Refer to the MCU hardware user's manual or datasheet to determine if it has TFU support.

Critical Section Macros

Implements a critical section. Interrupts with priority less than or equal to BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION are not serviced in critical sections. Interrupts with higher priority than BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION still execute in critical sections.

    FSP_CRITICAL_SECTION_DEFINE;

    /* Store the current interrupt state. */
    FSP_CRITICAL_SECTION_ENTER;

    /* Interrupts cannot run in this section if their priority is less than or equal to BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION. */

    /* Restore saved interrupt state. */
    FSP_CRITICAL_SECTION_EXIT;

Noncache Section

Variables placed in the following sections will be invalidated for caching. To place the variables in these noncache sections, use the BSP_PLACE_IN_SECTION macro to define them. (e.g. uint32_t value BSP_PLACE_IN_SECTION(".data_noncache") = 1) Data with and without initial values can be placed.

• .data_noncache
  • Places noncache data for user applications
• .dmac_link_mode
  • Place DMAC link mode descriptor
  • See Link Mode Example for how to place descriptors
• .shared_noncache_buffer
  • Place noncache data that can be shared between cores when multi-core processing
  • To prevent unexpected initialization of variables, define variables placed here only in the primary project
  • This is only for the FSP driver, and it is not possible to place noncache data used by user applications
• .noncache_buffer
  • Places noncache data exclusively for each core without sharing between cores
  • This is only for the FSP driver, and it is not possible to place noncache data used by user applications

Note

In EWARM, do not mix variables with and without initial values. A warning will occur. To avoid the warning, perform the following operations.

• Explicitly define "0" even for variables without initial values. (e.g. uint32_t value BSP_PLACE_IN_SECTION(".data_noncache") = 0)
• If you cannot explicitly define the value, you can prevent the warning from occurring by adding "--diag_suppress Be006" to Project Option -> C/C++ Compiler -> Extra Options.

Memory attributes

Attributes and Regions can be set in the CPU-MPU/MMU of the BSP property.

• Attribute: Select cacheability settings.
• Region: Define the address and other information that specifies the attribute.

For example, in the SystemRAM area, the cacheability settings shown below are used:

• Attribute: Set Attribute 1 to Normal memory, Inner/Outer Write-Through non-transient, R/W Allocate.
• Region:
  • Set the starting address (Base) and the ending address (Limit) of the memory area.
  • Set the Shareability field to Non-shareable and the Attribute Index to Attribute1 to enable cache.

The configuration values are generated as macro values in bsp_mcu_cpu_memory_cfg.h and are reflected in the ARM core registers in the startup code.

Note

In the case of the write-back policy, the write operation basically updates data in the cache, and data updates to main memory are performed according to the state of the cache. If it is necessary to explicitly update data to main memory, a separate clean operation must be performed. Please use the following BSP API functions for the clean operation:

- R_BSP_CacheCleanAll

- R_BSP_CacheCleanInvalidateAll

If you need to invalidate the cache (clean data from the cache) in addition to the clean operation, use the following BSP API functions:

- R_BSP_CacheCleanRange

- R_BSP_CacheCleanInvalidateRange

When using Cortex-R52 as the secondary core on the RZ/T2H for multi-core operation, set Cortex-R52 CPU0 ATCM via AXIS (0x20000000 - 0x2007FFFF) and Cortex-R52 CPU1 ATCM via AXIS (0x21000000 - 0x2107FFFF) to Device Memory.

Memory Management Unit

In the CPU-MMU (CA55), a virtual address is assigned to a physical address, so the CPU accesses the virtual address. The use of virtual addresses enables access with different attributes from the CPU. For example, in RZ/T2H CA55, a virtual address noncache is placed in the area offset 0x0020_0000 (Reserved) from the physical address (System SRAM) in order to realize cache access to System SRAM and access noncache.

• Region01 (System SRAM : Cache)
  • Virtual address: 0x1000_0000
  • Physical address: 0x1000_0000
  • Size: 0x0020_0000
• Region02 (System SRAM mirror : Non-cache)
  • Virtual address: 0x1020_0000
  • Physical address: 0x1000_0000
  • Size: 0x0020_0000

Note that if a bus master other than the CPU accesses the same resource, direct access to the physical address is required. For example, when setting the source/destination address for a DMA transfer, the virtual address must be converted to a physical address. If address translation is required within a driver, such as FSP's DMAC driver, the BSP APIs (R_BSP_MmuVatoPa, R_BSP_MmuPatoVa) are used to perform address translation. If address translation is required within a user application, these BSP APIs should be used. Refer to FSP Module (DMAC, USB, Ethernet) for specific implementation examples of BSP API.

Note

When using Cortex-R52 as the secondary core on the RZ/T2H for multi-core operation, set Cortex-R52 CPU0 ATCM via AXIS (0x20000000 - 0x2007FFFF) and Cortex-R52 CPU1 ATCM via AXIS (0x21000000 - 0x2107FFFF) to Device Memory.

TrustZone Address Space Controller (TZC-400)

The TZC-400 module can be configured from the BSP properties of the RZ microprocessor containing the TZC-400.

• TZC-400-0: DDR SDRAM A0/A1 I/F.
• TZC-400-1: DDR SDRAM A4 I/F.
• TZC-400-2: PCIE Unit 0/1.
• TZC-400-3: DDR SDRAM R2 I/F.
• TZC-400-4: DDR SDRAM R3 I/F.
• TZC-400-5: SYSRAM unit 0/1/2/3.
• TZC-400-6: BSC
• TZC-400-7: xSPI unit 0/1.
• TZC-400-8: Cortex-R52 CPU0/1 AXIS (TCM).

The configuration values are generated as macro values in bsp_mcu_tzc400_memory_cfg.h and reflected in the ARM core registers in the startup code.

The default settings of the TZC-400 modules allow access in unprivileged and privileged in non-secure and secure in region 0.

For example, in RZT2H device, when creating the access rule in TZC-400-0: DDR SDRAM A0/A1 I/F, the settings shown below are used:

• Enter the filter unit in the Gatekeeper field.
• Region 0: Enter the filter unit in the attribute field.
• Region 0: Enable write control in attribute.
• Region 0: Enable read control in attribute.
• Region 0: Set ID (e.g. allow unprivileged and privileged access in non-secure, allow unprivileged and privileged access in secure) in NSAID read/write enable.

Note

When using Cortex-R52 as the secondary core on the RZ/T2H for multi-core operation, set filters 0 and 1 on the TZC-400-8 to enable access to the TCM of Cortex-R52 CPU0 and CPU1.

Module Reset

The reset state and the release can be set for each peripheral module. To secure processing after release from a module reset, dummy read the same register at sevral times after writing to initiate release from the module reset.

Note

Dummy reads are performed several times in the R_BSP_ModuleResetDisable function according to the RZ microprocessor manual. However, depending on the device used, the number of dummy reads for RTC and LCDC may not be met. In that case, please perform additional dummy read processing after API execution. For example, in the case of the RZT2H, the RTC requires 300 dummy reads and the LCDC requires 100 dummy reads.

Software Reset

Note

If the core that called the software reset function is different from the core you want to reset, you must execute the WFI instruction manually.

Configuration

The BSP is heavily data driven with most features and functionality being configured based on the content from configuration files. Configuration files represent the settings specified by the user and are generated when the project is built and/or when the Generate Project Content button is clicked in the FSP Configuration editor.

Build Time Configurations for fsp_common

The following build time configurations are defined in fsp_cfg/bsp/bsp_cfg.h:

Configuration	Options	Default	Description
MCU Vcc (mV)	Value must between 0 and 3800 (3.8V)	3300	Some peripherals require different settings based on the supplied voltage. Entering Vcc here (in mV) allows the relevant driver modules to configure the associated peripherals accordingly.
Parameter checking	Enabled Disabled	Disabled	When enabled, parameter checking for the BSP is turned on. In addition, any modules whose parameter checking configuration is set to 'Default (BSP)' will perform parameter checking as well.
Assert Failures	Return FSP_ERR_ASSERTION Call fsp_error_log then Return FSP_ERR_ASSERTION Use assert() to Halt Execution Disable checks that would return FSP_ERR_ASSERTION	Return FSP_ERR_ASSERTION	Define the behavior of the FSP_ASSERT() macro.
Error Log	No Error Log Errors Logged via fsp_error_log	No Error Log	Specify error logging behavior.
Soft Reset	Disabled Enabled	Disabled	Support for soft reset. If disabled, registers are assumed to be set to their default value during startup.
Port Protect	Disabled Enabled	Enabled	Keep the write protection function related GPIO settings locked when they are not being modified. If disabled they will be unlocked during startup.
Early BSP Initialization	Enabled Disabled	Disabled	Enable this option to use BSP functions before C runtime initialization (BSP_WARM_START_RESET or BSP_WARM_START_POST_CLOCK).
Multiplex Interrupt	Enabled Disabled	Disabled	Enable multiplex interrupt system-wide.

Duplication of resources

In the case of the secondary project (Non-primary cores), duplicate resource are indicated as the followings in Configuration tab when using resources that are used in the linked the primary (CR52_0 (CPU0) or CA55_0) project.

• BSP
  • Settings marked as "Valid only for primary core" are executed only for the primary project.
    • Master MPU
    • TrustZone Address Space Controller (TZC-400)
    • Address Expander
• Clocks
  • In secondary projects, this will be greyed out and cannot be set.
• Pins
  • The secondary project does not see the pin settings that you set in the primary project.
• Interrupts
  • There is no mutual exclusion control. If the user specifies an interrupt, be careful of resource overlaps.
• Event Links
  • The secondary project does not see the event factor that you set in the primary project.
• Stacks
  • Duplicate resource are indicated as red character that you set in the primary project.

Core Comparison

RZ/T2 uses Cortex-R52(CR52) and Cortex-A55(CA55) cores. The following is a cautionary execution when porting programs to different cores.

Specifications	CR52	CA55	Porting from CR52 to CA55	Porting from CA55 to CR52
Instruction set	AArch32 (32bit)	AArch64 (64bit)	Stack consumption doubles as CPU registers go from 32-bit to 64-bit.	-
Address space	4GB	32GB	Pointer type size changes from 32-bit to 64-bit.	Data placed in areas larger than 4 GB will need to be rearranged.
Cache	Instruction/data cache	L1 instruction/data cache L2 cache L3 cache	-	CA55-specific BSP API cannot be used. - R_BSP_CacheL3PowerCtrl()
Memory management	CPU-MPU	CPU-MMU	The non-cache section placed in System SRAM is allocated to a different area (Reserved) from the physical address as a virtual address. When handling physical addresses in user applications, address conversion is performed using the BSP API (R_BSP_MmuVatoPa, R_BSP_MmuPatoVa) that converts addresses.	CA55-specific BSP API cannot be used. - R_BSP_MmuVatoPa() - R_BSP_MmuPatoVa()
Interrupt	GIC	GIC-600	-	CA55-specific BSP API cannot be used. - R_BSP_GICD_xxxx() - R_BSP_GICR_xxxx() - R_BSP_GICC_xxxx()
Trigonometric Function Unit (TFU)	FSP supported	FSP not supported	Unable to use TFU-related BSP API.	-

Modules
	RZT2H
	RZT2L
	RZT2M
	RZT2ME

Macros
#define	BSP_IRQ_DISABLED
#define	FSP_RETURN(err)
#define	FSP_ERROR_LOG(err)
#define	FSP_ASSERT(a)
#define	FSP_ERROR_RETURN(a, err)
#define	FSP_CRITICAL_SECTION_ENTER
#define	FSP_CRITICAL_SECTION_EXIT
#define	FSP_INVALID_VECTOR
#define	BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x)
#define	BSP_SECTION_AARCH64_STACK
#define	BSP_STACK_ALIGNMENT
#define	R_BSP_MODULE_START(ip, channel)
#define	R_BSP_MODULE_STOP(ip, channel)

Enumerations
enum	fsp_ip_t
enum	fsp_signal_t
enum	bsp_warm_start_event_t
enum	bsp_delay_units_t
enum	bsp_reg_protect_t
enum	bsp_reset_t
enum	bsp_cluster_reset_auto_release_t
enum	bsp_module_reset_t
enum	bsp_resource_state_t
enum	bsp_resource_num_t
enum	bsp_grp_irq_t

Variables
uint32_t	SystemCoreClock

Macro Definition Documentation

BSP_IRQ_DISABLED

#define BSP_IRQ_DISABLED

Used to signify that an ELC event is not able to be used as an interrupt.

FSP_RETURN

#define FSP_RETURN

(

err

)

Macro to log and return error without an assertion.

FSP_ERROR_LOG

#define FSP_ERROR_LOG

(

err

)

This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in user code and do required debugging (breakpoints, stack dump, etc) in this function.

FSP_ASSERT

#define FSP_ASSERT

(

a

)

Default assertion calls FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP functions.

FSP_ERROR_RETURN

#define FSP_ERROR_RETURN	(		a,
			err
	)

All FSP error codes are returned using this macro. Calls FSP_ERROR_LOG function if condition "a" is false. Used to identify runtime errors in FSP functions.

FSP_CRITICAL_SECTION_ENTER

#define FSP_CRITICAL_SECTION_ENTER

This macro temporarily saves the current interrupt state and disables interrupts.

FSP_CRITICAL_SECTION_EXIT

#define FSP_CRITICAL_SECTION_EXIT

This macro restores the previously saved interrupt state, reenabling interrupts.

FSP_INVALID_VECTOR

#define FSP_INVALID_VECTOR

Used to signify that the requested IRQ vector is not defined in this system.

BSP_CFG_HANDLE_UNRECOVERABLE_ERROR

#define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR

(

x

)

In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will alert the user of the error. The user can override this default behavior by defining their own BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro.

BSP_SECTION_AARCH64_STACK

#define BSP_SECTION_AARCH64_STACK

Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file.

BSP_STACK_ALIGNMENT

#define BSP_STACK_ALIGNMENT

Stacks (and heap) must be sized and aligned to an integer multiple of this number.

R_BSP_MODULE_START

#define R_BSP_MODULE_START	(		ip,
			channel
	)

Cancels the module stop state.

Parameters

ip	fsp_ip_t enum value for the module to be stopped
channel	The channel. Use channel 0 for modules without channels.

R_BSP_MODULE_STOP

#define R_BSP_MODULE_STOP	(		ip,
			channel
	)

Enables the module stop state.

Parameters

ip	fsp_ip_t enum value for the module to be stopped
channel	The channel. Use channel 0 for modules without channels.

Enumeration Type Documentation

fsp_ip_t

enum fsp_ip_t

Available modules.

Enumerator
FSP_IP_CGC	Clock Generation Circuit.
FSP_IP_CLMA	Clock Monitor Circuit.
FSP_IP_MSTP	Module Stop.
FSP_IP_ICU	Interrupt Control Unit.
FSP_IP_BSC	Bus State Contoller.
FSP_IP_CKIO	CKIO.
FSP_IP_DMAC	DMA Controller.
FSP_IP_ELC	Event Link Controller.
FSP_IP_IOPORT	I/O Ports.
FSP_IP_MTU3	Multi-Function Timer Pulse Unit.
FSP_IP_POE3	Port Output Enable for MTU3.
FSP_IP_GPT	General PWM Timer.
FSP_IP_POEG	Port Output Enable for GPT.
FSP_IP_TFU	Arithmetic Unit for Trigonometric Functions.
FSP_IP_CMT	Compare Match Timer.
FSP_IP_CMTW	Compare Match Timer W.
FSP_IP_WDT	Watch Dog Timer.
FSP_IP_RTC	Real Time Clock.
FSP_IP_ETHSS	Ethernet Subsystem.
FSP_IP_GMAC	Ethernet MAC.
FSP_IP_ETHSW	Ethernet Switch.
FSP_IP_ESC	EtherCAT Slave Controller.
FSP_IP_USBHS	USB High Speed.
FSP_IP_SCI	Serial Communications Interface.
FSP_IP_IIC	I2C Bus Interface.
FSP_IP_CANFD	Controller Area Network with Flexible Data Rate.
FSP_IP_SPI	Serial Peripheral Interface.
FSP_IP_XSPI	expanded Serial Peripheral Interface
FSP_IP_CRC	Cyclic Redundancy Check Calculator.
FSP_IP_BSCAN	Boundary Scan.
FSP_IP_DSMIF	Delta Sigma Interface.
FSP_IP_ADC12	12-Bit A/D Converter
FSP_IP_TSU	Temperature Sensor.
FSP_IP_DOC	Data Operation Circuit.
FSP_IP_SYSRAM	System SRAM.
FSP_IP_ENCIF	Encoder Interface.
FSP_IP_SHOSTIF	Serial Host Interface.
FSP_IP_AFMT	A-Format.
FSP_IP_HDSL	HIPERFACE DSL.
FSP_IP_BISS	BiSS-C.
FSP_IP_ENDAT	EnDat 2.2.

fsp_signal_t

enum fsp_signal_t

Signals that can be mapped to an interrupt.

Enumerator
FSP_SIGNAL_INTCPU0	Software interrupt 0.
FSP_SIGNAL_INTCPU1	Software interrupt 1.
FSP_SIGNAL_INTCPU2	Software interrupt 2.
FSP_SIGNAL_INTCPU3	Software interrupt 3.
FSP_SIGNAL_INTCPU4	Software interrupt 4.
FSP_SIGNAL_INTCPU5	Software interrupt 5.
FSP_SIGNAL_IRQ0	External pin interrupt 0.
FSP_SIGNAL_IRQ1	External pin interrupt 1.
FSP_SIGNAL_IRQ2	External pin interrupt 2.
FSP_SIGNAL_IRQ3	External pin interrupt 3.
FSP_SIGNAL_IRQ4	External pin interrupt 4.
FSP_SIGNAL_IRQ5	External pin interrupt 5.
FSP_SIGNAL_IRQ6	External pin interrupt 6.
FSP_SIGNAL_IRQ7	External pin interrupt 7.
FSP_SIGNAL_IRQ8	External pin interrupt 8.
FSP_SIGNAL_IRQ9	External pin interrupt 9.
FSP_SIGNAL_IRQ10	External pin interrupt 10.
FSP_SIGNAL_IRQ11	External pin interrupt 11.
FSP_SIGNAL_IRQ12	External pin interrupt 12.
FSP_SIGNAL_IRQ13	External pin interrupt 13.
FSP_SIGNAL_BSC_CMI	Refresh compare match interrupt.
FSP_SIGNAL_DMAC0_INT0	DMAC0 transfer completion 0.
FSP_SIGNAL_DMAC0_INT1	DMAC0 transfer completion 1.
FSP_SIGNAL_DMAC0_INT2	DMAC0 transfer completion 2.
FSP_SIGNAL_DMAC0_INT3	DMAC0 transfer completion 3.
FSP_SIGNAL_DMAC0_INT4	DMAC0 transfer completion 4.
FSP_SIGNAL_DMAC0_INT5	DMAC0 transfer completion 5.
FSP_SIGNAL_DMAC0_INT6	DMAC0 transfer completion 6.
FSP_SIGNAL_DMAC0_INT7	DMAC0 transfer completion 7.
FSP_SIGNAL_DMAC0_INT8	DMAC0 transfer completion 8.
FSP_SIGNAL_DMAC0_INT9	DMAC0 transfer completion 9.
FSP_SIGNAL_DMAC0_INT10	DMAC0 transfer completion 10.
FSP_SIGNAL_DMAC0_INT11	DMAC0 transfer completion 11.
FSP_SIGNAL_DMAC0_INT12	DMAC0 transfer completion 12.
FSP_SIGNAL_DMAC0_INT13	DMAC0 transfer completion 13.
FSP_SIGNAL_DMAC0_INT14	DMAC0 transfer completion 14.
FSP_SIGNAL_DMAC0_INT15	DMAC0 transfer completion 15.
FSP_SIGNAL_DMAC1_INT0	DMAC1 transfer completion 0.
FSP_SIGNAL_DMAC1_INT1	DMAC1 transfer completion 1.
FSP_SIGNAL_DMAC1_INT2	DMAC1 transfer completion 2.
FSP_SIGNAL_DMAC1_INT3	DMAC1 transfer completion 3.
FSP_SIGNAL_DMAC1_INT4	DMAC1 transfer completion 4.
FSP_SIGNAL_DMAC1_INT5	DMAC1 transfer completion 5.
FSP_SIGNAL_DMAC1_INT6	DMAC1 transfer completion 6.
FSP_SIGNAL_DMAC1_INT7	DMAC1 transfer completion 7.
FSP_SIGNAL_DMAC1_INT8	DMAC1 transfer completion 8.
FSP_SIGNAL_DMAC1_INT9	DMAC1 transfer completion 9.
FSP_SIGNAL_DMAC1_INT10	DMAC1 transfer completion 10.
FSP_SIGNAL_DMAC1_INT11	DMAC1 transfer completion 11.
FSP_SIGNAL_DMAC1_INT12	DMAC1 transfer completion 12.
FSP_SIGNAL_DMAC1_INT13	DMAC1 transfer completion 13.
FSP_SIGNAL_DMAC1_INT14	DMAC1 transfer completion 14.
FSP_SIGNAL_DMAC1_INT15	DMAC1 transfer completion 15.
FSP_SIGNAL_CMT0_CMI	CMT0 Compare match.
FSP_SIGNAL_CMT1_CMI	CMT1 Compare match.
FSP_SIGNAL_CMT2_CMI	CMT2 Compare match.
FSP_SIGNAL_CMT3_CMI	CMT3 Compare match.
FSP_SIGNAL_CMT4_CMI	CMT4 Compare match.
FSP_SIGNAL_CMT5_CMI	CMT5 Compare match.
FSP_SIGNAL_CMTW0_CMWI	CMTW0 Compare match.
FSP_SIGNAL_CMTW0_IC0I	CMTW0 Input capture of register 0.
FSP_SIGNAL_CMTW0_IC1I	CMTW0 Input capture of register 1.
FSP_SIGNAL_CMTW0_OC0I	CMTW0 Output compare of register 0.
FSP_SIGNAL_CMTW0_OC1I	CMTW0 Output compare of register 1.
FSP_SIGNAL_CMTW1_CMWI	CMTW1 Compare match.
FSP_SIGNAL_CMTW1_IC0I	CMTW1 Input capture of register 0.
FSP_SIGNAL_CMTW1_IC1I	CMTW1 Input capture of register 1.
FSP_SIGNAL_CMTW1_OC0I	CMTW1 Output compare of register 0.
FSP_SIGNAL_CMTW1_OC1I	CMTW1 Output compare of register 1.
FSP_SIGNAL_TGIA0	MTU0.TGRA input capture/compare match.
FSP_SIGNAL_TGIB0	MTU0.TGRB input capture/compare match.
FSP_SIGNAL_TGIC0	MTU0.TGRC input capture/compare match.
FSP_SIGNAL_TGID0	MTU0.TGRD input capture/compare match.
FSP_SIGNAL_TCIV0	MTU0.TCNT overflow.
FSP_SIGNAL_TGIE0	MTU0.TGRE compare match.
FSP_SIGNAL_TGIF0	MTU0.TGRF compare match.
FSP_SIGNAL_TGIA1	MTU1.TGRA input capture/compare match.
FSP_SIGNAL_TGIB1	MTU1.TGRB input capture/compare match.
FSP_SIGNAL_TCIV1	MTU1.TCNT overflow.
FSP_SIGNAL_TCIU1	MTU1.TCNT underflow.
FSP_SIGNAL_TGIA2	MTU2.TGRA input capture/compare match.
FSP_SIGNAL_TGIB2	MTU2.TGRB input capture/compare match.
FSP_SIGNAL_TCIV2	MTU2.TCNT overflow.
FSP_SIGNAL_TCIU2	MTU2.TCNT underflow.
FSP_SIGNAL_TGIA3	MTU3.TGRA input capture/compare match.
FSP_SIGNAL_TGIB3	MTU3.TGRB input capture/compare match.
FSP_SIGNAL_TGIC3	MTU3.TGRC input capture/compare match.
FSP_SIGNAL_TGID3	MTU3.TGRD input capture/compare match.
FSP_SIGNAL_TCIV3	MTU3.TCNT overflow.
FSP_SIGNAL_TGIA4	MTU4.TGRA input capture/compare match.
FSP_SIGNAL_TGIB4	MTU4.TGRB input capture/compare match.
FSP_SIGNAL_TGIC4	MTU4.TGRC input capture/compare match.
FSP_SIGNAL_TGID4	MTU4.TGRD input capture/compare match.
FSP_SIGNAL_TCIV4	MTU4.TCNT overflow/underflow.
FSP_SIGNAL_TGIU5	MTU5.TGRU input capture/compare match.
FSP_SIGNAL_TGIV5	MTU5.TGRV input capture/compare match.
FSP_SIGNAL_TGIW5	MTU5.TGRW input capture/compare match.
FSP_SIGNAL_TGIA6	MTU6.TGRA input capture/compare match.
FSP_SIGNAL_TGIB6	MTU6.TGRB input capture/compare match.
FSP_SIGNAL_TGIC6	MTU6.TGRC input capture/compare match.
FSP_SIGNAL_TGID6	MTU6.TGRD input capture/compare match.
FSP_SIGNAL_TCIV6	MTU6.TCNT overflow.
FSP_SIGNAL_TGIA7	MTU7.TGRA input capture/compare match.
FSP_SIGNAL_TGIB7	MTU7.TGRB input capture/compare match.
FSP_SIGNAL_TGIC7	MTU7.TGRC input capture/compare match.
FSP_SIGNAL_TGID7	MTU7.TGRD input capture/compare match.
FSP_SIGNAL_TCIV7	MTU7.TCNT overflow/underflow.
FSP_SIGNAL_TGIA8	MTU8.TGRA input capture/compare match.
FSP_SIGNAL_TGIB8	MTU8.TGRB input capture/compare match.
FSP_SIGNAL_TGIC8	MTU8.TGRC input capture/compare match.
FSP_SIGNAL_TGID8	MTU8.TGRD input capture/compare match.
FSP_SIGNAL_TCIV8	MTU8.TCNT overflow.
FSP_SIGNAL_OEI1	Output enable interrupt 1.
FSP_SIGNAL_OEI2	Output enable interrupt 2.
FSP_SIGNAL_OEI3	Output enable interrupt 3.
FSP_SIGNAL_OEI4	Output enable interrupt 4.
FSP_SIGNAL_GPT0_CCMPA	GPT0 GTCCRA input capture/compare match.
FSP_SIGNAL_GPT0_CCMPB	GPT0 GTCCRB input capture/compare match.
FSP_SIGNAL_GPT0_CMPC	GPT0 GTCCRC compare match.
FSP_SIGNAL_GPT0_CMPD	GPT0 GTCCRD compare match.
FSP_SIGNAL_GPT0_CMPE	GPT0 GTCCRE compare match.
FSP_SIGNAL_GPT0_CMPF	GPT0 GTCCRF compare match.
FSP_SIGNAL_GPT0_OVF	GPT0 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT0_UDF	GPT0 GTCNT underflow.
FSP_SIGNAL_GPT0_DTE	GPT0 Dead time error.
FSP_SIGNAL_GPT1_CCMPA	GPT1 GTCCRA input capture/compare match.
FSP_SIGNAL_GPT1_CCMPB	GPT1 GTCCRB input capture/compare match.
FSP_SIGNAL_GPT1_CMPC	GPT1 GTCCRC compare match.
FSP_SIGNAL_GPT1_CMPD	GPT1 GTCCRD compare match.
FSP_SIGNAL_GPT1_CMPE	GPT1 GTCCRE compare match.
FSP_SIGNAL_GPT1_CMPF	GPT1 GTCCRF compare match.
FSP_SIGNAL_GPT1_OVF	GPT1 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT1_UDF	GPT1 GTCNT underflow.
FSP_SIGNAL_GPT1_DTE	GPT1 Dead time error.
FSP_SIGNAL_GPT2_CCMPA	GPT2 GTCCRA input capture/compare match.
FSP_SIGNAL_GPT2_CCMPB	GPT2 GTCCRB input capture/compare match.
FSP_SIGNAL_GPT2_CMPC	GPT2 GTCCRC compare match.
FSP_SIGNAL_GPT2_CMPD	GPT2 GTCCRD compare match.
FSP_SIGNAL_GPT2_CMPE	GPT2 GTCCRE compare match.
FSP_SIGNAL_GPT2_CMPF	GPT2 GTCCRF compare match.
FSP_SIGNAL_GPT2_OVF	GPT2 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT2_UDF	GPT2 GTCNT underflow.
FSP_SIGNAL_GPT2_DTE	GPT2 Dead time error.
FSP_SIGNAL_GPT3_CCMPA	GPT3 GTCCRA input capture/compare match.
FSP_SIGNAL_GPT3_CCMPB	GPT3 GTCCRB input capture/compare match.
FSP_SIGNAL_GPT3_CMPC	GPT3 GTCCRC compare match.
FSP_SIGNAL_GPT3_CMPD	GPT3 GTCCRD compare match.
FSP_SIGNAL_GPT3_CMPE	GPT3 GTCCRE compare match.
FSP_SIGNAL_GPT3_CMPF	GPT3 GTCCRF compare match.
FSP_SIGNAL_GPT3_OVF	GPT3 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT3_UDF	GPT3 GTCNT underflow.
FSP_SIGNAL_GPT3_DTE	GPT3 Dead time error.
FSP_SIGNAL_GPT4_CCMPA	GPT4 GTCCRA input capture/compare match.
FSP_SIGNAL_GPT4_CCMPB	GPT4 GTCCRB input capture/compare match.
FSP_SIGNAL_GPT4_CMPC	GPT4 GTCCRC compare match.
FSP_SIGNAL_GPT4_CMPD	GPT4 GTCCRD compare match.
FSP_SIGNAL_GPT4_CMPE	GPT4 GTCCRE compare match.
FSP_SIGNAL_GPT4_CMPF	GPT4 GTCCRF compare match.
FSP_SIGNAL_GPT4_OVF	GPT4 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT4_UDF	GPT4 GTCNT underflow.
FSP_SIGNAL_GPT4_DTE	GPT4 Dead time error.
FSP_SIGNAL_GPT5_CCMPA	GPT5 GTCCRA input capture/compare match.
FSP_SIGNAL_GPT5_CCMPB	GPT5 GTCCRB input capture/compare match.
FSP_SIGNAL_GPT5_CMPC	GPT5 GTCCRC compare match.
FSP_SIGNAL_GPT5_CMPD	GPT5 GTCCRD compare match.
FSP_SIGNAL_GPT5_CMPE	GPT5 GTCCRE compare match.
FSP_SIGNAL_GPT5_CMPF	GPT5 GTCCRF compare match.
FSP_SIGNAL_GPT5_OVF	GPT5 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT5_UDF	GPT5 GTCNT underflow.
FSP_SIGNAL_GPT5_DTE	GPT5 Dead time error.
FSP_SIGNAL_GPT6_CCMPA	GPT6 GTCCRA input capture/compare match.
FSP_SIGNAL_GPT6_CCMPB	GPT6 GTCCRB input capture/compare match.
FSP_SIGNAL_GPT6_CMPC	GPT6 GTCCRC compare match.
FSP_SIGNAL_GPT6_CMPD	GPT6 GTCCRD compare match.
FSP_SIGNAL_GPT6_CMPE	GPT6 GTCCRE compare match.
FSP_SIGNAL_GPT6_CMPF	GPT6 GTCCRF compare match.
FSP_SIGNAL_GPT6_OVF	GPT6 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT6_UDF	GPT6 GTCNT underflow.
FSP_SIGNAL_GPT6_DTE	GPT6 Dead time error.
FSP_SIGNAL_GPT7_CCMPA	GPT7 GTCCRA input capture/compare match.
FSP_SIGNAL_GPT7_CCMPB	GPT7 GTCCRB input capture/compare match.
FSP_SIGNAL_GPT7_CMPC	GPT7 GTCCRC compare match.
FSP_SIGNAL_GPT7_CMPD	GPT7 GTCCRD compare match.
FSP_SIGNAL_GPT7_CMPE	GPT7 GTCCRE compare match.
FSP_SIGNAL_GPT7_CMPF	GPT7 GTCCRF compare match.
FSP_SIGNAL_GPT7_OVF	GPT7 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT7_UDF	GPT7 GTCNT underflow.
FSP_SIGNAL_GPT7_DTE	GPT7 Dead time error.
FSP_SIGNAL_GPT8_CCMPA	GPT8 GTCCRA input capture/compare match.
FSP_SIGNAL_GPT8_CCMPB	GPT8 GTCCRB input capture/compare match.
FSP_SIGNAL_GPT8_CMPC	GPT8 GTCCRC compare match.
FSP_SIGNAL_GPT8_CMPD	GPT8 GTCCRD compare match.
FSP_SIGNAL_GPT8_CMPE	GPT8 GTCCRE compare match.
FSP_SIGNAL_GPT8_CMPF	GPT8 GTCCRF compare match.
FSP_SIGNAL_GPT8_OVF	GPT8 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT8_UDF	GPT8 GTCNT underflow.
FSP_SIGNAL_GPT8_DTE	GPT8 Dead time error.
FSP_SIGNAL_GPT9_CCMPA	GPT9 GTCCRA input capture/compare match.
FSP_SIGNAL_GPT9_CCMPB	GPT9 GTCCRB input capture/compare match.
FSP_SIGNAL_GPT9_CMPC	GPT9 GTCCRC compare match.
FSP_SIGNAL_GPT9_CMPD	GPT9 GTCCRD compare match.
FSP_SIGNAL_GPT9_CMPE	GPT9 GTCCRE compare match.
FSP_SIGNAL_GPT9_CMPF	GPT9 GTCCRF compare match.
FSP_SIGNAL_GPT9_OVF	GPT9 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT9_UDF	GPT9 GTCNT underflow.
FSP_SIGNAL_GPT9_DTE	GPT9 Dead time error.
FSP_SIGNAL_GPT10_CCMPA	GPT10 GTCCRA input capture/compare match.
FSP_SIGNAL_GPT10_CCMPB	GPT10 GTCCRB input capture/compare match.
FSP_SIGNAL_GPT10_CMPC	GPT10 GTCCRC compare match.
FSP_SIGNAL_GPT10_CMPD	GPT10 GTCCRD compare match.
FSP_SIGNAL_GPT10_CMPE	GPT10 GTCCRE compare match.
FSP_SIGNAL_GPT10_CMPF	GPT10 GTCCRF compare match.
FSP_SIGNAL_GPT10_OVF	GPT10 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT10_UDF	GPT10 GTCNT underflow.
FSP_SIGNAL_GPT10_DTE	GPT10 Dead time error.
FSP_SIGNAL_GPT11_CCMPA	GPT11 GTCCRA input capture/compare match.
FSP_SIGNAL_GPT11_CCMPB	GPT11 GTCCRB input capture/compare match.
FSP_SIGNAL_GPT11_CMPC	GPT11 GTCCRC compare match.
FSP_SIGNAL_GPT11_CMPD	GPT11 GTCCRD compare match.
FSP_SIGNAL_GPT11_CMPE	GPT11 GTCCRE compare match.
FSP_SIGNAL_GPT11_CMPF	GPT11 GTCCRF compare match.
FSP_SIGNAL_GPT11_OVF	GPT11 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT11_UDF	GPT11 GTCNT underflow.
FSP_SIGNAL_GPT11_DTE	GPT11 Dead time error.
FSP_SIGNAL_GPT12_CCMPA	GPT12 GTCCRA input capture/compare match.
FSP_SIGNAL_GPT12_CCMPB	GPT12 GTCCRB input capture/compare match.
FSP_SIGNAL_GPT12_CMPC	GPT12 GTCCRC compare match.
FSP_SIGNAL_GPT12_CMPD	GPT12 GTCCRD compare match.
FSP_SIGNAL_GPT12_CMPE	GPT12 GTCCRE compare match.
FSP_SIGNAL_GPT12_CMPF	GPT12 GTCCRF compare match.
FSP_SIGNAL_GPT12_OVF	GPT12 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT12_UDF	GPT12 GTCNT underflow.
FSP_SIGNAL_GPT12_DTE	GPT12 Dead time error.
FSP_SIGNAL_GPT13_CCMPA	GPT13 GTCCRA input capture/compare match.
FSP_SIGNAL_GPT13_CCMPB	GPT13 GTCCRB input capture/compare match.
FSP_SIGNAL_GPT13_CMPC	GPT13 GTCCRC compare match.
FSP_SIGNAL_GPT13_CMPD	GPT13 GTCCRD compare match.
FSP_SIGNAL_GPT13_CMPE	GPT13 GTCCRE compare match.
FSP_SIGNAL_GPT13_CMPF	GPT13 GTCCRF compare match.
FSP_SIGNAL_GPT13_OVF	GPT13 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT13_UDF	GPT13 GTCNT underflow.
FSP_SIGNAL_GPT13_DTE	GPT13 Dead time error.
FSP_SIGNAL_POEG0_GROUP0	POEG group A interrupt for channels in LLPP.
FSP_SIGNAL_POEG0_GROUP1	POEG group B interrupt for channels in LLPP.
FSP_SIGNAL_POEG0_GROUP2	POEG group C interrupt for channels in LLPP.
FSP_SIGNAL_POEG0_GROUP3	POEG group D interrupt for channels in LLPP.
FSP_SIGNAL_POEG1_GROUP0	POEG group A interrupt for channels in NONSAFETY.
FSP_SIGNAL_POEG1_GROUP1	POEG group B interrupt for channels in NONSAFETY.
FSP_SIGNAL_POEG1_GROUP2	POEG group C interrupt for channels in NONSAFETY.
FSP_SIGNAL_POEG1_GROUP3	POEG group D interrupt for channels in NONSAFETY.
FSP_SIGNAL_GMAC_LPI	GMAC1 energy efficient.
FSP_SIGNAL_GMAC_PMT	GMAC1 power management.
FSP_SIGNAL_GMAC_SBD	GMAC1 general interrupt.
FSP_SIGNAL_ETHSW_INTR	Ethernet Switch interrupt.
FSP_SIGNAL_ETHSW_DLR	Ethernet Switch DLR interrupt.
FSP_SIGNAL_ETHSW_PRP	Ethernet Switch PRP interrupt.
FSP_SIGNAL_ETHSW_IHUB	Ethernet Switch Integrated Hub interrupt.
FSP_SIGNAL_ETHSW_PTRN0	Ethernet Switch RX Pattern Matcher interrupt 0.
FSP_SIGNAL_ETHSW_PTRN1	Ethernet Switch RX Pattern Matcher interrupt 1.
FSP_SIGNAL_ETHSW_PTRN2	Ethernet Switch RX Pattern Matcher interrupt 2.
FSP_SIGNAL_ETHSW_PTRN3	Ethernet Switch RX Pattern Matcher interrupt 3.
FSP_SIGNAL_ETHSW_PTRN4	Ethernet Switch RX Pattern Matcher interrupt 4.
FSP_SIGNAL_ETHSW_PTRN5	Ethernet Switch RX Pattern Matcher interrupt 5.
FSP_SIGNAL_ETHSW_PTRN6	Ethernet Switch RX Pattern Matcher interrupt 6.
FSP_SIGNAL_ETHSW_PTRN7	Ethernet Switch RX Pattern Matcher interrupt 7.
FSP_SIGNAL_ETHSW_PTRN8	Ethernet Switch RX Pattern Matcher interrupt 8.
FSP_SIGNAL_ETHSW_PTRN9	Ethernet Switch RX Pattern Matcher interrupt 9.
FSP_SIGNAL_ETHSW_PTRN10	Ethernet Switch RX Pattern Matcher interrupt 10.
FSP_SIGNAL_ETHSW_PTRN11	Ethernet Switch RX Pattern Matcher interrupt 11.
FSP_SIGNAL_ETHSW_PTPOUT0	Ethernet switch timer pulse output 0.
FSP_SIGNAL_ETHSW_PTPOUT1	Ethernet switch timer pulse output 1.
FSP_SIGNAL_ETHSW_PTPOUT2	Ethernet switch timer pulse output 2.
FSP_SIGNAL_ETHSW_PTPOUT3	Ethernet switch timer pulse output 3.
FSP_SIGNAL_ETHSW_TDMAOUT0	Ethernet Switch TDMA timer output 0.
FSP_SIGNAL_ETHSW_TDMAOUT1	Ethernet Switch TDMA timer output 1.
FSP_SIGNAL_ETHSW_TDMAOUT2	Ethernet Switch TDMA timer output 2.
FSP_SIGNAL_ETHSW_TDMAOUT3	Ethernet Switch TDMA timer output 3.
FSP_SIGNAL_ESC_SYNC0	EtherCAT Sync0 interrupt.
FSP_SIGNAL_ESC_SYNC1	EtherCAT Sync1 interrupt.
FSP_SIGNAL_ESC_CAT	EtherCAT interrupt.
FSP_SIGNAL_ESC_SOF	EtherCAT SOF interrupt.
FSP_SIGNAL_ESC_EOF	EtherCAT EOF interrupt.
FSP_SIGNAL_ESC_WDT	EtherCAT WDT interrupt.
FSP_SIGNAL_ESC_RST	EtherCAT RESET interrupt.
FSP_SIGNAL_USB_HI	USB (Host) interrupt.
FSP_SIGNAL_USB_FI	USB (Function) interrupt.
FSP_SIGNAL_USB_FDMA0	USB (Function) DMA 0 transmit completion.
FSP_SIGNAL_USB_FDMA1	USB (Function) DMA 1 transmit completion.
FSP_SIGNAL_SCI0_ERI	SCI0 Receive error.
FSP_SIGNAL_SCI0_RXI	SCI0 Receive data full.
FSP_SIGNAL_SCI0_TXI	SCI0 Transmit data empty.
FSP_SIGNAL_SCI0_TEI	SCI0 Transmit end.
FSP_SIGNAL_SCI1_ERI	SCI1 Receive error.
FSP_SIGNAL_SCI1_RXI	SCI1 Receive data full.
FSP_SIGNAL_SCI1_TXI	SCI1 Transmit data empty.
FSP_SIGNAL_SCI1_TEI	SCI1 Transmit end.
FSP_SIGNAL_SCI2_ERI	SCI2 Receive error.
FSP_SIGNAL_SCI2_RXI	SCI2 Receive data full.
FSP_SIGNAL_SCI2_TXI	SCI2 Transmit data empty.
FSP_SIGNAL_SCI2_TEI	SCI2 Transmit end.
FSP_SIGNAL_SCI3_ERI	SCI3 Receive error.
FSP_SIGNAL_SCI3_RXI	SCI3 Receive data full.
FSP_SIGNAL_SCI3_TXI	SCI3 Transmit data empty.
FSP_SIGNAL_SCI3_TEI	SCI3 Transmit end.
FSP_SIGNAL_SCI4_ERI	SCI4 Receive error.
FSP_SIGNAL_SCI4_RXI	SCI4 Receive data full.
FSP_SIGNAL_SCI4_TXI	SCI4 Transmit data empty.
FSP_SIGNAL_SCI4_TEI	SCI4 Transmit end.
FSP_SIGNAL_IIC0_EEI	IIC0 Transfer error or event generation.
FSP_SIGNAL_IIC0_RXI	IIC0 Receive data full.
FSP_SIGNAL_IIC0_TXI	IIC0 Transmit data empty.
FSP_SIGNAL_IIC0_TEI	IIC0 Transmit end.
FSP_SIGNAL_IIC1_EEI	IIC1 Transfer error or event generation.
FSP_SIGNAL_IIC1_RXI	IIC1 Receive data full.
FSP_SIGNAL_IIC1_TXI	IIC1 Transmit data empty.
FSP_SIGNAL_IIC1_TEI	IIC1 Transmit end.
FSP_SIGNAL_CAN_RXF	CANFD RX FIFO interrupt.
FSP_SIGNAL_CAN_GLERR	CANFD Global error interrupt.
FSP_SIGNAL_CAN0_TX	CAFND0 Channel TX interrupt.
FSP_SIGNAL_CAN0_CHERR	CAFND0 Channel CAN error interrupt.
FSP_SIGNAL_CAN0_COMFRX	CAFND0 Common RX FIFO or TXQ interrupt.
FSP_SIGNAL_CAN1_TX	CAFND1 Channel TX interrupt.
FSP_SIGNAL_CAN1_CHERR	CAFND1 Channel CAN error interrupt.
FSP_SIGNAL_CAN1_COMFRX	CAFND1 Common RX FIFO or TXQ interrupt.
FSP_SIGNAL_SPI0_SPRI	SPI0 Reception buffer full.
FSP_SIGNAL_SPI0_SPTI	SPI0 Transmit buffer empty.
FSP_SIGNAL_SPI0_SPII	SPI0 SPI idle.
FSP_SIGNAL_SPI0_SPEI	SPI0 errors.
FSP_SIGNAL_SPI0_SPCEND	SPI0 Communication complete.
FSP_SIGNAL_SPI1_SPRI	SPI1 Reception buffer full.
FSP_SIGNAL_SPI1_SPTI	SPI1 Transmit buffer empty.
FSP_SIGNAL_SPI1_SPII	SPI1 SPI idle.
FSP_SIGNAL_SPI1_SPEI	SPI1 errors.
FSP_SIGNAL_SPI1_SPCEND	SPI1 Communication complete.
FSP_SIGNAL_SPI2_SPRI	SPI2 Reception buffer full.
FSP_SIGNAL_SPI2_SPTI	SPI2 Transmit buffer empty.
FSP_SIGNAL_SPI2_SPII	SPI2 SPI idle.
FSP_SIGNAL_SPI2_SPEI	SPI2 errors.
FSP_SIGNAL_SPI2_SPCEND	SPI2 Communication complete.
FSP_SIGNAL_XSPI0_INT	xSPI0 Interrupt
FSP_SIGNAL_XSPI0_INTERR	xSPI0 Error interrupt
FSP_SIGNAL_XSPI1_INT	xSPI1 Interrupt
FSP_SIGNAL_XSPI1_INTERR	xSPI1 Error interrupt
FSP_SIGNAL_DSMIF0_CDRUI	DSMIF0 current data register update (ORed ch0 to ch2)
FSP_SIGNAL_DSMIF1_CDRUI	DSMIF1 current data register update (ORed ch3 to ch5)
FSP_SIGNAL_ADC0_ADI	ADC0 A/D scan end interrupt.
FSP_SIGNAL_ADC0_GBADI	ADC0 A/D scan end interrupt for Group B.
FSP_SIGNAL_ADC0_GCADI	ADC0 A/D scan end interrupt for Group C.
FSP_SIGNAL_ADC0_CMPAI	ADC0 Window A compare match.
FSP_SIGNAL_ADC0_CMPBI	ADC0 Window B compare match.
FSP_SIGNAL_ADC1_ADI	ADC1 A/D scan end interrupt.
FSP_SIGNAL_ADC1_GBADI	ADC1 A/D scan end interrupt for Group B.
FSP_SIGNAL_ADC1_GCADI	ADC1 A/D scan end interrupt for Group C.
FSP_SIGNAL_ADC1_CMPAI	ADC1 Window A compare match.
FSP_SIGNAL_ADC1_CMPBI	ADC1 Window B compare match.
FSP_SIGNAL_ENCIF_INT0	ENCIF CH0 Interrupt A.
FSP_SIGNAL_ENCIF_INT1	ENCIF CH0 Interrupt B.
FSP_SIGNAL_ENCIF_INT2	ENCIF CH0 OUTPUT FIFO Interrupt.
FSP_SIGNAL_ENCIF_INT3	ENCIF CH0 INPUT FIFO Interrupt.
FSP_SIGNAL_ENCIF_INT4	ENCIF CH1 Interrupt A.
FSP_SIGNAL_ENCIF_INT5	ENCIF CH1 Interrupt B.
FSP_SIGNAL_ENCIF_INT6	ENCIF CH1 OUTPUT FIFO Interrupt.
FSP_SIGNAL_ENCIF_INT7	ENCIF CH1 INPUT FIFO Interrupt.
FSP_SIGNAL_CPU0_ERR0	Cortex-R52 CPU0 error event 0.
FSP_SIGNAL_CPU0_ERR1	Cortex-R52 CPU0 error event 1.
FSP_SIGNAL_CPU1_ERR0	Cortex-R52 CPU1 error event 0.
FSP_SIGNAL_CPU1_ERR1	Cortex-R52 CPU1 error event 1.
FSP_SIGNAL_PERI_ERR0	Peripherals error event 0.
FSP_SIGNAL_PERI_ERR1	Peripherals error event 1.
FSP_SIGNAL_INTCPU6	Software interrupt 6.
FSP_SIGNAL_INTCPU7	Software interrupt 7.
FSP_SIGNAL_IRQ14	External pin interrupt 14.
FSP_SIGNAL_IRQ15	External pin interrupt 15.
FSP_SIGNAL_GPT14_CCMPA	GPT14 GTCCRA input capture/compare match.
FSP_SIGNAL_GPT14_CCMPB	GPT14 GTCCRB input capture/compare match.
FSP_SIGNAL_GPT14_CMPC	GPT14 GTCCRC compare match.
FSP_SIGNAL_GPT14_CMPD	GPT14 GTCCRD compare match.
FSP_SIGNAL_GPT14_CMPE	GPT14 GTCCRE compare match.
FSP_SIGNAL_GPT14_CMPF	GPT14 GTCCRF compare match.
FSP_SIGNAL_GPT14_OVF	GPT14 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT14_UDF	GPT14 GTCNT underflow.
FSP_SIGNAL_GPT15_CCMPA	GPT15 GTCCRA input capture/compare match.
FSP_SIGNAL_GPT15_CCMPB	GPT15 GTCCRB input capture/compare match.
FSP_SIGNAL_GPT15_CMPC	GPT15 GTCCRC compare match.
FSP_SIGNAL_GPT15_CMPD	GPT15 GTCCRD compare match.
FSP_SIGNAL_GPT15_CMPE	GPT15 GTCCRE compare match.
FSP_SIGNAL_GPT15_CMPF	GPT15 GTCCRF compare match.
FSP_SIGNAL_GPT15_OVF	GPT15 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT15_UDF	GPT15 GTCNT underflow.
FSP_SIGNAL_GPT16_CCMPA	GPT16 GTCCRA input capture/compare match.
FSP_SIGNAL_GPT16_CCMPB	GPT16 GTCCRB input capture/compare match.
FSP_SIGNAL_GPT16_CMPC	GPT16 GTCCRC compare match.
FSP_SIGNAL_GPT16_CMPD	GPT16 GTCCRD compare match.
FSP_SIGNAL_GPT16_CMPE	GPT16 GTCCRE compare match.
FSP_SIGNAL_GPT16_CMPF	GPT16 GTCCRF compare match.
FSP_SIGNAL_GPT16_OVF	GPT16 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT16_UDF	GPT16 GTCNT underflow.
FSP_SIGNAL_GPT17_CCMPA	GPT17 GTCCRA input capture/compare match.
FSP_SIGNAL_GPT17_CCMPB	GPT17 GTCCRB input capture/compare match.
FSP_SIGNAL_GPT17_CMPC	GPT17 GTCCRC compare match.
FSP_SIGNAL_GPT17_CMPD	GPT17 GTCCRD compare match.
FSP_SIGNAL_GPT17_CMPE	GPT17 GTCCRE compare match.
FSP_SIGNAL_GPT17_CMPF	GPT17 GTCCRF compare match.
FSP_SIGNAL_GPT17_OVF	GPT17 GTCNT overflow (GTPR compare match)
FSP_SIGNAL_GPT17_UDF	GPT17 GTCNT underflow.
FSP_SIGNAL_POEG2_GROUP0	POEG group A interrupt for channels in SAFETY.
FSP_SIGNAL_POEG2_GROUP1	POEG group B interrupt for channels in SAFETY.
FSP_SIGNAL_POEG2_GROUP2	POEG group C interrupt for channels in SAFETY.
FSP_SIGNAL_POEG2_GROUP3	POEG group D interrupt for channels in SAFETY.
FSP_SIGNAL_RTC_ALM	Alarm interrupt.
FSP_SIGNAL_RTC_1S	1 second interrupt
FSP_SIGNAL_RTC_PRD	Fixed interval interrupt.
FSP_SIGNAL_SCI5_ERI	SCI5 Receive error.
FSP_SIGNAL_SCI5_RXI	SCI5 Receive data full.
FSP_SIGNAL_SCI5_TXI	SCI5 Transmit data empty.
FSP_SIGNAL_SCI5_TEI	SCI5 Transmit end.
FSP_SIGNAL_IIC2_EEI	IIC2 Transfer error or event generation.
FSP_SIGNAL_IIC2_RXI	IIC2 Receive data full.
FSP_SIGNAL_IIC2_TXI	IIC2 Transmit data empty.
FSP_SIGNAL_IIC2_TEI	IIC2 Transmit end.
FSP_SIGNAL_SPI3_SPRI	SPI3 Reception buffer full.
FSP_SIGNAL_SPI3_SPTI	SPI3 Transmit buffer empty.
FSP_SIGNAL_SPI3_SPII	SPI3 SPI idle.
FSP_SIGNAL_SPI3_SPEI	SPI3 errors.
FSP_SIGNAL_SPI3_SPCEND	SPI3 Communication complete.
FSP_SIGNAL_DREQ	External DMA request.
FSP_SIGNAL_CAN_RF_DMAREQ0	CAFND RX FIFO 0 DMA request.
FSP_SIGNAL_CAN_RF_DMAREQ1	CAFND RX FIFO 1 DMA request.
FSP_SIGNAL_CAN_RF_DMAREQ2	CAFND RX FIFO 2 DMA request.
FSP_SIGNAL_CAN_RF_DMAREQ3	CAFND RX FIFO 3 DMA request.
FSP_SIGNAL_CAN_RF_DMAREQ4	CAFND RX FIFO 4 DMA request.
FSP_SIGNAL_CAN_RF_DMAREQ5	CAFND RX FIFO 5 DMA request.
FSP_SIGNAL_CAN_RF_DMAREQ6	CAFND RX FIFO 6 DMA request.
FSP_SIGNAL_CAN_RF_DMAREQ7	CAFND RX FIFO 7 DMA request.
FSP_SIGNAL_CAN0_CF_DMAREQ	CAFND0 First common FIFO DMA request.
FSP_SIGNAL_CAN1_CF_DMAREQ	CAFND1 First common FIFO DMA request.
FSP_SIGNAL_ADC0_WCMPM	ADC0 compare match.
FSP_SIGNAL_ADC0_WCMPUM	ADC0 compare mismatch.
FSP_SIGNAL_ADC1_WCMPM	ADC1 compare match.
FSP_SIGNAL_ADC1_WCMPUM	ADC1 compare mismatch.
FSP_SIGNAL_TCIV4_OF	MTU4.TCNT overflow.
FSP_SIGNAL_TCIV4_UF	MTU4.TCNT underflow.
FSP_SIGNAL_TCIV7_OF	MTU7.TCNT overflow.
FSP_SIGNAL_TCIV7_UF	MTU7.TCNT underflow.
FSP_SIGNAL_IOPORT_GROUP1	Input edge detection of input port group 1.
FSP_SIGNAL_IOPORT_GROUP2	Input edge detection of input port group 2.
FSP_SIGNAL_IOPORT_SINGLE0	Input edge detection of single input port 0.
FSP_SIGNAL_IOPORT_SINGLE1	Input edge detection of single input port 1.
FSP_SIGNAL_IOPORT_SINGLE2	Input edge detection of single input port 2.
FSP_SIGNAL_IOPORT_SINGLE3	Input edge detection of single input port 3.
FSP_SIGNAL_GPT0_ADTRGA	GPT0 GTADTRA compare match.
FSP_SIGNAL_GPT0_ADTRGB	GPT0 GTADTRB compare match.
FSP_SIGNAL_GPT1_ADTRGA	GPT1 GTADTRA compare match.
FSP_SIGNAL_GPT1_ADTRGB	GPT1 GTADTRB compare match.
FSP_SIGNAL_GPT2_ADTRGA	GPT2 GTADTRA compare match.
FSP_SIGNAL_GPT2_ADTRGB	GPT2 GTADTRB compare match.
FSP_SIGNAL_GPT3_ADTRGA	GPT3 GTADTRA compare match.
FSP_SIGNAL_GPT3_ADTRGB	GPT3 GTADTRB compare match.
FSP_SIGNAL_GPT4_ADTRGA	GPT4 GTADTRA compare match.
FSP_SIGNAL_GPT4_ADTRGB	GPT4 GTADTRB compare match.
FSP_SIGNAL_GPT5_ADTRGA	GPT5 GTADTRA compare match.
FSP_SIGNAL_GPT5_ADTRGB	GPT5 GTADTRB compare match.
FSP_SIGNAL_GPT6_ADTRGA	GPT6 GTADTRA compare match.
FSP_SIGNAL_GPT6_ADTRGB	GPT6 GTADTRB compare match.
FSP_SIGNAL_GPT7_ADTRGA	GPT7 GTADTRA compare match.
FSP_SIGNAL_GPT7_ADTRGB	GPT7 GTADTRB compare match.
FSP_SIGNAL_GPT8_ADTRGA	GPT8 GTADTRA compare match.
FSP_SIGNAL_GPT8_ADTRGB	GPT8 GTADTRB compare match.
FSP_SIGNAL_GPT9_ADTRGA	GPT9 GTADTRA compare match.
FSP_SIGNAL_GPT9_ADTRGB	GPT9 GTADTRB compare match.
FSP_SIGNAL_GPT10_ADTRGA	GPT10 GTADTRA compare match.
FSP_SIGNAL_GPT10_ADTRGB	GPT10 GTADTRB compare match.
FSP_SIGNAL_GPT11_ADTRGA	GPT11 GTADTRA compare match.
FSP_SIGNAL_GPT11_ADTRGB	GPT11 GTADTRB compare match.
FSP_SIGNAL_GPT12_ADTRGA	GPT12 GTADTRA compare match.
FSP_SIGNAL_GPT12_ADTRGB	GPT12 GTADTRB compare match.
FSP_SIGNAL_GPT13_ADTRGA	GPT13 GTADTRA compare match.
FSP_SIGNAL_GPT13_ADTRGB	GPT13 GTADTRB compare match.

bsp_warm_start_event_t

enum bsp_warm_start_event_t

Different warm start entry locations in the BSP.

Enumerator
BSP_WARM_START_RESET	Called almost immediately after reset. No C runtime environment, clocks, or IRQs.
BSP_WARM_START_POST_CLOCK	Called after clock initialization. No C runtime environment or IRQs.
BSP_WARM_START_POST_C	Called after clocks and C runtime environment have been set up.

bsp_delay_units_t

enum bsp_delay_units_t

Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds

Enumerator
BSP_DELAY_UNITS_SECONDS	Requested delay amount is in seconds.
BSP_DELAY_UNITS_MILLISECONDS	Requested delay amount is in milliseconds.
BSP_DELAY_UNITS_MICROSECONDS	Requested delay amount is in microseconds.

bsp_reg_protect_t

enum bsp_reg_protect_t

The different types of registers that can be protected.

Enumerator
BSP_REG_PROTECT_CGC	Enables writing to the registers related to the clock generation circuit.
BSP_REG_PROTECT_LPC_RESET	Enables writing to the registers related to low power consumption and reset.
BSP_REG_PROTECT_GPIO	Enables writing to the registers related to GPIO.
BSP_REG_PROTECT_SYSTEM	Enables writing to the registers related to Non-Safety reg.

bsp_reset_t

enum bsp_reset_t

CPU to be reset target.

Enumerator
BSP_RESET_CR52_0	Software reset for CR52_0.
BSP_RESET_CR52_1	Software reset for CR52_1.
BSP_RESET_CA55_CLUSTER	Software reset for CA55_CLUSTER.
BSP_RESET_CA55_0	Software reset for CA55_0.
BSP_RESET_CA55_1	Software reset for CA55_1.
BSP_RESET_CA55_2	Software reset for CA55_2.
BSP_RESET_CA55_3	Software reset for CA55_3.

bsp_cluster_reset_auto_release_t

enum bsp_cluster_reset_auto_release_t

CA55 cluster reset auto reset release status.

bsp_module_reset_t

enum bsp_module_reset_t

The different types of registers that can control the reset of peripheral modules related to Ethernet.

Enumerator
BSP_MODULE_RESET_XSPI0	Enables writing to the registers related to xSPI Unit 0 reset control.
BSP_MODULE_RESET_XSPI1	Enables writing to the registers related to xSPI Unit 1 reset control.
BSP_MODULE_RESET_GMAC0_PCLKH	Enables writing to the registers related to GMAC (PCLKH clock domain) reset control.
BSP_MODULE_RESET_GMAC0_PCLKM	Enables writing to the registers related to GMAC (PCLKM clock domain) reset control.
BSP_MODULE_RESET_ETHSW	Enables writing to the registers related to ETHSW reset control.
BSP_MODULE_RESET_ESC_BUS	Enables writing to the registers related to ESC (Bus clock domain) reset control.
BSP_MODULE_RESET_ESC_IP	Enables writing to the registers related to ESC (IP clock domain) reset control.
BSP_MODULE_RESET_ESC_ETH_SUBSYSTEM	Enables writing to the registers related to Ethernet subsystem register reset control.
BSP_MODULE_RESET_MII	Enables writing to the registers related to MII converter reset control.
BSP_MODULE_RESET_GMAC1_ACLK	Enables writing to the registers related to GMAC Unit 1 (PCLKAH clock domain) reset control.
BSP_MODULE_RESET_GMAC1_HCLK	Enables writing to the registers related to GMAC Unit 1 (PCLKAM clock domain) reset control.
BSP_MODULE_RESET_GMAC2_ACLK	Enables writing to the registers related to GMAC Unit 2 (PCLKAH clock domain) reset control.
BSP_MODULE_RESET_GMAC2_HCLK	Enables writing to the registers related to GMAC Unit 2 (PCLKAM clock domain) reset control.
BSP_MODULE_RESET_SHOSTIF_MASTER_BUS_CLOCK	Enables writing to the registers related to SHOSTIF (Master bus clock domain) reset control.
BSP_MODULE_RESET_SHOSTIF_SLAVE_BUS_CLOCK	Enables writing to the registers related to SHOSTIF (Slave bus clock domain) reset control.
BSP_MODULE_RESET_SHOSTIF_IP_CLOCK	Enables writing to the registers related to SHOSTIF (IP clock domain) reset control.
BSP_MODULE_RESET_AFMT0	Enables writing to the registers related to AFMT0 reset control.
BSP_MODULE_RESET_HDSL0	Enables writing to the registers related to HDSL0 reset control.
BSP_MODULE_RESET_BISS0	Enables writing to the registers related to BISS0 reset control.
BSP_MODULE_RESET_ENDAT0	Enables writing to the registers related to ENDAT0 reset control.
BSP_MODULE_RESET_AFMT1	Enables writing to the registers related to AFMT1 reset control.
BSP_MODULE_RESET_HDSL1	Enables writing to the registers related to HDSL1 reset control.
BSP_MODULE_RESET_BISS1	Enables writing to the registers related to BISS1 reset control.
BSP_MODULE_RESET_ENDAT1	Enables writing to the registers related to ENDAT1 reset control.
BSP_MODULE_RESET_PCIE	Enables writing to the registers related to PCIE reset control.
BSP_MODULE_RESET_DDRSS_RST_N	Enables writing to the registers related to DDRSS rst_n reset control.
BSP_MODULE_RESET_DDRSS_RST_PWROKLN	Enables writing to the registers related to DDRSS PwrOkln reset control.
BSP_MODULE_RESET_DDRSS_RESET	Enables writing to the registers related to DDRSS Reset reset control.
BSP_MODULE_RESET_DDRSS_AXI0_ARESETN	Enables writing to the registers related to DDRSS axi0_ARESETn reset control.
BSP_MODULE_RESET_DDRSS_AXI1_ARESETN	Enables writing to the registers related to DDRSS axi1_ARESETn reset control.
BSP_MODULE_RESET_DDRSS_AXI2_ARESETN	Enables writing to the registers related to DDRSS axi2_ARESETn reset control.
BSP_MODULE_RESET_DDRSS_AXI3_ARESETN	Enables writing to the registers related to DDRSS axi3_ARESETn reset control.
BSP_MODULE_RESET_DDRSS_AXI4_ARESETN	Enables writing to the registers related to DDRSS axi4_ARESETn reset control.
BSP_MODULE_RESET_DDRSS_MC_PRESETN	Enables writing to the registers related to DDRSS MC_PRESETn reset control.
BSP_MODULE_RESET_DDRSS_PHY_PRESETN	Enables writing to the registers related to DDRSS PHY_PRESETn reset control.

bsp_resource_state_t

enum bsp_resource_state_t

The semaphore resource state shared by CPU0 and CPU1

Enumerator
BSP_RESOURCE_STATE_BEING_USED	Semaphore resource being used.
BSP_RESOURCE_STATE_NOT_BEING_USED	Semaphore resource not being used.

bsp_resource_num_t

enum bsp_resource_num_t

The semaphore resource number shared by CPU0 and CPU1

Enumerator
BSP_RESOURCE_NUM_0	Semaphore resource number 0.
BSP_RESOURCE_NUM_1	Semaphore resource number 1.
BSP_RESOURCE_NUM_2	Semaphore resource number 2.
BSP_RESOURCE_NUM_3	Semaphore resource number 3.
BSP_RESOURCE_NUM_4	Semaphore resource number 4.
BSP_RESOURCE_NUM_5	Semaphore resource number 5.
BSP_RESOURCE_NUM_6	Semaphore resource number 6.
BSP_RESOURCE_NUM_7	Semaphore resource number 7.

bsp_grp_irq_t

enum bsp_grp_irq_t

Which interrupts can have callbacks registered.

Enumerator
BSP_GRP_IRQ_UNSUPPORTED	NMI Group IRQ are not supported.

Function Documentation

R_FSP_VersionGet()

fsp_err_t R_FSP_VersionGet

(

fsp_pack_version_t *const

p_version

)

Get the FSP version based on compile time macros.

Parameters

[out]

p_version

Memory address to return version information to.

Return values

FSP_SUCCESS	Version information stored.
FSP_ERR_ASSERTION	The parameter p_version is NULL.

Default_Handler()

void Default_Handler

(

void

)

Default exception handler.

system_init()

BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void system_init

(

void

)

After boot processing, LSI starts executing here.

SystemInit()

void SystemInit

(

void

)

Initialize the MCU and the runtime environment.

R_BSP_WarmStart()

void R_BSP_WarmStart

(

bsp_warm_start_event_t

event

)

This function is called at various points during the startup process. This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user implemented version. One of the main uses for this function is to call functional safety code during the startup process. To use this function just copy this function into your own code and modify it to meet your needs.

Parameters

[in]

event

Where the code currently is in the start up process

Note

All programs that are executed when a BSP_WARM_START_RESET, or BSP_WARM_START_POST_CLOCK event occurs must be placed in the LOADER section(BTCM for CR52 core, SystemRAM for CA55 core). These events occur before the copy of the application program in the startup code is executed, so the application program is on ROM and cannot be executed at that time. The FSP linker script specifies that the .warm_start section be placed in the LOADER section. Adding a section specification to the definition of a function or variable makes it easier to place it in the LOADER section.

R_BSP_CacheEnableInst()

void R_BSP_CacheEnableInst

(

void

)

Enable instruction caching.

R_BSP_CacheEnableData()

void R_BSP_CacheEnableData

(

void

)

Enable data caching.

R_BSP_CacheEnableMemoryProtect()

void R_BSP_CacheEnableMemoryProtect

(

void

)

Enable memory protect.

R_BSP_CacheDisableInst()

void R_BSP_CacheDisableInst

(

void

)

Disable instruction caching.

R_BSP_CacheDisableData()

void R_BSP_CacheDisableData

(

void

)

Disable data caching.

R_BSP_CacheDisableMemoryProtect()

void R_BSP_CacheDisableMemoryProtect

(

void

)

Disable memory protect.

R_BSP_CacheCleanAll()

void R_BSP_CacheCleanAll

(

void

)

Clean data cache by set/way. Clean means writing the cache data to memory and clear the dirty bits if there is a discrepancy between the cache and memory data.

R_BSP_CacheInvalidateAll()

void R_BSP_CacheInvalidateAll

(

void

)

Invalidate data cache by set/way. Also Invalidate instruction cache.

Invalidate means to delete cache data.

R_BSP_CacheCleanInvalidateAll()

void R_BSP_CacheCleanInvalidateAll

(

void

)

Clean and Invalidate data cache by set/way. Also Invalidate instruction cache.

Clean means writing the cache data to memory and clear the dirty bits if there is a discrepancy between the cache and memory data.

Invalidate means to delete cache data.

R_BSP_CacheCleanRange()

void R_BSP_CacheCleanRange	(	uintptr_t	base_address,
		uintptr_t	length
	)

Clean data cache and Invalidate instruction cache by address.

Clean means writing the cache data to memory and clear the dirty bits if there is a discrepancy between the cache and memory data.

Invalidate means to delete cache data.

Parameters

[in]	base_address	Start address of area you want to Clean.
[in]	length	Size of area you want to Clean.

R_BSP_CacheInvalidateRange()

void R_BSP_CacheInvalidateRange	(	uintptr_t	base_address,
		uintptr_t	length
	)

Invalidate instruction and data cache by address.

Invalidate means to delete cache data.

Parameters

[in]	base_address	Start address of area you want to Invalidate.
[in]	length	Size of area you want to Invalidate.

R_BSP_CacheCleanInvalidateRange()

void R_BSP_CacheCleanInvalidateRange	(	uintptr_t	base_address,
		uintptr_t	length
	)

Clean and Invalidate data cache and Invalidate instruction cache by address.

Clean means writing the cache data to memory and clear the dirty bits if there is a discrepancy between the cache and memory data.

Invalidate means to delete cache data.

Parameters

[in]	base_address	Start address of area you want to Clean and Invalidate.
[in]	length	Size of area you want to Clean and Invalidate.

R_BSP_CacheL3PowerCtrl()

void R_BSP_CacheL3PowerCtrl

(

void

)

Powers on and off the L3 cache way. CA55 only.

R_FSP_CurrentIrqGet()

__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet

(

void

)

Return active interrupt vector number value

Returns

Active interrupt vector number value

R_FSP_SystemClockHzGet()

__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet

(

fsp_priv_clock_t

clock

)

Gets the frequency of a system clock.

Returns

Frequency of requested clock in Hertz.

R_BSP_SoftwareDelay()

void R_BSP_SoftwareDelay	(	uint32_t	delay,
		bsp_delay_units_t	units
	)

Delay for at least the specified duration in units and return.

Parameters

[in]	delay	The number of 'units' to delay.
[in]	units	The 'base' (bsp_delay_units_t) for the units specified. Valid values are: BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS, BSP_DELAY_UNITS_MICROSECONDS. For example: At 200 MHz one cycle takes 1/200 microsecond or 5 nanoseconds. At 800 MHz one cycle takes 1/800 microsecond or 1.25 nanoseconds. Therefore one run through bsp_prv_software_delay_loop() takes: ~ (1.25 * BSP_DELAY_LOOP_CYCLES) or 5 ns. A delay of 2 us therefore requires 2000ns/5ns or 400 loops.

The 'theoretical' maximum delay that may be obtained is determined by a full 32 bit loop count and the system clock rate. @200MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 200000000) = 85 seconds. @800MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 800000000) = 21 seconds.

Note that requests for very large delays will be affected by rounding in the calculations and the actual delay achieved may be slightly longer. @200 MHz, for example, a request for 85 seconds will be closer to 86 seconds.

Note also that if the calculations result in a loop_cnt of zero, the bsp_prv_software_delay_loop() function is not called at all. In this case the requested delay is too small (nanoseconds) to be carried out by the loop itself, and the overhead associated with executing the code to just get to this point has certainly satisfied the requested delay.

Note

R_BSP_SoftwareDelay() obtains the system clock value by reading the SystemCoreClock variable. Therefore, R_BSP_SoftwareDelay() cannot be used until after the SystemCoreClock has been updated. The SystemCoreClock is updated by executing SystemCoreClockUpdate() in startup; users cannot call R_BSP_SoftwareDelay() inside R_BSP_WarmStart(BSP_WARM_START_RESET) and R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK) since they are invoked before SystemCoreClockUpdate() in startup.

This function will delay for at least the specified duration. Due to overhead in calculating the correct number of loops to delay, very small delay values (generally 1-5 microseconds) may be significantly longer than specified. Approximate overhead for this function is as follows:

• CR52: 94-117 cycles

If more accurate microsecond timing must be performed in software it is recommended to use bsp_prv_software_delay_loop() directly. In this case, use BSP_DELAY_LOOP_CYCLES or BSP_DELAY_LOOPS_CALCULATE() to convert a calculated delay cycle count to a number of software delay loops.

Delays may be longer than expected when compiler optimization is turned off.

R_FSP_IsrContextSet()

__STATIC_INLINE void R_FSP_IsrContextSet	(	IRQn_Type const	irq,
		void *	p_context
	)

Sets the ISR context associated with the requested IRQ.

Parameters

[in]	irq	IRQ number (parameter checking must ensure the IRQ number is valid before calling this function.
[in]	p_context	ISR context for IRQ.

R_BSP_IrqClearPending()

__STATIC_INLINE void R_BSP_IrqClearPending

(

IRQn_Type

irq

)

Clear the GIC pending interrupt.

Parameters

[in]

irq

Interrupt for which to clear the Pending bit. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.

R_BSP_IrqPendingGet()

__STATIC_INLINE uint32_t R_BSP_IrqPendingGet

(

IRQn_Type

irq

)

Get the GIC pending interrupt.

Parameters

[in]

irq

Interrupt that gets a pending bit.. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.

Returns

Value indicating the status of the level interrupt.

R_BSP_IrqCfg()

__STATIC_INLINE void R_BSP_IrqCfg	(	IRQn_Type const	irq,
		uint32_t	priority,
		void *	p_context
	)

Sets the interrupt priority and context.

Parameters

[in]	irq	The IRQ number to configure.
[in]	priority	GIC priority of the interrupt
[in]	p_context	The interrupt context is a pointer to data required in the ISR.

R_BSP_IrqEnableNoClear()

__STATIC_INLINE void R_BSP_IrqEnableNoClear

(

IRQn_Type const

irq

)

Enable the IRQ in the GIC (Without clearing the pending bit).

Parameters

[in]

irq

The IRQ number to enable. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.

R_BSP_IrqEnable()

__STATIC_INLINE void R_BSP_IrqEnable

(

IRQn_Type const

irq

)

Enable the IRQ in the GIC (With clearing the pending bit).

Parameters

[in]

irq

The IRQ number to enable. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.

R_BSP_IrqDisable()

__STATIC_INLINE void R_BSP_IrqDisable

(

IRQn_Type const

irq

)

Disables interrupts in the GIC.

Parameters

[in]

irq

The IRQ number to disable in the GIC. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.

R_BSP_IrqCfgEnable()

__STATIC_INLINE void R_BSP_IrqCfgEnable	(	IRQn_Type const	irq,
		uint32_t	priority,
		void *	p_context
	)

Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt.

Parameters

[in]	irq	Interrupt number.
[in]	priority	GIC priority of the interrupt
[in]	p_context	The interrupt context is a pointer to data required in the ISR.

R_FSP_IsrContextGet()

__STATIC_INLINE void* R_FSP_IsrContextGet

(

IRQn_Type const

irq

)

Finds the ISR context associated with the requested IRQ.

Parameters

[in]

irq

IRQ number (parameter checking must ensure the IRQ number is valid before calling this function.

Returns

ISR context for IRQ.

R_BSP_IrqDetectTypeSet()

__STATIC_INLINE void R_BSP_IrqDetectTypeSet	(	IRQn_Type const	irq,
		uint32_t	detect_type
	)

Sets the interrupt detect type.

Parameters

[in]	irq	The IRQ number to configure.
[in]	detect_type	GIC detect type of the interrupt (0 : active-HIGH level, 1 : rising edge-triggerd).

R_BSP_IrqGroupSet()

__STATIC_INLINE void R_BSP_IrqGroupSet	(	IRQn_Type const	irq,
		uint32_t	interrupt_group
	)

Sets the interrupt Group.

Parameters

[in]	irq	The IRQ number to configure.
[in]	interrupt_group	GIC interrupt group number ( 0 : FIQ, 1 : IRQ ).

R_BSP_IrqMaskLevelSet()

__STATIC_INLINE void R_BSP_IrqMaskLevelSet

(

uint32_t

mask_level

)

Sets the interrupt mask level.

Parameters

[in]

mask_level

The interrupt mask level

R_BSP_IrqMaskLevelGet()

__STATIC_INLINE uint32_t R_BSP_IrqMaskLevelGet

(

void

)

Gets the interrupt mask level.

Returns

Value indicating the interrupt mask level.

R_BSP_RegisterProtectEnable()

void R_BSP_RegisterProtectEnable

(

bsp_reg_protect_t

regs_to_protect

)

Enable register protection. Registers that are protected cannot be written to. Register protection is enabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR).

Parameters

[in]

regs_to_protect

Registers which have write protection enabled.

R_BSP_RegisterProtectDisable()

void R_BSP_RegisterProtectDisable

(

bsp_reg_protect_t

regs_to_unprotect

)

Disable register protection. Registers that are protected cannot be written to. Register protection is disabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR).

Parameters

[in]

regs_to_unprotect

Registers which have write protection disabled.

R_BSP_SystemReset()

void R_BSP_SystemReset

(

void

)

Occur the system software reset.

R_BSP_CPUReset()

void R_BSP_CPUReset

(

bsp_reset_t

cpu

)

Occur the CPU software reset.

Parameters

[in]

cpu

to be reset state.

Note

With Cortex-A55, you cannot use resets that are not automatically released when a software reset is executed.

R_BSP_CPUResetAutoRelease()

void R_BSP_CPUResetAutoRelease

(

bsp_reset_t

cpu

)

Occur the CPU software reset. When using this function, the CPU reset state is automatically released after an elapsed time corresponding to the setting value in SCKCR2.DIVSELSUB bit.

Parameters

[in]

cpu

to be reset state.

R_BSP_CPUResetRelease()

void R_BSP_CPUResetRelease

(

bsp_reset_t

cpu

)

Release the CPU reset state.

Parameters

[in]

cpu

to be release reset state.

R_BSP_ModuleResetEnable()

void R_BSP_ModuleResetEnable

(

bsp_module_reset_t

module_to_enable

)

Enable module reset state.

Parameters

[in]

module_to_enable

Modules to enable module reset state.

R_BSP_ModuleResetDisable()

void R_BSP_ModuleResetDisable

(

bsp_module_reset_t

module_to_disable

)

Disable module reset state.

Parameters

[in]

module_to_disable

Modules to disable module reset state.

Note

After reset release is performed by the module control register, a dummy read is performed to allow access to other than the RTC and LCDC. This is done several times according to the RZ microprocessor manual. However, the dummy read count for the RTC and LCDC may not be met depending on the device used. In that case, please perform additional dummy read processing after API execution. For example, in the case of RZT2H, 300 dummy reads are required for RTC and 100 dummy reads are required for LCDC.

__sinf()

BSP_TFU_INLINE float __sinf

(

float

angle

)

Calculates sine of the given angle.

Parameters

[in]

angle

The value of an angle in radian.

Return values

Sine	value of an angle.

__cosf()

BSP_TFU_INLINE float __cosf

(

float

angle

)

Calculates cosine of the given angle.

Parameters

[in]

angle

The value of an angle in radian.

Return values

Cosine

value of an angle.

__sincosf()

BSP_TFU_INLINE void __sincosf	(	float	angle,
		float *	sin,
		float *	cos
	)

Calculates sine and cosine of the given angle.

Parameters

[in]	angle	The value of an angle in radian.
[out]	sin	Sine value of an angle.
[out]	cos	Cosine value of an angle.

__atan2f()

BSP_TFU_INLINE float __atan2f	(	float	y_cord,
		float	x_cord
	)

Calculates the arc tangent based on given X-cordinate and Y-cordinate values.

Parameters

[in]	y_cord	Y-Axis cordinate value.
[in]	x_cord	X-Axis cordinate value.

Return values

Arc	tangent for given values.

__hypotf()

BSP_TFU_INLINE float __hypotf	(	float	x_cord,
		float	y_cord
	)

Calculates the hypotenuse based on given X-cordinate and Y-cordinate values.

Parameters

[in]	y_cord	Y-cordinate value.
[in]	x_cord	X-cordinate value.

Return values

Hypotenuse

for given values.

__atan2hypotf()

BSP_TFU_INLINE void __atan2hypotf	(	float	y_cord,
		float	x_cord,
		float *	atan2,
		float *	hypot
	)

Calculates the arc tangent and hypotenuse based on given X-cordinate and Y-cordinate values.

Parameters

[in]	y_cord	Y-cordinate value.
[in]	x_cord	X-cordinate value.
[out]	atan2	Arc tangent for given values.
[out]	hypot	Hypotenuse for given values.

__sinfx()

BSP_TFU_INLINE uint32_t __sinfx

(

uint32_t

angle

)

Calculates sine of the given angle.

Parameters

[in]

angle

The value of an angle.

Return values

Sine	value of an angle.

__cosfx()

BSP_TFU_INLINE uint32_t __cosfx

(

uint32_t

angle

)

Calculates cosine of the given angle.

Parameters

[in]

angle

The value of an angle in radian.

Return values

Cosine

value of an angle.

__sincosfx()

BSP_TFU_INLINE void __sincosfx	(	uint32_t	angle,
		uint32_t *	sin,
		uint32_t *	cos
	)

Calculates sine and cosine of the given angle.

Parameters

[in]	angle	The value of an angle.
[out]	sin	Sine value of an angle.
[out]	cos	Cosine value of an angle.

__atan2fx()

BSP_TFU_INLINE uint32_t __atan2fx	(	uint32_t	y_cord,
		uint32_t	x_cord
	)

Calculates the arc tangent based on given X-cordinate and Y-cordinate values.

Parameters

[in]	y_cord	Y-Axis cordinate value.
[in]	x_cord	X-Axis cordinate value.

Return values

Arc	tangent for given values.

__hypotfx()

BSP_TFU_INLINE int32_t __hypotfx	(	uint32_t	x_cord,
		uint32_t	y_cord
	)

Calculates the hypotenuse based on given X-cordinate and Y-cordinate values.

Parameters

[in]	y_cord	Y-cordinate value.
[in]	x_cord	X-cordinate value.

Return values

Hypotenuse

for given values.

__atan2hypotfx()

BSP_TFU_INLINE void __atan2hypotfx	(	uint32_t	y_cord,
		uint32_t	x_cord,
		uint32_t *	atan2,
		int32_t *	hypot
	)

Calculates the arc tangent and hypotenuse based on given X-cordinate and Y-cordinate values.

Parameters

[in]	y_cord	Y-cordinate value.
[in]	x_cord	X-cordinate value.
[out]	atan2	Arc tangent for given values.
[out]	hypot	Hypotenuse for given values.

r_bsp_software_delay_loop()

BSP_ATTRIBUTE_STACKLESS void r_bsp_software_delay_loop

(

__attribute__((unused)) uint32_t

loop_cnt

)

This assembly language routine takes roughly 4 cycles per loop. 2 additional cycles occur when the loop exits. The 'naked' attribute indicates that the specified function does not need prologue/epilogue sequences generated by the compiler.

Parameters

[in]

loop_cnt

The number of loops to iterate.

R_BSP_GroupIrqWrite()

fsp_err_t R_BSP_GroupIrqWrite	(	bsp_grp_irq_t	irq,
		void(*)(bsp_grp_irq_t irq)	p_callback
	)

Register a callback function for supported interrupts. If NULL is passed for the callback argument then any previously registered callbacks are unregistered.

Parameters

[in]	irq	Interrupt for which to register a callback.
[in]	p_callback	Pointer to function to call when interrupt occurs.

Return values

FSP_ERR_UNSUPPORTED

NMI Group IRQ are not supported in RZ/A3UL.

R_BSP_GICD_SetCtlr()

void R_BSP_GICD_SetCtlr

(

bsp_gicd_ctlr_bit_t

bit

)

Set GICD_CTLR Register.

Parameters

[in]

bit

Set value of GICD_CTRL register bit.

R_BSP_GICD_GetCtlr()

uint32_t R_BSP_GICD_GetCtlr

(

void

)

Get value of GICD_CTLR Register.

Return values

GICD_CTLR

register value.

R_BSP_GICD_Enable()

void R_BSP_GICD_Enable

(

bsp_gicd_ctlr_bit_t

bit

)

Set the values specified in the argument to EnableGrp0 bit, EnableGrp1NS bit, and EnableGrp1S bit of GICD_CTLR, to enable interrupts for any interrupt group.

Parameters

[in]

bit

Set value of GICD_CTRL register bit.

R_BSP_GICD_Disable()

void R_BSP_GICD_Disable

(

bsp_gicd_ctlr_bit_t

bit

)

Set the values specified in the argument to EnableGrp0 bit, EnableGrp1NS bit, and EnableGrp1S bit of GICD_CTLR, to disable interrupts for any interrupt group.

Parameters

[in]

bit

Clear value of GICD_CTRL register bit.

R_BSP_GICD_AffinityRouteEnable()

void R_BSP_GICD_AffinityRouteEnable

(

bsp_gicd_ctlr_bit_t

bit

)

Set the values specified in the argument to ARE_S bit and ARE_NS bit of GICD_CTLR, to enable Affinity Routing for Secure state and/or Non-secure state.

Parameters

[in]

bit

Set value of GICD_CTRL register bit.

R_BSP_GICD_SpiEnable()

void R_BSP_GICD_SpiEnable

(

IRQn_Type

irq

)

Enable interrupt forwarding to the CPU interface by set the bit of GICD_ISENABLERn to 1 corresponding to the ID specified in the argument.

Parameters

[in]

irq

Interrupt number ID.

R_BSP_GICD_SpiDisable()

void R_BSP_GICD_SpiDisable

(

IRQn_Type

irq

)

Disable interrupt forwarding to the CPU interface by set the bit of GICD_ICENABLERn to 1 corresponding to the ID specified in the argument.

Parameters

[in]

irq

Interrupt number ID.

R_BSP_GICD_SetSpiPriority()

void R_BSP_GICD_SetSpiPriority	(	IRQn_Type	irq,
		uint32_t	priority
	)

Sets the value specified for GICD_IPRIORITYRn to set the interrupt priority for the specified ID.

Parameters

[in]	irq	Interrupt number ID.
[in]	priority	Interrupt Priority.

R_BSP_GICD_GetSpiPriority()

uint32_t R_BSP_GICD_GetSpiPriority

(

IRQn_Type

irq

)

Gets the interrupt priority for the specified ID by reads the value of GICD_IPRIORITYRn.

Parameters

[in]

irq

Interrupt number ID.

Return values

interrupt

priority.

R_BSP_GICD_SetSpiRoute()

void R_BSP_GICD_SetSpiRoute	(	IRQn_Type	irq,
		uint64_t	route,
		bsp_gicd_irouter_route_t	mode
	)

Set affinity routing information that is SPI Affinity level and routing mode to GICD_IROUTERn.

Parameters

[in]	irq	Interrupt number ID.
[in]	route	Affinity route settings. Since it will be used as it is as the setting value of the Affinity level, write the value of Aff0 from bit 7 to bit 0, the value of Aff1 from bit 15 to bit 8, the value of Aff2 from bit 23 to bit 16, and the value of Aff3 from bit 39 to bit 32.
[in]	mode	Mode of routing

R_BSP_GICD_GetSpiRoute()

uint64_t R_BSP_GICD_GetSpiRoute

(

IRQn_Type

irq

)

Get affinity routing information that is SPI Affinity level and routing mode by reads GICD_IROUTERn.

Parameters

[in]

irq

Interrupt number ID.

Return values

interrupt

routing information. Aff0 is stored in bit 7 to bit 0, Aff1 in bit 15 to bit 8, Aff2 in bit 23 to bit 16, Routing mode in bit 31, and Aff3 in bit 39 to bit 32.

R_BSP_GICD_SetSpiSense()

void R_BSP_GICD_SetSpiSense	(	IRQn_Type	irq,
		bsp_gicd_icfgr_sense_t	sense
	)

Set interrupt as edge-triggered or level-sensitive.

Parameters

[in]	irq	Interrupt number ID.
[in]	sense	Interrupt trigger sense.

R_BSP_GICD_GetSpiSense()

uint32_t R_BSP_GICD_GetSpiSense

(

IRQn_Type

irq

)

Get interrupt trigger information.

Parameters

[in]

irq

Interrupt number ID.

Return values

Value

that means interrupt trigger sense, which is edge-triggered or level-sensitive.

R_BSP_GICD_SetSpiPending()

void R_BSP_GICD_SetSpiPending

(

IRQn_Type

irq

)

Sets the specified interrupt to the pending state by write to GICD_ISPENDRn.

Parameters

[in]

irq

Interrupt number ID.

R_BSP_GICD_GetSpiPending()

uint32_t R_BSP_GICD_GetSpiPending

(

IRQn_Type

irq

)

Sets the specified interrupt to the pending state by write to GICD_ISPENDRn.

Parameters

[in]

irq

Interrupt number ID.

Return values

Information

of SPI pending.

R_BSP_GICD_SetSpiClearPending()

void R_BSP_GICD_SetSpiClearPending

(

IRQn_Type

irq

)

Clear the specified interrupt to the pending state by write to GICD_ICPENDRn.

Parameters

[in]

irq

Interrupt number ID.

R_BSP_GICD_GetSpiClearPending()

uint32_t R_BSP_GICD_GetSpiClearPending

(

IRQn_Type

irq

)

Gets information about whether the specified interrupt is pending state by reading the value of GICD_ICPENDRn.

Parameters

[in]

irq

Interrupt number ID.

Return values

Information

of SPI pending.

R_BSP_GICD_SetSpiSecurity()

void R_BSP_GICD_SetSpiSecurity	(	IRQn_Type	irq,
		bsp_gic_igroupr_secure_t	group
	)

Set SPI security group. The combination of the modifier bit of GICD_IGRPMODR and the status bit of GICD_IGROUPR determines whether the security group is Secure Group 0, Non-Secure Group 1, or Secure Group 1.

Parameters

[in]	irq	Interrupt number ID.
[in]	group	Security group.

R_BSP_GICD_SetSpiSecurityLine()

void R_BSP_GICD_SetSpiSecurityLine	(	uint32_t	line,
		bsp_gic_igroupr_secure_t	group
	)

Sets SPI security group with each 32 interrupts (each line). The combination of the modifier bit of GICD_IGRPMODR and the status bit of GICD_IGROUPR determines whether the security group is Secure Group 0, Non-Secure Group 1, or Secure Group 1.

Parameters

[in]	line	Line of GICD_IGRPMODRn register. Line is the quotient of the interrupt ID divided by 32. For example, an interrupt with IDs 32 to 63 corresponds to line 1.
[in]	group	Security group.

R_BSP_GICD_SetSpiSecurityAll()

void R_BSP_GICD_SetSpiSecurityAll

(

bsp_gic_igroupr_secure_t

group

)

Set SPI security group for all GICD_IGRPMODRn register. The combination of the modifier bit of GICD_IGRPMODR and the status bit of GICD_IGROUPR determines whether the security group is Secure Group 0, Non-Secure Group 1, or Secure Group 1.

Parameters

[in]

group

Security group.

R_BSP_GICD_SetSpiClass()

void R_BSP_GICD_SetSpiClass	(	IRQn_Type	irq,
		bsp_gicd_iclar_class_t	class_group
	)

Sets whether the Class0 or Class1 class is the target of the SPI.

Parameters

[in]	irq	Interrupt number ID.
[in]	class_group	Interrupt class.

Note

R_BSP_GICR_SetClass can be set whether each interrupt is Class0 or Class1.

R_BSP_GICR_Enable()

void R_BSP_GICR_Enable

(

void

)

Enables Redistributor and configue power management by access GICR_PWRR and GICR_WAKER. This BSP sets GICR_WAKER.ProcessorSleep to 0, so wake_request signal wake-up the core when the core is powered off is disabled.

R_BSP_GICR_SgiPpiEnable()

void R_BSP_GICR_SgiPpiEnable

(

IRQn_Type

irq

)

Enable SGI or PPI forwarding to the CPU interface by set the bit of GICR_ISENABLER0 to 1 corresponding to the ID specified in the argument.

Parameters

[in]

irq

Interrupt number ID.

R_BSP_GICR_SgiPpiDisable()

void R_BSP_GICR_SgiPpiDisable

(

IRQn_Type

irq

)

Disable SGI of PPI forwarding to the CPU interface by set the bit of GICR_ICENABLER0 to 1 corresponding to the ID specified in the argument.

Parameters

[in]

irq

Interrupt number ID.

R_BSP_GICR_SetSgiPpiPriority()

void R_BSP_GICR_SetSgiPpiPriority	(	IRQn_Type	irq,
		uint32_t	priority
	)

Sets the value specified for GICR_IPRIORITYRn to set the interrupt priority for the specified ID.

Parameters

[in]	irq	Interrupt number ID.
[in]	priority	Interrupt Priority.

R_BSP_GICR_GetSgiPpiPriority()

uint32_t R_BSP_GICR_GetSgiPpiPriority

(

IRQn_Type

irq

)

Gets the interrupt priority for the specified ID by reads the value of GICR_IPRIORITYRn.

Parameters

[in]

irq

Interrupt number ID.

Return values

interrupt

priority.

R_BSP_GICR_SetSgiPpiSense()

void R_BSP_GICR_SetSgiPpiSense	(	IRQn_Type	irq,
		bsp_gicd_icfgr_sense_t	sense
	)

Set interrupt as edge-triggered or level-sensitive.

Parameters

[in]	irq	Interrupt number ID.
[in]	sense	Interrupt trigger sense.

R_BSP_GICR_GetSgiPpiSense()

uint32_t R_BSP_GICR_GetSgiPpiSense

(

IRQn_Type

irq

)

Get interrupt trigger information.

Parameters

[in]

irq

Interrupt number ID.

Return values

Value

that means interrupt trigger sense, which is edge-triggered or level-sensitive.

R_BSP_GICR_SetSgiPpiPending()

void R_BSP_GICR_SetSgiPpiPending

(

IRQn_Type

irq

)

Sets the specified interrupt to the pending state by write to GICR_ISPENDR0.

Parameters

[in]

irq

Interrupt number ID.

R_BSP_GICR_GetSgiPpiPending()

uint32_t R_BSP_GICR_GetSgiPpiPending

(

IRQn_Type

irq

)

Gets information about whether the specified interrupt is pending state by reading the value of GICR_ISPENDR0.

Parameters

[in]

irq

Interrupt number ID.

Return values

Information

of SGI or PPI pending.

R_BSP_GICR_SetSgiPpiClearPending()

void R_BSP_GICR_SetSgiPpiClearPending

(

IRQn_Type

irq

)

Clear the specified interrupt to the pending state by write to GICR_ICPENDR0.

Parameters

[in]

irq

Interrupt number ID.

R_BSP_GICR_GetSgiPpiClearPending()

uint32_t R_BSP_GICR_GetSgiPpiClearPending

(

IRQn_Type

irq

)

Gets information about whether the specified interrupt is pending state by reading the value of GICR_ICPENDR0.

Parameters

[in]

irq

Interrupt number ID.

Return values

Information

of SGI or PPI pending.

R_BSP_GICR_SetSgiPpiSecurity()

void R_BSP_GICR_SetSgiPpiSecurity	(	IRQn_Type	irq,
		bsp_gic_igroupr_secure_t	group
	)

Set SGI and PPI security group. The combination of the modifier bit of GICR_IGRPMODR0 and the status bit of GICR_IGROUPR determines whether the security group is Secure Group 0, Non-Secure Group 1, or Secure Group 1.

Parameters

[in]	irq	Interrupt number ID.
[in]	group	Security group.

R_BSP_GICR_SetSgiPpiSecurityLine()

void R_BSP_GICR_SetSgiPpiSecurityLine

(

bsp_gic_igroupr_secure_t

group

)

Sets security group for all SGI and PPI. The combination of the modifier bit of GICR_IGRPMODR0 and the status bit of GICR_IGROUPR0 determines whether the security group is Secure Group 0, Non-Secure Group 1, or Secure Group 1.

Parameters

[in]

group

Security group.

R_BSP_GICR_SetClass()

void R_BSP_GICR_SetClass

(

bsp_gicd_iclar_class_t

class_group

)

Sets the interrupt class to either Class0 or Class1.

Parameters

[in]

class_group

Interrupt class group.

R_BSP_GICR_GetRoute()

uint32_t R_BSP_GICR_GetRoute

(

void

)

Get routing information (Affinity level value) by reading bit[63:32] of GICR_TYPER.

Return values

value

interrupt routing information. Aff3 is stored from bit 31 to bit 24, Aff2 from bit 23 to bit 16, Aff1 from bit15 to 8, and Aff0 from bit 7 to 0.

R_BSP_GICC_SetMaskLevel()

void R_BSP_GICC_SetMaskLevel

(

uint64_t

mask_level

)

Set interrupt mask level to Interrupt Priority Mask Register.

Parameters

[in]

mask_level

Mask level.

R_BSP_GICC_GetMaskLevel()

uint64_t R_BSP_GICC_GetMaskLevel

(

void

)

Get interrupt mask level information from Interrupt Priority Mask Register.

Return values

Information

of mask level.

R_BSP_GICC_SetEoiGrp0()

void R_BSP_GICC_SetEoiGrp0

(

IRQn_Type

irq

)

Set end of interrupt to End Of Interrupt Register 0 for Group 0.

Parameters

[in]

irq

Interrupt number ID.

R_BSP_GICC_SetEoiGrp1()

void R_BSP_GICC_SetEoiGrp1

(

IRQn_Type

irq

)

Set end of interrupt to End Of Interrupt Register 1 for Group 1.

Parameters

[in]

irq

Interrupt number ID.

R_BSP_GICC_Get_IntIdGrp0()

uint32_t R_BSP_GICC_Get_IntIdGrp0

(

void

)

Get interrupt ID being asserted from Group 0 by reading Interrupt Acknowledge Register 0.

Return values

Interrupt

ID number.

R_BSP_GICC_Get_IntIdGrp1()

uint32_t R_BSP_GICC_Get_IntIdGrp1

(

void

)

Get interrupt ID being asserted from Group 1 by reading Interrupt Acknowledge Register 1.

Return values

Interrupt

ID number.

R_BSP_MmuVatoPa()

fsp_err_t R_BSP_MmuVatoPa	(	uint64_t	vaddress,
		uint64_t *	p_paddress
	)

Convert virtual address into physical address.

Parameters

[in]	vaddress	Virtual address to convert.
[out]	p_paddress	Pointer to store physical address.

Return values

FSP_SUCCESS	Successful
FSP_ERR_INVALID_ADDRESS	Virtual address is invalid address.

R_BSP_MmuPatoVa()

fsp_err_t R_BSP_MmuPatoVa	(	uint64_t	paddress,
		uint64_t *	p_vaddress,
		bsp_mmu_conversion_flag_t	cache_flag
	)

Convert physical address into virtual address.

Parameters

[in]	paddress	Physical address to convert.
[out]	p_vaddress	Pointer to store virtual address.
[in]	cache_flag	Cache flag to select VA.

Return values

FSP_SUCCESS	Successful
FSP_ERR_INVALID_ADDRESS	Physical address is invalid address.

Variable Documentation

SystemCoreClock

uint32_t SystemCoreClock

System Clock Frequency (Core Clock)