Clock Generation Circuit (r_cgc)

Functions
fsp_err_t	R_CGC_Open (cgc_ctrl_t *const p_ctrl, cgc_cfg_t const *const p_cfg)
fsp_err_t	R_CGC_ClocksCfg (cgc_ctrl_t *const p_ctrl, cgc_clocks_cfg_t const *const p_clock_cfg)
fsp_err_t	R_CGC_ClockStart (cgc_ctrl_t *const p_ctrl, cgc_clock_t clock_source, cgc_pll_cfg_t const *const p_pll_cfg)
fsp_err_t	R_CGC_ClockStop (cgc_ctrl_t *const p_ctrl, cgc_clock_t clock_source)
fsp_err_t	R_CGC_ClockCheck (cgc_ctrl_t *const p_ctrl, cgc_clock_t clock_source)
fsp_err_t	R_CGC_SystemClockSet (cgc_ctrl_t *const p_ctrl, cgc_clock_t clock_source, cgc_divider_cfg_t const *const p_divider_cfg)
fsp_err_t	R_CGC_SystemClockGet (cgc_ctrl_t *const p_ctrl, cgc_clock_t *const p_clock_source, cgc_divider_cfg_t *const p_divider_cfg)
fsp_err_t	R_CGC_OscStopDetectEnable (cgc_ctrl_t *const p_ctrl)
fsp_err_t	R_CGC_OscStopDetectDisable (cgc_ctrl_t *const p_ctrl)
fsp_err_t	R_CGC_OscStopStatusClear (cgc_ctrl_t *const p_ctrl)
fsp_err_t	R_CGC_CallbackSet (cgc_ctrl_t *const p_ctrl, void(*p_callback)(cgc_callback_args_t *), void const *const p_context, cgc_callback_args_t *const p_callback_memory)
fsp_err_t	R_CGC_Close (cgc_ctrl_t *const p_ctrl)

Detailed Description

Driver for the CGC peripheral on RZ microprocessor. This module implements the CGC Interface.

Note

This module is not required for the initial clock configuration. Initial clock settings are configurable on the Clocks tab of the FSP Configuration editor. The initial clock settings are applied by the BSP during the startup process before main.

Overview

Features

The CGC module supports runtime modifications of clock settings. Key features include the following:

• Supports changing dividers for the internal clocks (provided they are supported on the device)
  • Supports changing the clock provided to xSPIn (XSPI_CLKn)
  • Supports changing the external bus clock (CKIO) and the clock supplied to BSC
  • Supports changing the clock supplied to CANFD (PCLKCAN)
  • Supports changing the Ethernet PHY reference clock (PLL1 divider clock or Main clock oscillator)
  • Supports changing SCI asynchronous serial clock (PCLKSCIn)
  • Supports changing SCIE asynchronous serial clock (PCLKSCIEn)
  • Supports changing SPI asynchronous serial clock (PCLKSPIn)
  • Supports changing the clock provided to LCDC (LCDC_clkd)
  • Supports changing the clock provided to ENCOUT (PCLKENCO)
  • Supports changing the frequency of the clock provided to CPU core
  • Supports changing the base clock frequency for peripheral clocks
• Supports changing the standby setting of PLL.
• Supports starting or stopping the low-speed on-chip oscillator (LOCO).
• When the system core clock frequency changes, the following things are updated:
  • The CMSIS standard global variable SystemCoreClock is updated to reflect the new clock frequency.
• Supports changing dividers for the internal clocks

Internal Clocks for RZ/T2M and RZ/T2L

The RZ microprocessor have multiple internal clocks. Each clock domain has its own divider that can be updated in R_CGC_SystemClockSet().

The internal clocks include:

• CPUnCLK: Core clock used for CR52 CPU0/1 core
• ICLK: Clock used for DMAC, ICU, CPU AXIM, ENCIF and BSC
• PCLKH/PCLKM/PCLKL/PCLKADC/PCLKGPTL: Peripheral clocks, refer to the table "Specifications of Clock Generation Circuit (Internal Clock)" in the hardware manual to see which peripherals are controlled by which clocks.
• PCLKCAN: Peripheral module clock for CANFD
• BSC_CLK/CKIO: External bus clock
• XSPI_CLKn: xSPIn serial clock
• ETHn_REFCLK: Reference clock to the external Ethernet PHY
• PCLKSPIn: Peripheral module clock for SPIn (Asynchronous serial clock)
• PCLKSCIn: Peripheral module clock for SCIn (Asynchronous serial clock)

Warning

If CPU0CLK is used at 800MHz or 600MHz, MDW setting must be 1 (ATCM 1-wait state).

Maximum XSPI_CLKn clock frequency is 75 MHz at 3.3 V.

Internal Clocks for RZ/T2H

The RZ microprocessor have multiple internal clocks. Each clock domain has its own divider that can be updated in R_CGC_SystemClockSet().

The internal clocks include:

• CPUnCLK: Core clock used for CR52 CPU0/1 core
• CA55CnCLK: Core clock used for CA55 CORE0 to 3
• CA55SCLK: CA55 DSU clock
• PCLKCAN: Peripheral module clock for CANFD
• BSC_CLK/CKIO: External bus clock
• XSPI_CLKn: xSPIn serial clock
• ETHn_REFCLK: Reference clock to the external Ethernet PHY
• PCLKSPIn: Peripheral module clock for SPIn (Asynchronous serial clock)
• PCLKSCIn: Peripheral module clock for SCIn (Asynchronous serial clock)
• PCLKSCIEn: Peripheral module clock for SCIEn (Asynchronous serial clock)
• LCDC_clkd: LCDC clock
• PCLKENCO: Peripheral module clock for ENCOUT

Warning

If CPUnCLK is used at 1000MHz, MDW setting must be 1 (ATCM 1-wait state).

Configuration

Note

The initial clock settings are configurable on the Clocks tab of the FSP Configuration editor.

The default stabilization times are determined based on development boards provided by Renesas, but are generally valid for most designs. Depending on the target board hardware configuration and requirements these values may need to be adjusted for reliability or startup speed.

Build Time Configurations for r_cgc

The following build time configurations are defined in fsp_cfg/r_cgc_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.

Configurations for System > Clock Generation Circuit (r_cgc)

This module can be added to the Stacks tab via New Stack > System > Clock Generation Circuit (r_cgc).

Configuration	Options	Default	Description
Name	Name must be a valid C symbol	g_cgc0	Module name.

Clock Configuration

This module is used to configure the system clocks. There are no module specific clock configurations required to use it.

Usage Notes

Starting or Stopping the low-speed on-chip oscillator (LOCO).

Warning

Starting or Stopping the low-speed on-chip oscillator (LOCO) when using CLMA are subject to constraints described in the footnote of the section "LOCOCR: Low-Speed On-Chip Oscillator Control Register" in the hardware manual.

Examples

Basic Example for RZ/T2M and RZ/T2L

This is a basic example of minimal use of the CGC in an application for RZ/T2M and RZ/T2L.

void cgc_basic_example (void)
{
    fsp_err_t err = FSP_SUCCESS;


    /* Initializes the CGC module. */
    err = R_CGC_Open(&g_cgc0_ctrl, &g_cgc0_cfg);

    /* Handle any errors. This function should be defined by the user. */
    handle_error(err);



    /* Set divisors for CPU0  (and CPU1) clock to run at maximum frequency at 800 MHz.
     * Clock settings other than CPU are not intended to be changed, so set the default values. */
    cgc_divider_cfg_t dividers =
    {
        .sckcr_b.fselxspi0      = CGC_FSEL_XSPI_CLOCK_DIV_64,
        .sckcr_b.divselxspi0    = CGC_DIVSEL_XSPI_CLOCK_DIV_3,
        .sckcr_b.fselxspi1      = CGC_FSEL_XSPI_CLOCK_DIV_64,
        .sckcr_b.divselxspi1    = CGC_DIVSEL_XSPI_CLOCK_DIV_3,
        .sckcr_b.ckio_div       = CGC_CLOCK_OUT_CLOCK_DIV_4,
        .sckcr_b.fselcanfd_div  = CGC_CANFD_CLOCK_DIV_20,
        .sckcr_b.phy_sel        = CGC_PHY_CLOCK_MAIN_OSC,
        .sckcr_b.spi0_async_sel = CGC_SPI_ASYNC_CLOCK_96MHZ,
        .sckcr_b.spi1_async_sel = CGC_SPI_ASYNC_CLOCK_96MHZ,
        .sckcr_b.spi2_async_sel = CGC_SPI_ASYNC_CLOCK_96MHZ,
        .sckcr_b.sci0_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ,
        .sckcr_b.sci1_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ,
        .sckcr_b.sci2_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ,
        .sckcr_b.sci3_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ,
        .sckcr_b.sci4_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ,

        .sckcr2_b.fsel0cr52      = CGC_CPU_CLOCK_DIV_1,
 #if 2 == BSP_FEATURE_BSP_CR52_CORE_NUM
        .sckcr2_b.fsel1cr52      = CGC_CPU_CLOCK_DIV_1,
 #endif
        .sckcr2_b.div_sub_sel    = CGC_BASECLOCK_DIV_3,
        .sckcr2_b.spi3_async_sel = CGC_SPI_ASYNC_CLOCK_96MHZ,
        .sckcr2_b.sci5_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ,
    };

    /* Apply divisors to CPU0 clock. */
    err = R_CGC_SystemClockSet(&g_cgc0_ctrl, CGC_CLOCK_PLL0, &dividers);
    handle_error(err);

}

Basic Example for RZ/T2H

This is a basic example of minimal use of the CGC in an application for RZ/T2H.

void cgc_basic_example_t2h (void)
{
    fsp_err_t err = FSP_SUCCESS;


    /* Initializes the CGC module. */
    err = R_CGC_Open(&g_cgc0_ctrl, &g_cgc0_cfg);

    /* Handle any errors. This function should be defined by the user. */
    handle_error(err);



    /* Set divisors for CPU0  (and CPU1) clock to run at maximum frequency at 800 MHz.
     * Clock settings other than CPU are not intended to be changed, so set the default values. */
    cgc_divider_cfg_t dividers =
    {
        .sckcr_b.fselxspi0     = CGC_FSEL_XSPI_CLOCK_DIV_64,
        .sckcr_b.divselxspi0   = CGC_DIVSEL_XSPI_CLOCK_DIV_3,
        .sckcr_b.fselxspi1     = CGC_FSEL_XSPI_CLOCK_DIV_64,
        .sckcr_b.divselxspi1   = CGC_DIVSEL_XSPI_CLOCK_DIV_3,
        .sckcr_b.ckio_div      = CGC_CLOCK_OUT_CLOCK_DIV_4,
        .sckcr_b.fselcanfd_div = CGC_CANFD_CLOCK_DIV_20,
        .sckcr_b.phy_sel       = CGC_PHY_CLOCK_MAIN_OSC,

        .sckcr2_b.cr52cpu0       = CGC_CPU_CLOCK_DIV_1,
        .sckcr2_b.cr52cpu1       = CGC_CPU_CLOCK_DIV_1,
        .sckcr2_b.ca55core0      = CGC_CPU_CLOCK_DIV_1,
        .sckcr2_b.ca55core1      = CGC_CPU_CLOCK_DIV_1,
        .sckcr2_b.ca55core2      = CGC_CPU_CLOCK_DIV_1,
        .sckcr2_b.ca55core3      = CGC_CPU_CLOCK_DIV_1,
        .sckcr2_b.ca55sclk       = CGC_CPU_CLOCK_DIV_1,
        .sckcr2_b.spi3_async_sel = CGC_SPI_ASYNC_CLOCK_96MHZ,
        .sckcr2_b.sci5_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ,

        .sckcr3_b.spi0_async_sel = CGC_SPI_ASYNC_CLOCK_96MHZ,
        .sckcr3_b.spi1_async_sel = CGC_SPI_ASYNC_CLOCK_96MHZ,
        .sckcr3_b.spi2_async_sel = CGC_SPI_ASYNC_CLOCK_96MHZ,
        .sckcr3_b.sci0_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ,
        .sckcr3_b.sci1_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ,
        .sckcr3_b.sci2_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ,
        .sckcr3_b.sci3_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ,
        .sckcr3_b.sci4_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ,
        .sckcr3_b.lcdc_div_sel   = CGC_LCDC_DIV_2,

        .sckcr4_b.scie0_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ,
        .sckcr4_b.scie1_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ,
        .sckcr4_b.scie2_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ,
        .sckcr4_b.scie3_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ,
        .sckcr4_b.scie4_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ,
        .sckcr4_b.scie5_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ,
        .sckcr4_b.scie6_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ,
        .sckcr4_b.scie7_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ,
        .sckcr4_b.scie8_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ,
        .sckcr4_b.scie9_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ,
        .sckcr4_b.scie10_async_sel = CGC_SCIE_ASYNC_CLOCK_96MHZ,
        .sckcr4_b.scie11_async_sel = CGC_SCIE_ASYNC_CLOCK_96MHZ,
        .sckcr4_b.encoutclk        = CGC_ENCOUT_CLOCK_20MHZ,
    };

    /* Apply divisors to CPU0 clock. */
    err = R_CGC_SystemClockSet(&g_cgc0_ctrl, CGC_CLOCK_PLL0, &dividers);
    handle_error(err);

}

Configuring Multiple Clocks for RZ/T2M and RZ/T2L

This example demonstrates configuring multiple clocks in a single function call using R_CGC_ClocksCfg() for RZ/T2M and RZ/T2L.

void cgc_clocks_cfg_example (void)
{
    fsp_err_t err = FSP_SUCCESS;

    /* Initializes the CGC module. */
    err = R_CGC_Open(&g_cgc0_ctrl, &g_cgc0_cfg);

    /* Handle any errors. This function should be defined by the user. */
    handle_error(err);


    /* Set divisors for CPU0 (and CPU1) clock to run at minimum frequency at 150 MHz. */
    cgc_clocks_cfg_t clocks_cfg;

    clocks_cfg.divider_cfg.sckcr_b.fselxspi0      = CGC_FSEL_XSPI_CLOCK_DIV_64;
    clocks_cfg.divider_cfg.sckcr_b.divselxspi0    = CGC_DIVSEL_XSPI_CLOCK_DIV_3;
    clocks_cfg.divider_cfg.sckcr_b.fselxspi1      = CGC_FSEL_XSPI_CLOCK_DIV_64;
    clocks_cfg.divider_cfg.sckcr_b.divselxspi1    = CGC_DIVSEL_XSPI_CLOCK_DIV_3;
    clocks_cfg.divider_cfg.sckcr_b.ckio_div       = CGC_CLOCK_OUT_CLOCK_DIV_4;
    clocks_cfg.divider_cfg.sckcr_b.fselcanfd_div  = CGC_CANFD_CLOCK_DIV_20;
    clocks_cfg.divider_cfg.sckcr_b.phy_sel        = CGC_PHY_CLOCK_MAIN_OSC;
    clocks_cfg.divider_cfg.sckcr_b.spi0_async_sel = CGC_SPI_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr_b.spi1_async_sel = CGC_SPI_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr_b.spi2_async_sel = CGC_SPI_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr_b.sci0_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr_b.sci1_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr_b.sci2_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr_b.sci3_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr_b.sci4_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ;

    clocks_cfg.divider_cfg.sckcr2_b.fsel0cr52 = CGC_CPU_CLOCK_DIV_4;
 #if 2 == BSP_FEATURE_BSP_CR52_CORE_NUM
    clocks_cfg.divider_cfg.sckcr2_b.fsel1cr52 = CGC_CPU_CLOCK_DIV_4;
 #endif
    clocks_cfg.divider_cfg.sckcr2_b.div_sub_sel    = CGC_BASECLOCK_DIV_4;
    clocks_cfg.divider_cfg.sckcr2_b.spi3_async_sel = CGC_SPI_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr2_b.sci5_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ;

    /* Start the LOCO clock */
    clocks_cfg.loco_state = CGC_CLOCK_CHANGE_START;

    /* Start the PLL1 clock */
    clocks_cfg.pll1_state = CGC_CLOCK_CHANGE_START;

    /* R_CGC_ClocksCfg() can be used to set clock divisors and
     * to start/stop LOCO and PLL1 clock
     */
    err = R_CGC_ClocksCfg(&g_cgc0_ctrl, &clocks_cfg);
    handle_error(err);


    /* Also, R_CGC_ClockStart() and R_CGC_ClockStop() can be used
     * to start/stop LOCO and PLL1 clock
     */
}

Configuring Multiple Clocks for RZ/T2H

This example demonstrates configuring multiple clocks in a single function call using R_CGC_ClocksCfg() for RZ/T2H.

void cgc_clocks_cfg_example_t2h (void)
{
    fsp_err_t err = FSP_SUCCESS;

    /* Initializes the CGC module. */
    err = R_CGC_Open(&g_cgc0_ctrl, &g_cgc0_cfg);

    /* Handle any errors. This function should be defined by the user. */
    handle_error(err);


    /* Set divisors for CPU0 (and CPU1) clock to run at minimum frequency at 150 MHz. */
    cgc_clocks_cfg_t clocks_cfg;

    clocks_cfg.divider_cfg.sckcr_b.fselxspi0     = CGC_FSEL_XSPI_CLOCK_DIV_64;
    clocks_cfg.divider_cfg.sckcr_b.divselxspi0   = CGC_DIVSEL_XSPI_CLOCK_DIV_3;
    clocks_cfg.divider_cfg.sckcr_b.fselxspi1     = CGC_FSEL_XSPI_CLOCK_DIV_64;
    clocks_cfg.divider_cfg.sckcr_b.divselxspi1   = CGC_DIVSEL_XSPI_CLOCK_DIV_3;
    clocks_cfg.divider_cfg.sckcr_b.ckio_div      = CGC_CLOCK_OUT_CLOCK_DIV_4;
    clocks_cfg.divider_cfg.sckcr_b.fselcanfd_div = CGC_CANFD_CLOCK_DIV_20;
    clocks_cfg.divider_cfg.sckcr_b.phy_sel       = CGC_PHY_CLOCK_MAIN_OSC;

    clocks_cfg.divider_cfg.sckcr2_b.cr52cpu0       = CGC_CPU_CLOCK_DIV_2;
    clocks_cfg.divider_cfg.sckcr2_b.cr52cpu1       = CGC_CPU_CLOCK_DIV_2;
    clocks_cfg.divider_cfg.sckcr2_b.ca55core0      = CGC_CPU_CLOCK_DIV_2;
    clocks_cfg.divider_cfg.sckcr2_b.ca55core1      = CGC_CPU_CLOCK_DIV_2;
    clocks_cfg.divider_cfg.sckcr2_b.ca55core2      = CGC_CPU_CLOCK_DIV_2;
    clocks_cfg.divider_cfg.sckcr2_b.ca55core3      = CGC_CPU_CLOCK_DIV_2;
    clocks_cfg.divider_cfg.sckcr2_b.ca55sclk       = CGC_CPU_CLOCK_DIV_2;
    clocks_cfg.divider_cfg.sckcr2_b.spi3_async_sel = CGC_SPI_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr2_b.sci5_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ;

    clocks_cfg.divider_cfg.sckcr3_b.spi0_async_sel = CGC_SPI_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr3_b.spi1_async_sel = CGC_SPI_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr3_b.spi2_async_sel = CGC_SPI_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr3_b.sci0_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr3_b.sci1_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr3_b.sci2_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr3_b.sci3_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr3_b.sci4_async_sel = CGC_SCI_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr3_b.lcdc_div_sel   = CGC_LCDC_DIV_2;

    clocks_cfg.divider_cfg.sckcr4_b.scie0_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr4_b.scie1_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr4_b.scie2_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr4_b.scie3_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr4_b.scie4_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr4_b.scie5_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr4_b.scie6_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr4_b.scie7_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr4_b.scie8_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr4_b.scie9_async_sel  = CGC_SCIE_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr4_b.scie10_async_sel = CGC_SCIE_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr4_b.scie11_async_sel = CGC_SCIE_ASYNC_CLOCK_96MHZ;
    clocks_cfg.divider_cfg.sckcr4_b.encoutclk        = CGC_ENCOUT_CLOCK_20MHZ;

    /* Start the LOCO clock */
    clocks_cfg.loco_state = CGC_CLOCK_CHANGE_START;

    /* Start PLL clocks */
    clocks_cfg.pll0_state = CGC_CLOCK_CHANGE_START;
    clocks_cfg.pll2_state = CGC_CLOCK_CHANGE_START;
    clocks_cfg.pll3_state = CGC_CLOCK_CHANGE_START;

    clocks_cfg.pll0_ssc_cfg.pll_ssc_enable                    = CGC_PLL_SSC_ENABLE_DEFAULT;
    clocks_cfg.pll0_ssc_cfg.pll_ssc_modulation_freq_ctrl      = CGC_PLL_SSC_MFR_DEFAULT;
    clocks_cfg.pll0_ssc_cfg.pll_ssc_modulation_rate_ctrl      = CGC_PLL_SSC_MRR_DEFAULT;
    clocks_cfg.pll2_ssc_cfg.pll_ssc_enable                    = CGC_PLL_SSC_ENABLE_DEFAULT;
    clocks_cfg.pll2_ssc_cfg.pll_ssc_modulation_freq_ctrl      = CGC_PLL_SSC_MFR_DEFAULT;
    clocks_cfg.pll2_ssc_cfg.pll_ssc_modulation_rate_ctrl      = CGC_PLL_SSC_MRR_DEFAULT;
    clocks_cfg.pll3_vco_cfg.pll_divider_p                     = CGC_PLL_VCO_DIVIDER_P_DEFAULT;
    clocks_cfg.pll3_vco_cfg.pll_divider_m                     = CGC_PLL_VCO_DIVIDER_M_DEFAULT;
    clocks_cfg.pll3_vco_cfg.pll_divider_s                     = CGC_PLL_VCO_DIVIDER_S_DEFAULT;
    clocks_cfg.pll3_vco_cfg.pll_divider_delta_sigma_modulator = CGC_PLL_VCO_DIVIDER_K_DEFAULT;

    /* R_CGC_ClocksCfg() can be used to set clock divisors and
     * to start/stop LOCO and PLL1 clock
     */
    err = R_CGC_ClocksCfg(&g_cgc0_ctrl, &clocks_cfg);
    handle_error(err);


    /* Also, R_CGC_ClockStart() and R_CGC_ClockStop() can be used
     * to start/stop LOCO and PLL clocks
     */
}

Data Structures
struct	cgc_instance_ctrl_t

---

Data Structure Documentation

cgc_instance_ctrl_t

struct cgc_instance_ctrl_t

CGC private control block. DO NOT MODIFY. Initialization occurs when R_CGC_Open() is called.

Function Documentation

R_CGC_Open()

fsp_err_t R_CGC_Open	(	cgc_ctrl_t *const	p_ctrl,
		cgc_cfg_t const *const	p_cfg
	)

Initialize the CGC API. Implements cgc_api_t::open.

Return values

FSP_SUCCESS	CGC successfully initialized.
FSP_ERR_ASSERTION	Invalid input argument.
FSP_ERR_ALREADY_OPEN	Module is already open.

R_CGC_ClocksCfg()

fsp_err_t R_CGC_ClocksCfg	(	cgc_ctrl_t *const	p_ctrl,
		cgc_clocks_cfg_t const *const	p_clock_cfg
	)

Reconfigures all main system clocks. This API can be used for any of the following purposes:

• start or stop clocks

If the requested system clock source has a stabilization flag, this function blocks waiting for the stabilization flag of the requested system clock source to be set. If the requested system clock source was just started and it has no stabilization flag, this function blocks for the stabilization time required by the requested system clock source according to the Electrical Characteristics section of the hardware manual. If the requested system clock source has no stabilization flag and it is already running, it is assumed to be stable and this function will not block.

Do not attempt to stop the requested clock source or the source of the PLL if the PLL will be running after this operation completes.

Implements cgc_api_t::clocksCfg.

Return values

FSP_SUCCESS	Clock configuration applied successfully.
FSP_ERR_ASSERTION	Invalid input argument.
FSP_ERR_NOT_OPEN	Module is not open.
FSP_ERR_NOT_STABILIZED	Clock not stabilized.
FSP_ERR_INVALID_ARGUMENT	Clock configuration setting is invalid.

R_CGC_ClockStart()

fsp_err_t R_CGC_ClockStart	(	cgc_ctrl_t *const	p_ctrl,
		cgc_clock_t	clock_source,
		cgc_pll_cfg_t const *const	p_pll_cfg
	)

Start the specified clock if it is not currently active. Implements cgc_api_t::clockStart.

Return values

FSP_SUCCESS	Clock initialized successfully.
FSP_ERR_ASSERTION	Invalid input argument.
FSP_ERR_NOT_OPEN	Module is not open.

R_CGC_ClockStop()

fsp_err_t R_CGC_ClockStop	(	cgc_ctrl_t *const	p_ctrl,
		cgc_clock_t	clock_source
	)

Stop the specified clock if it is active. Implements cgc_api_t::clockStop.

Return values

FSP_SUCCESS	Clock stopped successfully.
FSP_ERR_ASSERTION	Invalid input argument.
FSP_ERR_NOT_OPEN	Module is not open.
FSP_ERR_IN_USE	Attempt to stop the current system clock or the PLL source clock.
FSP_ERR_NOT_STABILIZED	Clock not stabilized after starting.

R_CGC_ClockCheck()

fsp_err_t R_CGC_ClockCheck	(	cgc_ctrl_t *const	p_ctrl,
		cgc_clock_t	clock_source
	)

Check the specified clock for stability. Implements cgc_api_t::clockCheck.

Return values

FSP_SUCCESS	Clock is running and stable.
FSP_ERR_ASSERTION	Invalid input argument.
FSP_ERR_NOT_OPEN	Module is not open.
FSP_ERR_NOT_STABILIZED	Clock not stabilized.
FSP_ERR_CLOCK_INACTIVE	Clock not turned on.

R_CGC_SystemClockSet()

fsp_err_t R_CGC_SystemClockSet	(	cgc_ctrl_t *const	p_ctrl,
		cgc_clock_t	clock_source,
		cgc_divider_cfg_t const *const	p_divider_cfg
	)

Set the specified clock as the system clock and configure the internal dividers. Implements cgc_api_t::systemClockSet.

This function also updates the SystemCoreClock CMSIS global variable.

Return values

FSP_SUCCESS	Operation performed successfully.
FSP_ERR_ASSERTION	Invalid input argument.
FSP_ERR_NOT_OPEN	Module is not open.
FSP_ERR_CLOCK_INACTIVE	The specified clock source is inactive.
FSP_ERR_NOT_STABILIZED	The clock source is not stabilized after being turned off or PLL clock source is not stable.

R_CGC_SystemClockGet()

fsp_err_t R_CGC_SystemClockGet	(	cgc_ctrl_t *const	p_ctrl,
		cgc_clock_t *const	p_clock_source,
		cgc_divider_cfg_t *const	p_divider_cfg
	)

Return the current system clock source and configuration. Implements cgc_api_t::systemClockGet.

Return values

FSP_SUCCESS	Parameters returned successfully.
FSP_ERR_ASSERTION	Invalid input argument.
FSP_ERR_NOT_OPEN	Module is not open.

R_CGC_OscStopDetectEnable()

fsp_err_t R_CGC_OscStopDetectEnable

(

cgc_ctrl_t *const

p_ctrl

)

Enable the oscillation stop detection for the main clock. API not supported.

Implements cgc_api_t::oscStopDetectEnable.

Return values

FSP_ERR_UNSUPPORTED

API not supported.

R_CGC_OscStopDetectDisable()

fsp_err_t R_CGC_OscStopDetectDisable

(

cgc_ctrl_t *const

p_ctrl

)

Disable the oscillation stop detection for the main clock. API not supported.

Implements cgc_api_t::oscStopDetectDisable.

Return values

FSP_ERR_UNSUPPORTED

API not supported.

R_CGC_OscStopStatusClear()

fsp_err_t R_CGC_OscStopStatusClear

(

cgc_ctrl_t *const

p_ctrl

)

Clear the Oscillation Stop Detection Status register. API not supported.

Implements cgc_api_t::oscStopStatusClear.

Return values

FSP_ERR_UNSUPPORTED

API not supported.

R_CGC_CallbackSet()

fsp_err_t R_CGC_CallbackSet	(	cgc_ctrl_t *const	p_ctrl,
		void(*)(cgc_callback_args_t *)	p_callback,
		void const *const	p_context,
		cgc_callback_args_t *const	p_callback_memory
	)

Updates the user callback and has option of providing memory for callback structure. Implements cgc_api_t::callbackSet

Return values

FSP_ERR_UNSUPPORTED

API not supported.

R_CGC_Close()

fsp_err_t R_CGC_Close

(

cgc_ctrl_t *const

p_ctrl

)

Closes the CGC module. Implements cgc_api_t::close.

Return values

FSP_SUCCESS	The module is successfully closed.
FSP_ERR_ASSERTION	Invalid input argument.
FSP_ERR_NOT_OPEN	Module is not open.