Functions
fsp_err_t	R_ETHSW_Open (ether_switch_ctrl_t const p_ctrl, ether_switch_cfg_t const const p_cfg)

fsp_err_t	R_ETHSW_Close (ether_switch_ctrl_t *const p_ctrl)

fsp_err_t	R_ETHSW_SpeedCfg (ether_switch_ctrl_t *const p_ctrl, uint32_t const port, ethsw_link_speed_t const speed)

fsp_err_t	R_ETHSW_MacTableSet (ether_switch_ctrl_t const p_ctrl, ethsw_mac_table_entry_addr_t p_mac_entry_addr, ethsw_mac_table_entry_info_t *p_mac_entry_info)

fsp_err_t	R_ETHSW_MacTableGet (ether_switch_ctrl_t const p_ctrl, ethsw_mac_table_entry_addr_t p_mac_entry_addr, ethsw_mac_table_entry_info_t *p_mac_entry_info)

fsp_err_t	R_ETHSW_MacTableConfigSet (ether_switch_ctrl_t const p_ctrl, ethsw_mac_table_config_t p_mac_table_config)

fsp_err_t	R_ETHSW_MacTableClear (ether_switch_ctrl_t const p_ctrl, ethsw_mac_table_clear_mode_t p_mac_table_clear)

fsp_err_t	R_ETHSW_LearningSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool enable)

fsp_err_t	R_ETHSW_PortForwardAdd (ether_switch_ctrl_t *const p_ctrl, uint32_t port)

fsp_err_t	R_ETHSW_PortForwardDel (ether_switch_ctrl_t *const p_ctrl, uint32_t port)

fsp_err_t	R_ETHSW_FloodUnknownSet (ether_switch_ctrl_t const p_ctrl, ethsw_flood_unknown_config_t p_flood_config)

fsp_err_t	R_ETHSW_LinkStateGet (ether_switch_ctrl_t const p_ctrl, uint32_t port, ethsw_link_status_t p_state_link)

fsp_err_t	R_ETHSW_FrameSizeMaxSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, uint32_t frame_size_max)

fsp_err_t	R_ETHSW_DlrInitSet (ether_switch_ctrl_t const p_ctrl, ethsw_dlr_init_t p_dlr_init)

fsp_err_t	R_ETHSW_DlrUninitSet (ether_switch_ctrl_t *const p_ctrl)

fsp_err_t	R_ETHSW_DlrEnableSet (ether_switch_ctrl_t *const p_ctrl)

fsp_err_t	R_ETHSW_DlrDisableSet (ether_switch_ctrl_t *const p_ctrl)

fsp_err_t	R_ETHSW_DlrBeaconStateGet (ether_switch_ctrl_t const p_ctrl, uint32_t port, ethsw_dlr_beacon_state_t p_beacon_state)

fsp_err_t	R_ETHSW_DlrNodeStateGet (ether_switch_ctrl_t const p_ctrl, ethsw_dlr_node_state_t p_node_state)

fsp_err_t	R_ETHSW_DlrSvIpGet (ether_switch_ctrl_t const p_ctrl, uint32_t p_ip_addr)

fsp_err_t	R_ETHSW_DlrSvPriorityGet (ether_switch_ctrl_t const p_ctrl, uint8_t p_priority)

fsp_err_t	R_ETHSW_DlrVlanGet (ether_switch_ctrl_t const p_ctrl, uint16_t p_vlan_info)

fsp_err_t	R_ETHSW_DlrSvMacGet (ether_switch_ctrl_t const p_ctrl, ethsw_mac_addr_t p_addr_mac)

fsp_err_t	R_ETHSW_RxPatternMatcherSet (ether_switch_ctrl_t const p_ctrl, ethsw_rx_pattern_matcher_t p_rx_pattern_matcher)

fsp_err_t	R_ETHSW_RxPatternMatcherCallback (ether_switch_ctrl_t const p_ctrl, void(p_rx_pattern_callback_func)(ethsw_rx_pattern_event_t event, ethsw_rx_pattern_event_data_t *p_data))

fsp_err_t	R_ETHSW_PreemptQueueSet (ether_switch_ctrl_t const p_ctrl, ethsw_preempt_queue_t p_preempt_queue)

fsp_err_t	R_ETHSW_PreemptPortControlConfigSet (ether_switch_ctrl_t const p_ctrl, uint32_t port, ethsw_preempt_port_ctrl_config_t p_preempt_port_ctrl)

fsp_err_t	R_ETHSW_PreemptPortControlEnableSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool frame_preempt_enable)

fsp_err_t	R_ETHSW_PreemptHoldReqForceSet (ether_switch_ctrl_t *const p_ctrl, ethsw_port_mask_t holdreq_request_port_mask)

fsp_err_t	R_ETHSW_PreemptHoldReqReleaseSet (ether_switch_ctrl_t *const p_ctrl, ethsw_port_mask_t holdreq_release_port_mask)

fsp_err_t	R_ETHSW_PreemptStatusGet (ether_switch_ctrl_t const p_ctrl, uint32_t port, ethsw_preempt_status_t p_preempt_status)

fsp_err_t	R_ETHSW_MmctlQgateSet (ether_switch_ctrl_t const p_ctrl, ethsw_mmclt_qgate_t p_mmctl_qgate)

fsp_err_t	R_ETHSW_MmctlPoolSizeSet (ether_switch_ctrl_t const p_ctrl, ethsw_mmctl_pool_size_t p_pool_size)

fsp_err_t	R_ETHSW_MmctlQueueAssignSet (ether_switch_ctrl_t const p_ctrl, ethsw_mmctl_queue_assign_t p_queue_assign)

fsp_err_t	R_ETHSW_MmctlYellowLengthSet (ether_switch_ctrl_t const p_ctrl, uint32_t port, ethsw_yellow_length_t p_yellow_length)

fsp_err_t	R_ETHSW_QueueFlushEventSet (ether_switch_ctrl_t const p_ctrl, ethsw_queue_flush_event_t p_queue_flush_event)

fsp_err_t	R_ETHSW_MmctlQueueClosedNonemptyStatusGet (ether_switch_ctrl_t const p_ctrl, ethsw_mmctl_qclosed_nonempty_t p_qclosed_nonempty)

fsp_err_t	R_ETHSW_StatisticsSwitchGet (ether_switch_ctrl_t const p_ctrl, bool clear, ethsw_statistics_switch_base_t p_statistics_switch)

fsp_err_t	R_ETHSW_StatisticsMacGet (ether_switch_ctrl_t const p_ctrl, uint32_t port, ethsw_statistics_mac_t p_statistics_mac)

fsp_err_t	R_ETHSW_StatisticsMacClear (ether_switch_ctrl_t *const p_ctrl)

fsp_err_t	R_ETHSW_Statistics8023brGet (ether_switch_ctrl_t const p_ctrl, uint32_t port, bool clear, ethsw_statistics_8023br_t p_statistics_8023br)

fsp_err_t	R_ETHSW_StatisticsDlrGet (ether_switch_ctrl_t const p_ctrl, ethsw_statistics_dlr_t p_statistics_dlr)

fsp_err_t	R_ETHSW_CqfEnableSet (ether_switch_ctrl_t const p_ctrl, uint32_t port, ethsw_cqf_enable_t p_cqf_enable)

fsp_err_t	R_ETHSW_SnoopParserSet (ether_switch_ctrl_t const p_ctrl, ethsw_snoop_parser_config_t p_parser_cnf)

fsp_err_t	R_ETHSW_SnoopArithSet (ether_switch_ctrl_t const p_ctrl, ethsw_snoop_arith_config_t p_arith_cnf)

fsp_err_t	R_ETHSW_EeeSet (ether_switch_ctrl_t const p_ctrl, uint32_t port, ethsw_eee_t p_cnf_eee)

fsp_err_t	R_ETHSW_StormTimeSet (ether_switch_ctrl_t *const p_ctrl, uint16_t storm_time)

fsp_err_t	R_ETHSW_BcastLimitSet (ether_switch_ctrl_t *const p_ctrl, uint16_t storm_frames)

fsp_err_t	R_ETHSW_McastLimitSet (ether_switch_ctrl_t *const p_ctrl, uint16_t storm_frames)

fsp_err_t	R_ETHSW_TxRateSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, float rate)

fsp_err_t	R_ETHSW_QosModeSet (ether_switch_ctrl_t const p_ctrl, uint32_t port, ethsw_qos_mode_t p_qos_mode)

fsp_err_t	R_ETHSW_QosPrioValnSet (ether_switch_ctrl_t const p_ctrl, uint32_t port, ethsw_qos_prio_vlan_t p_qos_prio_vlan)

fsp_err_t	R_ETHSW_QosPrioIpSet (ether_switch_ctrl_t const p_ctrl, uint32_t port, ethsw_qos_prio_ip_t p_qos_prio_ip)

fsp_err_t	R_ETHSW_QosPrioTypeSet (ether_switch_ctrl_t const p_ctrl, ethsw_qos_prio_type_t p_qos_prio_ethtype)

fsp_err_t	R_ETHSW_MirrorSet (ether_switch_ctrl_t const p_ctrl, ethsw_mirror_conf_t p_mirror_conf)

fsp_err_t	R_ETHSW_CtEnableSet (ether_switch_ctrl_t *const p_ctrl, ethsw_port_mask_t port_mask)

fsp_err_t	R_ETHSW_CtDelaySet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, uint32_t ct_delay)

fsp_err_t	R_ETHSW_PulseGeneratorInit (ether_switch_ctrl_t *const p_ctrl, uint32_t time_num)

fsp_err_t	R_ETHSW_PulseGeneratorSet (ether_switch_ctrl_t const p_ctrl, ethsw_ts_pulse_generator_t p_pulse)

fsp_err_t	R_ETHSW_PortAuthSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool auth_state)

fsp_err_t	R_ETHSW_PortCtrlDirSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool dir_state)

fsp_err_t	R_ETHSW_PortEapolSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool eapol_state)

fsp_err_t	R_ETHSW_BpduSet (ether_switch_ctrl_t *const p_ctrl, bool bpdu_state)

fsp_err_t	R_ETHSW_VlanDefaultSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, uint16_t vlan_id)

fsp_err_t	R_ETHSW_VlanPortAdd (ether_switch_ctrl_t *const p_ctrl, uint32_t port, uint16_t vlan_id)

fsp_err_t	R_ETHSW_VlanPortRemove (ether_switch_ctrl_t *const p_ctrl, uint32_t port, uint16_t vlan_id)

fsp_err_t	R_ETHSW_VlanInModeSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_vlan_in_mode_t vlan_in_mode)

fsp_err_t	R_ETHSW_VlanOutModeSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_vlan_out_mode_t vlan_out_mode)

fsp_err_t	R_ETHSW_VlanVerifySet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool enable)

fsp_err_t	R_ETHSW_VlanDiscardUnknownSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool enable)

fsp_err_t	R_ETHSW_TdmaEnableSet (ether_switch_ctrl_t const p_ctrl, ethsw_tdma_enable_t p_tdma_enable)

fsp_err_t	R_ETHSW_TdmaScheduleSet (ether_switch_ctrl_t const p_ctrl, ethsw_tdma_schedule_entry_t p_tdma_schedule_entry, uint16_t tdma_schedule_entry_count)

fsp_err_t	R_ETHSW_TdmaGpioModeSet (ether_switch_ctrl_t *const p_ctrl, uint8_t gpio_num, ethsw_tdma_gpio_mode_t gpio_mode)

fsp_err_t	R_ETHSW_TdmaCounter0Set (ether_switch_ctrl_t *const p_ctrl, uint32_t tdma_counter0)

fsp_err_t	R_ETHSW_TdmaCounter0Get (ether_switch_ctrl_t const p_ctrl, uint32_t p_tdma_counter0)

fsp_err_t	R_ETHSW_TdmaCounter1Set (ether_switch_ctrl_t const p_ctrl, ethsw_tdma_counter1_t p_tdma_counter1)

fsp_err_t	R_ETHSW_TdmaCounter1Get (ether_switch_ctrl_t const p_ctrl, ethsw_tdma_counter1_t p_tdma_counter1)

fsp_err_t	R_ETHSW_TdmaHoldReqClear (ether_switch_ctrl_t *const p_ctrl)

fsp_err_t	R_ETHSW_TimeEnableSet (ether_switch_ctrl_t const p_ctrl, ethsw_time_enable_t p_time_enable)

fsp_err_t	R_ETHSW_TimeTransmitTimestampSet (ether_switch_ctrl_t const p_ctrl, ethsw_time_transmit_t p_time_transmit)

fsp_err_t	R_ETHSW_TimeValueSet (ether_switch_ctrl_t const p_ctrl, ethsw_timestamp_t p_timestamp)

fsp_err_t	R_ETHSW_TimeValueGet (ether_switch_ctrl_t const p_ctrl, ethsw_timestamp_t p_timestamp)

fsp_err_t	R_ETHSW_TimeValueGetAll (ether_switch_ctrl_t const p_ctrl, ethsw_timestamp_t p_timer0, ethsw_timestamp_t *p_timer1)

fsp_err_t	R_ETHSW_TimePeerDelaySet (ether_switch_ctrl_t const p_ctrl, uint32_t port, ethsw_time_peerdelay_t p_peerdelay)

fsp_err_t	R_ETHSW_TimeOffsetSet (ether_switch_ctrl_t const p_ctrl, ethsw_time_offset_correction_t p_offset)

fsp_err_t	R_ETHSW_TimeRateSet (ether_switch_ctrl_t const p_ctrl, ethsw_time_rate_correction_t p_rate)

fsp_err_t	R_ETHSW_TimeDomainSet (ether_switch_ctrl_t const p_ctrl, ethsw_time_domain_t p_domain)

Detailed Description

Provides API for using Ethernet Switch. It implements the Ethernet Switch Interface.

Overview

With the ethernet switch function, this LSI enables to build the network topology such as line type without external switching hub.

Features

Three external ports and one internal port
Integrated 10/100/1000 MACs with flexible rate PHY interface up to 1Gbps
3 Gbps non-blocking switching capacity etc..

Configuration

Build Time Configurations for r_ethsw

The following build time configurations are defined in fsp_cfg/r_ether_switch_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.

Configurations for Networking > Ethernet (r_ethsw)

This module can be added to the Stacks tab via New Stack > Networking > Ethernet (r_ethsw).

Configuration	Options	Default	Description
Management > Management port specific tag	Disabled Enabled	Disabled	Enable or Disable management port specific tag.
Management > Management port specific tag ID	Specify a value between 0x1 and 0xFFFF.	0xE001	Select management port specific tag ID.
Interrupts > Interrupt Priority	MCU Specific Options		Select the interrupt priority.
Interrupts > Callback	Name must be a valid C symbol	NULL	Select the callback function provided when an interrupt occurs
Interrupts > Context	Name must be a valid C symbol	NULL	Select the argument of callback, is void* type
Name	Name must be a valid C symbol	g_ethsw0	Module name.
Channel	0	0	Select the Ethernet controller channel number.
Link signal change	Disable Enable	Disable	Enable or disable callback by PHYLINK change.

Usage Notes

Limitations

Developers should be aware of the following limitations when using the ETHSW:

Only 1 channel is configuratable.

Data Structures
struct	ethsw_instance_ctrl_t

struct	ethsw_extend_cfg_t

struct	ethsw_port_mask_t

struct	ethsw_mac_table_entry_addr_t

struct	ethsw_mac_table_entry_info_t

struct	ethsw_mac_table_config_t

struct	ethsw_flood_unknown_config_t

struct	ethsw_dlr_init_t

struct	ethsw_rx_pattern_ctrl_t

union	ethsw_rx_pattern_data_t

struct	ethsw_rx_pattern_matcher_t

struct	ethsw_rx_pattern_event_data_t

struct	ethsw_preempt_queue_t

struct	ethsw_preempt_port_ctrl_config_t

struct	ethsw_preempt_status_t

struct	ethsw_mmclt_qgate_t

struct	ethsw_mmctl_pool_size_t

struct	ethsw_mmctl_queue_assign_t

struct	ethsw_yellow_length_t

struct	ethsw_queue_flush_event_t

struct	ethsw_cqf_enable_t

struct	ethsw_snoop_parser_config_t

struct	ethsw_snoop_arith_config_t

struct	ethsw_eee_t

struct	ethsw_qos_mode_t

struct	ethsw_qos_prio_ip_t

struct	ethsw_qos_prio_type_t

struct	ethsw_mirror_conf_t

struct	ethsw_ts_pulse_generator_t

union	ethsw_tdma_callback_data_t

struct	ethsw_tdma_enable_t

struct	ethsw_tdma_schedule_entry_t

struct	ethsw_tdma_counter1_t

struct	ethsw_time_enable_t

struct	ethsw_timestamp_t

struct	ethsw_time_transmit_t

struct	ethsw_time_peerdelay_t

struct	ethsw_time_offset_correction_t

struct	ethsw_time_rate_correction_t

Macros
#define	ETHSW_PORT_MGMT
	Management port number. More...

#define	ETHER_SWITCH_TDMA_GPIO_COUNT
	Noumber of TDMA_GPIO.

#define	ETHSW_QUEUE_COUNT
	Number of queues ETHSW has.

#define	ETHSW_QUEUE_COUNT
	Number of queues ETHSW has.

#define	ETHSW_TDMA_GPIO_COUNT
	Number of TDMA_GPIO.

Typedefs
typedef uint8_t	ethsw_mac_addr_t[ETHSW_MAC_ADDR_LENGTH]

typedef uint8_t	ethsw_mmctl_qclosed_nonempty_t[4]

Enumerations
enum	ethsw_specific_tag_t

enum	ethsw_phylink_t

enum	ethsw_link_speed_t

enum	ethsw_mac_table_clear_mode_t

enum	ethsw_link_status_t

enum	ethsw_dlr_event_t

enum	ethsw_dlr_beacon_state_t

enum	ethsw_dlr_node_state_t

enum	ethsw_rx_pattern_mode_t

enum	ethsw_rx_pattern_event_t

enum	ethsw_preempt_verify_status_t

enum	ethsw_mmctl_qgate_action_t

enum	ethsw_mmctl_pool_id_t

enum	ethsw_queu_flush_action_t

enum	ethsw_snoop_offset_type_t

enum	ethsw_snoop_comp_type_t

enum	ethsw_snoop_action_t

enum	ethsw_snoop_operat_t

enum	ethsw_mirr_mode_t

enum	ethsw_vlan_in_mode_t

enum	ethsw_vlan_out_mode_t

enum	ethsw_tdma_event_t

enum	ethsw_tdma_gpio_mode_t

enum	ethsw_time_event_t

Data Structure Documentation

◆ ethsw_instance_ctrl_t

struct ethsw_instance_ctrl_t

ETHER SWITCH control block. DO NOT INITIALIZE. Initialization occurs when ether_switch_api_t::open is called.

Data Fields
uint32_t	open	Used to determine if the channel is configured.
ether_switch_cfg_t const *	p_switch_cfg	Pointer to initial configurations.
R_ETHSW_Type *	p_reg_switch	Pointer to Ethernet Switch peripheral registers.
R_ETHSS_Type *	p_reg_ethss	Pointer to Ethernet Subsystem peripheral registers.
R_ETHSW_PTP_Type *	p_reg_ethsw_ptp	Pointer to PTP Timer Pulse Control Registers.

◆ ethsw_extend_cfg_t

struct ethsw_extend_cfg_t

Extend Configuration parameters.

Data Fields
ethsw_specific_tag_t	specific_tag	Enable or Disable Management port specific frmame tag.
uint16_t	specific_tag_id	Management port specific frmame tag ID, when specific_tag is enable.
ethsw_phylink_t	phylink

◆ ethsw_port_mask_t

struct ethsw_port_mask_t

Port mask

Data Fields
uint32_t	mask: 4	[3.. 0] Port Mask: bit0=Port0, bit1=Port1, bit2=Port2, bit3=Port3(Management Port)
uint32_t	__pad0__: 29	[4..31]

◆ ethsw_mac_table_entry_addr_t

struct ethsw_mac_table_entry_addr_t

Address in MAC table entry

Data Fields
ethsw_mac_addr_t *	mac_addr	MAC address pointer.
uint16_t	vlan_id	VLAN ID.

◆ ethsw_mac_table_entry_info_t

struct ethsw_mac_table_entry_info_t

Information in MAC table entry

Data Fields
ethsw_port_mask_t	port_mask	port mask
uint32_t	priority	switching priority

◆ ethsw_mac_table_config_t

struct ethsw_mac_table_config_t

MAC table config

Data Fields
bool	learning	Enable/disable MAC learning.
bool	aging	Enable/disable address aging.
bool	migration	Enable/disable the migration of devices from one port to another.
bool	independent_vlan	Enable/disable independent VLAN learning.
bool	discard_unknown	Enable/disable discarding of unknown destination frames.

◆ ethsw_flood_unknown_config_t

struct ethsw_flood_unknown_config_t

Flood domain configuration for unknown frames

Data Fields
ethsw_port_mask_t	port_mask_bcast	flood domain port mask for broadcasts with unkown destination
ethsw_port_mask_t	port_mask_mcast	flood domain port mask for multicasts with unkown destination
ethsw_port_mask_t	port_mask_ucast	flood domain port mask for unicasts with unkown destination

◆ ethsw_dlr_init_t

struct ethsw_dlr_init_t

DLR initilize

Data Fields
ethsw_mac_addr_t *	p_host_addr
	host MAC address pointer

◆ ethsw_rx_pattern_ctrl_t

struct ethsw_rx_pattern_ctrl_t

RX Pattern Matcher Function Control

Data Fields
bool	match_not	The functions of this control are executed if the pattern does not match.
bool	mgmt_fwd	The frame is forwarded to the management port only.
bool	discard	The frame is discarded.
bool	set_prio	Set frame priority, overriding normal classification.
ethsw_rx_pattern_mode_t	mode	Operating mode.
bool	timer_sel_ovr	Overrides the default timer to use by timestamp operations.
bool	force_forward	The frame is forwarded to the ports indicated in PORTMASK,.
bool	hub_trigger	The port defined in the PORTMASK setting is allowed for transmitting one frame. Usable for Hub mode only.
bool	match_red	Enable the pattern matcher only when the TDMA indicates that this is the RED period.
bool	match_not_red	Enable the pattern matcher only when the TDMA indicates that this is not the RED period.
bool	vlan_skip	Skips VLAN tag (4 bytes)
uint8_t	priority	Priority of the frame used when SET_PRIO is set.
bool	learning_dis	The hardware learning function is not executed.
ethsw_port_mask_t	port_mask	A port mask used depending on the control bits (for example, HUBTRIGGER).
bool	imc_trigger	The ports defined in the PORTMASK setting are allowed for transmitting one frame from the queues indicated by QUEUESEL.
bool	imc_trigger_dely	The ports defined in the PORTMASK setting are allowed for transmitting one frame from the queues indicated by QUEUESEL. Delayed by the value programmed in MMCTL_DLY_QTRIGGER_CTRL.
bool	swap_bytes	The byte order is swapped from the order received by the frame.
bool	match_lt	The Length/Type field in the frame is compared against the value in length_type in the compare register.
uint8_t	timer_sel	Override value to use when TIMER_SEL_OVR is set to 1 for selecting the timer for this frame.
uint8_t	queue_sel	A queue selector for the HUBTRIGGER function.

◆ ethsw_rx_pattern_data_t

union ethsw_rx_pattern_data_t

RX Pattern Matcher Function Data

◆ ethsw_rx_pattern_matcher_t

struct ethsw_rx_pattern_matcher_t

The parameter for set/get the Rx pattern matcher function

Data Fields
uint16_t	pattern_sel	Pattern matcher number (0..11)
ethsw_port_mask_t	pattern_port_mask	Port mask.
bool	pattern_int	When true, called back from ISR.
ethsw_rx_pattern_ctrl_t *	p_pattern_ctrl	RX Pattern Matcher Function Control.
ethsw_rx_pattern_data_t *	p_pattern_data	RX Pattern Matcher Function Data.

◆ ethsw_rx_pattern_event_data_t

struct ethsw_rx_pattern_event_data_t

Callback parameter of the Rx pattern matcher

Data Fields
uint16_t	match_int	Pattern mask to indicate pattern match.
uint16_t	error_int	Error for each port.

◆ ethsw_preempt_queue_t

struct ethsw_preempt_queue_t

The parameter for set preemptable queue

◆ ethsw_preempt_port_ctrl_config_t

struct ethsw_preempt_port_ctrl_config_t

The parameter for set frame configuration of frame preemption for each ports

Data Fields
bool	verify_dis	When set to 1, disables the verify process required for preemption operation. When PREEMPT_ENA is set to 1, preemption is not operational until the verify process validates that the peer port is also capable of performing frame preemption. Setting VERIFY_DIS disables this process and allows frame preemption without running the verify process.
bool	response_dis	When set to 1 prevents the MAC from responding to "verify" frames. "verify" frames are always replied to unless PREEMPT_ENA is set to 0 and RESPONSE_DIS is set to 1. This bit must be kept at 0 to be compliant with 802.3br.
uint8_t	addfragsize	Minimum fragment size in increments of 64 bytes. Sets the minimum mPacket size when preempting a Preemptable frame. The default value of 0 corresponds to 64 bytes, a value of 1 corresponds to 128 bytes, and so on.
uint8_t	tx_verify_time	Preemption verification timeout in milliseconds. When preemption is enabled and verification is running, this is the timeout to wait for a RESPONSE frame after sending a VERIFY frames +/? 1 ms. VERIFY frames are sent after the timeout up to two more times. Default value is 10 ms. When the value is set to less than 5 ms, it does not meet the 20% precision required by the 802.3br, so it is recommended to use larger times.
bool	rx_strict_pre	When set to 1, the preamble is checked so all bytes except the SFD are 0x55. When set to 0, only the last 2 bytes of the preamble are checked (SFD/SMD and FRAG_COUNT). It is recommended to set this bit to 1 to comply with the 802.3br specification. This bit must be set to 0 if only non-802.3br traffic is expected (for example, normal Ethernet traffic) and if custom preamble is used.
bool	rx_br_smd_dis	When set to 1, the receiver does not decode the 802.3br SMDs and assumes all frames areexpress frames. This bit must be set to 0 for correct operation with 802.3br, and can be set to 1 when 802.3br is not enabled to avoid false detection of SMDs. Setting this bit to 1 also causes any preempted frame to be aborted, bringing the re- assembly state machine to IDLE.
bool	rx_strict_br_ctl	When set to 1, strict checking of VERIFY and RESPONSE frames is enabled. When set to 1, the frame contents and frame length checks are also performed on these frames. The mCRC is always checked regardless of the value of this register. This bit must be set to 0 to be compliant with the functionality described in IEEE 802.3br.
bool	tx_mcrc_inv	When set to 1, the 32-bit XOR mask used to calculate the mCRC for transmitted frames is inverted. This bit must always be written to 0 and only used for debugging.
bool	rx_mcrc_inv	When set to 1, the 32-bit XOR mask used to calculate the mCRC for received frames is inverted. This bit must always be written to 0 and only used for debugging.

◆ ethsw_preempt_status_t

struct ethsw_preempt_status_t

The parameter for get preemption status

Data Fields
ethsw_preempt_verify_status_t	verify_status
bool	preempt_state	A per-port bit that indicates if a port is in a preempted state. This is a real-time indication meant for debugging.
bool	hold_req_state	A per-port bit that indicates if a port is preempted using MM_CTL.request (hold_req). This isa real-time indication meant for debugging.
uint8_t	min_pfrm_adj	Adjust the minimum mPacket length, in increments of 4 bytes.
uint8_t	last_pfrm_adj	Adjust the preemptable threshold when reaching the end of the frame, in increments of 4 bytes. Incrementing this value increments the length of the last mPacket.

◆ ethsw_mmclt_qgate_t

struct ethsw_mmclt_qgate_t

queue gate

Data Fields
ethsw_port_mask_t	port_mask	Per-port bit mask.
ethsw_mmctl_qgate_action_t	action[ETHSW_QUEUE_COUNT]	Gate action for queue number 0..7.

◆ ethsw_mmctl_pool_size_t

struct ethsw_mmctl_pool_size_t

The parameter for set/get memory pool size function

Data Fields
ethsw_mmctl_pool_id_t	pool_id	MMCTL pool ID.
uint16_t	cells	Memory pool size, in sells.

◆ ethsw_mmctl_queue_assign_t

struct ethsw_mmctl_queue_assign_t

The parameter for function that assins a memory pool for a queue.

Data Fields
uint8_t	queue_num	Queue number.
ethsw_mmctl_pool_id_t	pool_id	MMCTL pool ID.

◆ ethsw_yellow_length_t

struct ethsw_yellow_length_t

The parameter for set / get length in bytes of the YELLOW period.

Data Fields
bool	enable	When true, length is valid.
uint16_t	length	Specify the byte length of the YELLOW period in units of 4 bytes.

◆ ethsw_queue_flush_event_t

struct ethsw_queue_flush_event_t

The parameter for set / get queue flush event.

Data Fields
ethsw_port_mask_t	port_mask	Per-port bit mask.
uint8_t	queue_mask	1 bit per queue indicating for which queues of the ports indicated by port_mask the flush state is changed as indicated in action.
ethsw_queu_flush_action_t	action	Selects the flush state for the queues indicated by queue_mask in the ports indicated by port_mask.

◆ ethsw_cqf_enable_t

struct ethsw_cqf_enable_t

The parameter for set CQF enable configuration

Data Fields
union ethsw_cqf_enable_t	__unnamed__
uint8_t	cqf_queue	Select which two physical queues are used for CQF. The queues used are QUEUE_SEL0 and QUEUE_SEL0 + 1. Frames are written into QUEUE_SEL0 when the gate control selected with GATE_SEL0 is 0, and into QUEUE_SEL0 + 1 when the gate control is 1.
uint8_t	cqf_gate_sel	Select which gate control signal is used for selecting the output queue (these signals are the same as the ETHSW_TDMAOUT pins).
bool	use_sop	When set to 1, the CFQ queue is determined when the SOP is received at the frame writerin the memory controller. When set to 0, the queue is determined when the EOP is received at the frame writer.
bool	cqf_gate_ref_sel	Select whether the gate control signal used for the CQF group is based on the egress port when set to 0, or the ingress port when set to 1.

◆ ethsw_snoop_parser_config_t

struct ethsw_snoop_parser_config_t

Snoop parser config

Data Fields
uint8_t	arith_block	Arithmetic blkoc ID (0..1).
uint8_t	parser_id	Parser ID (0..3).
bool	enable	true:enble, false:disable.
ethsw_snoop_offset_type_t	offs_type	Snooping mode.
ethsw_snoop_comp_type_t	comp_type	How to handle matched frames.
uint8_t	offset	An offset in bytes to locate the data for comparison within the frame.
uint8_t	comp_value	The value to compare the frame data with at the given offset.
uint8_t	mask_value2	When ETHSW_SNOOP_COMP_8, bitmask for single byte compares. When ETHSW_SNOOP_COMP_8OR, 2nd compare value. When ETHSW_SNOOP_COMP_16 or ETHSW_SNOOP_COMP_16PLUS, least significant bits of a 16-bit compare value.

◆ ethsw_snoop_arith_config_t

struct ethsw_snoop_arith_config_t

Snoop arithmetic config

Data Fields
uint8_t	arith_block	Arithmetic blkoc ID (0..1).
ethsw_snoop_operat_t	operat	Operation of paraser result.
ethsw_snoop_action_t	action	Arithmetic action.

◆ ethsw_eee_t

struct ethsw_eee_t

EEE

Data Fields
bool	enable	State of EEE auto mode (true:enabled/false:disabled)
uint32_t	idle_time	Idle time of EEE.
uint32_t	wakeup_time	Wakeup time of EEE.

◆ ethsw_qos_mode_t

struct ethsw_qos_mode_t

QoS mode

Data Fields
bool	vlan_enable	VLAN Priority Enable.
bool	ip_enable	IP Priority Enable.
bool	mac_enable	MAC Based Priority Enable.
bool	type_enable	TYPE Based Priority Enable.
uint8_t	default_pri	Default Priority Enable Setting.

◆ ethsw_qos_prio_ip_t

struct ethsw_qos_prio_ip_t

QoS IP priority

Data Fields
uint8_t	diffserv	The DiffServ field of the IP packet.
uint8_t	priority	The priority to assign.

◆ ethsw_qos_prio_type_t

struct ethsw_qos_prio_type_t

QoS Ethertype priority

Data Fields
uint16_t	type1	The first type to match against. A value of 0 disables that match.
uint8_t	prio1	The priority to be assigned for the first match.
uint16_t	type2	The second type to match against. A value of 0 disables that match.
uint8_t	prio2	The priority to be assigned for the second match.

◆ ethsw_mirror_conf_t

struct ethsw_mirror_conf_t

mirror port config

Data Fields
uint32_t	mirror_port	The port id that will received all mirrored frames.
ethsw_mirr_mode_t	mirror_mode	The mode of mirroring to configure.
ethsw_port_mask_t	port_map	The port map to which the mirror configuration will be applied to.
ethsw_mac_addr_t *	mac_addr	MAC address pointer.

◆ ethsw_ts_pulse_generator_t

struct ethsw_ts_pulse_generator_t

The parameter for set/get pulse generator.

Data Fields
uint8_t	pulse_num	Pulse generator number (0..3)
bool	enable	When true, enable.
uint32_t	start_sec	Pulse start second.
uint32_t	start_ns	Pulse start nanosecond.
uint16_t	wide	Pulse width.
uint32_t	period_sec	Pulse period second.
uint32_t	period_ns	Pulse period anosecond.

◆ ethsw_tdma_callback_data_t

union ethsw_tdma_callback_data_t

tdma callback data

Data Fields
uint16_t	tcv_s_idx	index of TCV sequence entry (valu of TDMA_IRQ_STAT_ACK_b.TCV_IDX_ACK)

◆ ethsw_tdma_enable_t

struct ethsw_tdma_enable_t

tdma enable parameter

Data Fields
bool	enable
	True is enable, false:disabel.

uint8_t	time_num
	Timer number to use as TDMA time source.

ethsw_port_mask_t	port_mask
	Port mask that TDMA operat.

uint32_t	tdma_start
	Start nano time for the first cycle of TDMA.

uint32_t	tdma_modulo
	System timer modulo for 1 second.

uint32_t	tdma_cycle
	Periodic cycle time for TDMA scheduler.

◆ ethsw_tdma_schedule_entry_t

struct ethsw_tdma_schedule_entry_t

TDMA schedule entry parameter

Data Fields
uint32_t	time_offset	Time offset from the TDMA Cycle Start.
ethsw_port_mask_t	port_mask	Bit mask (one per output port) that controls which queues of the ports are gated, triggered, hold request generation, and which ports change their Cut-Through mode setting.
uint8_t	gate_state	Bit mask, gate state of queue 0 to 7 (bit0:queue0, bit1:queue1, .., bit7:queue7). Value 0 is close, value 1 is open.
uint8_t	gpio_mask	Generic bits that control the output pins ETHSW_TDMAOUT0..3.
bool	interrupt	Indicates this entry generates an interrupt to the CPU when activated.
bool	hold_req	Preemption hold request. Generates a hold request to ports enabled in port_mask.
bool	gate_mode	Gate mode enable when set to 1.
bool	trigger_mode	Trigger mode enable when set to 1. GATE_MODE must be 0, otherwise, GATE_MODE has precedence.
bool	in_ct_ena	Input Cut-Through Enable.
bool	out_ct_ena	Output Cut-Through Enable.
bool	red_period	Period Color Control (for Profinet IRT)
bool	inc_crt1	Increment Control for Counter 1.
bool	inc_crt0	Increment Control for Counter 0.

◆ ethsw_tdma_counter1_t

struct ethsw_tdma_counter1_t

The parameter for set/get TDMA counter 1 function

Data Fields
bool	write_value	When true, set value to counter 1.
uint8_t	value	Setted counter 1 value.
uint8_t	max_value	Maximum value of counter 1.
bool	int_enable	When true, enable counter 1 interrupt.
uint8_t	int_value	Counter 1 value when the interrupt occurred.

◆ ethsw_time_enable_t

struct ethsw_time_enable_t

Timer enable/disable parameter

Data Fields
uint8_t	time_num	Timer number (range is 0..1).
bool	enable	Enables/disables the timer specified by time_num. (true is enable, false is disable)
uint8_t	clock_period	Clock period (specify 8).

◆ ethsw_timestamp_t

struct ethsw_timestamp_t

Timestamp parameter

Data Fields
uint8_t	time_num	Timer number.
uint32_t	time_sec	Second.
uint32_t	time_nsec	Nanosecond.
uint32_t	timestamp_id	Timeatamp ID.

◆ ethsw_time_transmit_t

struct ethsw_time_transmit_t

Transmit timestamp parameter

Data Fields
ethsw_port_mask_t	port_mask
	(Bit0=Port0, Bit1=Port1, Bit2=Port2) More...

void(*	p_time_callback )(ethsw_time_event_t event, uint32_t port, ethsw_timestamp_t *p_timestamp)
	Pointer to the timestamp parameter.

Field Documentation

◆ port_mask

ethsw_port_mask_t ethsw_time_transmit_t::port_mask

(Bit0=Port0, Bit1=Port1, Bit2=Port2)

Per Port Transmit Timestamp Capture Interrupt Enable.

◆ ethsw_time_peerdelay_t

struct ethsw_time_peerdelay_t

Peer delay info

Data Fields
uint8_t	time_num	Timer number.
uint32_t	peerdelay	Peer delay value.

◆ ethsw_time_offset_correction_t

struct ethsw_time_offset_correction_t

offset correction parameter

Data Fields
uint8_t	time_num	Timer number (0 or 1)
uint8_t	offs_inc	Offset correction increment.
uint32_t	offs_corr	Offset correction counter.
uint32_t	offset	Offset correction value.

◆ ethsw_time_rate_correction_t

struct ethsw_time_rate_correction_t

Rate correction parameter

Data Fields
uint8_t	time_num	timer number (0 or 1)
int32_t	rate	Correction rate.

Macro Definition Documentation

◆ ETHSW_PORT_MGMT

#define ETHSW_PORT_MGMT

Management port number.

Ethernet port macros

Typedef Documentation

◆ ethsw_mac_addr_t

typedef uint8_t ethsw_mac_addr_t[ETHSW_MAC_ADDR_LENGTH]

MAC address

◆ ethsw_mmctl_qclosed_nonempty_t

typedef uint8_t ethsw_mmctl_qclosed_nonempty_t[4]

The parameter for QclosedNonempty status

Enumeration Type Documentation

◆ ethsw_specific_tag_t

enum ethsw_specific_tag_t

Enable/Disable Management Port Specific Frame Tagging

Enumerator
ETHSW_SPECIFIC_TAG_DISABLE	Disable.
ETHSW_SPECIFIC_TAG_ENABLE	Enable.

◆ ethsw_phylink_t

enum ethsw_phylink_t

Enable/Disable PHYLINK Change Interrupt

Enumerator
ETHSW_PHYLINK_DISABLE	Disable.
ETHSW_PHYLINK_ENABLE	Enable.

◆ ethsw_link_speed_t

enum ethsw_link_speed_t

Speed and duplex of the port

Enumerator
ETHSW_LINK_SPEED_NO_LINK	Link is not established.
ETHSW_LINK_SPEED_10H	Link status is 10Mbit/s and half duplex.
ETHSW_LINK_SPEED_10F	Link status is 10Mbit/s and full duplex.
ETHSW_LINK_SPEED_100H	Link status is 100Mbit/s and half duplex.
ETHSW_LINK_SPEED_100F	Link status is 100Mbit/s and full duplex.
ETHSW_LINK_SPEED_1000H	Link status is 1000Mbit/s and half duplex.
ETHSW_LINK_SPEED_1000F	Link status is 1000Mbit/s and full duplex.

◆ ethsw_mac_table_clear_mode_t

enum ethsw_mac_table_clear_mode_t

MAC table clear modes

Enumerator
ETHSW_MAC_TABLE_CLEAR_STATIC	Static MAC table entries.
ETHSW_MAC_TABLE_CLEAR_DYNAMIC	Learned MAC table entries.
ETHSW_MAC_TABLE_CLEAR_ALL	Static and learn entries.

◆ ethsw_link_status_t

enum ethsw_link_status_t

Link status

Enumerator
ETHSW_LINK_STATE_DOWN	Link Down.
ETHSW_LINK_STATE_UP	Link Up.

◆ ethsw_dlr_event_t

enum ethsw_dlr_event_t

DLR events for the DLR State Machine

Enumerator
ETHSW_DLR_EVENT_LINKLOST	Link was lost.
ETHSW_DLR_EVENT_OWNFRAME	the device received its own frame
ETHSW_DLR_EVENT_LINKRESTORED	Link is restored.
ETHSW_DLR_EVENT_BEACONFRAME	Beacon Frame received.
ETHSW_DLR_EVENT_BEACONTIMEOUT	Beacon Timer timed out.
ETHSW_DLR_EVENT_NEWSUPERVISOR	a new Ring Supervisor was detected
ETHSW_DLR_EVENT_NEWSTATE	Beacon Hardware detected new state.

◆ ethsw_dlr_beacon_state_t

enum ethsw_dlr_beacon_state_t

DLR beacon frame receive status

Enumerator
ETHSW_DLR_BEACON_INVALID	Not receiving the valid beacon frmae.
ETHSW_DLR_BEACON_VALID	Receiving the valid beacon frmae.

◆ ethsw_dlr_node_state_t

enum ethsw_dlr_node_state_t

DLR node status

Enumerator
ETHSW_DLR_NODE_IDLE	Idole State.
ETHSW_DLR_NODE_NORMAL	Normal State.
ETHSW_DLR_NODE_FAULT	Fault State.

◆ ethsw_rx_pattern_mode_t

enum ethsw_rx_pattern_mode_t

Operating mode of RX Pattern Matcher

Enumerator
ETHSW_RX_PATTER_MODE_FIXED	Mode1: Fixed 12-byte match.
ETHSW_RX_PATTER_MODE_LOOKUP	Mode2: 2-byte lookup mode.
ETHSW_RX_PATTER_MODE_RANGE_MATCH	Mode3: 2-byte range match at set offset.
ETHSW_RX_PATTER_MODE_RANGE_NOT_MATCH	Mode4: 2-byte range not-match at set offset.

◆ ethsw_rx_pattern_event_t

enum ethsw_rx_pattern_event_t

Callback event of the Rx pattern matcher

Enumerator
ETHSW_RX_PATTERN_MATCHER	Rx pattern matcher event.

◆ ethsw_preempt_verify_status_t

enum ethsw_preempt_verify_status_t

Port status of verification for frame preemption

Enumerator
ETHSW_PREEMPT_VERIFY_STATUS_UNKNOWN	Unknown (during reset)
ETHSW_PREEMPT_VERIFY_STATUS_INITIAL	Initial (when preemption is disabled)
ETHSW_PREEMPT_VERIFY_STATUS_VERIFYING	Verifying.
ETHSW_PREEMPT_VERIFY_STATUS_SUCCEEDED	Succeeded.
ETHSW_PREEMPT_VERIFY_STATUS_FAILED	Failed.
ETHSW_PREEMPT_VERIFY_STATUS_DISABLED	Disabled (if preempt verification is disabled)

◆ ethsw_mmctl_qgate_action_t

enum ethsw_mmctl_qgate_action_t

queue gate action

◆ ethsw_mmctl_pool_id_t

enum ethsw_mmctl_pool_id_t

MMCTL pool ID.

Enumerator
ETHSW_MMCTL_POOL_ID_0	Pool 0.
ETHSW_MMCTL_POOL_ID_1	Pool 1.
ETHSW_MMCTL_POOL_ID_GLOBAL	Global Pool.

◆ ethsw_queu_flush_action_t

enum ethsw_queu_flush_action_t

The action of queue flush event.

Enumerator
ETHSW_QUEUE_FLUSH_DISABLE	Disable flush.
ETHSW_QUEUE_FLUSH_WHEN_QUEUE_IS_CLOSING	Flush when queue is closed, discarding any new frames.
ETHSW_QUEUE_FLUSH_WHEN_QUEUE_CLOSE	Flush on queue close until empty, then stops flushing.
ETHSW_QUEUE_FLUSH_TRIGGER	TRIGGER flush until empty, then return to current flush mode.

◆ ethsw_snoop_offset_type_t

enum ethsw_snoop_offset_type_t

Enumerator
ETHSW_SNOOP_OFFS_ETHER1	The offset starts counting from the first byte of the MAC destination address.
ETHSW_SNOOP_OFFS_ETHER2	The offset can either be specified starting after the MAC source address.
ETHSW_SNOOP_OFFS_VLAN	The offset can either be specified starting starting after any optional VLAN tags.
ETHSW_SNOOP_OFFS_IPDATA	The offset can either be specified starting starting after an IP header.
ETHSW_SNOOP_OFFS_IPPROT	The offset is ignored. The compare value is compared with the protocol field located within the IP.

◆ ethsw_snoop_comp_type_t

enum ethsw_snoop_comp_type_t

Enumerator
ETHSW_SNOOP_COMP_8	Applies a bitmask (AND) and compare single byte value.
ETHSW_SNOOP_COMP_8OR	Compare two different single byte value.
ETHSW_SNOOP_COMP_16	Compare a 16-bit value.
ETHSW_SNOOP_COMP_16PLUS	Repeats the 16-bit comparison at offset + 2, if the 16-bit comparison at offset failed.

◆ ethsw_snoop_action_t

enum ethsw_snoop_action_t

Snooping actions

Enumerator
ETHSW_SNOOP_ACTION_DISABLE	Disabled, no snooping occurs (forward normally).
ETHSW_SNOOP_ACTION_ONLY_MGMT	Forward to management port only.
ETHSW_SNOOP_ACTION_COPY_MGMT	Forward normally and copy to management port.
ETHSW_SNOOP_ACTION_DISCARD	Discard the frame.

◆ ethsw_snoop_operat_t

enum ethsw_snoop_operat_t

Enumerator
ETHSW_SNOOP_OPERAT_AND	AND all selected inputs.
ETHSW_SNOOP_OPERAT_OR	OR all selected inputs.

◆ ethsw_mirr_mode_t

enum ethsw_mirr_mode_t

port mirroring modes

Enumerator
ETHSW_MIRR_MODE_DISABLE	Disable.
ETHSW_MIRR_MODE_EGRESS_DA	Enable, Egress DA match.
ETHSW_MIRR_MODE_EGRESS_SA	Enable, Egress SA match.
ETHSW_MIRR_MODE_INGRESS_DA	Enable, Ingress DA match.
ETHSW_MIRR_MODE_INGRESS_SA	Enable, Ingress SA match.
ETHSW_MIRR_MODE_INGRESS_PORT	Enable, Ingress port match.
ETHSW_MIRR_MODE_EGRESS_PORT	Enable, Egress port match.

◆ ethsw_vlan_in_mode_t

enum ethsw_vlan_in_mode_t

VLAN input processing modes

Enumerator
ETHSW_VLANIN_PASSTHROUGH_OVERRIDE	Single Tagging with Passthrough/VID Overwrite.
ETHSW_VLANIN_REPLACE	Single Tagging with Replace.
ETHSW_VLANIN_TAG_ALWAYS	Tag always.
ETHSW_VLANIN_DISABLE	Disable VLAN.

◆ ethsw_vlan_out_mode_t

enum ethsw_vlan_out_mode_t

VLAN output processing mode

Enumerator
ETHSW_VLANOUT_DISABLE	No manipulation.
ETHSW_VLANOUT_STRIP	Strip mode.
ETHSW_VLANOUT_TAGTHROUGH	Tag Thru mode.
ETHSW_VLANOUT_DOMAINTRANSP	Domain / Transparent mode.

◆ ethsw_tdma_event_t

enum ethsw_tdma_event_t

tdma callback event

Enumerator
ETHSW_TDMA_CALLBACK_TCV_INT	Active event of TCV sequence entry.
ETHSW_TDMA_CALLBACK_COUNTER1_INT	Active event of TDMA count1.

◆ ethsw_tdma_gpio_mode_t

enum ethsw_tdma_gpio_mode_t

TDMA GPIO operating mode

Enumerator
ETHSW_TDMA_GPIO_MODE_LEVEL	level mode
ETHSW_TDMA_GPIO_MODE_STROBE	strobe mode
ETHSW_TDMA_GPIO_MODE_TOGGLE	toggle mode

◆ ethsw_time_event_t

enum ethsw_time_event_t

Timer callback event

Function Documentation

◆ R_ETHSW_Open()

fsp_err_t R_ETHSW_Open	(	ether_switch_ctrl_t *const	p_ctrl,
		ether_switch_cfg_t const *const	p_cfg
	)

Open the switch ports and gets it ready to pass through the frames.

Return values

FSP_SUCCESS	Channel opened successfully.
FSP_ERR_ASSERTION	Pointer to ETHER SWITCH control block or configuration structure is NULL.
FSP_ERR_ALREADY_OPEN	Control block has already been opened or channel is being used by another instance. Call close() then open() to reconfigure.
FSP_ERR_INVALID_CHANNEL	Invalid channel number is given.
FSP_ERR_INVALID_ARGUMENT	Interrupt is not enabled.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_Close()

fsp_err_t R_ETHSW_Close ( ether_switch_ctrl_t *const p_ctrl )

Close the switch ports

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened

◆ R_ETHSW_SpeedCfg()

fsp_err_t R_ETHSW_SpeedCfg	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t const	port,
		ethsw_link_speed_t const	speed
	)

Configs speed and duplex of the port

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_MacTableSet()

fsp_err_t R_ETHSW_MacTableSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_mac_table_entry_addr_t *	p_mac_entry_addr,
		ethsw_mac_table_entry_info_t *	p_mac_entry_info
	)

Sets the static MAC address entry for the given MAC address.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_TIMEOUT	Timeout error

◆ R_ETHSW_MacTableGet()

fsp_err_t R_ETHSW_MacTableGet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_mac_table_entry_addr_t *	p_mac_entry_addr,
		ethsw_mac_table_entry_info_t *	p_mac_entry_info
	)

Retrieves the port mask for the given MAC address from the static MAC table.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_TIMEOUT	Timeout error

◆ R_ETHSW_MacTableConfigSet()

fsp_err_t R_ETHSW_MacTableConfigSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_mac_table_config_t *	p_mac_table_config
	)

Configures the MAC learning and aging parameters of MAC table.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_MacTableClear()

fsp_err_t R_ETHSW_MacTableClear	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_mac_table_clear_mode_t *	p_mac_table_clear
	)

Clears specific types of entries from the MAC table or clears the whole table.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.
FSP_ERR_TIMEOUT	Timeout error

◆ R_ETHSW_LearningSet()

fsp_err_t R_ETHSW_LearningSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		bool	enable
	)

Sets learning state for the given port.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_PortForwardAdd()

fsp_err_t R_ETHSW_PortForwardAdd	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port
	)

Enables the forwarding of incoming frames on a port for RSTP.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_PortForwardDel()

fsp_err_t R_ETHSW_PortForwardDel	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port
	)

Disables the forwarding of incoming frames on a port for RSTP

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_FloodUnknownSet()

fsp_err_t R_ETHSW_FloodUnknownSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_flood_unknown_config_t *	p_flood_config
	)

Set the flood domain port masks for frames with unknown destinations

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_LinkStateGet()

fsp_err_t R_ETHSW_LinkStateGet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		ethsw_link_status_t *	p_state_link
	)

Return link state for given port.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_FrameSizeMaxSet()

fsp_err_t R_ETHSW_FrameSizeMaxSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		uint32_t	frame_size_max
	)

Sets maximum frame size of given port.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_DlrInitSet()

fsp_err_t R_ETHSW_DlrInitSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_dlr_init_t *	p_dlr_init
	)

Initialize DLR module

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_TIMEOUT	Timeout error

◆ R_ETHSW_DlrUninitSet()

fsp_err_t R_ETHSW_DlrUninitSet ( ether_switch_ctrl_t *const p_ctrl )

Uninitialize DLR module

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_TIMEOUT	Timeout error

◆ R_ETHSW_DlrEnableSet()

fsp_err_t R_ETHSW_DlrEnableSet ( ether_switch_ctrl_t *const p_ctrl )

Enable DLR module

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

◆ R_ETHSW_DlrDisableSet()

fsp_err_t R_ETHSW_DlrDisableSet ( ether_switch_ctrl_t *const p_ctrl )

Disable DLR module.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

◆ R_ETHSW_DlrBeaconStateGet()

fsp_err_t R_ETHSW_DlrBeaconStateGet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		ethsw_dlr_beacon_state_t *	p_beacon_state
	)

Gets the beacon receive status of the specified port.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_DlrNodeStateGet()

fsp_err_t R_ETHSW_DlrNodeStateGet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_dlr_node_state_t *	p_node_state
	)

Gets DLR node status.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_DlrSvIpGet()

fsp_err_t R_ETHSW_DlrSvIpGet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t *	p_ip_addr
	)

Gets IP address of DLR supervisor.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_DlrSvPriorityGet()

fsp_err_t R_ETHSW_DlrSvPriorityGet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint8_t *	p_priority
	)

Gets preference of DLR supervisor.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_DlrVlanGet()

fsp_err_t R_ETHSW_DlrVlanGet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint16_t *	p_vlan_info
	)

Gets VLAN ID of DLR beacon frame.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_DlrSvMacGet()

fsp_err_t R_ETHSW_DlrSvMacGet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_mac_addr_t *	pp_addr_mac
	)

Gets MAC address of DLR beacon frame.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_RxPatternMatcherSet()

fsp_err_t R_ETHSW_RxPatternMatcherSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_rx_pattern_matcher_t *	p_rx_pattern_matcher
	)

Sets Rx pattern matcher

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_RxPatternMatcherCallback()

fsp_err_t R_ETHSW_RxPatternMatcherCallback	(	ether_switch_ctrl_t *const	p_ctrl,
		void()(ethsw_rx_pattern_event_t event, ethsw_rx_pattern_event_data_t p_data)	p_rx_pattern_callback_func
	)

Register the callback function for getting events from Rx pattern matcher. Unregister if NULL is specified in the callback function.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

◆ R_ETHSW_PreemptQueueSet()

fsp_err_t R_ETHSW_PreemptQueueSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_preempt_queue_t *	p_preempt_queue
	)

Set Preemptable queues configures

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_PreemptPortControlConfigSet()

fsp_err_t R_ETHSW_PreemptPortControlConfigSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		ethsw_preempt_port_ctrl_config_t *	p_preempt_port_ctrl
	)

Set Qbu frame configuration of each ports

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_PreemptPortControlEnableSet()

fsp_err_t R_ETHSW_PreemptPortControlEnableSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		bool	frame_preempt_enable
	)

Enable/Disable Qbu frame preempt at each ports

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_PreemptHoldReqForceSet()

fsp_err_t R_ETHSW_PreemptHoldReqForceSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_port_mask_t	holdreq_request_port_mask
	)

forces a preempt request using MM_CTL.request(hold_req).

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_PreemptHoldReqReleaseSet()

fsp_err_t R_ETHSW_PreemptHoldReqReleaseSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_port_mask_t	holdreq_release_port_mask
	)

forces a release of preemption request using MM_CTL.request(hold_req).

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_PreemptStatusGet()

fsp_err_t R_ETHSW_PreemptStatusGet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		ethsw_preempt_status_t *	p_preempt_status
	)

Get a status of frame preemption

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_MmctlQgateSet()

fsp_err_t R_ETHSW_MmctlQgateSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_mmclt_qgate_t *	p_mmctl_qgate
	)

Sets queue gate.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_MmctlPoolSizeSet()

fsp_err_t R_ETHSW_MmctlPoolSizeSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_mmctl_pool_size_t *	p_pool_size
	)

Sets memory pool size, in sells

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_MmctlQueueAssignSet()

fsp_err_t R_ETHSW_MmctlQueueAssignSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_mmctl_queue_assign_t *	p_queue_assign
	)

Assigns a pool to the specified queue.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_MmctlYellowLengthSet()

fsp_err_t R_ETHSW_MmctlYellowLengthSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		ethsw_yellow_length_t *	p_yellow_length
	)

Sets length in bytes of the YELLOW period for specified port.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_QueueFlushEventSet()

fsp_err_t R_ETHSW_QueueFlushEventSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_queue_flush_event_t *	p_queue_flush_event
	)

Sets Queue Flush Event.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_MmctlQueueClosedNonemptyStatusGet()

fsp_err_t R_ETHSW_MmctlQueueClosedNonemptyStatusGet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_mmctl_qclosed_nonempty_t *	p_qclosed_nonempty
	)

Get the status shows whether there are frames left in the closed queue.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_StatisticsSwitchGet()

fsp_err_t R_ETHSW_StatisticsSwitchGet	(	ether_switch_ctrl_t *const	p_ctrl,
		bool	clear,
		ethsw_statistics_switch_base_t *	p_statistics_switch
	)

Gets Switch Base Statistics counters.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_StatisticsMacGet()

fsp_err_t R_ETHSW_StatisticsMacGet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		ethsw_statistics_mac_t *	p_statistics_mac
	)

Gets MAC Statistics counters for the specified port.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_StatisticsMacClear()

fsp_err_t R_ETHSW_StatisticsMacClear ( ether_switch_ctrl_t *const p_ctrl )

Clears MAC Statistics counters for all ports.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

◆ R_ETHSW_Statistics8023brGet()

fsp_err_t R_ETHSW_Statistics8023brGet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		bool	clear,
		ethsw_statistics_8023br_t *	p_statistics_8023br
	)

Gets Global Discard and 802.3br Statistics counters.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_StatisticsDlrGet()

fsp_err_t R_ETHSW_StatisticsDlrGet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_statistics_dlr_t *	p_statistics_dlr
	)

Gets DLR Statistics counters for the specified port.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_CqfEnableSet()

fsp_err_t R_ETHSW_CqfEnableSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		ethsw_cqf_enable_t *	p_cqf_enable
	)

Sets enable CQF.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_SnoopParserSet()

fsp_err_t R_ETHSW_SnoopParserSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_snoop_parser_config_t *	p_parser_cnf
	)

Sets a snooping parser configuration

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_SnoopArithSet()

fsp_err_t R_ETHSW_SnoopArithSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_snoop_arith_config_t *	p_arith_cnf
	)

Sets snooping arithmetic configuration

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_EeeSet()

fsp_err_t R_ETHSW_EeeSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		ethsw_eee_t *	p_cnf_eee
	)

Enables/disables and configure the Energy Efficient Ethernet Mode of the switch.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_StormTimeSet()

fsp_err_t R_ETHSW_StormTimeSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint16_t	storm_time
	)

Sets the timeframe for the broadcast/multicast rate limiting in ms.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

◆ R_ETHSW_BcastLimitSet()

fsp_err_t R_ETHSW_BcastLimitSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint16_t	storm_frames
	)

Sets the max. allowed broadcast frames that can be received in a given time.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

◆ R_ETHSW_McastLimitSet()

fsp_err_t R_ETHSW_McastLimitSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint16_t	storm_frames
	)

Sets the max. allowed multicast frames that can be received in a given time.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

◆ R_ETHSW_TxRateSet()

fsp_err_t R_ETHSW_TxRateSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		float	rate
	)

Sets the max. allowed bandwidth for the given port in percent.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_QosModeSet()

fsp_err_t R_ETHSW_QosModeSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		ethsw_qos_mode_t *	p_qos_mode
	)

Sets the priority resolution mode to use for a specific port. It also defines the default priority if no priority resolution produced a result.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_QosPrioValnSet()

fsp_err_t R_ETHSW_QosPrioValnSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		ethsw_qos_prio_vlan_t *	p_qos_prio_vlan
	)

Sets the priority mapping between VLAN tag priorities and the switch core priorities.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_QosPrioIpSet()

fsp_err_t R_ETHSW_QosPrioIpSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		ethsw_qos_prio_ip_t *	p_qos_prio_ip
	)

Sets the priority for the given DiffServ field of an IP packet for the given port. Up to 64 different DiffServ entries may be defined per port.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_QosPrioTypeSet()

fsp_err_t R_ETHSW_QosPrioTypeSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_qos_prio_type_t *	p_qos_prio_ethtype
	)

Sets the priority for the given Ethertypes to the given values.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_MirrorSet()

fsp_err_t R_ETHSW_MirrorSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_mirror_conf_t *	p_mirror_conf
	)

Sets the dedicated port that will received all frames that are mirrored as well as the type of mirrored frames.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_CtEnableSet()

fsp_err_t R_ETHSW_CtEnableSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_port_mask_t	port_mask
	)

Sets enable cut-through for the specified port.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

◆ R_ETHSW_CtDelaySet()

fsp_err_t R_ETHSW_CtDelaySet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		uint32_t	ct_delay
	)

Sets the cut-through delay for the specified port, delay Value in 400 ns / 40 ns / 8 ns increments (fequency of the MII PHY interface). This is a programmable value in MII clock cycles that can delay the assertion of the cut-through flag to the forwarding engine in order to hide the variable latency of the forwarding decision.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_PulseGeneratorInit()

fsp_err_t R_ETHSW_PulseGeneratorInit	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	time_num
	)

Initilize pulse generator.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_PulseGeneratorSet()

fsp_err_t R_ETHSW_PulseGeneratorSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_ts_pulse_generator_t *	p_pulse
	)

Sets pulse generator.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_PortAuthSet()

fsp_err_t R_ETHSW_PortAuthSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		bool	auth_state
	)

Sets authorization state for given port.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_PortCtrlDirSet()

fsp_err_t R_ETHSW_PortCtrlDirSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		bool	dir_state
	)

Sets controlled direction for given port.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_PortEapolSet()

fsp_err_t R_ETHSW_PortEapolSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		bool	eapol_state
	)

Sets EAPOL reception mode for given port.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_BpduSet()

fsp_err_t R_ETHSW_BpduSet	(	ether_switch_ctrl_t *const	p_ctrl,
		bool	bpdu_state
	)

Sest Bridge Protocol Frame (BPDU) forwarding mode. Enabling the BPDU forwarding mode this function will also disable the unchecked dropping of BPDU frames.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

◆ R_ETHSW_VlanDefaultSet()

fsp_err_t R_ETHSW_VlanDefaultSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		uint16_t	vlan_id
	)

Sets the default VLAN for input/output processing for the specified port.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_VlanPortAdd()

fsp_err_t R_ETHSW_VlanPortAdd	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		uint16_t	vlan_id
	)

Adds a VLAN for a given port to the VLAN domain table.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_VlanPortRemove()

fsp_err_t R_ETHSW_VlanPortRemove	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		uint16_t	vlan_id
	)

Removes a VLAN for a given port to the VLAN domain table.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_VlanInModeSet()

fsp_err_t R_ETHSW_VlanInModeSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		ethsw_vlan_in_mode_t	vlan_in_mode
	)

Sets the mode of VLAN input operations for the given port.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_VlanOutModeSet()

fsp_err_t R_ETHSW_VlanOutModeSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		ethsw_vlan_out_mode_t	vlan_out_mode
	)

Sets the mode of VLAN output operations for the given port.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_VlanVerifySet()

fsp_err_t R_ETHSW_VlanVerifySet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		bool	enable
	)

Set VLAN verification for the given port.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_VlanDiscardUnknownSet()

fsp_err_t R_ETHSW_VlanDiscardUnknownSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		bool	enable
	)

Set VLAN discartion of unknown frames for the given port.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_TdmaEnableSet()

fsp_err_t R_ETHSW_TdmaEnableSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_tdma_enable_t *	p_tdma_enable
	)

Enable or disable the TDMA scheduler.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_TdmaScheduleSet()

fsp_err_t R_ETHSW_TdmaScheduleSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_tdma_schedule_entry_t *	p_tdma_schedule_entry,
		uint16_t	tdma_schedule_entry_count
	)

Sets the TDMA scheduler entry.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_TdmaGpioModeSet()

fsp_err_t R_ETHSW_TdmaGpioModeSet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint8_t	gpio_num,
		ethsw_tdma_gpio_mode_t	gpio_mode
	)

Sets the operation mode for the specified TDMA_GPIO number.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_TdmaCounter0Set()

fsp_err_t R_ETHSW_TdmaCounter0Set	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	tdma_counter0
	)

Sets TDMA counter 0 The Counter 0 is 32-bit counter that is incremented when the TCV field INC_CTR0 is set to 1.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

◆ R_ETHSW_TdmaCounter0Get()

fsp_err_t R_ETHSW_TdmaCounter0Get	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t *	p_tdma_counter0
	)

Gets TDMA counter 0 The Counter 0 is 32-bit counter that is incremented when the TCV field INC_CTR0 is set to 1.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_TdmaCounter1Set()

fsp_err_t R_ETHSW_TdmaCounter1Set	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_tdma_counter1_t *	p_tdma_counter1
	)

Sets TDMA counter 1 The counter 1 is an 8-bit counter that is incremented when the TCV field INC_CTR1 is set to 1.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_TdmaCounter1Get()

fsp_err_t R_ETHSW_TdmaCounter1Get	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_tdma_counter1_t *	p_tdma_counter1
	)

Gets TDMA counter 1 The counter 1 is an 8-bit counter that is incremented when the TCV field INC_CTR1 is set to 1.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_TdmaHoldReqClear()

fsp_err_t R_ETHSW_TdmaHoldReqClear ( ether_switch_ctrl_t *const p_ctrl )

Clear the TDMA hold request

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

◆ R_ETHSW_TimeEnableSet()

fsp_err_t R_ETHSW_TimeEnableSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_time_enable_t *	p_time_enable
	)

Enables or disables the timer with the specified timer number.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_TimeTransmitTimestampSet()

fsp_err_t R_ETHSW_TimeTransmitTimestampSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_time_transmit_t *	p_time_transmit
	)

Enable Tx timestamping for an external port.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.

◆ R_ETHSW_TimeValueSet()

fsp_err_t R_ETHSW_TimeValueSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_timestamp_t *	p_timestamp
	)

Sets the current time value to the timer with the specified timer number.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_TimeValueGet()

fsp_err_t R_ETHSW_TimeValueGet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_timestamp_t *	p_timestamp
	)

Gets the current time value to the timer with the specified timer number.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.
FSP_ERR_TIMEOUT	Timeout error

◆ R_ETHSW_TimeValueGetAll()

fsp_err_t R_ETHSW_TimeValueGetAll	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_timestamp_t *	p_timer0,
		ethsw_timestamp_t *	p_timer1
	)

Gets the current time value to all timer (timer number 0 and 1).

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_TIMEOUT	Timeout error

◆ R_ETHSW_TimePeerDelaySet()

fsp_err_t R_ETHSW_TimePeerDelaySet	(	ether_switch_ctrl_t *const	p_ctrl,
		uint32_t	port,
		ethsw_time_peerdelay_t *	p_peerdelay
	)

Sets the peer delay value for the specified timer number of the specified port number.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_TimeOffsetSet()

fsp_err_t R_ETHSW_TimeOffsetSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_time_offset_correction_t *	p_offset
	)

Sets the offset correction for the specified timer number.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_TimeRateSet()

fsp_err_t R_ETHSW_TimeRateSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_time_rate_correction_t *	p_rate
	)

Sets clock rate corection for the specified timer.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

◆ R_ETHSW_TimeDomainSet()

fsp_err_t R_ETHSW_TimeDomainSet	(	ether_switch_ctrl_t *const	p_ctrl,
		ethsw_time_domain_t *	p_domain
	)

Sets the domain number for the specified timer.

Return values

FSP_SUCCESS	Command successfully.
FSP_ERR_ASSERTION	Pointer to ETHER control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_POINTER	Pointer to arguments are NULL.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

Functions

Detailed Description

Overview

Features

Configuration

Build Time Configurations for r_ethsw

Configurations for Networking > Ethernet (r_ethsw)

Usage Notes

Limitations

Data Structures

Macros

Typedefs

Enumerations

Data Structure Documentation

◆ ethsw_instance_ctrl_t

◆ ethsw_extend_cfg_t

◆ ethsw_port_mask_t

◆ ethsw_mac_table_entry_addr_t

◆ ethsw_mac_table_entry_info_t

◆ ethsw_mac_table_config_t

◆ ethsw_flood_unknown_config_t

◆ ethsw_dlr_init_t

Data Fields

◆ ethsw_rx_pattern_ctrl_t

◆ ethsw_rx_pattern_data_t

◆ ethsw_rx_pattern_matcher_t

◆ ethsw_rx_pattern_event_data_t

◆ ethsw_preempt_queue_t

◆ ethsw_preempt_port_ctrl_config_t

◆ ethsw_preempt_status_t

◆ ethsw_mmclt_qgate_t

◆ ethsw_mmctl_pool_size_t

◆ ethsw_mmctl_queue_assign_t

◆ ethsw_yellow_length_t

◆ ethsw_queue_flush_event_t

◆ ethsw_cqf_enable_t

◆ ethsw_snoop_parser_config_t

◆ ethsw_snoop_arith_config_t

◆ ethsw_eee_t

◆ ethsw_qos_mode_t

◆ ethsw_qos_prio_ip_t

◆ ethsw_qos_prio_type_t

◆ ethsw_mirror_conf_t

◆ ethsw_ts_pulse_generator_t

◆ ethsw_tdma_callback_data_t

◆ ethsw_tdma_enable_t

Data Fields

◆ ethsw_tdma_schedule_entry_t

◆ ethsw_tdma_counter1_t

◆ ethsw_time_enable_t

◆ ethsw_timestamp_t

◆ ethsw_time_transmit_t

Data Fields

Field Documentation

◆ port_mask

◆ ethsw_time_peerdelay_t

◆ ethsw_time_offset_correction_t

◆ ethsw_time_rate_correction_t

Macro Definition Documentation

◆ ETHSW_PORT_MGMT

Typedef Documentation

◆ ethsw_mac_addr_t

◆ ethsw_mmctl_qclosed_nonempty_t

Enumeration Type Documentation

◆ ethsw_specific_tag_t

◆ ethsw_phylink_t

◆ ethsw_link_speed_t

◆ ethsw_mac_table_clear_mode_t

◆ ethsw_link_status_t

◆ ethsw_dlr_event_t

◆ ethsw_dlr_beacon_state_t

◆ ethsw_dlr_node_state_t

◆ ethsw_rx_pattern_mode_t

◆ ethsw_rx_pattern_event_t

◆ ethsw_preempt_verify_status_t

◆ ethsw_mmctl_qgate_action_t

◆ ethsw_mmctl_pool_id_t

◆ ethsw_queu_flush_action_t

◆ ethsw_snoop_offset_type_t

◆ ethsw_snoop_comp_type_t