PCIE_EP (r_pcie_ep)

Functions
fsp_err_t	R_PCIE_EP_Open (pci_ctrl_t *const p_ctrl, pci_cfg_t const *const p_cfg)
fsp_err_t	R_PCIE_EP_ConfigurationRegisterWrite (pci_ctrl_t *const p_ctrl, pci_configuration_write_type_t transaction_type, pci_configuration_register_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_EP_ConfigurationRegisterRead (pci_ctrl_t *const p_ctrl, pci_configuration_read_type_t transaction_type, pci_configuration_register_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_EP_SelfConfigurationRegisterGet (pci_ctrl_t *const p_ctrl, uint32_t register_number, uint32_t *p_data)
fsp_err_t	R_PCIE_EP_SelfConfigurationRegisterSet (pci_ctrl_t *const p_ctrl, uint32_t register_number, uint32_t data)
fsp_err_t	R_PCIE_EP_IORegisterWrite (pci_ctrl_t *const p_ctrl, pci_io_register_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_EP_IORegisterRead (pci_ctrl_t *const p_ctrl, pci_io_register_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_EP_MessageWrite (pci_ctrl_t *const p_ctrl, pci_message_transfer_t *const p_transfer, bool with_data)
fsp_err_t	R_PCIE_EP_MessageRead (pci_ctrl_t *const p_ctrl, pci_message_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_EP_IntxAssert (pci_ctrl_t *const p_ctrl)
fsp_err_t	R_PCIE_EP_IntxDeassert (pci_ctrl_t *const p_ctrl)
fsp_err_t	R_PCIE_EP_LinkStatusGet (pci_ctrl_t *const p_ctrl, pci_status_t *const p_status)
fsp_err_t	R_PCIE_EP_LinkWidthChange (pci_ctrl_t *const p_ctrl, uint32_t link_width, uint32_t option)
fsp_err_t	R_PCIE_EP_LinkSpeedChange (pci_ctrl_t *const p_ctrl, pci_link_speed_t link_speed, uint32_t option)
fsp_err_t	R_PCIE_EP_LinkEqualizationRequest (pci_ctrl_t *const p_ctrl)
fsp_err_t	R_PCIE_EP_CallbackSet (pci_ctrl_t *const p_ctrl, void(*p_callback)(pci_callback_args_t *), void const *const p_context, pci_callback_args_t *const p_callback_memory)
fsp_err_t	R_PCIE_EP_Close (pci_ctrl_t *const p_ctrl)

Detailed Description

Driver for the PCI peripheral on RZ Microprocessor. This module implements the PCI Interface.

Overview

The PCI Express (PCIE) End Point HAL module supports transactions with an PCIE Root Complex device.

Features

• By accessing the memory space of the RZ Microprocessor, MRd/MWr requests are issued and data is exchanged with the PCIE device.
• The following is possible with Msg/MsgD requests.
  • Msg/MsgD can be sent/received.
• Can be set to either "1 Lane / 2 Channels" or "2 Lanes / 1 Channel".
• Can set its own Configuration Register0, including the Hwinit section, when opened.
• Can read/write its own Configuration Register.
• Can set BAR, PCIe and AXI window.
• INTx interrupts can be issued.
• MSI interrupts can be issued.
• Can get the link status.
• Can be notified when a function level reset is received.
• Two functions can be set.
• Link width can be dynamically changed and user can be notified.
• Link Speed can be dynamically changed.
• Equalization can be requested. Also, user can be notified when equalization is requested.

Configuration

Build Time Configurations for r_pcie_ep

The following build time configurations are defined in fsp_cfg/r_pcie_ep_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Link Mode	2Lanes / 1Channel 1Lane / 2Channels	2Lanes / 1Channel	Link Mode.
Multiplex Interrupt	Enabled Disabled	Disabled	Enable multiplex interrupt for a single driver.

Configurations for Connectivity > PCI (r_pcie_ep)

This module can be added to the Stacks tab via New Stack > Connectivity > PCI (r_pcie_ep).

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_pci_ep0	Module name.
General > Channel	Channel should be 0 or 1	0	Specify the PCIE channel.
General > Function	Function should be 0 or 1	0	Specify the PCIE EP function.
Type 0 Configuration Space Setting > Vender ID / Device ID > Vender ID	Manual Entry	0x0000	Vender ID.
Type 0 Configuration Space Setting > Vender ID / Device ID > Device ID	Manual Entry	0x0000	Device ID.
Type 0 Configuration Space Setting > Command > Memory Space Enable	Disable Enable	Disable	Memory Space Enable.
Type 0 Configuration Space Setting > Command > Bus Master Enable	Disable Enable	Disable	Bus Master Enable.
Type 0 Configuration Space Setting > Command > Parity Error Response	Disable Enable	Disable	Parity Error Response.
Type 0 Configuration Space Setting > Command > SERR# Enable	Disable Enable	Disable	SERR# Enable.
Type 0 Configuration Space Setting > Command > Interrupt Disable	Disable Enable	Disable	Interrupt Disable.
Type 0 Configuration Space Setting > Revision ID / Class Code > Revision ID	Manual Entry	0x00	Revision ID.
Type 0 Configuration Space Setting > Revision ID / Class Code > Class Code	Manual Entry	0x000	Class Code.
Type 0 Configuration Space Setting > Base Address Register 0 / 1 > Type	64bit	64bit	Base Address Register 0 / 1 Type.
Type 0 Configuration Space Setting > Base Address Register 0 / 1 > Prefetch	Disable Enable	Disable	Base Address Register 0 / 1 Prefetch.
Type 0 Configuration Space Setting > Base Address Register 0 / 1 > BAR0	Manual Entry	0x00000000	Base Address Register 0.
Type 0 Configuration Space Setting > Base Address Register 0 / 1 > BAR1	Manual Entry	0x00000000	Base Address Register 1.
Type 0 Configuration Space Setting > Base Address Register 2 / 3 > Type	64bit	64bit	Base Address Register 2 / 3 Type.
Type 0 Configuration Space Setting > Base Address Register 2 / 3 > Prefetch	Disable Enable	Disable	Base Address Register 2 / 3 Prefetch.
Type 0 Configuration Space Setting > Base Address Register 2 / 3 > BAR2	Manual Entry	0x00000000	Base Address Register 2.
Type 0 Configuration Space Setting > Base Address Register 2 / 3 > BAR3	Manual Entry	0x00000000	Base Address Register 3.
Type 0 Configuration Space Setting > Base Address Register 4 / 5 > Type	64bit	64bit	Base Address Register 4 / 5 Type.
Type 0 Configuration Space Setting > Base Address Register 4 / 5 > Prefetch	Disable Enable	Disable	Base Address Register 4 / 5 Prefetch.
Type 0 Configuration Space Setting > Base Address Register 4 / 5 > BAR4	Manual Entry	0x00000000	Base Address Register 4.
Type 0 Configuration Space Setting > Base Address Register 4 / 5 > BAR5	Manual Entry	0x00000000	Base Address Register 5.
Type 0 Configuration Space Setting > Subsystem ID > Subsystem Vendor ID	Manual Entry	0x0000	Subsystem Vendor ID.
Type 0 Configuration Space Setting > Subsystem ID > Subsystem ID	Manual Entry	0x0000	Subsystem ID.
Type 0 Configuration Space Setting > Interrupt Register > Interrupt Pin	Assert_INTA# Assert_INTB# Assert_INTC# Assert_INTD#	Assert_INTA#	Interrupt Pin.
Configuration Register Init List > Name	Name must be a valid C symbol	g_pci_ep0_configuration_register_init_list	Configuration Register Init List symbol name.
Configuration Register Init List > Length	The number of configuration register init lists must be a positive integer.	0	Number of Configuration Register Init List.
AXI Window Setting > AXI Window Setting 0 > Window Enable	Disabled Enabled	Enabled	AXI Window 0 Enable.
AXI Window Setting > AXI Window Setting 0 > AXI Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 0 Base Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 0 > AXI Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	AXI Window 0 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
AXI Window Setting > AXI Window Setting 0 > AXI Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 0 Destination Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 1 > Window Enable	Disabled Enabled	Disabled	AXI Window 1 Enable.
AXI Window Setting > AXI Window Setting 1 > AXI Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 1 Base Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 1 > AXI Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	AXI Window 1 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
AXI Window Setting > AXI Window Setting 1 > AXI Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 1 Destination Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 2 > Window Enable	Disabled Enabled	Disabled	AXI Window 2 Enable.
AXI Window Setting > AXI Window Setting 2 > AXI Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 2 Base Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 2 > AXI Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	AXI Window 2 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
AXI Window Setting > AXI Window Setting 2 > AXI Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 2 Destination Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 3 > Window Enable	Disabled Enabled	Disabled	AXI Window 3 Enable.
AXI Window Setting > AXI Window Setting 3 > AXI Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 3 Base Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 3 > AXI Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	AXI Window 3 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
AXI Window Setting > AXI Window Setting 3 > AXI Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 3 Destination Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 4 > Window Enable	Disabled Enabled	Disabled	AXI Window 4 Enable.
AXI Window Setting > AXI Window Setting 4 > AXI Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 4 Base Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 4 > AXI Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	AXI Window 4 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
AXI Window Setting > AXI Window Setting 4 > AXI Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 4 Destination Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 5 > Window Enable	Disabled Enabled	Disabled	AXI Window 5 Enable.
AXI Window Setting > AXI Window Setting 5 > AXI Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 5 Base Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 5 > AXI Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	AXI Window 5 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
AXI Window Setting > AXI Window Setting 5 > AXI Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 5 Destination Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 6 > Window Enable	Disabled Enabled	Disabled	AXI Window 6 Enable.
AXI Window Setting > AXI Window Setting 6 > AXI Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 6 Base Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 6 > AXI Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	AXI Window 6 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
AXI Window Setting > AXI Window Setting 6 > AXI Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 6 Destination Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 7 > Window Enable	Disabled Enabled	Disabled	AXI Window 7 Enable.
AXI Window Setting > AXI Window Setting 7 > AXI Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 7 Base Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 7 > AXI Window Mask (63bit width, Lower 12bits must be 1y)	Manual Entry	0x0000000000000FFF	AXI Window 7 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
AXI Window Setting > AXI Window Setting 7 > AXI Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 7 Destination Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 0 > Window Enable	Disabled Enabled	Enabled	PCIe Window 0 Enable.
PCIe Window Setting > PCIe Window Setting 0 > PCIe Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 0 Base Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 0 > PCIe Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	PCIe Window 0 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
PCIe Window Setting > PCIe Window Setting 0 > PCIe Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 0 Destination Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 1 > Window Enable	Disabled Enabled	Disabled	PCIe Window 1 Enable.
PCIe Window Setting > PCIe Window Setting 1 > PCIe Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 1 Base Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 1 > PCIe Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	PCIe Window 1 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
PCIe Window Setting > PCIe Window Setting 1 > PCIe Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 1 Destination Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 2 > Window Enable	Disabled Enabled	Disabled	PCIe Window 2 Enable.
PCIe Window Setting > PCIe Window Setting 2 > PCIe Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 2 Base Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 2 > PCIe Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	PCIe Window 2 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
PCIe Window Setting > PCIe Window Setting 2 > PCIe Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 2 Destination Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 3 > Window Enable	Disabled Enabled	Disabled	PCIe Window 3 Enable.
PCIe Window Setting > PCIe Window Setting 3 > PCIe Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 3 Base Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 3 > PCIe Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	PCIe Window 3 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
PCIe Window Setting > PCIe Window Setting 3 > PCIe Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 3 Destination Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 4 > Window Enable	Disabled Enabled	Disabled	PCIe Window 4 Enable.
PCIe Window Setting > PCIe Window Setting 4 > PCIe Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 4 Base Address The address must be 4Kbyte aligned..
PCIe Window Setting > PCIe Window Setting 4 > PCIe Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	PCIe Window 4 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
PCIe Window Setting > PCIe Window Setting 4 > PCIe Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 4 Destination Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 5 > Window Enable	Disabled Enabled	Disabled	PCIe Window 5 Enable.
PCIe Window Setting > PCIe Window Setting 5 > PCIe Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 5 Base Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 5 > PCIe Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	PCIe Window 5 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
PCIe Window Setting > PCIe Window Setting 5 > PCIe Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 5 Destination Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 6 > Window Enable	Disabled Enabled	Disabled	PCIe Window 6 Enable.
PCIe Window Setting > PCIe Window Setting 6 > PCIe Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 6 Base Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 6 > PCIe Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	PCIe Window 6 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
PCIe Window Setting > PCIe Window Setting 6 > PCIe Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 6 Destination Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 7 > Window Enable	Disabled Enabled	Disabled	PCIe Window 7 Enable.
PCIe Window Setting > PCIe Window Setting 7 > PCIe Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 7 Base Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 7 > PCIe Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	PCIe Window 7 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
PCIe Window Setting > PCIe Window Setting 7 > PCIe Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 7 Destination Address. The address must be 4Kbyte aligned.
PCIe Event Interrupt Sources > Event 0	DL_UpDown ASPM L1 Rejected RX_DLLP_PM_ENTER_L23 Enable BME Parity Error Interrupt CA (Completer Abort) Enable AXIM RAM Parity Error Interrupt Request Complete Speed change operation completion Up/Down Configure operation complete	0U	Select which event should trigger an Event interrupt.
PCIe Event Interrupt Sources > Event 1	ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR ERR_REPLAY_LOWER_CORRECTABLE_ERROR ERR_REPLAY_UPPER_CORRECTABLE_ERROR ERR_RPC_REPLAYFIFO_PERR TXB_PARITY_ERR	0U	Select which event should trigger an Event interrupt.
PCIe Event Interrupt Sources > Event 2	D3_hot_err_EN The ability to detect changes in CFG_LTR_MECHANISM	0U	Select which event should trigger an Event interrupt.
Interrupt > Callback	Name must be a valid C symbol	NULL	A user callback function. If this callback function is provided, it is called from the interrupt service routine (ISR).
Interrupt > Function Level Reset (FLR) Interrupt Priority	MCU Specific Options		Function Level Reset (FLR) Interrupt Priority.
Interrupt > Message Receive Interrupt Priority	MCU Specific Options		Message Receive Interrupt Priority.
Interrupt > EVENT Interrupt Priority	MCU Specific Options		EVENT Interrupt Priority.
Interrupt > Non-D0 State transition receive Interrupt Priority	MCU Specific Options		Non-D0 State transition receive Interrupt Priority.
Interrupt > Power OFF Interrupt Priority	MCU Specific Options		Power OFF Interrupt Priority.
Interrupt > PME_Turn_Off Message Interrupt Priority	MCU Specific Options		PME_Turn_Off Message Interrupt Priority.

Clock Configuration

There is no clock configuration for the PCIe module.

Pin Configuration

The following pins are available to connect to an external PCIe device:

• PCIE_REFCLK_P0: Ch0 Reference clock input (Positive)
• PCIE_REFCLK_N0: Ch0 Reference clock input (Negative)
• PCIE_REFCLK_P1: Ch1 Reference clock input (Positive)
• PCIE_REFCLK_N1: Ch1 Reference clock input (Negative)
• PCIE_RXDP_L0: Serial data input 0 (Positive)
• PCIE_RXDN_L0: Serial data input 0 (Negative)
• PCIE_RXDP_L1: Serial data input 1 (Positive)
• PCIE_RXDN_L1: Serial data input 1 (Negative)
• PCIE_TXDP_L0: Serial data output 0 (Positive)
• PCIE_TXDN_L0: Serial data output 0 (Negative)
• PCIE_TXDP_L1: Serial data output 1 (Positive)
• PCIE_TXDN_L1: Serial data output 1 (Negative)
• PCIE_RSTOUT0B: PCIE Reset output ch0 for Root Complex
• PCIE_RSTOUT1B: PCIE Reset output ch1 for Root Complex

Usage Notes

Configuration Register

List of Configuration Register

PCIE Configuration registers are accessed by other PCIe devices or by itself. The PCIE peripehral of RZ microprocessor supports the following configuration registers:

Address Offset	Register Number	Register symbol	Register name
0x000	0	PCI_EP_VID_Fi	Vendor and Device ID Register (Function #i) (i = 0, 1)
0x004	1	PCI_EP_COM_STA_Fi	Command and Status Register (Function #i) (i = 0, 1)
0x008	2	PCI_EP_RID_CC_Fi	Revision ID and Class Code Register (Function #i) (i = 0, 1)
0x00C	3	PCI_EP_CL_HT_Fi	Cache Line and Header Type Register (Function #i) (i = 0, 1)
0x010	4	PCI_EP_BAR0_Fi	Base Address Register 0 (Function #i) (i = 0, 1)
0x014	5	PCI_EP_BAR1_Fi	Base Address Register 1 (Function #i) (i = 0, 1)
0x018	6	PCI_EP_BAR2_Fi	Base Address Register 2 (Function #i) (i = 0, 1)
0x01C	7	PCI_EP_BAR3_Fi	Base Address Register 3 (Function #i) (i = 0, 1)
0x020	8	PCI_EP_BAR4_Fi	Base Address Register 4 (Function #i) (i = 0, 1)
0x024	9	PCI_EP_BAR5_Fi	Base Address Register 5 (Function #i) (i = 0, 1)
0x02C	11	PCI_EP_SUBSID_Fi	Subsystem ID Register (Function #i) (i = 0, 1)
0x034	13	PCI_EP_CP_Fi	Capabilities Pointer Register (Function #i) (i = 0, 1)
0x03C	15	PCI_EP_INT_Fi	Interrupt Register (Function #i) (i = 0, 1)
0x040	16	PCI_EP_PMC_Fi	PM Capabilities Register (Function #i) (i = 0, 1)
0x044	17	PCI_EP_PMSC_Fi	PM Status/Control Register (Function #i) (i = 0, 1)
0x060	24	PCI_EP_PCIEC_Fi	PCI Express Capability Register (Function #i) (i = 0, 1)
0x064	25	PCI_EP_DEVC_Fi	Device Capabilities Register (Function #i) (i = 0, 1)
0x068	26	PCI_EP_DEVCS_Fi	Device Control/Status Register (Function #i) (i = 0, 1)
0x06C	27	PCI_EP_LINKC_Fi	Link Capabilities Register (Function #i) (i = 0, 1)
0x070	28	PCI_EP_LINKCS_Fi	Link Control/Status Register (Function #i) (i = 0, 1)
0x084	33	PCI_EP_DEVC2_Fi	Device Capabilities 2 Register (Function #i) (i = 0, 1)
0x088	34	PCI_EP_DEVCS2_Fi	Device Control 2/Status 2 Register (Function #i) (i = 0, 1)
0x08C	35	PCI_EP_LINKC2_Fi	Link Capabilities 2 Register (Function #i) (i = 0, 1)
0x090	36	PCI_EP_LINCS2_Fi	Link Control 2/Status 2 Register (Function #i) (i = 0, 1)
0x0A0	40	PCI_EP_BARMSK00L_Fi	Base Address Register Mask00 (Lower) Register (Function #i) (i = 0, 1)
0x0A4	41	PCI_EP_BARMSK00U_Fi	Base Address Register Mask00 (Upper) Register (Function #i) (i = 0, 1)
0x0A8	42	PCI_EP_BARMSK01L_Fi	Base Address Register Mask01 (Lower) Register (Function #i) (i = 0, 1)
0x0AC	43	PCI_EP_BARMSK01U_Fi	Base Address Register Mask01 (Upper) Register (Function #i) (i = 0, 1)
0x0B0	44	PCI_EP_BARMSK02L_Fi	Base Address Register Mask02 (Lower) Register (Function #i) (i = 0, 1)
0x0B4	45	PCI_EP_BARMSK02U_Fi	Base Address Register Mask02 (Upper) Register (Function #i) (i = 0, 1)
0x0C8	50	PCI_EP_BSIZE00_01_Fi	Base Size 00/01 Register (Function #i) (i = 0, 1)
0x0CC	51	PCI_EP_BSIZE02_03_Fi	Base Size 02/03 Register (Function #i) (i = 0, 1)
0x0D0	52	PCI_EP_BSIZE04_05_Fi	Base Size 04/05 Register (Function #i) (i = 0, 1)
0x0D4	53	PCI_EP_BSIZE06_Fi	Base Size 06 Register (Function #i) (i = 0, 1)
0x0D8	54	PCI_EP_TSUPPORT00_01_02_Fi	Type Supported 00/01/02 Register (Function #i) (i = 0, 1)
0x0E0	56	PCI_EP_MSICAP_Fi	MSI Capability Register (Function #i) (i = 0, 1)
0x0E4	57	PCI_EP_MSGADR_Fi	Message Address Register (Function #i) (i = 0, 1)
0x0E8	58	PCI_EP_MSGUADR_Fi	Message Upper Address Register (Function #i) (i = 0, 1)
0x0EC	59	PCI_EP_MSGDAT_Fi	Message Data Register (Function #i) (i = 0, 1)
0x0F0	60	PCI_EP_MSKBIT_Fi	Mask Bits Register (Function #i) (i = 0, 1)
0x0F4	61	PCI_EP_PENDBIT_Fi	Pending Bits Register (Function #i) (i = 0, 1)
0x100	64	PCI_EP_ADVERC_Fi	Advanced Error Reporting Capability Register (Function #i) (i = 0, 1)
0x104	65	PCI_EP_UNCESTS_Fi	Uncorrectable Error Status Register (Function #i) (i = 0, 1)
0x108	66	PCI_EP_UNCEMASK_Fi	Uncorrectable Error Mask Register (Function #i) (i = 0, 1)
0x10C	67	PCI_EP_UNCESVY_Fi	Uncorrectable Error Severity Register (Function #i) (i = 0, 1)
0x110	68	PCI_EP_CESTS_Fi	Correctable Error Status Register (Function #i) (i = 0, 1)
0x114	69	PCI_EP_CEMASK_Fi	Correctable Error Mask Register (Function #i) (i = 0, 1)
0x118	70	PCI_EP_ADVECC_Fi	Advanced Error Capabilities and Control Register (Function #i) (i = 0, 1)
0x11C	71	PCI_EP_HLOG0_Fi	Header Log Register 0 (Function #i) (i = 0, 1)
0x120	72	PCI_EP_HLOG1_Fi	Header Log Register 1 (Function #i) (i = 0, 1)
0x124	73	PCI_EP_HLOG2_Fi	Header Log Register 2 (Function #i) (i = 0, 1)
0x128	74	PCI_EP_HLOG3_Fi	Header Log Register 3 (Function #i) (i = 0, 1)
0x150	84	PCI_EP_DEVSNEXTC_Fi	Device Serial Number Extended Capability Register (Function #i) (i = 0, 1)
0x154	85	PCI_EP_SNL_Fi	Serial Number Register (Lower DW) (Function #i) (i = 0, 1)
0x158	86	PCI_EP_SNU_Fi	Serial Number Register (Upper DW) (Function #i) (i = 0, 1)
0x1B0	108	PCI_EP_SPEECH_F0	Secondary PCI Express Extended Capability Header Register (Function #0)
0x1B4	109	PCI_EP_LINC3_F0	Link Control 3 Register (Function #0)
0x1B8	110	PCI_EP_LESTA_F0	Lane Error Status Register (Function #0)
0x1BC	111	PCI_EP_LEQCTI_F0	Lane Equalization Control Register (Function #0)

Initializaiton of Configuration Register

The PCIE_EP driver initializes the configuration register. Users can set the PCI compatible configuration registers up to address 0x40 using the FSP Configuration editor, and the configuration registers above address 0x40 can be set by setting pci_ep_configuration_register_init_t structure. The default template with one entry is shown below:

static const pci_configuration_register_init_t g_pci_ep0_configuration_register_init_list[PCIE_EP_CH0_F0_CONFIG_REG_INIT_LIST_NUM] =
{
    {
        /* Specify Register number.*/
        .register_number = 0x044 / 4,

        /* Value to be set in configuration register. */
        .init_value      = 0x00000100,

        /* Mask setting for values when setting configuration registers. */
        .init_value_mask = R_PCIE0_PCI_EP_PMSC_F0_PMEE_Msk,
    },
};

Access of Configuration Register

The PCIE_EP driver provides an API to access the own configuration space. Use R_PCIE_EP_SelfConfigurationRegisterSet or R_PCIE_EP_SelfConfigurationRegisterGet to access the configuration space of PCIe peripheral of this RZ Microprocessor.

AXI Window settings (PCIe to AXI)

The AXI Window settings are used when MWr/MRd data from PCI Express is transferred to AXI bus (Data Receive operation via MWr/MRd request). Set AXI Window Base and AXI Window Mask in the BAR region. (BAR: PCI Express Configuration Register, Base Address Register)

AXI access address is shown as below.

AXI Access Address = PCIe Access Address - BAR0 - AXI Window Base + AXI Window Destination

Example of AXI Window settings

Element	Setting Value	Settings
BAR0	0x0000_0000_1000_0000	Configuration Register "PCI_EP_BAR0_Fi"/"PCI_EP_BAR1_Fi". Can be set by Stack Configuration.
BAR Mask0	0x0000_0000_0FFF_FFFC	Configuration Register "PCI_EP_BARMSK00L_Fi"/"PCI_EP_BARMSK00U_Fi".
AXI Window Base	0x0000_0000_0010_0000	Can be set by Stack Configuration.
AXI Window Mask	0x0000_0000_0003_FFFF	Can be set by Stack Configuration.
AXI Window Destination	0x0000_0004_0100_0000	Can be set by Stack Configuration.

BAR0 Assigned region : 0x0000_0000_1000_0000 to 0x0000_0000_1FFF_FFFF (256 MB)

AXI Window region : 0x0000_0004_0100_0000 to 0x0000_0004_0103_FFFF (256 KB)

Up to four AXI windows can be configured in each BAR area. Setting examples of AXI windows allocated to each of the BAR areas is as follows:

BAR (Memory space)	Setting example 1	Setting example 2	Setting example 3	Setting example 4
64bit memory space (1) (BAR1,BAR0)	AXI Window 0, AXI Window 1, AXI Window 2, AXI Window 3	AXI Window 0, AXI Window 1, AXI Window 2	AXI Window 0, AXI Window 1	AXI Window 0

BAR (Memory space)	Setting example 1	Setting example 2	Setting example 3	Setting example 4
64bit memory space (2) (BAR3,BAR2)	AXI Window 4, AXI Window 5, AXI Window 6, AXI Window 7	AXI Window 4, AXI Window 5, AXI Window 6	AXI Window 4, AXI Window 5	AXI Window 4

Warning

When configuring the AXI window in the FSP configuration editor, note the following conditions:

• For the AXI Window Base Address setting, the address must be 4Kbyte aligned.
• For the AXI Window Mask setting, the lower 12 bits must be 1, and must be set 1 from the lowest bit. In addition, the 63rd bit must be 0.
• For the AXI Window Destination Address setting, the address must be 4Kbyte aligned.

PCIe Window settings (AXI to PCIe)

PCIe Window settings are used when MWr/MRd data from AXI bus is transferred to PCI Express (Data Transmit operation via MWr/MRd request).

PCIe access address is shown as below.

PCIe Access Address = AXI Access Address - PCIe Window Base + PCIe Window Destination

Example of PCIe Window settings

Element	Setting Value	Settings
BAR0	0x0000_0000_1000_0000	Configuration Register "PCI_EP_BAR0_Fi"/"PCI_EP_BAR1_Fi". Can be set by Stack Configuration.
BAR Mask0	0x0000_0000_07FF_FFFC	Configuration Register "PCI_EP_BARMSK00L_Fi"/"PCI_EP_BARMSK00U_Fi".
PCIe Window Base	0x0000_0000_0070_0000	Can be set by Stack Configuration.
PCIe Window Mask	0x0000_0000_000F_FFFF	Can be set by Stack Configuration.
PCIe Window Destination	0x0000_0004_0070_0000	Can be set by Stack Configuration.

BAR0 Assigned region : 0x0000_0000_1000_0000 to 0x0000_0000_17FF_FFFF (128 MB)

PCIe Window region : 0x0070_0000 to 0x007F_FFFF (1 MB)

Warning

When configuring the PCIe window in the FSP configuration editor, note the following conditions:

• For the PCIe Window Base Address setting, the address must be 4Kbyte aligned.
• For the PCIe Window Mask setting, the lower 12 bits must be 1, and must be set 1 from the lowest bit. In addition, the 63rd bit must be 0.
• For the PCIe Window Destination Address setting, the address must be 4Kbyte aligned.

Address Expander

Using the PCIE_EP HAL driver, other PCIe devices can be accessed through PCIEn space (8GB) or through PCIEn mirror space (256MB) (n=0,1). In particular, if the bus master supports 32-bit address space only, PCIEn space must be accessed through PCIEn mirror space. When using the mirror space, the address expander setting must first be configured in the BSP configuration. Consult Section "Address Expander" in the RZ microprocessor User's Manual for details.

Limitations

Examples

Configuration Space (above address 0x40) Initialization Example

The below is an example of configuration space initialization.

const pci_configuration_register_init_t p_pcie_cfg_reg_init[PCIE_CONFIGURATION_REGISTER_INIT_NUM] =
{
    {
        .register_number = 0x044 / 4,  /* PM Status/Control Register number */
        .init_value      = 0x00000100, /* PMEE = 1 : PME Enable */
        .init_value_mask = R_PCIE0_PCI_EP_PMSC_F0_PMEE_Msk,
    },
};

Basic Example

This is a basic example of minimal use of the PCIE_EP module in an application.

void pcie_ep_example ()
{
    fsp_err_t err = FSP_SUCCESS;

    /* Open PCIE module */
    err = R_PCIE_EP_Open(&g_pci0_ctrl, &g_pci0_cfg);

    /* Handle any errors. This function should be defined by the user. */
    handle_error(err);

    /* Wait for link training from the RC side */
}

Data Structures
struct	pcie_ep_window_settings_t
struct	pcie_ep_instance_ctrl_t
struct	pcie_ep_extended_cfg_t

Enumerations
enum	pcie_ep_link_mode_t

---

Data Structure Documentation

pcie_ep_window_settings_t

struct pcie_ep_window_settings_t

AXI/PCIe window setting structure.

Data Fields
uint64_t	base_address	AXI/PCIe Window Base address.
uint64_t	mask_address	AXI/PCIe Window Mask address.
uint64_t	destination_address	AXI/PCIe Destination address.
bool	window_enable	AXI/PCIe Window setting Enable/Disable.

pcie_ep_instance_ctrl_t

struct pcie_ep_instance_ctrl_t

Driver instance control structure.

pcie_ep_extended_cfg_t

struct pcie_ep_extended_cfg_t

PCIE_EP extension data structure.

Data Fields
pcie_ep_link_mode_t	link_mode	PCI Express Link mode.
pcie_ep_window_settings_t	axi_window_settings[R_PCIE_EP_NUM_AXI_WINDOW]	Settings the AXI Window (PCIe to AXI)
pcie_ep_window_settings_t	pci_window_settings[R_PCIE_EP_NUM_PCIE_WINDOW]	Settings the PCIe Window (AXI to PCIe)
uint32_t	event0_interrupts	Event0 interrupt enable bits.
uint32_t	event1_interrupts	Event1 interrupt enable bits.
uint32_t	event2_interrupts	Event2 interrupt enable bits.
IRQn_Type	msg_irq	PCI Express Message Receive Interrupt Number.
uint8_t	msg_ipl	PCI Express Message Receive Interrupt Priority.
IRQn_Type	flr_irq	Function Level Reset Interrupt Number.
uint8_t	flr_ipl	Function Level Reset Interrupt Priority.
IRQn_Type	d3_event_irq	Non-D0 State transition request receive output interrupt.
uint8_t	d3_event_ipl	Non-D0 State transition request receive output interrupt priority.
IRQn_Type	pme_turn_off_rcv_irq	PME_Turn_Off Message receive interrupt.
uint8_t	pme_turn_off_rcv_ipl	PME_Turn_Off Message receive interrupt priority.
IRQn_Type	poweroff_indication_l2_irq	POWEROFF indication on L2 interrupt.
uint8_t	poweroff_indication_l2_ipl	POWEROFF indication on L2 interrupt priority.
IRQn_Type	pcie_event_irq	Event Interrupt.
uint8_t	pcie_event_ipl	Event Interrupt priority.

Enumeration Type Documentation

pcie_ep_link_mode_t

enum pcie_ep_link_mode_t

PCI Express Link Mode

Enumerator
PCIE_EP_LINK_MODE_2LANE_1CHANNEL	PCIe 2 lanes x 1 channel.
PCIE_EP_LINK_MODE_1LANE_2CHANNEL	PCIe 1 lane x 2 channels.

Function Documentation

R_PCIE_EP_Open()

fsp_err_t R_PCIE_EP_Open	(	pci_ctrl_t *const	p_ctrl,
		pci_cfg_t const *const	p_cfg
	)

Initialize the PCIE_EP API. Implements pci_api_t::open.

Return values

FSP_SUCCESS	PCIE_EP successfully initialized.
FSP_ERR_ASSERTION	Invalid input argument.
FSP_ERR_ALREADY_OPEN	Module is already open.

R_PCIE_EP_ConfigurationRegisterWrite()

fsp_err_t R_PCIE_EP_ConfigurationRegisterWrite	(	pci_ctrl_t *const	p_ctrl,
		pci_configuration_write_type_t	transaction_type,
		pci_configuration_register_transfer_t *const	p_transfer
	)

Issuing CfgWr0/1 Request. API not supported. Implements pci_api_t::configurationRegisterWrite.

Return values

FSP_ERR_UNSUPPORTED

API not supported by PCIE_EP.

R_PCIE_EP_ConfigurationRegisterRead()

fsp_err_t R_PCIE_EP_ConfigurationRegisterRead	(	pci_ctrl_t *const	p_ctrl,
		pci_configuration_read_type_t	transaction_type,
		pci_configuration_register_transfer_t *const	p_transfer
	)

Issuing CfgRd0/1 Request. API not supported. Implements pci_api_t::configurationRegisterRead.

Return values

FSP_ERR_UNSUPPORTED

API not supported by PCIE_EP.

R_PCIE_EP_SelfConfigurationRegisterGet()

fsp_err_t R_PCIE_EP_SelfConfigurationRegisterGet	(	pci_ctrl_t *const	p_ctrl,
		uint32_t	register_number,
		uint32_t *	p_data
	)

Read message data from PCI. Implements pci_api_t::messageRead.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_PCIE_EP_SelfConfigurationRegisterSet()

fsp_err_t R_PCIE_EP_SelfConfigurationRegisterSet	(	pci_ctrl_t *const	p_ctrl,
		uint32_t	register_number,
		uint32_t	data
	)

Updates the value of configuration register of this PCIE device. Implements pci_api_t::selfConfigurationRegisterSet.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_PCIE_EP_IORegisterWrite()

fsp_err_t R_PCIE_EP_IORegisterWrite	(	pci_ctrl_t *const	p_ctrl,
		pci_io_register_transfer_t *const	p_transfer
	)

Issuing IOWr Request. API not supported. Implements pci_api_t::iORegisterWrite.

Return values

FSP_ERR_UNSUPPORTED

API not supported by PCIE_EP.

R_PCIE_EP_IORegisterRead()

fsp_err_t R_PCIE_EP_IORegisterRead	(	pci_ctrl_t *const	p_ctrl,
		pci_io_register_transfer_t *const	p_transfer
	)

Issuing IORd Request. API not supported. Implements pci_api_t::iORegisterRead.

Return values

FSP_ERR_UNSUPPORTED

API not supported by PCIE_EP.

R_PCIE_EP_MessageWrite()

fsp_err_t R_PCIE_EP_MessageWrite	(	pci_ctrl_t *const	p_ctrl,
		pci_message_transfer_t *const	p_transfer,
		bool	with_data
	)

Issuing Msg/MsgD Request. Implements pci_api_t::messageWrite.

Return values

FSP_SUCCESS	The message was issued successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_PCIE_EP_MessageRead()

fsp_err_t R_PCIE_EP_MessageRead	(	pci_ctrl_t *const	p_ctrl,
		pci_message_transfer_t *const	p_transfer
	)

Read message data from PCI. Implements pci_api_t::messageRead.

Return values

FSP_SUCCESS	The message was read successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_PCIE_EP_IntxAssert()

fsp_err_t R_PCIE_EP_IntxAssert

(

pci_ctrl_t *const

p_ctrl

)

Assert INTx interrupt Request. Either INTA - INTD set by configuration register is asserted.

Implements pci_api_t::intxAssert.

Return values

FSP_SUCCESS	The INTx assert is success.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_MODE	This function can't be called when MSI is enabled (MSIE bit in MSI Capability Register equals to 1).

R_PCIE_EP_IntxDeassert()

fsp_err_t R_PCIE_EP_IntxDeassert

(

pci_ctrl_t *const

p_ctrl

)

Deassert INTx interrupt Request. Either INTA - INTD set by configuration register is deasserted.

Implements pci_api_t::intxDeassert.

Return values

FSP_SUCCESS	The INTx deassert is success.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_MODE	This function can't be called when MSI is enabled (MSIE bit in MSI Capability Register equals to 1).

R_PCIE_EP_LinkStatusGet()

fsp_err_t R_PCIE_EP_LinkStatusGet	(	pci_ctrl_t *const	p_ctrl,
		pci_status_t *const	p_status
	)

Gets the Link status and LTSSM state. Implements pci_api_t::linkStatusGet.

Return values

FSP_SUCCESS	The PCI status is in p_status.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_PCIE_EP_LinkWidthChange()

fsp_err_t R_PCIE_EP_LinkWidthChange	(	pci_ctrl_t *const	p_ctrl,
		uint32_t	link_width,
		uint32_t	option
	)

Updates the PCI Express link width. Implements pci_api_t::linkWidthChange.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Required link width is invalid.
FSP_ERR_TIMEOUT	Link Width change was not done in time and timeout occurred.

R_PCIE_EP_LinkSpeedChange()

fsp_err_t R_PCIE_EP_LinkSpeedChange	(	pci_ctrl_t *const	p_ctrl,
		pci_link_speed_t	link_speed,
		uint32_t	option
	)

Updates the PCI Express link speed. Implements pci_api_t::linkSpeedChange.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Required link speed is invalid.
FSP_ERR_TIMEOUT	Link speed change was not done in time and timeout occurred.

R_PCIE_EP_LinkEqualizationRequest()

fsp_err_t R_PCIE_EP_LinkEqualizationRequest

(

pci_ctrl_t *const

p_ctrl

)

Requires the PCI Express link equalization request. Implements pci_api_t::linkEqualizationRequest.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_TIMEOUT	Link Equalization was not done in time and timeout occurred.

R_PCIE_EP_CallbackSet()

fsp_err_t R_PCIE_EP_CallbackSet	(	pci_ctrl_t *const	p_ctrl,
		void(*)(pci_callback_args_t *)	p_callback,
		void const *const	p_context,
		pci_callback_args_t *const	p_callback_memory
	)

Updates the user callback with the option to provide memory for the callback argument structure. Implements pci_api_t::callbackSet.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

R_PCIE_EP_Close()

fsp_err_t R_PCIE_EP_Close

(

pci_ctrl_t *const

p_ctrl

)

Closes the PCIE_EP module. Implements pci_api_t::close.

Return values

FSP_SUCCESS	The module is successfully closed.
FSP_ERR_ASSERTION	Invalid input argument.
FSP_ERR_NOT_OPEN	Module is not open.