PCIE_RC (r_pcie_rc)

Functions
fsp_err_t	R_PCIE_RC_Open (pci_ctrl_t *const p_ctrl, pci_cfg_t const *const p_cfg)
fsp_err_t	R_PCIE_RC_SelfConfigurationRegisterGet (pci_ctrl_t *const p_ctrl, uint32_t register_number, uint32_t *p_data)
fsp_err_t	R_PCIE_RC_SelfConfigurationRegisterSet (pci_ctrl_t *const p_ctrl, uint32_t register_number, uint32_t data)
fsp_err_t	R_PCIE_RC_MessageWrite (pci_ctrl_t *const p_ctrl, pci_message_transfer_t *const p_transfer, bool with_data)
fsp_err_t	R_PCIE_RC_MessageRead (pci_ctrl_t *const p_ctrl, pci_message_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_RC_ConfigurationRegisterWrite (pci_ctrl_t *const p_ctrl, pci_configuration_write_type_t transaction_type, pci_configuration_register_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_RC_ConfigurationRegisterRead (pci_ctrl_t *const p_ctrl, pci_configuration_read_type_t transaction_type, pci_configuration_register_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_RC_IORegisterWrite (pci_ctrl_t *const p_ctrl, pci_io_register_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_RC_IORegisterRead (pci_ctrl_t *const p_ctrl, pci_io_register_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_RC_LinkStatusGet (pci_ctrl_t *const p_ctrl, pci_status_t *const p_status)
fsp_err_t	R_PCIE_RC_IntxAssert (pci_ctrl_t *const p_ctrl)
fsp_err_t	R_PCIE_RC_IntxDeassert (pci_ctrl_t *const p_ctrl)
fsp_err_t	R_PCIE_RC_LinkWidthChange (pci_ctrl_t *const p_ctrl, uint32_t link_width, uint32_t option)
fsp_err_t	R_PCIE_RC_LinkSpeedChange (pci_ctrl_t *const p_ctrl, pci_link_speed_t link_speed, uint32_t option)
fsp_err_t	R_PCIE_RC_LinkEqualizationRequest (pci_ctrl_t *const p_ctrl)
fsp_err_t	R_PCIE_RC_CallbackSet (pci_ctrl_t *const p_ctrl, void(*p_callback)(pci_callback_args_t *), void const *const p_context, pci_callback_args_t *const p_callback_memory)
fsp_err_t	R_PCIE_RC_Close (pci_ctrl_t *const p_ctrl)

Detailed Description

Driver for the PCI peripheral on RZ Microprocessor. This module implements the PCI Interface.

Overview

The PCI Express (PCIE) Root Complex HAL module supports transactions with an PCIE End Point device.

Features

• By accessing the memory space of the RZ Microprocessor, MRd/MWr requests are issued and data is exchanged with the PCIE device.
• The CfgRd0/CfgWr0 requests can be used to read and write to Configuration Register 0 on the EP side.
• The following is possible with Msg/MsgD requests.
  • Msg/MsgD can be sent/received.
  • The Assert_INTx or Deassert_INTx message can be used to receive an INTx interrupt and notify via callback funtion.
  • The user can be notified of receipt of ERR_COR, ERR_NONFATAL, or ERR_FATAL messages. Errors are notified via the ICU_ERROR driver.
• Can be set to either "1 Lane / 2 Channels" or "2 Lanes / 1 Channel".
• Can set its own Configuration Register1, including the Hwinit section, when opened.
• Can read/write its own Configuration Register.
• Can set BAR, PCIe, AXI windows and MSI window.
• It is possible to accept MSI interrupts and notify the user.
• Can get the link status.
• When various events occur due to the PCIEn_INT_PCIE_EVT interrupt, the user can be notified along with the cause.
• Link width can be dynamically changed and user can be notified.
• Link Speed can be dynamically changed.
• Equalization can be requested. Also, user can be notified when equalization is requested.

Configuration

Build Time Configurations for r_pcie_rc

The following build time configurations are defined in fsp_cfg/r_pcie_rc_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Link Mode	2Lanes / 1Channel 1Lane / 2Channels	2Lanes / 1Channel	Link Mode.
Multiplex Interrupt	Enabled Disabled	Disabled	Enable multiplex interrupt for a single driver.

Configurations for Connectivity > PCI (r_pcie_rc)

This module can be added to the Stacks tab via New Stack > Connectivity > PCI (r_pcie_rc).

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_pci_rc0	Module name.
General > Channel	Channel should be 0 or 1	0	Specify the PCIE channel.
Type 1 Configuration Space Setting > Vender ID / Device ID > Vender ID	Manual Entry	0x0000	Vender ID.
Type 1 Configuration Space Setting > Vender ID / Device ID > Device ID	Manual Entry	0x0000	Device ID.
Type 1 Configuration Space Setting > Command > Memory Space Enable	Disable Enable	Disable	Memory Space Enable.
Type 1 Configuration Space Setting > Command > Bus Master Enable	Disable Enable	Disable	Bus Master Enable.
Type 1 Configuration Space Setting > Command > Parity Error Response	Disable Enable	Disable	Parity Error Response.
Type 1 Configuration Space Setting > Command > Assert INTx Interrupt Disable	Disable Enable	Disable	Assert INTx Interrupt Disable.
Type 1 Configuration Space Setting > Revision ID / Class Code > Revision ID	Manual Entry	0x00	Revision ID.
Type 1 Configuration Space Setting > Revision ID / Class Code > Class Code	Manual Entry	0x000	Class Code.
Type 1 Configuration Space Setting > Base Address Register 0 / 1 > Type	64bit	64bit	Base Address Register Type.
Type 1 Configuration Space Setting > Base Address Register 0 / 1 > Prefetch	Disable Enable	Disable	Base Address Register Prefetch.
Type 1 Configuration Space Setting > Base Address Register 0 / 1 > BAR0	Manual Entry	0x00000000	Base Address Register 0.
Type 1 Configuration Space Setting > Base Address Register 0 / 1 > BAR1	Manual Entry	0x00000000	Base Address Register 1.
Configuration Register Init List > Name	Name must be a valid C symbol	g_pci_rc0_configuration_register_init_list	Configuration Register Init List symbol name.
Configuration Register Init List > Length	The number of configuration register init lists must be a positive integer.	0	Number of Configuration Register Init List.
AXI Window Setting > AXI Window Setting 0 > Window Enable	Disabled Enabled	Enabled	AXI Window 0 Enable.
AXI Window Setting > AXI Window Setting 0 > AXI Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 0 Base Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 0 > AXI Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	AXI Window 0 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
AXI Window Setting > AXI Window Setting 0 > AXI Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 0 Destination Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 1 > Window Enable	Disabled Enabled	Disabled	AXI Window 1 Enable.
AXI Window Setting > AXI Window Setting 1 > AXI Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 1 Base Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 1 > AXI Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	AXI Window 1 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
AXI Window Setting > AXI Window Setting 1 > AXI Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 1 Destination Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 2 > Window Enable	Disabled Enabled	Disabled	AXI Window 2 Enable.
AXI Window Setting > AXI Window Setting 2 > AXI Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 2 Base Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 2 > AXI Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	AXI Window 2 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
AXI Window Setting > AXI Window Setting 2 > AXI Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 2 Destination Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 3 > Window Enable	Disabled Enabled	Disabled	AXI Window 3 Enable.
AXI Window Setting > AXI Window Setting 3 > AXI Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 3 Base Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 3 > AXI Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	AXI Window 3 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
AXI Window Setting > AXI Window Setting 3 > AXI Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 3 Destination Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 4 > Window Enable	Disabled Enabled	Disabled	AXI Window 4 Enable.
AXI Window Setting > AXI Window Setting 4 > AXI Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 4 Base Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 4 > AXI Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	AXI Window 4 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
AXI Window Setting > AXI Window Setting 4 > AXI Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 4 Destination Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 5 > Window Enable	Disabled Enabled	Disabled	AXI Window 5 Enable.
AXI Window Setting > AXI Window Setting 5 > AXI Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 5 Base Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 5 > AXI Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	AXI Window 5 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
AXI Window Setting > AXI Window Setting 5 > AXI Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 5 Destination Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 6 > Window Enable	Disabled Enabled	Disabled	AXI Window 6 Enable.
AXI Window Setting > AXI Window Setting 6 > AXI Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 6 Base Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 6 > AXI Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	AXI Window 6 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
AXI Window Setting > AXI Window Setting 6 > AXI Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 6 Destination Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 7 > Window Enable	Disabled Enabled	Disabled	AXI Window 7 Enable.
AXI Window Setting > AXI Window Setting 7 > AXI Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 7 Base Address. The address must be 4Kbyte aligned.
AXI Window Setting > AXI Window Setting 7 > AXI Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	AXI Window 7 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
AXI Window Setting > AXI Window Setting 7 > AXI Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	AXI Window 7 Destination Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 0 > Window Enable	Disabled Enabled	Enabled	PCIe Window 0 Enable.
PCIe Window Setting > PCIe Window Setting 0 > PCIe Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 0 Base Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 0 > PCIe Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	PCIe Window 0 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
PCIe Window Setting > PCIe Window Setting 0 > PCIe Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 0 Destination Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 1 > Window Enable	Disabled Enabled	Disabled	PCIe Window 1 Enable.
PCIe Window Setting > PCIe Window Setting 1 > PCIe Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 1 Base Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 1 > PCIe Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	PCIe Window 1 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
PCIe Window Setting > PCIe Window Setting 1 > PCIe Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 1 Destination Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 2 > Window Enable	Disabled Enabled	Disabled	PCIe Window 2 Enable.
PCIe Window Setting > PCIe Window Setting 2 > PCIe Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 2 Base Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 2 > PCIe Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	PCIe Window 2 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
PCIe Window Setting > PCIe Window Setting 2 > PCIe Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 2 Destination Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 3 > Window Enable	Disabled Enabled	Disabled	PCIe Window 3 Enable.
PCIe Window Setting > PCIe Window Setting 3 > PCIe Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 3 Base Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 3 > PCIe Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	PCIe Window 3 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
PCIe Window Setting > PCIe Window Setting 3 > PCIe Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 3 Destination Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 4 > Window Enable	Disabled Enabled	Disabled	PCIe Window 4 Enable. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 4 > PCIe Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 4 Base Address.
PCIe Window Setting > PCIe Window Setting 4 > PCIe Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	PCIe Window 4 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
PCIe Window Setting > PCIe Window Setting 4 > PCIe Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 4 Destination Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 5 > Window Enable	Disabled Enabled	Disabled	PCIe Window 5 Enable.
PCIe Window Setting > PCIe Window Setting 5 > PCIe Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 5 Base Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 5 > PCIe Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	PCIe Window 5 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
PCIe Window Setting > PCIe Window Setting 5 > PCIe Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 5 Destination Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 6 > Window Enable	Disabled Enabled	Disabled	PCIe Window 6 Enable.
PCIe Window Setting > PCIe Window Setting 6 > PCIe Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 6 Base Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 6 > PCIe Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	PCIe Window 6 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
PCIe Window Setting > PCIe Window Setting 6 > PCIe Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 6 Destination Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 7 > Window Enable	Disabled Enabled	Disabled	PCIe Window 7 Enable.
PCIe Window Setting > PCIe Window Setting 7 > PCIe Window Base (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 7 Base Address. The address must be 4Kbyte aligned.
PCIe Window Setting > PCIe Window Setting 7 > PCIe Window Mask (63bit width, Lower 12bits must be 1)	Manual Entry	0x0000000000000FFF	PCIe Window 7 Mask. The address of lower 12bits must be 1 and 63th bit must be 0.
PCIe Window Setting > PCIe Window Setting 7 > PCIe Window Destination (64bit width, 4KB boundary)	Manual Entry	0x0000000000000000	PCIe Window 7 Destination Address. The address must be 4Kbyte aligned.
MSI Setting > MSI Window > Window Enable	Disabled Enabled	Disabled	MSI Window Enable.
MSI Setting > MSI Window > MSI Receive Window Address (64bit width)	Manual Entry	0x0000000000000000	MSI Receive Window Address. The address must be aligned according to MSI Receive Window Mask.
MSI Setting > MSI Window > MSI Receive Window Mask (63bit width, Lower 2bits must be 1)	Manual Entry	0x0000000000000003	MSI Receive Window Mask. The address of lower 2bits must be 1.
PCIe Event Interrupt Sources > Event 0	DL_UpDown ASPM L1 Rejected RX_DLLP_PM_ENTER_L23 CA (Completer Abort) Request Complete Speed change operation completion Up/Down Configure operation complete	0U	Select which event should trigger an Event interrupt.
PCIe Event Interrupt Sources > Event 1	ERR_REPLAY_LOWER_UNCORRECTABLE_ERROR ERR_REPLAY_UPPER_UNCORRECTABLE_ERROR ERR_REPLAY_LOWER_CORRECTABLE_ERROR ERR_REPLAY_UPPER_CORRECTABLE_ERROR ERR_RPC_REPLAYFIFO_PERR TXB_PARITY_ERR	0U	Select which event should trigger an Event interrupt.
Interrupt > Callback	Name must be a valid C symbol	NULL	A user callback function. If this callback function is provided, it is called from the interrupt service routine (ISR).
Interrupt > INTA Interrupt Priority	MCU Specific Options		INTA Interrupt Priority.
Interrupt > INTB Interrupt Priority	MCU Specific Options		INTB Interrupt Priority.
Interrupt > INTC Interrupt Priority	MCU Specific Options		INTC Interrupt Priority.
Interrupt > INTD Interrupt Priority	MCU Specific Options		INTD Interrupt Priority.
Interrupt > MSI Interrupt Priority	MCU Specific Options		MSI Interrupt Priority.
Interrupt > Message Receive Interrupt Priority	MCU Specific Options		Message Receive Interrupt Priority.
Interrupt > EVENT Interrupt Priority	MCU Specific Options		EVENT Interrupt Priority.
Interrupt > Power OFF Interrupt Priority	MCU Specific Options		Power OFF Interrupt Priority.
Interrupt > Link Width Change Interrupt Priority	MCU Specific Options		Link Width Change Interrupt Priority.
Interrupt > Link Equalization Request Interrupt Priority	MCU Specific Options		Link Equalization Request Interrupt Priority.

Warning

When configuring the MSI window in the FSP configuration editor, note the following conditions:

• For the MSI Window Mask setting, the lower 2 bits must be 1, and the 63rd bit must be 0.
• For the MSI Window Address setting, it must be aligned with the size set by MSI Window Mask.

Clock Configuration

There is no clock configuration for the PCIe module.

Pin Configuration

The following pins are available to connect to an external PCIe device:

• PCIE_REFCLK_P0: Ch0 Reference clock input (Positive)
• PCIE_REFCLK_N0: Ch0 Reference clock input (Negative)
• PCIE_REFCLK_P1: Ch1 Reference clock input (Positive)
• PCIE_REFCLK_N1: Ch1 Reference clock input (Negative)
• PCIE_RXDP_L0: Serial data input 0 (Positive)
• PCIE_RXDN_L0: Serial data input 0 (Negative)
• PCIE_RXDP_L1: Serial data input 1 (Positive)
• PCIE_RXDN_L1: Serial data input 1 (Negative)
• PCIE_TXDP_L0: Serial data output 0 (Positive)
• PCIE_TXDN_L0: Serial data output 0 (Negative)
• PCIE_TXDP_L1: Serial data output 1 (Positive)
• PCIE_TXDN_L1: Serial data output 1 (Negative)
• PCIE_RSTOUT0B: PCIE Reset output ch0 for Root Complex
• PCIE_RSTOUT1B: PCIE Reset output ch1 for Root Complex

Usage Notes

Configuration Register

List of Configuration Register

PCIE Configuration registers are accessed by other PCIe devices or by itself. The PCIE peripehral of RZ microprocessor supports the following configuration registers:

Address Offset	Register Number	Register symbol	Register name
0x000	0	PCI_RC_VID	Vendor and Device ID Register
0x004	1	PCI_RC_COM_STA	Command and Status Register
0x008	2	PCI_RC_RID_CC	Revision ID and Class Code Register
0x00C	3	PCI_RC_CL_HT	Cache Line and Header Type Register
0x010	4	PCI_RC_BAR0	Base Address Register 0
0x014	5	PCI_RC_BAR1	Base Address Register 1
0x018	6	PCI_RC_BNR	Bus Number Register
0x01C	7	PCI_RC_IOBL_SS	I/O Base/Limit and Secondary Status Register
0x020	8	PCI_RC_MEMBL	Memory Base/Limit Register
0x024	9	PCI_RC_PMBL	Prefetchable Memory Base/Limit Register
0x028	10	PCI_RC_PBUP32	Prefetchable Base Upper 32bits Register
0x02C	11	PCI_RC_PLUP32	Prefetchable Limit Upper 32bits Register
0x030	12	PCI_RC_IOBLUP16	I/O Base/Limit Upper 16bits Register
0x034	13	PCI_RC_CP	Capability Pointer Register
0x03C	15	PCI_RC_BC_INT	Bridge Control and Interrupt Register
0x040	16	PCI_RC_PMC PM	Capabilities Register
0x044	17	PCI_RC_PMSC	PM Status/Control Register
0x060	24	PCI_RC_PCIEC	PCI Express Capability Register
0x064	25	PCI_RC_DEVC	Device Capabilities Register
0x068	26	PCI_RC_DEVCS	Device Control/Status Register
0x06C	27	PCI_RC_LINKC	Link Capabilities Register
0x070	28	PCI_RC_LINKCS	Link Control/Status Register
0x074	29	PCI_RC_SLOTC	Slot Capabilities Register
0x078	30	PCI_RC_SLOTCS	Slot Control/Status Register
0x07C	31	PCI_RC_ROOTCC	Root Control/Capabilities Register
0x080	32	PCI_RC_ROOTS	Root Status Register
0x084	33	PCI_RC_DEVC2	Device Capabilities 2 Register
0x088	34	PCI_RC_DEVCS2	Device Control 2/Status 2 Register
0x08C	35	PCI_RC_LINKC2	Link Capabilities 2 Register
0x090	36	PCI_RC_LINCS2	Link Control 2/Status 2 Register
0x0A0	40	PCI_RC_BARMSK00L	Base Address Register Mask 00 (Lower) Register
0x0A4	41	PCI_RC_BARMSK00U	Base Address Register Mask 00 (Upper) Register
0x0C8	50	PCI_RC_BSIZE00_01	Base Size 00/01 Register
0x0D8	54	PCI_RC_TSUPPORT00_01_02	Type Supported 00/01/02 Register
0x100	64	PCI_RC_ADVERC	Advanced Error Reporting Capability Register
0x104	65	PCI_RC_UNCESTS	Uncorrectable Error Status Register
0x108	66	PCI_RC_UNCEMASK	Uncorrectable Error Mask Register
0x10C	67	PCI_RC_UNCESVY	Uncorrectable Error Severity Register
0x110	68	PCI_RC_CESTS	Correctable Error Status Register
0x114	69	PCI_RC_CEMASK	Correctable Error Mask Register
0x118	70	PCI_RC_ADVECC	Advanced Error Capabilities and Control Register
0x11C	71	PCI_RC_HLOG0	Header Log Register 0
0x120	72	PCI_RC_HLOG1	Header Log Register 1
0x124	73	PCI_RC_HLOG2	Header Log Register 2
0x128	74	PCI_RC_HLOG3	Header Log Register 3
0x12C	75	PCI_RC_ROOTEC	Root Error Command Register
0x130	76	PCI_RC_ROOTES	Root Error Status Register
0x134	77	PCI_RC_ERRSI	Error Source Identification Register
0x150	84	PCI_RC_DEVSNEXTC	Device Serial Number Extended Capability Register
0x154	85	PCI_RC_SNL	Serial Number Register (Lower DW) Register
0x158	86	PCI_RC_SNU	Serial Number Register (Upper DW) Register
0x1B0	108	PCI_RC_SPEECH	Secondary PCI Express Extended Capability Header Register
0x1B4	109	PCI_RC_LINC3	Link Control 3 Register
0x1B8	110	PCI_RC_LESTA	Lane Error Status Register
0x1BC	111	PCI_RC_LEQCTL	Lane Equalization Control Register

Initializaiton of Configuration Register

The PCIE_RC driver initializes the configuration register, in paticular, the registers with the HwInit attribute can only be initialized in R_PCIE_RC_Open. Users can set the PCI compatible configuration registers up to address 0x40 using the FSP Configuration editor, and the configuration registers above address 0x40 can be set by setting pci_rc_configuration_register_init_t structure. The default template with one entry is shown below:

static const pci_configuration_register_init_t g_pci_rc0_configuration_register_init_list[PCIE_RC_CH0_CONFIG_REG_INIT_LIST_NUM] =
{
    {
        /* Specify Register number.*/
        .register_number = 0x06C / 4,

        /* Value to be set in configuration register. */
        .init_value      = 0x00000C00,

        /* Mask setting for values when setting configuration registers. */
        .init_value_mask = R_PCIE0_PCI_RC_LINKC_ASPMS_Msk,
    },
};

Access of Configuration Register

The PCIE_RC driver provides an API to access the own configuration space. Use R_PCIE_RC_SelfConfigurationRegisterSet or R_PCIE_RC_SelfConfigurationRegisterGet to access the configuration space of PCIe peripheral of this RZ Microprocessor, and R_PCIE_RC_ConfigurationRegisterWrite or R_PCIE_RC_ConfigurationRegisterRead to access the configuration space on the endpoint side.

Link retraining via configuration space

For example, to retrain the link, set the Retrain Link bits of "PCI_RC_LINKCS: Link Control/Status Register" (address offset = 0x070, register number = 28) in the configuration space to 1.

Interrupt Handling

The following events cause an interrupt and notify the user via callback function :

• Link width change
• Link Equalization Request

The status of these interrupts is indicated by Link Bandwidth Management Status bit (30 bit) / Link Autonomous Bandwidth Status (31 bit) in "PCI_RC_LINKCS : Link Control/Status Register" (address offset = 0x070, register number = 28) or Link Equalization Request (21 bit) in "PCI_RC_LINCS2 : Link Control 2/Status 2 Register" (address offset = 0x090, register number = 36).

These registers are located in the configuration space and must be cleared by the user after interrupt handling. HAL Driver does not clear these bits.

Error Handling

The PCI Express provides three types of error interrupts: Correctable, Fatal and Non Fatal.

Error interrupt callbacks will pass either PCI_RC_EVENT_CORRECTABLE_ERROR, PCI_RC_EVENT_UNCORRECTABLE_ERROR_NON_FATAL or PCI_RC_EVENT_UNCORRECTABLE_ERROR_FATAL in the pci_rc_callback_args_t::event field. Users can mask the error factor by setting "PCI_RC_UNCEMASK : Uncorrectable Error Mask Register" (address offset = 0x108, register number = 66) and "PCI_RC_CEMASK : Correctable Error Mask Register" (offset = 0x114, register number = 69) in the PCI configuration space.

The status of the error that occurred can be get via "PCI_RC_UNCESTS : Uncorrectable Error Status Register" (address offset = 0x104, regisister number = 65) and "PCI_RC_CESTS : Correctable Error Status Register" (address offset = 0x110, register number = 68) in the configuration space. After the error is notified via the callback function, the user must clear the error factor.

The PCIE outputs an error signal to the ICU. ICU can output PERI_ERRn interrupt (Peripherals error event n) to GIC or cause error reset when ICU accepts error signal from PCIE. To use PERI_ERRn interrupt or reset at PCIE, Interruput Controller Unit (ICU) ERROR (r_icu_error) need to be configured. When the PERI_ERRn interrupt is configured to use interrupt and triggered, the callback function registered during open is called.

AXI Window settings (PCIe to AXI)

The AXI Window settings are used when MWr/MRd data from PCI Express is transferred to AXI bus (Data Receive operation via MWr/MRd request). Set AXI Window Base and AXI Window Mask in the BAR region. (BAR: PCI Express Configuration Register, Base Address Register)

AXI access address is shown as below.

AXI Access Address = PCIe Access Address - BAR0 - AXI Window Base + AXI Window Destination

Example of AXI Window settings

Element	Setting Value	Settings
BAR0	0x0000_0000_1000_0000	Configuration Register "PCI_RC_BAR0"/"PCI_RC_BAR1". Can be set by Stack Configuration.
BAR Mask0	0x0000_0000_0FFF_FFFC	Configuration Register "PCI_RC_BARMSK00L"/"PCI_RC_BARMSK00U".
AXI Window Base	0x0000_0000_0010_0000	Can be set by Stack Configuration.
AXI Window Mask	0x0000_0000_0003_FFFF	Can be set by Stack Configuration.
AXI Window Destination	0x0000_0004_0100_0000	Can be set by Stack Configuration.

BAR0 Assigned region : 0x0000_0000_1000_0000 to 0x0000_0000_1FFF_FFFF (256 MB)

AXI Window region : 0x0100_0000 to 0x0103_FFFF (256 KB)

Warning

When configuring the AXI window in the FSP configuration editor, note the following conditions:

• For the AXI Window Base Address setting, the address must be 4Kbyte aligned.
• For the AXI Window Mask setting, the loweer 12 bits must be 1, and must be set 1 from the lowest bit. In addition, the 63rd bit must be 0.
• For the AXI Window Destination Address setting, the address must be 4Kbyte aligned.

PCIe Window settings (AXI to PCIe)

PCIe Window settings are used when MWr/MRd data from AXI bus is transferred to PCI Express (Data Transmit operation via MWr/MRd request).

PCIe access address is shown as below.

PCIe Access Address = AXI Access Address - PCIe Window Base + PCIe Window Destination

Example of PCIe Window settings

Element	Setting Value	Settings
BAR0	0x0000_0000_1000_0000	Configuration Register "PCI_RC_BAR0"/"PCI_RC_BAR1". Can be set by Stack Configuration.
BAR Mask0	0x0000_0000_07FF_FFFC	Configuration Register "PCI_RC_BARMSK00L"/"PCI_RC_BARMSK00U".
PCIe Window Base	0x0000_0000_0070_0000	Can be set by Stack Configuration.
PCIe Window Mask	0x0000_0000_000F_FFFF	Can be set by Stack Configuration.
PCIe Window Destination	0x0000_0004_0070_0000	Can be set by Stack Configuration.

BAR0 Assigned region : 0x0000_0000_1000_0000 to 0x0000_0000_17FF_FFFF (128 MB)

PCIe Window region : 0x0070_0000 to 0x007F_FFFF (1 MB)

Warning

When configuring the PCIe window in the FSP configuration editor, note the following conditions:

• For the PCIe Window Base Address setting, the address must be 4Kbyte aligned.
• For the PCIe Window Mask setting, the lower 12 bits must be 1, and must be set 1 from the lowest bit. In addition, the 63rd bit must be 0.
• For the PCIe Window Destination Address setting, the address must be 4Kbyte aligned.

Address Expander

Using the PCIE_RC HAL driver, other PCIe devices can be accessed through PCIEn space (8GB) or through PCIEn mirror space (256MB) (n=0,1). In particular, if the bus master supports 32-bit address space only, PCIEn space must be accessed through PCIEn mirror space. When using the mirror space, the address expander setting must first be configured in the BSP configuration. Consult Section "Address Expander" in the RZ microprocessor User's Manual for details.

Limitations

Examples

Configuration Space (above address 0x40) Initialization Example

The below is an example of configuration space initialization.

const pci_configuration_register_init_t p_pcie_cfg_reg_init[PCIE_CONFIGURATION_REGISTER_INIT_NUM] =
{
    {
        .register_number = 0x06C / 4,  /* Link Capabilities Register number */
        .init_value      = 0x00000C00, /* ASPMS[1:0] = 3 : L0s and L1 Entry Supported */
        .init_value_mask = R_PCIE0_PCI_RC_LINKC_ASPMS_Msk,
    },
    {
        .register_number = 0x070 / 4,  /* Link Control/Status Register number */
        .init_value      = 0x00000C03, /* ASPMC[1:0] = 3 : L0s and L1 Entry Supported
                                        * LBMIE = 1      : Link Bandwidth Management Interrupt Enable
                                        * LABIE = 1      : Link Autonomous Bandwidth Interrupt Enable */
        .init_value_mask = R_PCIE0_PCI_RC_LINKCS_LABIE_Msk | R_PCIE0_PCI_RC_LINKCS_LBMIE_Msk |
                           R_PCIE0_PCI_RC_LINKCS_ASPMC_Msk,
    },
};

Basic Example

This is a basic example of minimal use of the PCIE_RC module in an application.

#define CFG_REG_COMMAND_AND_STATUS_REGISTER_NUM     (1)
#define CFG_REG_LINK_CONTROL_STATUS_REGISTER_NUM    (28)

#define PCIE_EXAMPLE_WRITE_DATA                     (0x12345678U)

uint32_t read_data;

void pcie_rc_example (void)
{
    fsp_err_t err = FSP_SUCCESS;

    /* Open PCIE module */
    err = R_PCIE_RC_Open(&g_pci0_ctrl, &g_pci0_cfg);

    /* Handle any errors. This function should be defined by the user. */
    handle_error(err);

    /* Link retrain */
    pci_status_t link_status;
    do
    {
        /* Set RL (Retrain Link) bit of Link Control/Status Register to 1 for link retraining. */
        uint32_t linkcs;
        (void) R_PCIE_RC_SelfConfigurationRegisterGet(&g_pci0_ctrl, CFG_REG_LINK_CONTROL_STATUS_REGISTER_NUM, &linkcs);
        linkcs |= R_PCIE0_PCI_RC_LINKCS_RL_Msk;
        (void) R_PCIE_RC_SelfConfigurationRegisterSet(&g_pci0_ctrl, CFG_REG_LINK_CONTROL_STATUS_REGISTER_NUM, linkcs);

        (void) R_PCIE_RC_LinkStatusGet(&g_pci0_ctrl, &link_status);
    } while (true != link_status.is_link_up);

    /* Bus Master and Memory space Enable */
    uint32_t com_sta;
    R_PCIE_RC_SelfConfigurationRegisterGet(&g_pci0_ctrl, CFG_REG_COMMAND_AND_STATUS_REGISTER_NUM, &com_sta);
    com_sta |= (R_PCIE0_PCI_RC_COM_STA_MSE_Msk | R_PCIE0_PCI_RC_COM_STA_BME_Msk);
    R_PCIE_RC_SelfConfigurationRegisterSet(&g_pci0_ctrl, CFG_REG_COMMAND_AND_STATUS_REGISTER_NUM, com_sta);

    /* After R_PCIE_RC_Open() and any required device specific initialization, data can be write/read directly to/from the PCIE_EP device.
     * Set PCIEn space address or PCIEn mirror space address as PCIE0_SPACE_BASE.
     * When access via PCIEn mirror space, need to configure the address expander in advance. */
    *((volatile uint32_t *) PCIE0_SPACE_BASE) = PCIE_EXAMPLE_WRITE_DATA;

    read_data = *((volatile uint32_t *) PCIE0_SPACE_BASE);

    /* Verify the read_data. */
    if (read_data != PCIE_EXAMPLE_WRITE_DATA)
    {
        /* Verify error. */
        __BKPT(0);
    }
}

PCIE_RC Interrupt Handling via Callback Example

This is an example of a PCIE_RC callback when Link width change / Link Equalization Request event occurred.

#define CFG_REG_LINK_CONTROL_STATUS_REGISTER_NUM        (28)
#define CFG_REG_LINK_CONTROL_2_STATUS_2_REGISTER_NUM    (36)

void user_pcie_rc_interrupt_handling_callback (pci_callback_args_t * p_args)
{
    if (PCI_EVENT_LINK_WIDTH_CHANGE == p_args->event)
    {
        /* User must clear the Link Bandwidth Management Status bit (bit 30) and the Link Autonomous Status bit (bit 31)
         * in the Link Control/Status Register (Configuration register offset 0x70) in the user callback function.  */
        uint32_t linkcs;
        R_PCIE_RC_SelfConfigurationRegisterGet(&g_pci0_ctrl, CFG_REG_LINK_CONTROL_STATUS_REGISTER_NUM, &linkcs);
        linkcs |= (R_PCIE0_PCI_RC_LINKCS_LBMS_Msk | R_PCIE0_PCI_RC_LINKCS_LABS_Msk);
        R_PCIE_RC_SelfConfigurationRegisterSet(&g_pci0_ctrl, CFG_REG_LINK_CONTROL_STATUS_REGISTER_NUM, linkcs);

        /* Dummy read to ensure that interrupt event is cleared. */
        uint32_t dummy;
        R_PCIE_RC_SelfConfigurationRegisterGet(&g_pci0_ctrl, CFG_REG_LINK_CONTROL_STATUS_REGISTER_NUM, &dummy);

        /* Add application code when Link Band Change event occurred. */
    }

    if (PCI_EVENT_LINK_EQUALIZATION_REQUEST == p_args->event)
    {
        /* User must clear the Link Equalization Request bit (bit 21) in the Link Control 2 / Status 2 Register
         * (Configuration register offset 0x90) in the user callback function. */
        uint32_t linkcs2;
        R_PCIE_RC_SelfConfigurationRegisterGet(&g_pci0_ctrl, CFG_REG_LINK_CONTROL_2_STATUS_2_REGISTER_NUM, &linkcs2);
        linkcs2 |= R_PCIE0_PCI_RC_LINKCS2_LER_Msk;
        R_PCIE_RC_SelfConfigurationRegisterSet(&g_pci0_ctrl, CFG_REG_LINK_CONTROL_2_STATUS_2_REGISTER_NUM, linkcs2);

        /* Dummy read to ensure that interrupt event is cleared. */
        uint32_t dummy;
        R_PCIE_RC_SelfConfigurationRegisterGet(&g_pci0_ctrl, CFG_REG_LINK_CONTROL_2_STATUS_2_REGISTER_NUM, &dummy);

        /* Add application code when Link Equalization event occurred. */
    }
}

PCIE_RC Error Handling via Callback Example

This is an example of a PCIE_RC callback when error occurred.

#define CFG_REG_UNCORRECTABLE_ERROR_STATUS_REGISTER_NUM    (65)
#define CFG_REG_CORRECTABLE_ERROR_STATUS_REGISTER_NUM      (68)

void user_pcie_rc_error_callback (pci_callback_args_t * p_args)
{
    if (PCI_EVENT_CORRECTABLE_ERROR == p_args->event)
    {
        /* Read Correctable Error Status Register. */
        uint32_t cests;
        R_PCIE_RC_SelfConfigurationRegisterGet(&g_pci0_ctrl, CFG_REG_CORRECTABLE_ERROR_STATUS_REGISTER_NUM, &cests);

        /* Add application code when correctable error occurred. */
    }

    if (PCI_EVENT_UNCORRECTABLE_ERROR_NON_FATAL == p_args->event)
    {
        /* Read Uncorrectable Error Status Register. */
        uint32_t uncests;
        R_PCIE_RC_SelfConfigurationRegisterGet(&g_pci0_ctrl, CFG_REG_UNCORRECTABLE_ERROR_STATUS_REGISTER_NUM, &uncests);

        /* Add application code when uncorrectable error occurred. */
    }

    if (PCI_EVENT_UNCORRECTABLE_ERROR_FATAL == p_args->event)
    {
        /* Read Uncorrectable Error Status Register. */
        uint32_t uncests;
        R_PCIE_RC_SelfConfigurationRegisterGet(&g_pci0_ctrl, CFG_REG_UNCORRECTABLE_ERROR_STATUS_REGISTER_NUM, &uncests);

        /* Add application code when uncorrectable error occurred. */
    }
}

Data Structures
struct	pcie_rc_window_settings_t
struct	pcie_rc_msi_window_settings_t
struct	pcie_rc_instance_ctrl_t
struct	pcie_rc_extended_cfg_t

Enumerations
enum	pcie_rc_link_mode_t

---

Data Structure Documentation

pcie_rc_window_settings_t

struct pcie_rc_window_settings_t

AXI/PCIe window setting structure.

Data Fields
uint64_t	base_address	AXI/PCIe Window Base address.
uint64_t	mask_address	AXI/PCIe Window Mask address.
uint64_t	destination_address	AXI/PCIe Destination address.
bool	window_enable	AXI/PCIe Window setting Enable/Disable.

pcie_rc_msi_window_settings_t

struct pcie_rc_msi_window_settings_t

MSI window setting structure.

Data Fields
uint64_t	base_address	MSI Receive Window Base address.
uint64_t	mask_address	MSI Receive Window Mask Address.
bool	window_enable	MSI Receive Window setting Enable/Disable.

pcie_rc_instance_ctrl_t

struct pcie_rc_instance_ctrl_t

Driver instance control structure.

pcie_rc_extended_cfg_t

struct pcie_rc_extended_cfg_t

PCIE_RC extension data structure.

Data Fields
pcie_rc_link_mode_t	link_mode	PCI Express Link mode.
pcie_rc_window_settings_t	axi_window_settings[R_PCIE_RC_NUM_AXI_WINDOW]	Settings the AXI Window (PCIe to AXI)
pcie_rc_window_settings_t	pci_window_settings[R_PCIE_RC_NUM_PCIE_WINDOW]	Settings the PCIe Window (AXI to PCIe)
pcie_rc_msi_window_settings_t	msi_window_setting	Setting the MSI Window.
uint32_t	event0_interrupts	Event0 interrupt enable bits.
uint32_t	event1_interrupts	Event1 interrupt enable bits.
IRQn_Type	msg_irq	Message Receive Interrupt Number.
uint8_t	msg_ipl	Message Receive Interrupt Priority.
IRQn_Type	link_width_change_irq	Link width change interrupt.
uint8_t	link_width_change_ipl	Link width change interrupt priority.
IRQn_Type	link_equalization_request_irq	Link Equalization Request interrupt.
uint8_t	link_equalization_request_ipl	Link Equalization Request interrupt priority.
IRQn_Type	poweroff_indication_l2_irq	POWEROFF indication on L2 interrupt.
uint8_t	poweroff_indication_l2_ipl	POWEROFF indication on L2 interrupt priority.
IRQn_Type	pcie_event_irq	Event Interrupt.
uint8_t	pcie_event_ipl	Event Interrupt priority.

Enumeration Type Documentation

pcie_rc_link_mode_t

enum pcie_rc_link_mode_t

PCI Express Link Mode

Enumerator
PCIE_RC_LINK_MODE_2LANE_1CHANNEL	PCIe 2 lanes x 1 channel.
PCIE_RC_LINK_MODE_1LANE_2CHANNEL	PCIe 1 lane x 2 channels.

Function Documentation

R_PCIE_RC_Open()

fsp_err_t R_PCIE_RC_Open	(	pci_ctrl_t *const	p_ctrl,
		pci_cfg_t const *const	p_cfg
	)

Initialize the PCIE_RC API. Implements pci_api_t::open.

Return values

FSP_SUCCESS	PCIE_RC successfully initialized.
FSP_ERR_ASSERTION	Invalid input argument.
FSP_ERR_ALREADY_OPEN	Module is already open.

R_PCIE_RC_SelfConfigurationRegisterGet()

fsp_err_t R_PCIE_RC_SelfConfigurationRegisterGet	(	pci_ctrl_t *const	p_ctrl,
		uint32_t	register_number,
		uint32_t *	p_data
	)

Gets the value of configuration register of this PCIE. Implements pci_api_t::selfConfigurationRegisterGet.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

R_PCIE_RC_SelfConfigurationRegisterSet()

fsp_err_t R_PCIE_RC_SelfConfigurationRegisterSet	(	pci_ctrl_t *const	p_ctrl,
		uint32_t	register_number,
		uint32_t	data
	)

Updates the value of configuration register of this PCIE device. Implements pci_api_t::selfConfigurationRegisterSet.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

R_PCIE_RC_MessageWrite()

fsp_err_t R_PCIE_RC_MessageWrite	(	pci_ctrl_t *const	p_ctrl,
		pci_message_transfer_t *const	p_transfer,
		bool	with_data
	)

Issuing Msg/MsgD Request. Implements pci_api_t::messageWrite.

Return values

FSP_SUCCESS	The message was issued successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_PCIE_RC_MessageRead()

fsp_err_t R_PCIE_RC_MessageRead	(	pci_ctrl_t *const	p_ctrl,
		pci_message_transfer_t *const	p_transfer
	)

Read message data from PCI. Implements pci_api_t::messageRead.

Return values

FSP_SUCCESS	The message was read successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_PCIE_RC_ConfigurationRegisterWrite()

fsp_err_t R_PCIE_RC_ConfigurationRegisterWrite	(	pci_ctrl_t *const	p_ctrl,
		pci_configuration_write_type_t	transaction_type,
		pci_configuration_register_transfer_t *const	p_transfer
	)

Issuing CfgWr0/1 Request. Implements pci_api_t::configurationRegisterWrite.

Return values

FSP_SUCCESS	The configuration write was issued successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_PCIE_RC_ConfigurationRegisterRead()

fsp_err_t R_PCIE_RC_ConfigurationRegisterRead	(	pci_ctrl_t *const	p_ctrl,
		pci_configuration_read_type_t	transaction_type,
		pci_configuration_register_transfer_t *const	p_transfer
	)

Issuing CfgRd0/1 Request. Implements pci_api_t::configurationRegisterRead.

Return values

FSP_SUCCESS	The configuration write was issued successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_PCIE_RC_IORegisterWrite()

fsp_err_t R_PCIE_RC_IORegisterWrite	(	pci_ctrl_t *const	p_ctrl,
		pci_io_register_transfer_t *const	p_transfer
	)

Issuing IOWr Request. API not supported. Implements pci_api_t::iORegisterWrite.

Return values

FSP_ERR_UNSUPPORTED

API not supported by PCIE_RC.

R_PCIE_RC_IORegisterRead()

fsp_err_t R_PCIE_RC_IORegisterRead	(	pci_ctrl_t *const	p_ctrl,
		pci_io_register_transfer_t *const	p_transfer
	)

Issuing IORd Request. API not supported. Implements pci_api_t::iORegisterRead.

Return values

FSP_ERR_UNSUPPORTED

API not supported by PCIE_RC.

R_PCIE_RC_LinkStatusGet()

fsp_err_t R_PCIE_RC_LinkStatusGet	(	pci_ctrl_t *const	p_ctrl,
		pci_status_t *const	p_status
	)

Gets the Link status and LTSSM state. Implements pci_api_t::linkStatusGet.

Return values

FSP_SUCCESS	The PCI status is in p_status.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_PCIE_RC_IntxAssert()

fsp_err_t R_PCIE_RC_IntxAssert

(

pci_ctrl_t *const

p_ctrl

)

Assert INTx interrupt Request. API not supported.

Implements pci_api_t::intxAssert.

Return values

FSP_ERR_UNSUPPORTED

API not supported by PCIE_RC.

R_PCIE_RC_IntxDeassert()

fsp_err_t R_PCIE_RC_IntxDeassert

(

pci_ctrl_t *const

p_ctrl

)

Deassert INTx interrupt Request. API not supported.

Implements pci_api_t::intxDeassert.

Return values

FSP_ERR_UNSUPPORTED

API not supported by PCIE_RC.

R_PCIE_RC_LinkWidthChange()

fsp_err_t R_PCIE_RC_LinkWidthChange	(	pci_ctrl_t *const	p_ctrl,
		uint32_t	link_width,
		uint32_t	option
	)

Updates the PCI Express link width. Implements pci_api_t::linkWidthChange.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Required link width is invalid.
FSP_ERR_TIMEOUT	Link Width change was not done in time and timeout occurred.

R_PCIE_RC_LinkSpeedChange()

fsp_err_t R_PCIE_RC_LinkSpeedChange	(	pci_ctrl_t *const	p_ctrl,
		pci_link_speed_t	link_speed,
		uint32_t	option
	)

Updates the PCI Express link speed. Implements pci_api_t::linkSpeedChange.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_INVALID_ARGUMENT	Required link speed is invalid.
FSP_ERR_TIMEOUT	Link speed change was not done in time and timeout occurred.

R_PCIE_RC_LinkEqualizationRequest()

fsp_err_t R_PCIE_RC_LinkEqualizationRequest

(

pci_ctrl_t *const

p_ctrl

)

Requires the PCI Express link equalization request. Implements pci_api_t::linkEqualizationRequest.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_TIMEOUT	Link Equalization was not done in time and timeout occurred.

R_PCIE_RC_CallbackSet()

fsp_err_t R_PCIE_RC_CallbackSet	(	pci_ctrl_t *const	p_ctrl,
		void(*)(pci_callback_args_t *)	p_callback,
		void const *const	p_context,
		pci_callback_args_t *const	p_callback_memory
	)

Updates the user callback with the option to provide memory for the callback argument structure. Implements pci_api_t::callbackSet.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

R_PCIE_RC_Close()

fsp_err_t R_PCIE_RC_Close

(

pci_ctrl_t *const

p_ctrl

)

Closes the PCIE_RC module. Implements pci_api_t::close.

Return values

FSP_SUCCESS	The module is successfully closed.
FSP_ERR_ASSERTION	Invalid input argument.
FSP_ERR_NOT_OPEN	Module is not open.