Functions
fsp_err_t	RM_ETHERCAT_SSC_PORT_Open (ethercat_ssc_port_ctrl_t const p_ctrl, ethercat_ssc_port_cfg_t const const p_cfg)
	EtherCAT Slave Controller is initialized with this function. This function includes PHY initialization and ESC EEPROM loading. Afterwards, EtherCAT communication begins. Also EtherCAT interrupts are permitted if the interrupts are used. In order to receive the EtherCAT, EtherCAT Sync0, EtherCAT Sync1 interrupt event, it's necessary to register a callback function. Implements ethercat_ssc_port_api_t::open. More...

fsp_err_t	RM_ETHERCAT_SSC_PORT_Close (ethercat_ssc_port_ctrl_t *const p_ctrl)

Detailed Description

Middleware for EtherCAT Slave Stack Code (SSC) on RZ microprocessors. This module implements the EtherCAT SSC Interface.

Overview

This module provides the hardware port layer for EtherCAT Slave Stack Code. The control target is the EtherCAT Slave Controller (ESC). This module uses the EtherCAT slave stack code generated by the SSC tools provided by Beckhoff Automation GmbH. Users must register as a member of the EtherCAT Technology Group (ETG) to obtain SSC tools.:https://www.ethercat.org/en/downloads/downloads_01DCC32A10294F2EA866F7E46FB0285F.htm After initializing this module, refer to the SSC API reference to use the EtherCAT slave stack. The hardware access layer API referenced from the stack are also implemented. Please include renesashw.h in the stack source file which has hardware access.

Features

The EtherCAT SSC port module supports the following features:

Number of EtherCAT ports: 3
Interrupts: EtherCAT interrupt, Sync0 interrupt, Sync1 interrupt
Hardware access layer specified by SSC (including timer)
Initialize ESC and PHY to enable EtherCAT communication

Configuration

Build Time Configurations for rm_ethercat_ssc_port

The following build time configurations are defined in fsp_cfg/rm_ethercat_ssc_port_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Reset Port	MCU Specific Options		Specify port number of ESC_RESETOUT#

Configurations for Networking > EtherCAT SSC Port (rm_ethercat_ssc_port)

This module can be added to the Stacks tab via New Stack > Networking > EtherCAT SSC Port (rm_ethercat_ssc_port).

Configuration	Options	Default	Description
PHY > Reset Signal Hold Time (ms)	Manual Entry	1	Time to keep the PHY reset signal low.
PHY > Reset Wait Time (us)	Manual Entry	15000	Wait time to access the PHY register after the PHY reset signal is released.
PHY > Offset Address	Manual Entry	0	The offset address of PHY in case of using the EtherCAT.
Delay Time of TXC > Port 0	0 ns 10 ns 20 ns 30 ns	0 ns	Set the delay time for TXC of the Port 0
Delay Time of TXC > Port 1	0 ns 10 ns 20 ns 30 ns	0 ns	Set the delay time for TXC of the Port 1
Delay Time of TXC > Port 2	0 ns 10 ns 20 ns 30 ns	0 ns	Set the delay time for TXC of the Port 2
Interrupts > EtherCAT Interrupt Priority	MCU Specific Options		Select the EtherCAT interrupt priority.
Interrupts > EtherCAT SYNC0 Interrupt Priority	MCU Specific Options		Select the EtherCAT SYNC0 interrupt priority.
Interrupts > EtherCAT SYNC1 Interrupt Priority	MCU Specific Options		Select the EtherCAT SYNC1 interrupt priority.
Interrupts > Callback	Name must be a valid C symbol	NULL	Callback provided when an ISR occurs
Name	Name must be a valid C symbol	g_ethercat_ssc_port0	Module name.
EEPROM Size	Under 32Kbits Over 32Kbits	Under 32Kbits	Specify whether to use Normal or Inverted.

Clock Configuration

This module is used to configure the system clocks. There are no module specific clock configurations required to use it.

Pin Configuration

The RM_ETHERCAT_SSC_PORT module is used for configuring pins.

Usage Notes

Limitations

Developers should be aware of the following limitations when using the RM_ETHERCAT_SSC_PORT:

Port configuration is EtherCAT port only.

ETHERCAT SSC Port Basic Example

This is a basic example of minimal use of the ETHERCAT SSC Port in an application.

void ethercat_ssc_port_basic_example (void)
{
    fsp_err_t err = FSP_SUCCESS;
    /* Initializes the module before using the EtherCAT Slave Stack. */
    /* The instance of EtherCAT SSC Port instance can be accessed as gp_ether_cat_ssc_port */
    err = RM_ETHERCAT_SSC_PORT_Open(gp_ethercat_ssc_port->p_ctrl, gp_ethercat_ssc_port->p_cfg);
    /* Handle any errors. This function should be defined by the user. */
    handle_error(err);
    /* Close the module after using the EtherCAT Slave Stack. */
    RM_ETHERCAT_SSC_PORT_Close(gp_ethercat_ssc_port->p_ctrl);
}
/* Example callback called when EtherCAT interrupt. */
void ssc_port_callback (ethercat_ssc_port_callback_args_t * p_args)
{
    switch (p_args->event)
    {
        case ETHERCAT_SSC_PORT_EVENT_ESC_CAT_INTERRUPT:
        {
/* ESC CAT Interrupt application */
            break;
        }
        case ETHERCAT_SSC_PORT_EVENT_ESC_SYNC0_INTERRUPT:
        {
/* ESC SYNC0 Interrupt application */
            break;
        }
        case ETHERCAT_SSC_PORT_EVENT_ESC_SYNC1_INTERRUPT:
        {
/* ESC SYNC1 Interrupt application */
            break;
        }
        default:
        {
            /* Do Nothing! */
        }
    }
}

Data Structures
struct	ethercat_ssc_port_instance_ctrl_t

struct	ethercat_ssc_port_extend_cfg_t

Enumerations
enum	ethercat_ssc_port_eeprom_size_t

enum	ethercat_ssc_port_txc_delay_t

Data Structure Documentation

◆ ethercat_ssc_port_instance_ctrl_t

struct ethercat_ssc_port_instance_ctrl_t

EtherCAT SSC port control block. DO NOT INITIALIZE. Initialization occurs when ethercat_ssc_port_api_t::open is called.

Data Fields
uint32_t	open	Flag to indicate if EtherCAT SSC port instance has been initialized.
ethercat_ssc_port_cfg_t const *	p_cfg	Pointer to initial configurations.
R_ESC_INI_Type *	p_reg_ini	Pointer to EtherCAT Initial Configuration registers.
R_ESC_Type *	p_reg	Pointer to EtherCAT Slave Controller registers.

◆ ethercat_ssc_port_extend_cfg_t

struct ethercat_ssc_port_extend_cfg_t

Extended configuration

Data Fields
ethercat_ssc_port_eeprom_size_t	eeprom_size	EEPROM memory size.
ethercat_ssc_port_txc_delay_t	txc0	Port 0 TXC delay time.
ethercat_ssc_port_txc_delay_t	txc1	Port 1 TXC delay time.
ethercat_ssc_port_txc_delay_t	txc2	Port 2 TXC delay time.
ether_phy_instance_t const *	p_ether_phy_instance[BSP_FEATURE_ESC_MAX_PORTS]	Pointer to ETHER_PHY instance.

Enumeration Type Documentation

◆ ethercat_ssc_port_eeprom_size_t

enum ethercat_ssc_port_eeprom_size_t

EEPROM memory size of the EtherCAT

Enumerator
ETHERCAT_SSC_PORT_EEPROM_SIZE_UNDER_32KBIT	Up to 16KBit.
ETHERCAT_SSC_PORT_EEPROM_SIZE_OVER_32KBIT	32KBit to 4MBit

◆ ethercat_ssc_port_txc_delay_t

enum ethercat_ssc_port_txc_delay_t

Delay time of TXC

Enumerator
ETHERCAT_SSC_PORT_TXC_DELAY_00NS	0 ns
ETHERCAT_SSC_PORT_TXC_DELAY_10NS	10 ns
ETHERCAT_SSC_PORT_TXC_DELAY_20NS	20 ns
ETHERCAT_SSC_PORT_TXC_DELAY_30NS	30 ns

Function Documentation

◆ RM_ETHERCAT_SSC_PORT_Open()

fsp_err_t RM_ETHERCAT_SSC_PORT_Open	(	ethercat_ssc_port_ctrl_t *const	p_ctrl,
		ethercat_ssc_port_cfg_t const *const	p_cfg
	)

EtherCAT Slave Controller is initialized with this function. This function includes PHY initialization and ESC EEPROM loading. Afterwards, EtherCAT communication begins. Also EtherCAT interrupts are permitted if the interrupts are used. In order to receive the EtherCAT, EtherCAT Sync0, EtherCAT Sync1 interrupt event, it's necessary to register a callback function. Implements ethercat_ssc_port_api_t::open.

Return values

FSP_SUCCESS	Opened successfully
FSP_ERR_ASSERTION	A required input pointer is NULL
FSP_ERR_ALREADY_OPEN	Control block has already been opened
FSP_ERR_INVALID_ARGUMENT	Irq number lower then 0.
FSP_ERR_INVALID_HW_CONDITION	ESC EEPROM loading error
FSP_ERR_TIMEOUT	ESC EEPROM loading timeout error

◆ RM_ETHERCAT_SSC_PORT_Close()

fsp_err_t RM_ETHERCAT_SSC_PORT_Close ( ethercat_ssc_port_ctrl_t *const p_ctrl )

Disables interrupts. Removes power and releases hardware lock. Implements ethercat_ssc_port_api_t::close.