Serial Communications Interface (SCI) UART (r_sci_uart)

Functions
fsp_err_t	R_SCI_UART_Open (uart_ctrl_t *const p_ctrl, uart_cfg_t const *const p_cfg)
fsp_err_t	R_SCI_UART_Read (uart_ctrl_t *const p_ctrl, uint8_t *const p_dest, uint32_t const bytes)
fsp_err_t	R_SCI_UART_Write (uart_ctrl_t *const p_ctrl, uint8_t const *const p_src, uint32_t const bytes)
fsp_err_t	R_SCI_UART_BaudSet (uart_ctrl_t *const p_ctrl, void const *const p_baud_setting)
fsp_err_t	R_SCI_UART_InfoGet (uart_ctrl_t *const p_ctrl, uart_info_t *const p_info)
fsp_err_t	R_SCI_UART_Close (uart_ctrl_t *const p_ctrl)
fsp_err_t	R_SCI_UART_Abort (uart_ctrl_t *const p_ctrl, uart_dir_t communication_to_abort)
fsp_err_t	R_SCI_UART_BaudCalculate (sci_uart_baud_calculation_t const *const p_baud_target, sci_uart_clock_source_t clock_source, sci_baud_setting_t *const p_baud_setting)
fsp_err_t	R_SCI_UART_CallbackSet (uart_ctrl_t *const p_ctrl, void(*p_callback)(uart_callback_args_t *), void const *const p_context, uart_callback_args_t *const p_callback_memory)
fsp_err_t	R_SCI_UART_ReadStop (uart_ctrl_t *const p_ctrl, uint32_t *remaining_bytes)

Detailed Description

Driver for the SCI peripheral on RZ microprocessor. This module implements the UART Interface.

Overview

Features

The SCI UART module supports the following features:

• Full-duplex UART communication
• Interrupt-driven data transmission and reception
• Invoking the user-callback function with an event code (RX/TX complete, TX data empty, RX char, error, etc)
• Baud-rate change at run-time
• Bit rate modulation and noise cancellation
• CTS/RTS hardware flow control (with an associated pin)
• RS-485 Half Duplex driver support with external RS-485 transceiver
• Integration with the DMAC transfer module
• Abort in-progress read/write operations
• FIFO support on supported channels

Configuration

Build Time Configurations for r_sci_uart

The following build time configurations are defined in fsp_cfg/r_sci_uart_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
FIFO Support	Enable Disable	Disable	Enable FIFO support for the SCI_UART module.
DMAC Support	Enable Disable	Disable	Enable DMAC support for the SCI_UART module. Even if DMAC support is enabled, DMAC is not used without adding DMAC driver.
Flow Control Support	Enable Disable	Disable	Enable flow control support using a user provided pin.
Multiplex Interrupt	Enabled Disabled	Disabled	Enable multiplex interrupt for a single driver.

Configurations for Connectivity > UART (r_sci_uart)

This module can be added to the Stacks tab via New Stack > Connectivity > UART (r_sci_uart).

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_uart0	Module name.
General > Channel	Value must be an integer between 0 and 5	0	Select the SCI channel. Do not select the safety channel when using DMAC.
General > Data Bits	8bits 7bits 9bits	8bits	Select the number of bits per word.
General > Parity	None Odd Even	None	Select the parity mode.
General > Stop Bits	1bit 2bits	1bit	Select the number of stop bits.
Baud > Baud Rate	Value must be an integer greater than 0	115200	Enter the desired baud rate. If the requested baud rate cannot be achieved, the settings with the smallest percent error are used. The theoretical calculated baud rate and percent error are printed in a comment in the generated sci_baud_setting_t structure.
Baud > Baud Rate Modulation	Disabled Enabled	Disabled	Enabling baud rate modulation reduces the percent error of the actual baud rate with respect to the requested baud rate. It does this by modulating the number of cycles per clock, so some bits are slightly longer than others.
Baud > Max Error (%)	Must be a valid non negative integer with a maximum configurable value of 100	5	Maximum percent error allowed during baud calculation. This is used by the algorithm to determine whether or not to consider using less accurate alternative register settings. NOTE: The baud calculation does not show an error in the tool if this percent error was not achieved. The calculated percent error is recorded in a comment in the generated sci_baud_setting_t structure.
Baud > Synchronizer Bypass	Not Bypassed (The operation clock is SCInASYNCCLK) Bypassed (The operating clock is same as PCLKM)	Not Bypassed (The operation clock is SCInASYNCCLK)	Select whether to bypass the synchronizer circuit between the bus clock and operation clock.
Flow Control > CTS/RTS Selection	MCU Specific Options		Select either CTS or RTS function on the CTSn_RTSn pin of SCI channel n or select CTS function on CTSn pin and RTS function on CTSn_RTSn pin of SCI channel n (Available on selected MCUs and channels).
Flow Control > Software RTS Port	MCU Specific Options		Specify the flow control pin port for the MCU.
Flow Control > Software RTS Pin	Disabled 0 1 2 3 4 5 6 7	Disabled	Specify the flow control pin for the MCU.
Extra > RS-485 > DE Pin	Disable Enable	Disable	Enable or disable the DE pin for use in RS-485 half-duplex mode.
Extra > RS-485 > DE Pin Polarity	Active Low Active High	Active High	Select the polarity of the DE pin.
Extra > RS-485 > DE Pin Assertion Time	Must be a valid integer greater than 0 and less than or equal to 31.	1	Configure the time between assertion of the DE pin and the start of a write transfer. The time is specified in multiples of the SCI base clock period.
Extra > RS-485 > DE Pin Negation Time	Must be a valid integer greater than 0 and less than or equal to 31.	1	Configure the time between the end of a write transfer and the negation of the DE pin. The time is specified in multiples of the SCI base clock period.
Extra > Clock Source	Internal Clock Internal Clock With Output on SCK External Clock 8x baud rate External Clock 16x baud rate	Internal Clock	Selection of the clock source to be used in the baud-rate clock generator. When internal clock is used the baud rate can be output on the SCK pin.
Extra > Start bit detection	Falling Edge Low Level	Falling Edge	Start bit detected as falling edge or low level.
Extra > Noise Filter	Base Clock Signal divided by 1 On Chip Baud Rate Generator source clock divided by 1 On Chip Baud Rate Generator source clock divided by 2 On Chip Baud Rate Generator source clock divided by 4 On Chip Baud Rate Generator source clock divided by 8 Disable	Disable	Enable the digital noise filter on RXDn pin. The digital noise filter block in SCI consists of two-stage flipflop circuits.
Extra > Receive FIFO Trigger Level	One Max	Max	Unused if the channel has no FIFO or if DMAC is used for reception. Set to One to get a callback immediately when each byte is received. Set to Max to get a callback when FIFO is full or after 15 bit times with no data (fewer interrupts).
Interrupts > Callback	Name must be a valid C symbol	user_uart_callback	A user callback function can be provided. If this callback function is provided, it will be called from the interrupt service routine (ISR).
Interrupts > Receive Interrupt Priority	MCU Specific Options		Select the receive interrupt priority.
Interrupts > Transmit Data Empty Interrupt Priority	MCU Specific Options		Select the transmit interrupt priority.
Interrupts > Transmit End Interrupt Priority	MCU Specific Options		Select the transmit end interrupt priority.
Interrupts > Error Interrupt Priority	MCU Specific Options		Select the error interrupt priority.

Pin Configuration

This module uses TXD and RXD to communicate to external devices. CTS or RTS or both (CTS and RTS) can be controlled by the hardware. When the internal clock is the source for the baud-rate generator the SCK pin can be used to output a clock with the same frequency as the bit rate.

Usage Notes

• When configured for "Hardware CTS and Software RTS" the configured flow control pin will be used for RTS. The pin will be set high inside of the receive ISR while data is being read. It will be set low when all data is read.
• When configured for "Hardware CTS and Hardware RTS" the CTSn_RTSn pin will be used for RTS function and the CTSn pin will be used for CTS function on channel n.
• The driver will follow correct hardware flow control function when CTSn_RTSn pin is connected to CTSn pin when "Hardware CTS and Hardware RTS" flow control is selected. The data will still be transferred when CTSn_RTSn and CTSn are disconnected as the CTSn pin is internally pulled low on the hardware when CTSn pin is configured as a peripheral pin for SCI module. Do not configure CTSn pin if the hardware flow control is not desired.

Limitations

• Reception is still enabled after uart_api_t::communicationAbort API is called. Any characters received after abort and before the next call to read will arrive via the callback function with event UART_EVENT_RX_CHAR.
• When using 9-bit reception with DMAC, clear the upper 7 bits of data before processing the read data. The upper 7 bits contain status flags that are part of the register used to read data in 9-bit mode.
• DMAC activation is not available for safety channel.

Examples

SCI UART Example

uint8_t           g_dest[TRANSFER_LENGTH];
uint8_t           g_src[TRANSFER_LENGTH];
uint8_t           g_out_of_band_received[TRANSFER_LENGTH];
volatile uint32_t g_transfer_complete = 0;
volatile uint32_t g_receive_complete  = 0;
uint32_t          g_out_of_band_index = 0;
void r_sci_uart_basic_example (void)
{
    /* Initialize p_src to known data */
    for (uint32_t i = 0; i < TRANSFER_LENGTH; i++)
    {
        g_src[i] = (uint8_t) ('A' + (i % 26));
    }


    /* Open the transfer instance with initial configuration. */
    fsp_err_t err = R_SCI_UART_Open(&g_uart0_ctrl, &g_uart0_cfg);
    handle_error(err);



    /* Read data from UART. */
    err = R_SCI_UART_Read(&g_uart0_ctrl, g_dest, TRANSFER_LENGTH);
    handle_error(err);



    err = R_SCI_UART_Write(&g_uart0_ctrl, g_src, TRANSFER_LENGTH);
    handle_error(err);


    while (!g_transfer_complete)
    {
    }

    while (!g_receive_complete)
    {
    }
}

void example_callback (uart_callback_args_t * p_args)
{
    /* Handle the UART event */
    switch (p_args->event)
    {
        /* Received a character */
        case UART_EVENT_RX_CHAR:
        {
            /* Only put the next character in the receive buffer if there is space for it */
            if (sizeof(g_out_of_band_received) > g_out_of_band_index)
            {
                /* Write either the next one or two bytes depending on the receive data size */
                if (UART_DATA_BITS_8 >= g_uart0_cfg.data_bits)
                {
                    g_out_of_band_received[g_out_of_band_index++] = (uint8_t) p_args->data;
                }
                else
                {
                    uint16_t * p_dest = (uint16_t *) &g_out_of_band_received[g_out_of_band_index];
                    *p_dest              = (uint16_t) p_args->data;
                    g_out_of_band_index += 2;
                }
            }

            break;
        }

        /* Receive complete */
        case UART_EVENT_RX_COMPLETE:
        {
            g_receive_complete = 1;
            break;
        }

        /* Transmit complete */
        case UART_EVENT_TX_COMPLETE:
        {
            g_transfer_complete = 1;
            break;
        }

        default:
        {
        }
    }
}

SCI UART Baud Set Example

#define SCI_UART_BAUDRATE_19200      (19200)
#define SCI_UART_ERROR_RATE_x1000    (5000)
void r_sci_uart_baud_example (void)
{
    sci_baud_setting_t          baud_setting;
    sci_uart_baud_calculation_t baud_target;
    baud_target.baudrate               = SCI_UART_BAUDRATE_19200;
    baud_target.bitrate_modulation     = false;
    baud_target.baud_rate_error_x_1000 = SCI_UART_ERROR_RATE_x1000;

    fsp_err_t err = R_SCI_UART_BaudCalculate(&baud_target, SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK, &baud_setting);
    handle_error(err);



    err = R_SCI_UART_BaudSet(&g_uart0_ctrl, (void *) &baud_setting);
    handle_error(err);

}

Data Structures
struct	sci_uart_instance_ctrl_t
struct	sci_uart_baud_calculation_t
struct	sci_baud_setting_t
struct	sci_uart_rs485_setting_t
struct	sci_uart_extended_cfg_t

Enumerations
enum	sci_uart_clock_t
enum	sci_uart_flow_control_t
enum	sci_uart_rx_fifo_trigger_t
enum	sci_uart_start_bit_t
enum	sci_uart_noise_cancellation_t
enum	sci_uart_rs485_enable_t
enum	sci_uart_rs485_de_polarity_t
enum	sci_uart_clock_source_t

---

Data Structure Documentation

sci_uart_instance_ctrl_t

struct sci_uart_instance_ctrl_t

UART instance control block.

sci_uart_baud_calculation_t

struct sci_uart_baud_calculation_t

Baudrate calculation configuration.

Data Fields
uint32_t	baudrate	Target baudrate.
bool	bitrate_modulation	Whether bitrate modulation use or not.
uint32_t	baud_rate_error_x_1000	Max baudrate percent error.

sci_baud_setting_t

struct sci_baud_setting_t

Register settings to achieve a desired baud rate and modulation duty.

sci_uart_rs485_setting_t

struct sci_uart_rs485_setting_t

Configuration settings for controlling the DE signal for RS-485.

Data Fields
sci_uart_rs485_enable_t	enable	Enable the DE signal.
sci_uart_rs485_de_polarity_t	polarity	DE signal polarity.
uint8_t	assertion_time: 5	Time in baseclock units after assertion of the DE signal and before the start of the write transfer.
uint8_t	negation_time: 5	Time in baseclock units after the end of a write transfer and before the DE signal is negated.

sci_uart_extended_cfg_t

struct sci_uart_extended_cfg_t

UART on SCI device Configuration

Data Fields
sci_uart_clock_t	clock	The source clock for the baud-rate generator. If internal optionally output baud rate on SCK.
sci_uart_start_bit_t	rx_edge_start	Start reception on falling edge.
sci_uart_noise_cancellation_t	noise_cancel	Noise cancellation setting.
sci_baud_setting_t *	p_baud_setting	Register settings for a desired baud rate.
sci_uart_rx_fifo_trigger_t	rx_fifo_trigger	Receive FIFO trigger level, unused if channel has no FIFO or if DMAC is used.
bsp_io_port_pin_t	flow_control_pin	UART Driver Enable pin.
sci_uart_flow_control_t	flow_control	CTS/RTS function.
sci_uart_rs485_setting_t	rs485_setting	RS-485 settings.
sci_uart_clock_source_t	clock_source	Clock source to generate SCK can either be selected as PCLKM or SCInASYNCCLK.

Enumeration Type Documentation

sci_uart_clock_t

enum sci_uart_clock_t

Enumeration for SCI clock source

Enumerator
SCI_UART_CLOCK_INT	Use internal clock for baud generation.
SCI_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT	Use internal clock for baud generation and output on SCK.
SCI_UART_CLOCK_EXT8X	Use external clock 8x baud rate.
SCI_UART_CLOCK_EXT16X	Use external clock 16x baud rate.

sci_uart_flow_control_t

enum sci_uart_flow_control_t

UART flow control mode definition

Enumerator
SCI_UART_FLOW_CONTROL_RTS	Use CTSn_RTSn pin for RTS.
SCI_UART_FLOW_CONTROL_CTS	Use CTSn_RTSn pin for CTS.
SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS	Use CTSn pin for CTS, CTSn_RTSn pin for RTS.
SCI_UART_FLOW_CONTROL_CTSRTS	Use SCI pin for CTS, external pin for RTS.

sci_uart_rx_fifo_trigger_t

enum sci_uart_rx_fifo_trigger_t

Receive FIFO trigger configuration.

Enumerator
SCI_UART_RX_FIFO_TRIGGER_1	Callback after each byte is received without buffering.
SCI_UART_RX_FIFO_TRIGGER_MAX	Callback when FIFO is full or after 15 bit times with no data (fewer interrupts)

sci_uart_start_bit_t

enum sci_uart_start_bit_t

Asynchronous Start Bit Edge Detection configuration.

Enumerator
SCI_UART_START_BIT_LOW_LEVEL	Detect low level on RXDn pin as start bit.
SCI_UART_START_BIT_FALLING_EDGE	Detect falling level on RXDn pin as start bit.

sci_uart_noise_cancellation_t

enum sci_uart_noise_cancellation_t

Noise cancellation configuration.

Enumerator
SCI_UART_NOISE_CANCELLATION_DISABLE	Disable noise cancellation.
SCI_UART_NOISE_CANCELLATION_ENABLE	Enable noise cancellation, The base clock signal divided by 1.
SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_1	Enable noise cancellation, The on-chip baud rate generator source clock divided by 1.
SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_2	Enable noise cancellation, The on-chip baud rate generator source clock divided by 2.
SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_4	Enable noise cancellation, The on-chip baud rate generator source clock divided by 4.
SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_8	Enable noise cancellation, The on-chip baud rate generator source clock divided by 8.

sci_uart_rs485_enable_t

enum sci_uart_rs485_enable_t

RS-485 Enable/Disable.

Enumerator
SCI_UART_RS485_DISABLE	RS-485 disabled.
SCI_UART_RS485_ENABLE	RS-485 enabled.

sci_uart_rs485_de_polarity_t

enum sci_uart_rs485_de_polarity_t

The polarity of the RS-485 DE signal.

Enumerator
SCI_UART_RS485_DE_POLARITY_HIGH	The DE signal is high when a write transfer is in progress.
SCI_UART_RS485_DE_POLARITY_LOW	The DE signal is low when a write transfer is in progress.

sci_uart_clock_source_t

enum sci_uart_clock_source_t

Source clock selection options for SCI.

Function Documentation

R_SCI_UART_Open()

fsp_err_t R_SCI_UART_Open	(	uart_ctrl_t *const	p_ctrl,
		uart_cfg_t const *const	p_cfg
	)

Configures the UART driver based on the input configurations. If reception is enabled at compile time, reception is enabled at the end of this function. Implements uart_api_t::open

Return values

FSP_SUCCESS	Channel opened successfully.
FSP_ERR_ASSERTION	Pointer to UART control block or configuration structure is NULL.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	The requested channel does not exist on this MCU.
FSP_ERR_ALREADY_OPEN	Control block has already been opened or channel is being used by another instance. Call close() then open() to reconfigure.
FSP_ERR_INVALID_ARGUMENT	Invalid input parameter.

Returns

See Common Error Codes or functions called by this function for other possible return codes. This function calls:

• transfer_api_t::open

R_SCI_UART_Read()

fsp_err_t R_SCI_UART_Read	(	uart_ctrl_t *const	p_ctrl,
		uint8_t *const	p_dest,
		uint32_t const	bytes
	)

Receives user specified number of bytes into destination buffer pointer. Implements uart_api_t::read

Return values

FSP_SUCCESS	Data reception successfully ends.
FSP_ERR_ASSERTION	Pointer to UART control block is NULL.
FSP_ERR_INVALID_ARGUMENT	Destination address or data size is not valid for 9-bit mode.
FSP_ERR_NOT_OPEN	The control block has not been opened
FSP_ERR_IN_USE	A previous read operation is still in progress.
FSP_ERR_UNSUPPORTED	SCI_UART_CFG_RX_ENABLE is set to 0

Returns

See Common Error Codes or functions called by this function for other possible return codes. This function calls:

• transfer_api_t::reconfigure

Note

If 9-bit data length is specified at R_SCI_UART_Open call, p_dest must be aligned 16-bit boundary.

R_SCI_UART_Write()

fsp_err_t R_SCI_UART_Write	(	uart_ctrl_t *const	p_ctrl,
		uint8_t const *const	p_src,
		uint32_t const	bytes
	)

Transmits user specified number of bytes from the source buffer pointer. Implements uart_api_t::write

Return values

FSP_SUCCESS	Data transmission finished successfully.
FSP_ERR_ASSERTION	Pointer to UART control block is NULL.
FSP_ERR_INVALID_ARGUMENT	Source address or data size is not valid for 9-bit mode.
FSP_ERR_NOT_OPEN	The control block has not been opened
FSP_ERR_IN_USE	A UART transmission is in progress
FSP_ERR_UNSUPPORTED	SCI_UART_CFG_TX_ENABLE is set to 0

Returns

See Common Error Codes or functions called by this function for other possible return codes. This function calls:

• transfer_api_t::reconfigure

Note

If 9-bit data length is specified at R_SCI_UART_Open call, p_src must be aligned on a 16-bit boundary.

R_SCI_UART_BaudSet()

fsp_err_t R_SCI_UART_BaudSet	(	uart_ctrl_t *const	p_ctrl,
		void const *const	p_baud_setting
	)

Updates the baud rate using the clock selected in Open. p_baud_setting is a pointer to a sci_baud_setting_t structure. Implements uart_api_t::baudSet

Warning

This terminates any in-progress transmission.

Return values

FSP_SUCCESS	Baud rate was successfully changed.
FSP_ERR_ASSERTION	Pointer to UART control block is NULL or the UART is not configured to use the internal clock.
FSP_ERR_NOT_OPEN	The control block has not been opened

R_SCI_UART_InfoGet()

fsp_err_t R_SCI_UART_InfoGet	(	uart_ctrl_t *const	p_ctrl,
		uart_info_t *const	p_info
	)

Provides the driver information, including the maximum number of bytes that can be received or transmitted at a time. Implements uart_api_t::infoGet

Return values

FSP_SUCCESS	Information stored in provided p_info.
FSP_ERR_ASSERTION	Pointer to UART control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened

R_SCI_UART_Close()

fsp_err_t R_SCI_UART_Close

(

uart_ctrl_t *const

p_ctrl

)

Aborts any in progress transfers. Disables interrupts, receiver, and transmitter. Closes lower level transfer drivers if used. Removes power. Implements uart_api_t::close

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to UART control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened

R_SCI_UART_Abort()

fsp_err_t R_SCI_UART_Abort	(	uart_ctrl_t *const	p_ctrl,
		uart_dir_t	communication_to_abort
	)

Provides API to abort ongoing transfer. Transmission is aborted after the current character is transmitted. Reception is still enabled after abort(). Any characters received after abort() and before the transfer is reset in the next call to read(), will arrive via the callback function with event UART_EVENT_RX_CHAR. Implements uart_api_t::communicationAbort

Return values

FSP_SUCCESS	UART transaction aborted successfully.
FSP_ERR_ASSERTION	Pointer to UART control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_UNSUPPORTED	The requested Abort direction is unsupported.

Returns

See Common Error Codes or functions called by this function for other possible return codes. This function calls:

• transfer_api_t::disable

R_SCI_UART_BaudCalculate()

fsp_err_t R_SCI_UART_BaudCalculate	(	sci_uart_baud_calculation_t const *const	p_baud_target,
		sci_uart_clock_source_t	clock_source,
		sci_baud_setting_t *const	p_baud_setting
	)

Calculates baud rate register settings. Evaluates and determines the best possible settings set to the baud rate related registers.

Parameters

[in]	p_baud_target	Baudrate calculation configuration.
[in]	clock_source	Clock source (PCLKM or SCInASYNCCLK) used for baudrate calculation.
[out]	p_baud_setting	Baud setting information stored here if successful

Return values

FSP_SUCCESS	Baud rate is set successfully
FSP_ERR_ASSERTION	Null pointer
FSP_ERR_INVALID_ARGUMENT	Baud rate is '0', error in calculated baud rate is larger than requested max error, or requested max error in baud rate is larger than 15%. Clock source frequency could not be get.

R_SCI_UART_CallbackSet()

fsp_err_t R_SCI_UART_CallbackSet	(	uart_ctrl_t *const	p_ctrl,
		void(*)(uart_callback_args_t *)	p_callback,
		void const *const	p_context,
		uart_callback_args_t *const	p_callback_memory
	)

Updates the user callback and has option of providing memory for callback structure. Implements uart_api_t::callbackSet

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

R_SCI_UART_ReadStop()

fsp_err_t R_SCI_UART_ReadStop	(	uart_ctrl_t *const	p_ctrl,
		uint32_t *	remaining_bytes
	)

Provides API to abort ongoing read. Reception is still enabled after abort(). Any characters received after abort() and before the transfer is reset in the next call to read(), will arrive via the callback function with event UART_EVENT_RX_CHAR. Implements uart_api_t::readStop

Return values

FSP_SUCCESS	UART transaction aborted successfully.
FSP_ERR_ASSERTION	Pointer to UART control block or remaining_bytes is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_UNSUPPORTED	The requested Abort direction is unsupported.

Returns

See Common Error Codes or functions called by this function for other possible return codes. This function calls:

• transfer_api_t::disable