SDRAM Interface

Detailed Description

Interface for external sdram communication.

Summary

The SDRAM interface provides APIs and definitions for SDRAM communication.

Data Structures
struct	sdram_cfg_t
struct	sdram_api_t
struct	sdram_instance_t

Typedefs
typedef void	sdram_ctrl_t

Enumerations
enum	sdram_data_bus_width_t
enum	sdram_address_bus_width_t
enum	sdram_write_burst_mode_t
enum	sdram_refresh_cycle_source_div_t

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Data Structure Documentation

sdram_cfg_t

struct sdram_cfg_t

SDRAM configuration

Data Fields
sdram_data_bus_width_t	data_width	Select data bus width.
sdram_address_bus_width_t	row_address_width	Number of bits of SDRAM Row address.
sdram_address_bus_width_t	column_address_width	Number of bits of SDRAM Column address.
uint32_t	ras_precharge_cycle	Cycle between PRECHARGE and ACTIVE command (tRP)
uint32_t	ras_to_cas_delay_cycle	Cycle between ACTIVE and READ/WRITE command (tRCD)
uint32_t	cas_latency	CAS Latency cycle (tCL)
uint32_t	write_recovery_cycle	Cycle between Data In and PRECHARGE command (tWR)
uint32_t	row_cycle	Cycle between REFRESH/ACTIVE and REFRESH/ACTIVE command (tRC)
uint32_t	auto_refresh_cycle	Auto-Refresh cycle time.
sdram_refresh_cycle_source_div_t	source_div	Auto-Refresh cycle clock source divider.
uint32_t	refresh_request_count	The number of continuous refresh cycles.
sdram_write_burst_mode_t	write_burst_mode	Select Burst Write or Single Write in MRS
void const *	p_extend	SDRAM hardware dependent configuration.

sdram_api_t

struct sdram_api_t

SDRAM implementations follow this API.

Data Fields
fsp_err_t(*	open )(sdram_ctrl_t *p_ctrl, sdram_cfg_t const *const p_cfg)
fsp_err_t(*	selfRefreshEnter )(sdram_ctrl_t *p_ctrl)
fsp_err_t(*	selfRefreshExit )(sdram_ctrl_t *p_ctrl)
fsp_err_t(*	powerDownEnter )(sdram_ctrl_t *p_ctrl)
fsp_err_t(*	powerDownExit )(sdram_ctrl_t *p_ctrl)
fsp_err_t(*	close )(sdram_ctrl_t *p_ctrl)

Field Documentation

open

fsp_err_t(* sdram_api_t::open) (sdram_ctrl_t *p_ctrl, sdram_cfg_t const *const p_cfg)

Open the SDRAM driver module.

Parameters

[in]	p_ctrl	Pointer to a driver handle
[in]	p_cfg	Pointer to a configuration structure

selfRefreshEnter

fsp_err_t(* sdram_api_t::selfRefreshEnter) (sdram_ctrl_t *p_ctrl)

Enter Self Refresh mode.

Parameters

[in]

p_ctrl

Pointer to a driver handle

selfRefreshExit

fsp_err_t(* sdram_api_t::selfRefreshExit) (sdram_ctrl_t *p_ctrl)

Exit Self Refresh mode.

Parameters

[in]

p_ctrl

Pointer to a driver handle

powerDownEnter

fsp_err_t(* sdram_api_t::powerDownEnter) (sdram_ctrl_t *p_ctrl)

Enter Power Down mode.

Parameters

[in]

p_ctrl

Pointer to a driver handle

powerDownExit

fsp_err_t(* sdram_api_t::powerDownExit) (sdram_ctrl_t *p_ctrl)

Exit Power Down mode.

Parameters

[in]

p_ctrl

Pointer to a driver handle

close

fsp_err_t(* sdram_api_t::close) (sdram_ctrl_t *p_ctrl)

Close the SDRAM driver module.

Parameters

[in]

p_ctrl

Pointer to a driver handle

sdram_instance_t

struct sdram_instance_t

This structure encompasses everything that is needed to use an instance of this interface.

Data Fields
sdram_ctrl_t *	p_ctrl	Pointer to the control structure for this instance.
sdram_cfg_t const *	p_cfg	Pointer to the configuration structure for this instance.
sdram_api_t const *	p_api	Pointer to the API structure for this instance.

Typedef Documentation

sdram_ctrl_t

typedef void sdram_ctrl_t

SDRAM control block. Allocate an instance specific control block to pass into the SDRAM API calls.

Enumeration Type Documentation

sdram_data_bus_width_t

enum sdram_data_bus_width_t

SDRAM data bus width.

Enumerator
SDRAM_DATA_BUS_WIDTH_8BIT	Data bus width 8bit.
SDRAM_DATA_BUS_WIDTH_16BIT	Data bus width 16bit.
SDRAM_DATA_BUS_WIDTH_32BIT	Data bus width 32bit.

sdram_address_bus_width_t

enum sdram_address_bus_width_t

Number of bits of SDRAM Row/Column address.

Enumerator
SDRAM_ADDRESS_BUS_WIDTH_8_BITS	Address bus width 8bit.
SDRAM_ADDRESS_BUS_WIDTH_9_BITS	Address bus width 9bit.
SDRAM_ADDRESS_BUS_WIDTH_10_BITS	Address bus width 10bit.
SDRAM_ADDRESS_BUS_WIDTH_11_BITS	Address bus width 11bit.
SDRAM_ADDRESS_BUS_WIDTH_12_BITS	Address bus width 12bit.
SDRAM_ADDRESS_BUS_WIDTH_13_BITS	Address bus width 13bit.

sdram_write_burst_mode_t

enum sdram_write_burst_mode_t

Write burst mode

Enumerator
SDRAM_WRITE_BURST_MODE_BURST	Burst write setting.
SDRAM_WRITE_BURST_MODE_SINGLE	Single write setting.

sdram_refresh_cycle_source_div_t

enum sdram_refresh_cycle_source_div_t

SDRAM Refresh cycle clock source divisors

Enumerator
SDRAM_REFRESH_CYCLE_SOURCE_DIV_1	SDRAM Refresh cycle clock source divided by 1.
SDRAM_REFRESH_CYCLE_SOURCE_DIV_2	SDRAM Refresh cycle clock source divided by 2.
SDRAM_REFRESH_CYCLE_SOURCE_DIV_4	SDRAM Refresh cycle clock source divided by 4.
SDRAM_REFRESH_CYCLE_SOURCE_DIV_8	SDRAM Refresh cycle clock source divided by 8.
SDRAM_REFRESH_CYCLE_SOURCE_DIV_16	SDRAM Refresh cycle clock source divided by 16.
SDRAM_REFRESH_CYCLE_SOURCE_DIV_32	SDRAM Refresh cycle clock source divided by 32.
SDRAM_REFRESH_CYCLE_SOURCE_DIV_64	SDRAM Refresh cycle clock source divided by 64.
SDRAM_REFRESH_CYCLE_SOURCE_DIV_128	SDRAM Refresh cycle clock source divided by 128.
SDRAM_REFRESH_CYCLE_SOURCE_DIV_256	SDRAM Refresh cycle clock source divided by 256.
SDRAM_REFRESH_CYCLE_SOURCE_DIV_512	SDRAM Refresh cycle clock source divided by 512.
SDRAM_REFRESH_CYCLE_SOURCE_DIV_1024	SDRAM Refresh cycle clock source divided by 1024.
SDRAM_REFRESH_CYCLE_SOURCE_DIV_2048	SDRAM Refresh cycle clock source divided by 2048.
SDRAM_REFRESH_CYCLE_SOURCE_DIV_4096	SDRAM Refresh cycle clock source divided by 4096.