RZT Flexible Software Package Documentation  Release v3.0.0

 
Expanded Serial Peripheral Interface (xSPI) HyperBus (r_xspi_hyper)

Functions

fsp_err_t R_XSPI_HYPER_Open (hyperbus_ctrl_t *p_ctrl, hyperbus_cfg_t const *const p_cfg)
 
fsp_err_t R_XSPI_HYPER_Close (hyperbus_ctrl_t *p_ctrl)
 
fsp_err_t R_XSPI_HYPER_BurstTypeSet (hyperbus_ctrl_t *p_ctrl, hyperbus_burst_type_t burst_type)
 
fsp_err_t R_XSPI_HYPER_AccessSpaceSet (hyperbus_ctrl_t *p_ctrl, hyperbus_space_select_t access_space)
 
fsp_err_t R_XSPI_HYPER_DirectTransfer (hyperbus_ctrl_t *const p_ctrl, hyperbus_direct_transfer_t *const p_transfer)
 
fsp_err_t R_XSPI_HYPER_Write (hyperbus_ctrl_t *p_ctrl, uint8_t const *const p_src, uint8_t *const p_dest, uint32_t byte_count)
 
fsp_err_t R_XSPI_HYPER_Erase (hyperbus_ctrl_t *p_ctrl, uint8_t *const p_device_address, uint32_t byte_count)
 
fsp_err_t R_XSPI_HYPER_StatusGet (hyperbus_ctrl_t *p_ctrl, hyperbus_status_t *const p_status)
 
fsp_err_t R_XSPI_HYPER_AutoCalibrate (hyperbus_ctrl_t *p_ctrl)
 

Detailed Description

Driver for the xSPI peripheral on RZ microprocessor. This module implements the HyperBus Interface.

Overview

The HyperBus peripheral interfaces with an external HyperRAM device to perform data I/O Operations.

Features

The xSPI Hyper driver has the following key features to support the HyperRAM device:

Configuration

HyperRAM

Build Time Configurations for r_xspi_hyper

The following build time configurations are defined in fsp_cfg/r_xspi_hyper_cfg.h:

ConfigurationOptionsDefaultDescription
Memory Mapping Address Space > Unit 0 > Chip Select 0 > Start AddressAddress should be the start address of xspi unit 0 external address space0x60000000 Start address of xSPI Unit 0 Chip Select 0 in memory mapping mode.
Memory Mapping Address Space > Unit 0 > Chip Select 0 > End AddressAddress should be within xspi unit 0 external address space0x600FFFFF End address of xSPI Unit 0 Chip Select 1 in memory mapping mode.
Memory Mapping Address Space > Unit 0 > Chip Select 1 > Start AddressAddress should be within xspi unit 0 external address space0x64000000 Start address of xSPI Unit 0 Chip Select 1 in memory mapping mode.
Memory Mapping Address Space > Unit 0 > Chip Select 1 > End AddressAddress should be within xspi unit 0 external address space0x640FFFFF End address of xSPI Unit 0 Chip Select 1 in memory mapping mode.
Memory Mapping Address Space > Unit 1 > Chip Select 0 > Start AddressAddress should be the start address of xspi unit 1 external address space0x68000000 Start address of xSPI Unit 1 Chip Select 0 in memory mapping mode.
Memory Mapping Address Space > Unit 1 > Chip Select 0 > End AddressAddress should be within xspi unit 1 external address space0x680FFFFF End address of xSPI Unit 1 Chip Select 0 in memory mapping mode.
Memory Mapping Address Space > Unit 1 > Chip Select 1 > Start AddressAddress should be within xspi unit 1 external address space0x6C000000 Start address of xSPI Unit 1 Chip Select 1 in memory mapping mode.
Memory Mapping Address Space > Unit 1 > Chip Select 1 > End AddressAddress should be within xspi unit 1 external address space0x6C0FFFFF End address of xSPI Unit 1 Chip Select 1 in memory mapping mode.
Memory Mapping Address Space > Memory Mapping Address Space Configuration SupportMCU Specific OptionsSupport status of Memory Mapping Address Space setting on this MCU. If Not supported, the address space set in Memory Mapping Address Space is invalid.
Parameter Checking
  • Default (BSP)
  • Enabled
  • Disabled
Default (BSP) If selected code for parameter checking is included in the build.
Unit 0 Prefetch Function
  • Enable
  • Disable
Disable Enable prefetch function on memory-mapped reads of xSPI Unit 0.
Unit 1 Prefetch Function
  • Enable
  • Disable
Disable Enable prefetch function on memory-mapped reads of xSPI Unit 1.
Unit 0 IO voltageMCU Specific OptionsVoltage setting of xSPI Unit 0.
Unit 1 IO voltageMCU Specific OptionsVoltage setting of xSPI Unit 1.

Configurations for Storage > HyperRAM (r_xspi_hyper)

This module can be added to the Stacks tab via New Stack > Storage > HyperRAM (r_xspi_hyper).

ConfigurationOptionsDefaultDescription
General > NameName must be a valid C symbolg_hyperbus0 Module name.
General > UnitUnit should be 0 or 11 Specify the XSPI unit number.
General > Chip Select
  • Chip Select 0
  • Chip Select 1
Chip Select 0 Specify the HyperBus chip select line to use.
General > RAM SizeMCU Specific OptionsSpecify the HyperRAM size.
General > Initial latency (Read)Refer to the RZT Configuration tool for available options.6 CYCLES Specify the read latency cycle
General > Initial latency (Memory Write)Refer to the RZT Configuration tool for available options.6 CYCLES Specify the write latency cycle in memory write
General > Initial latency (Register Write)Refer to the RZT Configuration tool for available options.0 CYCLE (No Latency) Specify the write latency cycle in register write
HyperBus Transaction Characteristics > Initial Burst TypeLinear burst (Burst type = 1)Linear burst (Burst type = 1) Set burst type when driver starts.
HyperBus Transaction Characteristics > Initial Access Space
  • Memory Space (AS = 0)
  • Register Space (AS = 1)
Memory Space (AS = 0) Set the Hyper device access address when starting the driver.
Auto Calibration > Data latching delayMust be a valid non-negative integer0x08 Set this to 0 to enable auto-calibration. 0x08 is the default value
Auto Calibration > Auto-Calibration AddressMust be a valid non-negative integer0x00 Set the address of the read/write destination to be performed for auto-calibration.
Bus Timing > CS minimum idle termRefer to the RZT Configuration tool for available options.7 CYCLES Define the CS minimum idle term.
Bus Timing > CS Asserting extension
  • No Extension
  • Extend 1 cycle
No Extension Define the CS asserting extension
Bus Timing > CS Negating extension
  • No Extension
  • Extend 1 cycle
No Extension Define the CS negating extension

Clock Configuration

The XSPI_CLKn frequencies can be set on the Clocks tab of FSP Configuration editor or by using the CGC Interface at run-time.

Pin Configuration

The following pins are available to connect to an external Hyper device:

Usage Notes

HYPER Memory Mapped Access

After R_XSPI_HYPER_Open() completes successfully, the HYPER device contents are mapped to External Address Space xSPIn or their mirror spaces and can be read like on-chip memory. Please refer to xSPI "Overview" section in your device's manual on address map details.

In the configurator properties, 'Memory Mapping Address Space Configuration Support' is set to either 'Supported' or 'Not Supported' depending on your device. The method of memory mapped access address configuration depends on the value of 'Memory Mapping Address Space Configuration Support'.

Example Configurations for the Device 'Memory Mapping Address Space Configuration Support' is 'Supported'

If 'Memory Mapping Address Space Configuration Support' is 'Supported', 'Memory Mapping Address Space' should be set appropriately for your device. The table below shows an example of 'Memory Mapping Address Space' configurations when 64MB memory is used as a slave device in each Chip Select.

Properties RZ/T2ME RZ/T2H
Memory Mapping Address Space > Unit 0 > Chip Select 0 > Start Address 0x60000000 (Fixed) 0x40000000 (Fixed)
Memory Mapping Address Space > Unit 0 > Chip Select 0 > End Address 0x63FFFFFF 0x43FFFFFF
Memory Mapping Address Space > Unit 0 > Chip Select 1 > Start Address 0x64000000 0x48000000
Memory Mapping Address Space > Unit 0 > Chip Select 1 > End Address 0x67FFFFFF 0x4BFFFFFF
Memory Mapping Address Space > Unit 1 > Chip Select 0 > Start Address 0x68000000 (Fixed) 0x50000000 (Fixed)
Memory Mapping Address Space > Unit 1 > Chip Select 0 > End Address 0x6BFFFFFF 0x53FFFFFF
Memory Mapping Address Space > Unit 1 > Chip Select 1 > Start Address 0x6C000000 0x58000000
Memory Mapping Address Space > Unit 1 > Chip Select 1 > End Address 0x6FFFFFFF 0x5BFFFFFF
Memory Mapping Address Space > Memory Mapping Address Space Configuration Support Supported Supported

The address space of each chip select set by the above configuration is as follows.

Address Space of Each Chip Select RZ/T2ME RZ/T2H
Unit 0 Chip Select 0 Start Address 0x60000000 (Fixed) 0x40000000 (Fixed)
Unit 0 Chip Select 0 End Address 0x63FFFFFF 0x43FFFFFF
Unit 0 Chip Select 1 Start Address 0x64000000 0x48000000
Unit 0 Chip Select 1 End Address 0x67FFFFFF 0x4BFFFFFF
Unit 1 Chip Select 0 Start Address 0x68000000 (Fixed) 0x50000000 (Fixed)
Unit 1 Chip Select 0 End Address 0x6BFFFFFF 0x53FFFFFF
Unit 1 Chip Select 1 Start Address 0x6C000000 0x58000000
Unit 1 Chip Select 1 End Address 0x6FFFFFFF 0x5BFFFFFF

Example Configurations for the Device 'Memory Mapping Address Space Configuration Support' is 'Not Supported'

If 'Memory Mapping Address Space Configuration Support' is 'Not Supported' for your device, 'Memory Mapping Address Space' configurations are invalid. In this case, the start address of each chip select is fixed by device, and only the size of the address space is configured in 'Memory Size' property. The table below shows an example of the address space configuration when 64MB memory is used as a slave device in Unit 0 Chip Select 0.

Properties RZ/T2M RZ/T2L
Memory Mapping Address Space > Memory Mapping Address Space Configuration Support Not Supported Not Supported
General > Unit 0 0
General > Chip Select 0 0
General > Memory Size 64MB 64MB

The address space of each chip select set by the above configuration is as follows.

Address Space of Each Chip Select RZ/T2M RZ/T2L
Unit 0 Chip Select 0 Start Address 0x60000000 (Fixed) 0x60000000 (Fixed)
Unit 0 Chip Select 0 End Address 0x63FFFFFF (64MB Size) 0x63FFFFFF (64MB Size)
Unit 0 Chip Select 1 Start Address 0x64000000 (Fixed) 0x64000000 (Fixed)
Unit 0 Chip Select 1 End Address 0x640FFFFF (default) 0x640FFFFF (default)
Unit 1 Chip Select 0 Start Address 0x68000000 (Fixed) 0x68000000 (Fixed)
Unit 1 Chip Select 0 End Address 0x680FFFFF (default) 0x680FFFFF (default)
Unit 1 Chip Select 1 Start Address 0x6C000000 (Fixed) 0x6C000000 (Fixed)
Unit 1 Chip Select 1 End Address 0x6C0FFFFF (default) 0x6C0FFFFF (default)

Dynamic address space selection (Memory and Register)

This driver allows user to dynamically select whether to access memory space or register space. Call R_XSPI_HYPER_AccessSpaceSet(), and assign HYPERBUS_SPACE_SELECT_MEMORY_SPACE or HYPERBUS_SPACE_SELECT_REGISTER_SPACE to the second argument.

Note that register space access is in limited situations, such as when changing the HyperRAM device-specific configuration.

Limitations

Examples

Basic Example

This is a basic example of minimal use of the HyperBus module in an application.

#define XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH (256)
uint16_t write_data[XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH];
uint16_t read_data[XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH];
void r_xspi_hyper_basic_example (void)
{
/* Write some data to the write buffer */
for (uint16_t i = 0; i < XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH; i++)
{
write_data[i] = i;
}
/* Open the XSPI_HYPER instance */
fsp_err_t err = R_XSPI_HYPER_Open(&g_hyperbus_ctrl, &g_hyperbus_cfg);
handle_error(err);
/* After R_XSPI_HYPER_Open() and any required device specific initialization, data can be write directly
* to the HyperRAM connected to XSPI unit 1 */
for (uint16_t i = 0; i < XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH; i++)
{
*((volatile uint16_t *) HYPERRAM_BASE_ADDRESS + 0x0000 + i) = write_data[i];
}
/* After R_XSPI_HYPER_Open() and any required device specific initialization, data can be read directly
* to the HyperRAM connected to XSPI unit 1 */
for (uint16_t i = 0; i < XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH; i++)
{
read_data[i] = *((volatile uint16_t *) HYPERRAM_BASE_ADDRESS + 0x0000 + i);
}
/* Verify the read data */
for (uint16_t i = 0; i < XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH; i++)
{
if (read_data[i] != write_data[i])
{
/* Verify error. */
__BKPT(0);
}
}
while (1)
{
;
}
}

Register Space Access Example (R_XSPI_HYPER_AccessSpaceSet)

This is an example of using R_XSPI_HYPER_AccessSpaceSet() to change the address space from memory to register.

#define HYPERRAM_DEVICE_ID_REGISTER0_ADDRESS (0x0U)
#define HYPERRAM_ID_REGISTER0_DEFAULT_VALUE (0x0C81U)
void r_xspi_hyper_access_space_register_example (void)
{
/* Open the XSPI_HYPER instance */
fsp_err_t err = R_XSPI_HYPER_Open(&g_hyperbus_ctrl, &g_hyperbus_cfg);
handle_error(err);
/* Change address space to register space */
handle_error(err);
/* Reading ID register 0 with Memory-mapping */
volatile uint16_t * p_id_register0_addr = (uint16_t *) HYPERRAM_BASE_ADDRESS +
HYPERRAM_DEVICE_ID_REGISTER0_ADDRESS;
/* Verify the ID register0 value. Apply __REV16 to account for endian difference. */
if (__REV16(HYPERRAM_ID_REGISTER0_DEFAULT_VALUE) != *p_id_register0_addr)
{
/* Verify error. */
__BKPT(0);
}
}

Reading Status Register Example (R_XSPI_HYPER_DirectTransfer)

This is an example of using R_XSPI_HYPER_DirectTransfer with read direction to read identification register 0 value from HyperRAM device.

#define HYPERRAM_CA_ID_REGISTER_0_READ (0xE00000000000U)
#define HYPERRAM_ID_REGISTER0_DEFAULT_VALUE (0x0C81U)
void r_xspi_hyper_direct_transfer_example (void)
{
hyperbus_direct_transfer_t hyper_direct_transfer_id =
{
/* Set Command-Address bits to access ID Register 0 Read. */
.command_address.command_address_info = (uint64_t) HYPERRAM_CA_ID_REGISTER_0_READ,
.data_length = 2,
.dummy_cycles = 6,
/* Read data is stored in .data member. */
.data = 0,
};
/* Open the XSPI_HYPER instance */
fsp_err_t err = R_XSPI_HYPER_Open(&g_hyperbus_ctrl, &g_hyperbus_cfg);
handle_error(err);
/* Send transaction to read ID Register 0 */
err = R_XSPI_HYPER_DirectTransfer(&g_hyperbus_ctrl, &hyper_direct_transfer_id);
handle_error(err);
/* Verify the ID register0 value. Apply __REV16 to account for endian difference. */
if (__REV16(HYPERRAM_ID_REGISTER0_DEFAULT_VALUE) != hyper_direct_transfer_id.data)
{
/* Verify error. */
__BKPT(0);
}
}

Change Initial Latency Example (R_XSPI_HYPER_DirectTransfer)

This is an example of changing the initial latency of HyperRAM. By sending register access command, rewrite the value of Confiugration register 0 of HyperRAM device.

Note
This is a setting example specific to the HyperRAM device installed in RZ/T2M RSK. Please refer to the respective device datasheet for details.
When using this example code, Set module configuration value as below.
  • General > Initial latency (Read) is 4 CYCLES
  • General > Initial latency (Memory Write) is 4 CYCLES
#define HYPERRAM_CA_CONFIGURATION_REGISTER_0_WRITE (0x600001000000U)
#define HYPERRAM_CONFIGURATION_REGISTER0_DEFAULT_VALUE (0x1F8FU)
#define HYPERRAM_CONFIGURATION_REGISTER0_INITIAL_LATENCY_4CLOCK_SET (0xFU)
#define HYPERRAM_CONFIGURATION_REGISTER0_INITIAL_LATENCY_VALUE_MASK (0xFF0FU)
#define HYPERRAM_CONFIGURATION_REGISTER0_INITIAL_LATENCY_OFFSET (4U)
#define XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH (256)
uint16_t write_data[XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH];
uint16_t read_data[XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH];
void r_xspi_hyper_change_initial_latency_example (void)
{
hyperbus_direct_transfer_t hyper_direct_transfer =
{
/* Set Command-Address bits to access Configuration Register 0 Write. */
.command_address.command_address_info = (uint64_t) HYPERRAM_CA_CONFIGURATION_REGISTER_0_WRITE,
.data_length = 2,
.dummy_cycles = 6,
/* Set the value of CR0 in the byte order of HyperBus protocol compliant.
* Initial latency will be changed from 6 cycles(default) to 4 cycles.
* (in HyperRAM with RZ/T2M RSK, the function bit of initial latency is CR0[7-4]) */
.data =
__REV16((HYPERRAM_CONFIGURATION_REGISTER0_INITIAL_LATENCY_4CLOCK_SET <<
HYPERRAM_CONFIGURATION_REGISTER0_INITIAL_LATENCY_OFFSET) |
(HYPERRAM_CONFIGURATION_REGISTER0_DEFAULT_VALUE &
HYPERRAM_CONFIGURATION_REGISTER0_INITIAL_LATENCY_VALUE_MASK)),
};
/* Open the XSPI_HYPER instance */
fsp_err_t err = R_XSPI_HYPER_Open(&g_hyperbus_ctrl, &g_hyperbus_cfg);
handle_error(err);
/* Send transaction to update Configuration Register 0 */
err = R_XSPI_HYPER_DirectTransfer(&g_hyperbus_ctrl, &hyper_direct_transfer);
handle_error(err);
/* Write some data */
for (uint16_t i = 0; i < XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH; i++)
{
write_data[i] = i;
}
/* After R_XSPI_HYPER_Open() and any required device specific initialization, data can be write directly
* to the HyperRAM connected to XSPI unit 1 */
for (uint16_t i = 0; i < XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH; i++)
{
*((volatile uint16_t *) HYPERRAM_BASE_ADDRESS + 0x0000 + i) = write_data[i];
}
/* After R_XSPI_HYPER_Open() and any required device specific initialization, data can be read directly
* to the HyperRAM connected to XSPI unit 1 */
for (uint16_t i = 0; i < XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH; i++)
{
read_data[i] = *((volatile uint16_t *) HYPERRAM_BASE_ADDRESS + 0x0000 + i);
}
/* Verify the read data */
for (uint16_t i = 0; i < XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH; i++)
{
if (read_data[i] != write_data[i])
{
/* Verify error. */
__BKPT(0);
}
}
}

The initial latency can be changed by changing the settings of bits [7:4] of CR0. The sample code describes the case of changing from the factory default 6 cycle latency (at a maximum operating frequency of 166 MHz) to 4 cycle latency (at a maximum operating frequency of 100 MHz). Set the latency cycle for the HyperBus controller and HyperRAM according to the specification of the using HyperRAM.

Data Structures

struct  xspi_hyper_instance_ctrl_t
 

Enumerations

enum  xspi_hyper_chip_select_t
 
enum  xspi_hyper_device_type_t
 
enum  xspi_hyper_memory_size_t
 
enum  xspi_hyper_transaction_interval_clocks_t
 
enum  xspi_hyper_cs_pulldown_clocks_t
 
enum  xspi_hyper_cs_pullup_clocks_t
 
enum  xspi_hyper_prefetch_function_t
 
enum  xspi_hyper_io_voltage_t
 

Data Structure Documentation

◆ xspi_hyper_instance_ctrl_t

struct xspi_hyper_instance_ctrl_t

Instance control block. DO NOT INITIALIZE. Initialization occurs when hyperbus_api_t::open is called

Enumeration Type Documentation

◆ xspi_hyper_chip_select_t

Enumerator
XSPI_HYPER_CHIP_SELECT_0 

Device connected to Chip-Select 0.

XSPI_HYPER_CHIP_SELECT_1 

Device connected to Chip-Select 1.

◆ xspi_hyper_device_type_t

Enumerator
XSPI_HYPER_DEVICE_TYPE_FLASH 

Device Memory type HyperFlash.

XSPI_HYPER_DEVICE_TYPE_RAM 

Device Memory type HyperRAM.

◆ xspi_hyper_memory_size_t

Enumerator
XSPI_HYPER_MEMORY_SIZE_1MB 

Memory size 1MB.

XSPI_HYPER_MEMORY_SIZE_2MB 

Memory size 2MB.

XSPI_HYPER_MEMORY_SIZE_4MB 

Memory size 4MB.

XSPI_HYPER_MEMORY_SIZE_8MB 

Memory size 8MB.

XSPI_HYPER_MEMORY_SIZE_16MB 

Memory size 16MB.

XSPI_HYPER_MEMORY_SIZE_32MB 

Memory size 32MB.

XSPI_HYPER_MEMORY_SIZE_64MB 

Memory size 64MB.

◆ xspi_hyper_transaction_interval_clocks_t

Enumerator
XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_1 

1 interval clocks

XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_2 

2 interval clocks

XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_3 

3 interval clocks

XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_4 

4 interval clocks

XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_5 

5 interval clocks

XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_6 

6 interval clocks

XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_7 

7 interval clocks

XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_8 

8 interval clocks

XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_9 

9 interval clocks

XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_10 

10 interval clocks

XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_11 

11 interval clocks

XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_12 

12 interval clocks

XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_13 

13 interval clocks

XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_14 

14 interval clocks

XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_15 

15 interval clocks

XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_16 

16 interval clocks

◆ xspi_hyper_cs_pulldown_clocks_t

Enumerator
XSPI_HYPER_CS_PULLDOWN_CLOCKS_NO_EXTENSION 

CS asserting No extension.

XSPI_HYPER_CS_PULLDOWN_CLOCKS_1 

CS asserting Extend 1 cycle.

◆ xspi_hyper_cs_pullup_clocks_t

Enumerator
XSPI_HYPER_CS_PULLUP_CLOCKS_NO_EXTENSION 

CS negating No extension.

XSPI_HYPER_CS_PULLUP_CLOCKS_1 

CS negating Extend 1 cycle.

◆ xspi_hyper_prefetch_function_t

Enumerator
XSPI_HYPER_PREFETCH_FUNCTION_DISABLE 

Prefetch function disable.

XSPI_HYPER_PREFETCH_FUNCTION_ENABLE 

Prefetch function enable.

◆ xspi_hyper_io_voltage_t

Enumerator
XSPI_HYPER_IO_VOLTAGE_1_8V 

IO voltage 1.8V.

XSPI_HYPER_IO_VOLTAGE_3_3V 

IO voltage 3.3V.

Function Documentation

◆ R_XSPI_HYPER_Open()

fsp_err_t R_XSPI_HYPER_Open ( hyperbus_ctrl_t p_ctrl,
hyperbus_cfg_t const *const  p_cfg 
)

Open the HYPER driver module. After the driver is open, the HyperRAM can be accessed like internal memory.

Implements hyperbus_api_t::open.

Return values
FSP_SUCCESSConfiguration was successful.
FSP_ERR_ASSERTIONThe parameter p_ctrl or p_cfg is NULL.
FSP_ERR_ALREADY_OPENDriver has already been opened with the same p_ctrl.

◆ R_XSPI_HYPER_Close()

fsp_err_t R_XSPI_HYPER_Close ( hyperbus_ctrl_t p_ctrl)

Close the HYPER driver module.

Implements hyperbus_api_t::close.

Return values
FSP_SUCCESSConfiguration was successful.
FSP_ERR_ASSERTIONp_instance_ctrl is NULL.
FSP_ERR_NOT_OPENDriver is not opened.
Note
If another chip select of the same unit is used by other drivers, the other chip select operation will also stop when this function is executed.

◆ R_XSPI_HYPER_BurstTypeSet()

fsp_err_t R_XSPI_HYPER_BurstTypeSet ( hyperbus_ctrl_t p_ctrl,
hyperbus_burst_type_t  burst_type 
)

Dynamic burst type configuration.

Implements hyperbus_api_t::burstTypeSet

Return values
FSP_ERR_UNSUPPORTEDAPI not supported by Hyper - HyperRAM. (Only can use Linear Burst)

◆ R_XSPI_HYPER_AccessSpaceSet()

fsp_err_t R_XSPI_HYPER_AccessSpaceSet ( hyperbus_ctrl_t p_ctrl,
hyperbus_space_select_t  access_space 
)

Dynamic access address space configuration.

Implements hyperbus_api_t::accessSpaceSet

Return values
FSP_SUCCESSAddress space successfully changed as specified by the argument.
FSP_ERR_ASSERTIONThe parameter p_ctrl is NULL.
FSP_ERR_NOT_OPENDriver is not opened.

◆ R_XSPI_HYPER_DirectTransfer()

fsp_err_t R_XSPI_HYPER_DirectTransfer ( hyperbus_ctrl_t *const  p_ctrl,
hyperbus_direct_transfer_t *const  p_transfer 
)

Read/Write raw data directly with the HyperRAM.

Implements hyperbus_api_t::directTransfer.

Return values
FSP_SUCCESSThe flash was programmed successfully.
FSP_ERR_ASSERTIONA required pointer is NULL.
FSP_ERR_NOT_OPENDriver is not opened.

◆ R_XSPI_HYPER_Write()

fsp_err_t R_XSPI_HYPER_Write ( hyperbus_ctrl_t p_ctrl,
uint8_t const *const  p_src,
uint8_t *const  p_dest,
uint32_t  byte_count 
)

Program a page of data to the flash.

Implements hyperbus_api_t::write.

Return values
FSP_ERR_UNSUPPORTEDAPI not supported by HyperBus - HyperRAM.

◆ R_XSPI_HYPER_Erase()

fsp_err_t R_XSPI_HYPER_Erase ( hyperbus_ctrl_t p_ctrl,
uint8_t *const  p_device_address,
uint32_t  byte_count 
)

Erase a block or sector of flash. The byte_count must exactly match one of the erase sizes defined in hyperbus_cfg_t. For chip erase, byte_count must be HYPER_FLASH_ERASE_SIZE_CHIP_ERASE.

Implements hyperbus_api_t::erase.

Return values
FSP_ERR_UNSUPPORTEDAPI not supported by HyperBus - HyperRAM.

◆ R_XSPI_HYPER_StatusGet()

fsp_err_t R_XSPI_HYPER_StatusGet ( hyperbus_ctrl_t p_ctrl,
hyperbus_status_t *const  p_status 
)

Gets the write or erase status of the flash.

Implements hyperbus_api_t::statusGet.

Return values
FSP_ERR_UNSUPPORTEDAPI not supported by HyperBus - HyperRAM.

◆ R_XSPI_HYPER_AutoCalibrate()

fsp_err_t R_XSPI_HYPER_AutoCalibrate ( hyperbus_ctrl_t p_ctrl)

Auto-calibrate the HyperRAM device using the preamble pattern.

Implements hyperbus_api_t::autoCalibrate.

Note
The preamble pattern must be written to the configured address before calling this API.
Return values
FSP_ERR_UNSUPPORTEDAPI not supported by HyperBus - HyperFlash. (Planned support for FSP v2.1.0 or later.)