Expanded Serial Peripheral Interface (xSPI) HyperBus (r_xspi_hyper)

Functions
fsp_err_t	R_XSPI_HYPER_Open (hyperbus_ctrl_t *p_ctrl, hyperbus_cfg_t const *const p_cfg)
fsp_err_t	R_XSPI_HYPER_Close (hyperbus_ctrl_t *p_ctrl)
fsp_err_t	R_XSPI_HYPER_BurstTypeSet (hyperbus_ctrl_t *p_ctrl, hyperbus_burst_type_t burst_type)
fsp_err_t	R_XSPI_HYPER_AccessSpaceSet (hyperbus_ctrl_t *p_ctrl, hyperbus_space_select_t access_space)
fsp_err_t	R_XSPI_HYPER_Write (hyperbus_ctrl_t *p_ctrl, uint8_t const *const p_src, uint8_t *const p_dest, uint32_t byte_count)
fsp_err_t	R_XSPI_HYPER_Erase (hyperbus_ctrl_t *p_ctrl, uint8_t *const p_device_address, uint32_t byte_count)
fsp_err_t	R_XSPI_HYPER_StatusGet (hyperbus_ctrl_t *p_ctrl, hyperbus_status_t *const p_status)
fsp_err_t	R_XSPI_HYPER_AutoCalibrate (hyperbus_ctrl_t *p_ctrl)

Detailed Description

Driver for the xSPI peripheral on RZ microprocessor. This module implements the HyperBus Interface.

Overview

The HyperBus peripheral interfaces with an external HyperRAM device to perform data I/O Operations.

Features

The xSPI Hyper driver has the following key features to support the HyperRAM device:

• Can be configured with HyperRAM device on either of the 2 channels
• Memory mapped read and write access to the HyperRAM memory space
• Memory mapped read and write access to the HyperRAM register space
• Can be configured the access destination address space: memory space or register space

Configuration

HyperRAM

Build Time Configurations for r_xspi_hyper

The following build time configurations are defined in fsp_cfg/r_xspi_hyper_cfg.h:

Configuration	Options	Default	Description
Custom Address Space > Unit0 > CS0 > Start Address	MCU Specific Options		Start address of xSPI Unit0 CS0 in memory mapping mode.
Custom Address Space > Unit0 > CS0 > End Address	Address should be within xspi unit0 external address space	0x600FFFFF	End address of xSPI Unit0 CS1 in memory mapping mode.
Custom Address Space > Unit0 > CS1 > Start Address	Address should be within xspi unit0 external address space	0x64000000	Start address of xSPI Unit0 CS1 in memory mapping mode.
Custom Address Space > Unit0 > CS1 > End Address	Address should be within xspi unit0 external address space	0x640FFFFF	End address of xSPI Unit0 CS1 in memory mapping mode.
Custom Address Space > Unit1 > CS0 > Start Address	MCU Specific Options		Start address of xSPI Unit1 CS0 in memory mapping mode.
Custom Address Space > Unit1 > CS0 > End Address	Address should be within xspi unit1 external address space	0x680FFFFF	End address of xSPI Unit1 CS0 in memory mapping mode.
Custom Address Space > Unit1 > CS1 > Start Address	Address should be within xspi unit1 external address space	0x6C000000	Start address of xSPI Unit1 CS1 in memory mapping mode.
Custom Address Space > Unit1 > CS1 > End Address	Address should be within xspi unit1 external address space	0x6C0FFFFF	End address of xSPI Unit1 CS1 in memory mapping mode.
Custom Address Space > Custom Address Space Enable	MCU Specific Options		When disabled, Custom Address Space is not applied and address space is set according to Flash Size. When enabled, Flash Size is disabled and Custom Address Space settings are applied.
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Unit 0 Prefetch Function	Enable Disable	Disable	Enable prefetch function on memory-mapped reads of xSPI Unit 0.
Unit 1 Prefetch Function	Enable Disable	Disable	Enable prefetch function on memory-mapped reads of xSPI Unit 1.
Unit 0 IO voltage	MCU Specific Options		Voltage setting of xSPI Unit0.
Unit 1 IO voltage	MCU Specific Options		Voltage setting of xSPI Unit1.

Configurations for Storage > HyperRAM (r_xspi_hyper)

This module can be added to the Stacks tab via New Stack > Storage > HyperRAM (r_xspi_hyper).

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_hyperbus0	Module name.
General > Unit	Unit should be 0 or 1	1	Specify the XSPI unit number.
General > Chip Select	Chip Select 0 Chip Select 1	Chip Select 0	Specify the HyperBus chip select line to use.
General > RAM Size	1MB 2MB 4MB 8MB 16MB 32MB 64MB	8MB	Specify the HyperRAM size.
General > Initial latency (Read)	Refer to the RZT Configuration tool for available options.	6 CYCLES	Specify the read latency cycle
General > Initial latency (Memory Write)	Refer to the RZT Configuration tool for available options.	6 CYCLES	Specify the write latency cycle in memory write
General > Initial latency (Register Write)	Refer to the RZT Configuration tool for available options.	0 CYCLE (No Latency)	Specify the write latency cycle in register write
HyperBus Transaction Characteristics > Initial Burst Type	Linear burst (Burst type = 1)	Linear burst (Burst type = 1)	Set burst type when driver starts.
HyperBus Transaction Characteristics > Initial Access Space	Memory Space (AS = 0) Register Space (AS = 1)	Memory Space (AS = 0)	Set the Hyper device access address when starting the driver.
Auto Calibration > Data latching delay	Must be a valid non-negative integer	0x08	Set this to 0 to enable auto-calibration. 0x08 is the default value
Auto Calibration > Auto-Calibration Address	Must be a valid non-negative integer	0x00	Set the address of the read/write destination to be performed for auto-calibration.
Bus Timing > CS minimum idle term	Refer to the RZT Configuration tool for available options.	7 CYCLES	Define the CS minimum idle term.
Bus Timing > CS Asserting extension	No Extension Extend 1 cycle	No Extension	Define the CS asserting extension
Bus Timing > CS Negating extension	No Extension Extend 1 cycle	No Extension	Define the CS negating extension

Clock Configuration

The XSPI_CLKn frequencies can be set on the Clocks tab of FSP Configuration editor or by using the CGC Interface at run-time.

Pin Configuration

The following pins are available to connect to an external Hyper device:

• XSPIn_CKP/CKN: HyperBus clock positive/negative output(Differential Clock. Command, address, and data information is output with respect to the crossing of these signals.)
• XSPIn_RWDS: HyperBus Read-Write-Data-Strobe signal
• XSPIn_CS0: HyperBus device 0 select
• XSPIn_CS1: HyperBus device 1 select
• XSPIn_IO0: DQ 0 I/O
• XSPIn_IO1: DQ 1 I/O
• XSPIn_IO2: DQ 2 I/O
• XSPIn_IO3: DQ 3 I/O
• XSPIn_IO4: DQ 4 I/O
• XSPIn_IO5: DQ 5 I/O
• XSPIn_IO6: DQ 6 I/O
• XSPIn_IO7: DQ 7 I/O

Usage Notes

HYPER Memory Mapped Access

After R_XSPI_HYPER_Open() completes successfully, the HyperRAM device contents are mapped to address 0x60000000 (unit 0) or 0x68000000 (unit 1) based on the unit configured and can be read like on-chip RAM. When not using the cache, access the HyperRAM device via the mirror space 0x40000000 (unit 0) or 0x48000000 (unit 1). Unit 0 and Unit 1 support until 128 MB of address space.

The address map details for the external address space xSPI in RZ/T2M and RZ/T2L is as follows:

Address	Space
0x40000000 to 0x43FFFFFF	unit 0 CS0 mirror space
0x44000000 to 0x47FFFFFF	unit 0 CS1 mirror space
0x48000000 to 0x4BFFFFFF	unit 1 CS0 mirror space
0x4C000000 to 0x4FFFFFFF	unit 1 CS1 mirror space
0x60000000 to 0x63FFFFFF	unit 0 CS0
0x64000000 to 0x67FFFFFF	unit 0 CS1
0x68000000 to 0x6BFFFFFF	unit 1 CS0
0x6C000000 to 0x6FFFFFFF	unit 1 CS1

The address map for the external address space xSPI in RZ/T2ME is as follows:

Address	Space
0x40000000 to 0x47FFFFFF	unit 0 CS0 mirror space + unit 0 CS1 mirror space
0x48000000 to 0x4FFFFFFF	unit 1 CS0 mirror space + unit 1 CS1 mirror space
0x60000000 to 0x67FFFFFF	unit 0 CS0 + unit 0 CS1
0x68000000 to 0x6FFFFFFF	unit 1 CS0 + unit 1 CS1

The address map for the external address space xSPI in RZ/T2H is as follows:

Address	Space
0x40000000 to 0x4FFFFFFF	unit 0 CS0 + unit 0 CS1
0x50000000 to 0x5FFFFFFF	unit 1 CS0 + unit 1 CS1

Note

When Custom Address Space Enable configuration setting for RZ/T2ME and RZ/T2H is Enable, start address of CS1 space depends on the CS1 start address set in Custom Address Space configuration. When Disable, the start address of CS1 space is set so that each CS uses half of the address space.

Dynamic address space selection (Memory and Register)

This driver allows user to dynamically select whether to access memory space or register space. Call R_XSPI_HYPER_AccessSpaceSet(), and assign HYPERBUS_SPACE_SELECT_MEMORY_SPACE or HYPERBUS_SPACE_SELECT_REGISTER_SPACE to the second argument.

Note that register space access is in limited situations, such as when changing the HyperRAM device-specific configuration.

Limitations

• Prefetch function support for memory-mapping access is applied to all slave devices connected xSPI0 or xSPI1. When connecting different types of devices (for example, HyperRAM and OSPI) to same xSPI unit, make sure that the prefetch function settings are the same.
• When Enable is selected in the Custom Address Space Enable configuration, Custom Address Space settings are applied to all slave devices connected xSPI0 or xSPI1. When connecting different types of devices (for example, QSPI and OSPI) to xSPI units, make sure that Custom Address Space settings are the same for all xSPI modules.

Examples

Basic Example

This is a basic example of minimal use of the HyperBus module in an application.

#define XSPI1_CS0_MIRROR_BASE                (0x48000000)
#define XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH    (256)
uint16_t write_data[XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH];
uint16_t read_data[XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH];

void r_xspi_hyper_basic_example (void)
{
    /* Write some data to the write buffer */
    for (uint16_t i = 0; i < XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH; i++)
    {
        write_data[i] = i;
    }


    /* Open the XSPI_HYPER instance */
    fsp_err_t err = R_XSPI_HYPER_Open(&g_hyperbus_ctrl, &g_hyperbus_cfg);
    handle_error(err);


    /* After R_XSPI_HYPER_Open() and any required device specific initialization, data can be write directly
     * to the HyperRAM connected to XSPI unit 1 */
    for (uint16_t i = 0; i < XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH; i++)
    {
        *((volatile uint16_t *) XSPI1_CS0_MIRROR_BASE + 0x0000 + i) = write_data[i];
    }

    /* After R_XSPI_HYPER_Open() and any required device specific initialization, data can be read directly
     * to the HyperRAM connected to XSPI unit 1 */
    for (uint16_t i = 0; i < XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH; i++)
    {
        read_data[i] = *((volatile uint16_t *) XSPI1_CS0_MIRROR_BASE + 0x0000 + i);
    }

    /* Verify the read data */
    for (uint16_t i = 0; i < XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH; i++)
    {
        if (read_data[i] != write_data[i])
        {
            /* Verify error. */
            __BKPT(0);
        }
    }

    while (1)
    {
        ;
    }
}

Register Space Access Example

This is an example of using R_XSPI_HYPER_AccessSpaceSet() to change the address space from memory to register.

#define XSPI1_CS0_MIRROR_BASE                   (0x48000000)
#define HYPERRAM_DEVICE_ID_REGISTER0_ADDRESS    (0x0U)
#define HYPERRAM_ID_REGISTER0_DEFAULT_VALUE     (0x810C)

void r_xspi_hyper_access_space_register_example (void)
{
    /* Open the XSPI_HYPER instance */
    fsp_err_t err = R_XSPI_HYPER_Open(&g_hyperbus_ctrl, &g_hyperbus_cfg);
    handle_error(err);


    /* Change address space to register space */
    err = R_XSPI_HYPER_AccessSpaceSet(&g_hyperbus_ctrl, HYPERBUS_SPACE_SELECT_REGISTER_SPACE);
    handle_error(err);


    /* Reading ID register 0 with Memory-mapping */
    volatile uint16_t * p_id_register0_addr = (uint16_t *) XSPI1_CS0_MIRROR_BASE +
                                              HYPERRAM_DEVICE_ID_REGISTER0_ADDRESS;

    /* Verify the ID register0 value */
    if (HYPERRAM_ID_REGISTER0_DEFAULT_VALUE != *p_id_register0_addr)
    {
        /* Verify error. */
        __BKPT(0);
    }
}

Change Initial Latency Example

This is an example of changing the initial latency of HyperRAM. By register space access, rewrite the value of Confiugration register 0 of HyperRAM device.

Note

This is a setting example specific to the HyperRAM device installed in RZ/T2M RSK. Please refer to the respective device datasheet for details.

When using this example code, Set module configuration value as below. Otherwise configure to default value.

• General > Initial latency (Read) is 4 CYCLES
• General > Initial latency (Memory Write) is 4 CYCLES
• HyperBus Transaction Characteristic > Initial Access Space is Register Space (AS = 1)

#define XSPI1_CS0_MIRROR_BASE                                          (0x48000000)
#define HYPERRAM_DEVICE_CONFIGURATION_REGISTER_0_ADDRESS               (0x1000U)
#define HYPERRAM_CONFIGURATION_REGISTER0_DEFAULT_VALUE                 (0x1F8F)
#define HYPERRAM_CONFIGURATION_REGISTER0_INITIAL_LATENCY_4CLOCK_SET    (0xFU)
#define HYPERRAM_CONFIGURATION_REGISTER0_INITIAL_LATENCY_VALUE_MASK    (0xFF0FU)
#define HYPERRAM_CONFIGURATION_REGISTER0_INITIAL_LATENCY_OFFSET        (4U)

#define XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH                              (256)
uint16_t write_data[XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH];
uint16_t read_data[XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH];

void r_xspi_hyper_change_initial_latency_example (void)
{
    /* Open the XSPI_HYPER instance */
    fsp_err_t err = R_XSPI_HYPER_Open(&g_hyperbus_ctrl, &g_hyperbus_cfg);
    handle_error(err);

    /* Set the address of Configuration register 0 (CR0) to user-defined local variable */
    volatile uint16_t * p_configuration_register0_addr = (uint16_t *) XSPI1_CS0_MIRROR_BASE +
                                                         (HYPERRAM_DEVICE_CONFIGURATION_REGISTER_0_ADDRESS >> 1);

    /* Rewrite the value of CR0 in the byte order of HyperBus protocol compliant.
     * Initial latency will be changed from 6 cycles(default) to 4 cycles.
     * (in HyperRAM with RZ/T2M RSK, the function bit of initial latency is CR0[7-4]) */
    *p_configuration_register0_addr = (uint16_t) __REV16((HYPERRAM_CONFIGURATION_REGISTER0_INITIAL_LATENCY_4CLOCK_SET <<
                                                          HYPERRAM_CONFIGURATION_REGISTER0_INITIAL_LATENCY_OFFSET) |
                                                         (HYPERRAM_CONFIGURATION_REGISTER0_DEFAULT_VALUE &
                                                          HYPERRAM_CONFIGURATION_REGISTER0_INITIAL_LATENCY_VALUE_MASK));

    __asm volatile ("dsb");

    /* Change address space access destination from register space to memory space */
    err = R_XSPI_HYPER_AccessSpaceSet(&g_hyperbus_ctrl, HYPERBUS_SPACE_SELECT_MEMORY_SPACE);
    handle_error(err);

    /* Write some data to the write buffer */
    for (uint16_t i = 0; i < XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH; i++)
    {
        write_data[i] = i;
    }

    /* After R_XSPI_HYPER_Open() and any required device specific initialization, data can be write directly
     * to the HyperRAM connected to XSPI unit 1 */
    for (uint16_t i = 0; i < XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH; i++)
    {
        *((volatile uint16_t *) XSPI1_CS0_MIRROR_BASE + 0x0000 + i) = write_data[i];
    }

    /* After R_XSPI_HYPER_Open() and any required device specific initialization, data can be read directly
     * to the HyperRAM connected to XSPI unit 1 */
    for (uint16_t i = 0; i < XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH; i++)
    {
        read_data[i] = *((volatile uint16_t *) XSPI1_CS0_MIRROR_BASE + 0x0000 + i);
    }

    /* Verify the read data */
    for (uint16_t i = 0; i < XSPI_HYPERRAM_EXAMPLE_DATA_LENGTH; i++)
    {
        if (read_data[i] != write_data[i])
        {
            /* Verify error. */
            __BKPT(0);
        }
    }
}

The initial latency can be changed by changing the settings of bits [7:4] of CR0. The sample code describes the case of changing from the factory default 6 cycle latency (at a maximum operating frequency of 166 MHz) to 4 cycle latency (at a maximum operating frequency of 100 MHz). Set the latency cycle for the HyperBus controller and HyperRAM according to the specification of the using HyperRAM.

Data Structures
struct	xspi_hyper_instance_ctrl_t

Enumerations
enum	xspi_hyper_chip_select_t
enum	xspi_hyper_device_type_t
enum	xspi_hyper_memory_size_t
enum	xspi_hyper_transaction_interval_clocks_t
enum	xspi_hyper_cs_pulldown_clocks_t
enum	xspi_hyper_cs_pullup_clocks_t
enum	xspi_hyper_prefetch_function_t
enum	xspi_hyper_io_voltage_t

---

Data Structure Documentation

xspi_hyper_instance_ctrl_t

struct xspi_hyper_instance_ctrl_t

Instance control block. DO NOT INITIALIZE. Initialization occurs when hyperbus_api_t::open is called

Enumeration Type Documentation

xspi_hyper_chip_select_t

enum xspi_hyper_chip_select_t

Enumerator
XSPI_HYPER_CHIP_SELECT_0	Device connected to Chip-Select 0.
XSPI_HYPER_CHIP_SELECT_1	Device connected to Chip-Select 1.

xspi_hyper_device_type_t

enum xspi_hyper_device_type_t

Enumerator
XSPI_HYPER_DEVICE_TYPE_FLASH	Device Memory type HyperFlash.
XSPI_HYPER_DEVICE_TYPE_RAM	Device Memory type HyperRAM.

xspi_hyper_memory_size_t

enum xspi_hyper_memory_size_t

Enumerator
XSPI_HYPER_MEMORY_SIZE_1MB	Memory size 1MB.
XSPI_HYPER_MEMORY_SIZE_2MB	Memory size 2MB.
XSPI_HYPER_MEMORY_SIZE_4MB	Memory size 4MB.
XSPI_HYPER_MEMORY_SIZE_8MB	Memory size 8MB.
XSPI_HYPER_MEMORY_SIZE_16MB	Memory size 16MB.
XSPI_HYPER_MEMORY_SIZE_32MB	Memory size 32MB.
XSPI_HYPER_MEMORY_SIZE_64MB	Memory size 64MB.

xspi_hyper_transaction_interval_clocks_t

enum xspi_hyper_transaction_interval_clocks_t

Enumerator
XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_1	1 interval clocks
XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_2	2 interval clocks
XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_3	3 interval clocks
XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_4	4 interval clocks
XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_5	5 interval clocks
XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_6	6 interval clocks
XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_7	7 interval clocks
XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_8	8 interval clocks
XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_9	9 interval clocks
XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_10	10 interval clocks
XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_11	11 interval clocks
XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_12	12 interval clocks
XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_13	13 interval clocks
XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_14	14 interval clocks
XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_15	15 interval clocks
XSPI_HYPER_TRANSACTION_INTERVAL_CLOCKS_16	16 interval clocks

xspi_hyper_cs_pulldown_clocks_t

enum xspi_hyper_cs_pulldown_clocks_t

Enumerator
XSPI_HYPER_CS_PULLDOWN_CLOCKS_NO_EXTENSION	CS asserting No extension.
XSPI_HYPER_CS_PULLDOWN_CLOCKS_1	CS asserting Extend 1 cycle.

xspi_hyper_cs_pullup_clocks_t

enum xspi_hyper_cs_pullup_clocks_t

Enumerator
XSPI_HYPER_CS_PULLUP_CLOCKS_NO_EXTENSION	CS negating No extension.
XSPI_HYPER_CS_PULLUP_CLOCKS_1	CS negating Extend 1 cycle.

xspi_hyper_prefetch_function_t

enum xspi_hyper_prefetch_function_t

Enumerator
XSPI_HYPER_PREFETCH_FUNCTION_DISABLE	Prefetch function disable.
XSPI_HYPER_PREFETCH_FUNCTION_ENABLE	Prefetch function enable.

xspi_hyper_io_voltage_t

enum xspi_hyper_io_voltage_t

Enumerator
XSPI_HYPER_IO_VOLTAGE_1_8V	IO voltage 1.8V.
XSPI_HYPER_IO_VOLTAGE_3_3V	IO voltage 3.3V.

Function Documentation

R_XSPI_HYPER_Open()

fsp_err_t R_XSPI_HYPER_Open	(	hyperbus_ctrl_t *	p_ctrl,
		hyperbus_cfg_t const *const	p_cfg
	)

Open the HYPER driver module. After the driver is open, the HyperRAM can be accessed like internal memory.

Implements hyperbus_api_t::open.

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	The parameter p_ctrl or p_cfg is NULL.
FSP_ERR_ALREADY_OPEN	Driver has already been opened with the same p_ctrl.

R_XSPI_HYPER_Close()

fsp_err_t R_XSPI_HYPER_Close

(

hyperbus_ctrl_t *

p_ctrl

)

Close the HYPER driver module.

Implements hyperbus_api_t::close.

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	p_instance_ctrl is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_XSPI_HYPER_BurstTypeSet()

fsp_err_t R_XSPI_HYPER_BurstTypeSet	(	hyperbus_ctrl_t *	p_ctrl,
		hyperbus_burst_type_t	burst_type
	)

Dynamic burst type configuration.

Implements hyperbus_api_t::burstTypeSet

Return values

FSP_ERR_UNSUPPORTED

API not supported by Hyper - HyperRAM. (Only can use Linear Burst)

R_XSPI_HYPER_AccessSpaceSet()

fsp_err_t R_XSPI_HYPER_AccessSpaceSet	(	hyperbus_ctrl_t *	p_ctrl,
		hyperbus_space_select_t	access_space
	)

Dynamic access address space configuration.

Implements hyperbus_api_t::accessSpaceSet

Return values

FSP_SUCCESS	Address space successfully changed as specified by the argument.
FSP_ERR_ASSERTION	The parameter p_ctrl is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_XSPI_HYPER_Write()

fsp_err_t R_XSPI_HYPER_Write	(	hyperbus_ctrl_t *	p_ctrl,
		uint8_t const *const	p_src,
		uint8_t *const	p_dest,
		uint32_t	byte_count
	)

Program a page of data to the flash.

Implements hyperbus_api_t::write.

Return values

FSP_ERR_UNSUPPORTED

API not supported by HyperBus - HyperRAM.

R_XSPI_HYPER_Erase()

fsp_err_t R_XSPI_HYPER_Erase	(	hyperbus_ctrl_t *	p_ctrl,
		uint8_t *const	p_device_address,
		uint32_t	byte_count
	)

Erase a block or sector of flash. The byte_count must exactly match one of the erase sizes defined in hyperbus_cfg_t. For chip erase, byte_count must be HYPER_FLASH_ERASE_SIZE_CHIP_ERASE.

Implements hyperbus_api_t::erase.

Return values

FSP_ERR_UNSUPPORTED

API not supported by HyperBus - HyperRAM.

R_XSPI_HYPER_StatusGet()

fsp_err_t R_XSPI_HYPER_StatusGet	(	hyperbus_ctrl_t *	p_ctrl,
		hyperbus_status_t *const	p_status
	)

Gets the write or erase status of the flash.

Implements hyperbus_api_t::statusGet.

Return values

FSP_ERR_UNSUPPORTED

API not supported by HyperBus - HyperRAM.

R_XSPI_HYPER_AutoCalibrate()

fsp_err_t R_XSPI_HYPER_AutoCalibrate

(

hyperbus_ctrl_t *

p_ctrl

)

Auto-calibrate the HyperRAM device using the preamble pattern.

Implements hyperbus_api_t::autoCalibrate.

Note

The preamble pattern must be written to the configured address before calling this API.

Return values

FSP_ERR_UNSUPPORTED

API not supported by HyperBus - HyperFlash. (Planned support for FSP v2.1.0 or later.)