The following build time configurations are defined in fsp_cfg/bsp/bsp_mcu_family_cfg.h:
| Configuration | Options | Default | Description |
| OFS0 register settings |
| OFS0 register settings > Independent WDT |
| Start Mode |
-
IWDT is Disabled
-
IWDT is automatically activated after a reset (Autostart mode)
| IWDT is Disabled | |
| Timeout Period |
-
128 cycles
-
512 cycles
-
1024 cycles
-
2048 cycles
| 2048 cycles | |
| Dedicated Clock Frequency Divisor |
| 128 | |
| Window End Position |
-
75%
-
50%
-
25%
-
0% (no window end position)
| 0% (no window end position) | |
| Window Start Position |
-
25%
-
50%
-
75%
-
100% (no window start position)
| 100% (no window start position) | |
| Reset Interrupt Request Select |
-
NMI request or interrupt request is enabled
-
Reset is enabled
| Reset is enabled | |
| Stop Control |
-
Counting continues
-
Stop counting when in Sleep, Snooze mode, or Software Standby
| Stop counting when in Sleep, Snooze mode, or Software Standby | |
| OFS1 register settings |
| Voltage Detection 0 Circuit Start |
-
Voltage monitor 0 reset is enabled after reset
-
Voltage monitor 0 reset is disabled after reset
| Voltage monitor 0 reset is disabled after reset | |
| Voltage Detection 0 Level |
-
3.88 V
-
2.91 V
-
2.62 V
-
2.33 V
-
1.86 V
-
1.65 V
| 1.86 V | |
| Enable or disable Flash Read Protection |
| Disabled | |
| Flash Read Protection Start | Value must be an integer between 0x01 and 0x3F (ROM) | 0x01 | |
| Flash Read Protection End | Value must be an integer between 0x01 and 0x3F | 0x3F | |
| P206/RES pin selection |
| RES input | |
| Enable inline BSP IRQ functions |
| Disabled | Using static inline functions will slightly increase code size, but will slightly decrease cycles taken in ISRs in return. |
| Main Oscillation Stabilization Time |
-
2^8/MOSC
-
2^9/MOSC
-
2^10/MOSC
-
2^11/MOSC
-
2^13/MOSC
-
2^15/MOSC
-
2^17/MOSC
-
2^18/MOSC
| 2^18/MOSC | |
| Use Low Voltage Mode | Not Supported | config.bsp.low_voltage_mode.disabled | Use the low voltage mode. This limits the ICLK operating frequency to 4 MHz and requires all clock dividers to be at least 4 when oscillation stop detection is used. |
| ID Code Mode |
-
Unlocked (Ignore ID)
-
Locked with All Erase support
-
Locked
| Unlocked (Ignore ID) | When set to 'Locked with All Erase support', the ID Code must be set in the debugger to read or write data to the MCU, but the All Erase command is still accepted regardless. When set to 'Locked', all erase/download/debug access is disabled unless the ID Code is provided. |
| ID Code (32 Hex Characters) | Value must be a 32 character long hex string | FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF | Set the ID Code for locking debug access. This setting is only used when the ID Code Mode is not set to Unlocked. |
| Fill Flash Gap |
| Fill gap | A section of code flash exists between the end of the vector table (near the start of flash) and the ROM registers (at address 0x400). Selecting 'Fill gap' will fill this area with a preselected set functions in order to reduce the amount of code flash used by FSP. If you would like to fill this area with your own code or data, select 'Do not fill gap' and manually place items in the section '.flash_gap'. |
