Detailed Description

Build Time Configurations for ra0e1_fsp

The following build time configurations are defined in fsp_cfg/bsp/bsp_mcu_family_cfg.h:

Configuration	Options	Default	Description
Enable inline BSP IRQ functions	Enabled Disabled	Disabled	Using static inline functions will slightly increase code size, but will slightly decrease cycles taken in ISRs in return.
Main Oscillation Stabilization Time	2^8/MOSC 2^9/MOSC 2^10/MOSC 2^11/MOSC 2^13/MOSC 2^15/MOSC 2^17/MOSC 2^18/MOSC	2^18/MOSC
Use Low Voltage Mode	Not Supported	Not Supported	Use the low voltage mode. This limits the ICLK operating frequency to 4 MHz and requires all clock dividers to be at least 4 when oscillation stop detection is used.

Groups	Modules
Analog	ADC (r_adc_d)
Connectivity	I2C Master (r_sau_i2c) IICA Master (r_iica_master) IICA Slave (r_iica_slave) LIN (r_sau_lin) SPI (r_sau_spi) UART (r_sau_uart) UART (r_uarta)
Input	External IRQ (r_icu)
Monitoring	CRC (r_crc) Independent Watchdog (r_iwdt) Low/Programmable Voltage Detection (r_lvd)
Power	Low Power Modes (r_lpm)
Storage	Flash (r_flash_lp)
System	Clock Generation Circuit (r_cgc) Event Link Controller (r_elc) I/O Port (r_ioport)
Timers	32-bit Interval Timer (r_tml) Realtime Clock (r_rtc_c) Timer, Independent Channel, 16-bit and 8-bit Timer Operation (r_tau) Timer, Simultaneous Channel Operation (r_tau_pwm)
Transfer	Transfer (r_dtc)

#define BSP_ELC_PERIPHERAL_MASK

Positions of event link set registers (ELSRs) available on this MCU

Sources of event signals to be linked to other peripherals or the CPU

Fixed vector enumeration

Possible peripherals to be linked to event signals