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RA Flexible Software Package Documentation
Release v5.2.0
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RA Flexible Software Package Documentation
Release v5.2.0
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Functions | |
| fsp_err_t | R_FSP_VersionGet (fsp_pack_version_t *const p_version) |
| void | Reset_Handler (void) |
| void | Default_Handler (void) |
| void | NMI_Handler (void) |
| BSP_SECTION_FLASH_GAP void | SystemInit (void) |
| void | R_BSP_WarmStart (bsp_warm_start_event_t event) |
| BSP_SECTION_FLASH_GAP void | R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect) |
| BSP_SECTION_FLASH_GAP void | R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect) |
| BSP_SECTION_FLASH_GAP void | R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units) |
| BSP_SECTION_FLASH_GAP fsp_err_t | R_BSP_GroupIrqWrite (bsp_grp_irq_t irq, void(*p_callback)(bsp_grp_irq_t irq)) |
| uint32_t | R_BSP_SourceClockHzGet (fsp_priv_source_clock_t clock) |
| __STATIC_INLINE IRQn_Type | R_FSP_CurrentIrqGet (void) |
| __STATIC_INLINE uint32_t | R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) |
| __STATIC_INLINE uint32_t | R_FSP_ClockDividerGet (uint32_t ckdivcr) |
| __STATIC_INLINE bsp_unique_id_t const * | R_BSP_UniqueIdGet (void) |
| __STATIC_INLINE void | R_BSP_FlashCacheDisable (void) |
| __STATIC_INLINE void | R_BSP_FlashCacheEnable (void) |
| BSP_SECTION_FLASH_GAP void | R_BSP_IrqClearPending (IRQn_Type irq) |
| BSP_SECTION_FLASH_GAP void | R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void *p_context) |
| BSP_SECTION_FLASH_GAP void | R_BSP_IrqEnableNoClear (IRQn_Type const irq) |
| BSP_SECTION_FLASH_GAP void | R_BSP_IrqEnable (IRQn_Type const irq) |
| BSP_SECTION_FLASH_GAP void | R_BSP_IrqDisable (IRQn_Type const irq) |
| BSP_SECTION_FLASH_GAP void | R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void *p_context) |
The BSP is responsible for getting the MCU from reset to the user's application. Before reaching the user's application, the BSP sets up the stacks, heap, clocks, interrupts, C runtime environment, and stack monitor.
All system clocks are set up during BSP initialization based on the settings in bsp_clock_cfg.h. These settings are derived from clock configuration information provided from the RA Configuration editor Clocks tab.
As RA MCUs are based on the Arm Cortex-M architecture, the NVIC Nested Vectored Interrupt Controller (NVIC) handles exceptions and interrupt configuration, prioritization and interrupt masking. In the Arm architecture, the NVIC handles exceptions. Some exceptions are known as System Exceptions. System exceptions are statically located at the "top" of the vector table and occupy vector numbers 1 to 15. Vector zero is reserved for the MSP Main Stack Pointer (MSP). The remaining 15 system exceptions are shown below:
NMI and Hard Fault exceptions are enabled out of reset and have fixed priorities. Other exceptions have configurable priorities and some can be disabled.
Group interrupt is the term used to describe the 12 sources that can trigger the Non-Maskable Interrupt (NMI). When an NMI occurs the NMI Handler examines the NMISR (status register) to determine the source of the interrupt. NMI interrupts take precedence over all interrupts, are usable only as CPU interrupts, and cannot activate the RA peripherals Data Transfer Controller (DTC) or Direct Memory Access Controller (DMAC).
Possible group interrupt sources include:
User configurable interrupts begin with slot 16. These may be external, or peripheral generated interrupts.
Although the number of available slots for the NVIC interrupt vector table may seem small, the BSP defines up to 512 events that are capable of generating an interrupt. By using Event Mapping, the BSP maps user-enabled events to NVIC interrupts. For an RA6M3 MCU, only 96 of these events may be active at any one time, but the user has flexibility by choosing which events generate the active event.
By allowing the user to select only the events they are interested in as interrupt sources, we are able to provide an interrupt service routine that is fast and event specific.
For example, on other microcontrollers a standard NVIC interrupt vector table might contain a single vector entry for the SCI0 (Serial Communications Interface) peripheral. The interrupt service routine for this would have to check a status register for the 'real' source of the interrupt. In the RA implementation there is a vector entry for each of the SCI0 events that we are interested in.
You might wonder how the BSP is able to place ISR addresses in the NVIC table without the user having explicitly defined one. All that is required by the BSP is that the interrupt event be given a priority.
This is accomplished through the use of the 'weak' attribute. The weak attribute causes the declaration to be emitted as a weak symbol rather than a global. A weak symbol is one that can be overridden by an accompanying strong reference with the same name. When the BSP declares a function as weak, user code can define the same function and it will be used in place of the BSP function. By defining all possible interrupt sources as weak, the vector table can be built at compile time and any user declarations (strong references) will be used at runtime.
Weak symbols are supported for ELF targets and also for a.out targets when using the GNU assembler and linker.
Note that in CMSIS system.c, there is also a weak definition (and a function body) for the Warm Start callback function R_BSP_WarmStart(). Because this function is defined in the same file as the weak declaration, it will be called as the 'default' implementation. The function may be overridden by the user by copying the body into their user application and modifying it as necessary. The linker identifies this as the 'strong' reference and uses it.
As the BSP is in the process of bringing up the board out of reset, there are three points where the user can request a callback. These are defined as the 'Pre Clock Init', 'Post Clock Init' and 'Post C' warm start callbacks.
As described above, this function is already weakly defined as R_BSP_WarmStart(), so it is a simple matter of redefining the function or copying the existing body from CMSIS system.c into the application code to get a callback. R_BSP_WarmStart() takes an event parameter of type bsp_warm_start_event_t which describes the type of warm start callback being made.
This function is not enabled/disabled and is always called for both events as part of the BSP startup. Therefore it needs a function body, which will not be called if the user is overriding it. The function body is located in system.c. To use this function just copy this function into your own code and modify it to meet your needs.
When Sub-Clock oscillator is populated in the application, the BSP startup code waits for some time(sub-clock stabilization time) to allow Sub-clock to stabilize. Enabling the watchdog (IWDT or WDT) timer with Auto start mode in an application using Sub-clock may cause system to generate Reset or NMI interrupt before reaching the application code if watchdog refresh register is not updated in the configured refresh Window. To overcome this problem a weakly defined callback R_BSP_SubClockStabilizeWait() can be overridden. Redefine the callback function in the application code and add code to update the watchdog refresh register. R_BSP_SubClockStabilizeWait() takes a parameter delay of type uint32_t which describes the time in milliseconds required to stabilize the sub-clock.
After Power-On-Reset, the BSP startup code may have to wait for some time(sub-clock stabilization time) to allow Sub-clock to stabilize. This can cause problem to RTC in case device is to be reset frequently. If Sub-Clock registers are not initialized during a reset, BSP actually does not have to wait for Sub-clock to stabilize. To overcome this problem, a weakly defined callback R_BSP_SubClockStabilizeWaitAfterReset() is provided. Reimplement the callback function in the application code to determine whether BSP has to wait for stabilization time based on the current reset type. R_BSP_SubClockStabilizeWaitAfterReset() takes a parameter delay of type uint32_t which describes the time in milliseconds required to stabilize the sub-clock.
This BSP configuration allows the user to skip the FSP C runtime initialization code by setting the "C Runtime Initialization" to "Disabled" on the BSP tab of the RA Configuration editor. Disabling this option is useful in cases where a non-standard linker script is being used or other modifications to the runtime initialization are desired. If this macro is disabled, the user must use the 'Post Clock Init' event from the warm start (described above) to run their own runtime initialization code.
The relatively low amount of on-chip SRAM available and lack of memory protection in an MCU means that heap use must be very carefully controlled to avoid memory leaks, overruns and attempted overallocation. Further, many RTOSes provide their own dynamic memory allocation system. For these reasons the default heap size is set at 0 bytes, effectively disabling dynamic memory. If it is required for an application setting a positive value to the "Heap size (bytes)" option in the RA Common configurations on the BSP tab will allocate a heap.
When error logging is enabled, the error logging function can be redefined on the command line by defining FSP_ERROR_LOG(err) to the desired function call. The default function implementation is FSP_ERROR_LOG(err)=fsp_error_log(err, FILE, LINE). This implementation uses the predefined macros FILE and LINE to help identify the location where the error occurred. Removing the line from the function call can reduce code size when error logging is enabled. Some compilers may support other predefined macros like FUNCTION, which could be helpful for customizing the error logger.
The BSP register protection functions utilize reference counters to ensure that an application which has specified a certain register and subsequently calls another function doesn't have its register protection settings inadvertently modified.
Each time R_BSP_RegisterProtectDisable() is called, the respective reference counter is incremented.
Each time R_BSP_RegisterProtectEnable() is called, the respective reference counter is decremented.
Both functions will only modify the protection state if their reference counter is zero.
Option-setting memory includes OFS registers OFS0 and OFS1, OSIS debugger ID code, and block protections settings BPS and PBPS. Option-setting memory is MCU specific, and not all MCUs implement all option-setting registers. Option-setting configurations available on the selected device are configurable in the BSP properties. These configurations are placed in sections to be loaded at the required flash address by the linker.
The ID code is a 16-byte value that can be used to protect the MCU from being connected to a debugger or from connecting in Serial Boot Mode. There are different settings that can be set for the ID code; please refer to the hardware manual for your device for available options.
On MCUs that support TrustZone, option-setting registers are placed in a different locations for Non-Secure projects than for Secure or Flat projects. This is handled automatically by the BSP and linker scripts.
All *_SEL registers default to allowing both Secure and Non-Secure access unless otherwise noted here. If block protection is configured in a Secure project, the BSP sets the corresponding configuration to Secure access only by updating the corresponding *_SEL register. Similarly, the LVD related settings in the OFSn_SEL registers are automatically set to Secure if the corresponding LVD monitor is used in the Secure project.
On MCUs that support TrustZone, Security Attribution Registers for modules used in the Secure project are configured to allow Secure access only as part of the startup code of the Secure project. This logic is skipped for Flat projects.
Implements a blocking software delay. A delay can be specified in microseconds, milliseconds or seconds. The delay is implemented based on the system clock rate.
Implements Trignometric math inline functions utilizing TFU hardware. These functions can calculate sine, cosine, arctangent and hypotenuse. The trigonometric library functions sinf(), cosf(), atan2f(), and hypotf() can be mapped to respective TFU functions by enabling TFU Mathlib property in FSP Configuration tool. Extended functions sincosf() and atan2hypotf() are also available when the TFU Mathlib property is enabled in the RA Configuration editor.
TFU functions are not reentrant. Disable the TFU Mathlib property in RA Configuration editor if reentrant access to trigonometric library functions is required.
Implements DSP (digital signal processing) functions via MACL (32-bit Multiply-Accumulator) hardware. These functions will support CMSIS DSP APIs to perform the calculation, the activation of MACL can be controlled by stack MACL (rm_cmsis_dsp) in the RA Configuration editor.
When stack MACL (rm_cmsis_dsp) is added, the CMSIS DSP APIs will generate normal functions which overrides weak functions of Arm and use hardware for calculating. When stack MACL (rm_cmsis_dsp) is not added, CMSIS DSP APIs will perform the calculation by using software.
For examples, how to use the CMSIS DSP APIs refer to the link: https://github.com/ARM-software/CMSIS-DSP/tree/main/Examples/ARM.
CMSIS APIs supported by MACL list:
| No | CMSIS DSP API | MACL BSP API | Description |
|---|---|---|---|
| 1 | arm_mult_q31 | R_BSP_MaclMulQ31 | Q31 vector multiplication |
| 2 | arm_scale_q31 | R_BSP_MaclScaleQ31 | Multiplies a Q31 vector by a scalar |
| 3 | arm_mat_mult_q31 | R_BSP_MaclMatMultQ31 | Q31 matrix multiplication |
| 4 | arm_mat_vec_mult_q31 | R_BSP_MaclMatVecMulQ31 | Q31 matrix and vector multiplication |
| 5 | arm_mat_scale_q31 | R_BSP_MaclMatScaleQ31 | Q31 matrix scaling |
| 6 | arm_biquad_cascade_df1_q31 | R_BSP_MaclBiquadCsdDf1Q31 | Processing function for the Q31 Biquad cascade filter |
| 7 | arm_conv_partial_q31 | R_BSP_MaclConvPartialQ31 | Partial convolution of Q31 sequences |
| 8 | arm_conv_q31 | R_BSP_MaclConvQ31 | Convolution of Q31 sequences |
| 9 | arm_correlate_q31 | R_BSP_MaclCorrelateQ31 | Correlation of Q31 sequences |
| 10 | arm_fir_decimate_q31 | R_BSP_MaclFirDecimateQ31 | Processing function for the Q31 FIR decimator |
| 11 | arm_fir_interpolate_q31 | R_BSP_MaclFirInterpolateQ31 | Processing function for the Q31 FIR interpolator |
| 12 | arm_fir_q31 | R_BSP_MaclFirQ31 | Processing function for Q31 FIR filter |
| 13 | arm_fir_sparse_q31 | R_BSP_MaclFirSparseQ31 | Processing function for the Q31 sparse FIR filter |
| 14 | arm_lms_norm_q31 | R_BSP_MaclLmsNormQ31 | Processing function for Q31 normalized LMS filter |
| 15 | arm_lms_q31 | R_BSP_MaclLmsQ31 | Processing function for Q31 LMS filter |
Implements a critical section. Some MCUs (MCUs with the BASEPRI register) support allowing high priority interrupts to execute during critical sections. On these MCUs, interrupts with priority less than or equal to BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION are not serviced in critical sections. Interrupts with higher priority than BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION still execute in critical sections.
Supports changing the Octal-SPI Clock (OCTACLK) during runtime if supported by the MCU. The OCTACLK source and clock divisor can be updated. It is user's responsibility to ensure the selected clock source is running before attempting to update OCTACLK.
In TrustZone secure projects, the BSP seals the main stack by placing the value 0xFEF5EDA5 above the stack top. For more information, refer to section 3.5 "Sealing a Stack" in "Secure software guidelines for ARMv8-M": https://developer.arm.com/documentation/100720/0300.
For MCUs with Cortex-M85 cores with D-Cache, limited support is available for enabling the D-Cache and automatically configuring predefined non-cacheable regions via the MPU during BSP initialization. For these MCUs, D-Cache is disabled by default because certain existing drivers do not support data coherency with D-Cache enabled. Enabling the D-Cache requires that data coherency be considered in any circumstance where a core interacts with other bus members.
The predefined non-cacheable regions configured by the MPU when D-Cache is enabled can be used to contain data that should not be cached, ensuring data coherency for that data. To use the predefined non-cacheable regions, place the data into the corresponding non-cacheable section defined by the linker script for the chosen toolchain. The predefined non-cacheable regions are not initialized by the BSP.
Use one of the .nocache sections to place non-cacheable data.
uint8_t uncached_uninitialized_buffer_sram[1024] BSP_PLACE_IN_SECTION(".nocache");
Section names differ by data region and compiler. Names predefined by the BSP are shown below.
| Region | Name (GCC, IAR, LLVM) | Name (AC6) |
|---|---|---|
| SRAM | .nocache | .bss.nocache |
| SDRAM | .nocache_sdram | .bss.nocache_sdram |
The BSP is heavily data driven with most features and functionality being configured based on the content from configuration files. Configuration files represent the settings specified by the user and are generated when the project is built and/or when the Generate Project Content button is clicked in the RA Configuration editor.
| Configuration | Options | Default | Description |
|---|---|---|---|
| Main stack size (bytes) | Value must be an integer multiple of 8 and between 8 and 0xFFFFFFFF | 0x400 | Set the size of the main program stack. NOTE: This entry is for the main stack. When using an RTOS, thread stacks can be configured in the properties for each thread. |
| Heap size (bytes) | Value must be 0 or an integer multiple of 8 between 8 and 0xFFFFFFFF. | 0 | The main heap is disabled by default. Set the heap size to a positive integer divisible by 8 to enable it. A minimum of 4K (0x1000) is recommended if standard library functions are to be used. |
| MCU Vcc (mV) | Value must between 0 and 5500 (5.5V) | 3300 | Some peripherals require different settings based on the supplied voltage. Entering Vcc here (in mV) allows the relevant driver modules to configure the associated peripherals accordingly. |
| Parameter checking |
| Disabled | When enabled, parameter checking for the BSP is turned on. In addition, any modules whose parameter checking configuration is set to 'Default (BSP)' will perform parameter checking as well. |
| Assert Failures |
| Return FSP_ERR_ASSERTION | Define the behavior of the FSP_ASSERT() macro. |
| Error Log |
| No Error Log | Specify error logging behavior. |
| Clock Registers not Reset Values during Startup |
| Disabled | If enabled, registers are assumed to be set to their reset value during startup. Enable this if another application such as a bootloader or Secure project has already configured the clocks before the startup code runs. |
| Main Oscillator Populated |
| Populated | Select whether or not there is a main oscillator (XTAL) on the board. This setting can be overridden in board_cfg.h. |
| PFS Protect |
| Enabled | Keep the PFS registers locked when they are not being modified. If disabled they will be unlocked during startup. |
| C Runtime Initialization |
| Enabled | Select if the C runtime initialization in the BSP is to be used. If disabled, use the BSP_WARM_START_POST_CLOCK event to run user defined equivalent. |
| Early BSP Initialization |
| Disabled | Enable this option to use BSP functions before C runtime initialization (BSP_WARM_START_RESET or BSP_WARM_START_POST_CLOCK). |
| Main Oscillator Clock Source |
| Crystal or Resonator | Select the main oscillator clock source. This setting can be overridden in board_cfg.h |
| Subclock Populated |
| Populated | Select whether or not there is a subclock crystal on the board. This setting can be overridden in board_cfg.h. |
| Subclock Drive (Drive capacitance availability varies by MCU) |
| Standard/Normal mode | Select the subclock oscillator drive capacitance. This setting can be overridden in board_cfg.h |
| Subclock Stabilization Time (ms) | Value must between 0 and 10000 | 1000 | Select the subclock oscillator stabilization time. This is only used in the startup code if the subclock is selected as the system clock on the Clocks tab or if the HOCO FLL function is enabled. This setting can be overridden in board_cfg.h |
Modules | |
| RA0E1 | |
| RA2A1 | |
| RA2A2 | |
| RA2E1 | |
| RA2E2 | |
| RA2E3 | |
| RA2L1 | |
| RA4E1 | |
| RA4E2 | |
| RA4M1 | |
| RA4M2 | |
| RA4M3 | |
| RA4T1 | |
| RA4W1 | |
| RA6E1 | |
| RA6E2 | |
| RA6M1 | |
| RA6M2 | |
| RA6M3 | |
| RA6M4 | |
| RA6M5 | |
| RA6T1 | |
| RA6T2 | |
| RA6T3 | |
| RA8D1 | |
| RA8M1 | |
| RA8T1 | |
Macros | |
| #define | R_BSP_MODULE_START(ip, channel) |
| #define | R_BSP_MODULE_STOP(ip, channel) |
| #define | BSP_IRQ_DISABLED |
| #define | FSP_LOG_PRINT(X) |
| #define | FSP_RETURN(err) |
| #define | FSP_ERROR_LOG(err) |
| #define | FSP_ASSERT(a) |
| #define | FSP_ERROR_RETURN(a, err) |
| #define | FSP_CRITICAL_SECTION_ENTER |
| #define | FSP_CRITICAL_SECTION_EXIT |
| #define | FSP_INVALID_VECTOR |
| #define | BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) |
| #define | BSP_STACK_ALIGNMENT |
Enumerations | |
| enum | bsp_reg_protect_t |
| enum | bsp_warm_start_event_t |
| enum | fsp_priv_source_clock_t |
| enum | bsp_grp_irq_t |
| enum | bsp_delay_units_t |
| enum | fsp_ip_t |
| enum | fsp_signal_t |
Variables | |
| uint32_t SystemCoreClock | BSP_SECTION_EARLY_INIT |
| #define R_BSP_MODULE_START | ( | ip, | |
| channel | |||
| ) |
Cancels the module stop state.
| ip | fsp_ip_t enum value for the module to be stopped |
| channel | The channel. Use channel 0 for modules without channels. |
| #define R_BSP_MODULE_STOP | ( | ip, | |
| channel | |||
| ) |
Enables the module stop state.
| ip | fsp_ip_t enum value for the module to be stopped |
| channel | The channel. Use channel 0 for modules without channels. |
| #define BSP_IRQ_DISABLED |
Used to signify that an ELC event is not able to be used as an interrupt.
| #define FSP_LOG_PRINT | ( | X | ) |
Macro that can be defined in order to enable logging in FSP modules.
| #define FSP_RETURN | ( | err | ) |
Macro to log and return error without an assertion.
| #define FSP_ERROR_LOG | ( | err | ) |
This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in user code and do required debugging (breakpoints, stack dump, etc) in this function.
| #define FSP_ASSERT | ( | a | ) |
Default assertion calls FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP functions.
| #define FSP_ERROR_RETURN | ( | a, | |
| err | |||
| ) |
All FSP error codes are returned using this macro. Calls FSP_ERROR_LOG function if condition "a" is false. Used to identify runtime errors in FSP functions.
| #define FSP_CRITICAL_SECTION_ENTER |
This macro temporarily saves the current interrupt state and disables interrupts.
| #define FSP_CRITICAL_SECTION_EXIT |
This macro restores the previously saved interrupt state, reenabling interrupts.
| #define FSP_INVALID_VECTOR |
Used to signify that the requested IRQ vector is not defined in this system.
| #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR | ( | x | ) |
In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will alert the user of the error. The user can override this default behavior by defining their own BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro.
| #define BSP_STACK_ALIGNMENT |
Stacks (and heap) must be sized and aligned to an integer multiple of this number.
| enum bsp_reg_protect_t |
The different types of registers that can be protected.
Different warm start entry locations in the BSP.
| enum bsp_grp_irq_t |
Which interrupts can have callbacks registered.
| enum bsp_delay_units_t |
Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds
| enum fsp_ip_t |
Available modules.
| enum fsp_signal_t |
Signals that can be mapped to an interrupt.
| fsp_err_t R_FSP_VersionGet | ( | fsp_pack_version_t *const | p_version | ) |
Get the FSP version based on compile time macros.
| [out] | p_version | Memory address to return version information to. |
| FSP_SUCCESS | Version information stored. |
| FSP_ERR_ASSERTION | The parameter p_version is NULL. |
| BSP_SECTION_FLASH_GAP void Reset_Handler | ( | void | ) |
MCU starts executing here out of reset. Main stack pointer is set up already.
| BSP_SECTION_FLASH_GAP void Default_Handler | ( | void | ) |
Default exception handler.
| BSP_SECTION_FLASH_GAP void NMI_Handler | ( | void | ) |
Non-maskable interrupt handler. This exception is defined by the BSP, unlike other system exceptions, because there are many sources that map to the NMI exception.
| BSP_SECTION_FLASH_GAP void SystemInit | ( | void | ) |
Initialize the MCU and the runtime environment.
| void R_BSP_WarmStart | ( | bsp_warm_start_event_t | event | ) |
This function is called at various points during the startup process. This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user implemented version. One of the main uses for this function is to call functional safety code during the startup process. To use this function just copy this function into your own code and modify it to meet your needs.
| [in] | event | Where the code currently is in the start up process |
This function is called at various points during the startup process. This implementation uses the event that is called right before main() to set up the pins.
| [in] | event | Where at in the start up process the code is currently at |
| BSP_SECTION_FLASH_GAP void R_BSP_RegisterProtectEnable | ( | bsp_reg_protect_t | regs_to_protect | ) |
Enable register protection. Registers that are protected cannot be written to. Register protection is enabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR).
| [in] | regs_to_protect | Registers which have write protection enabled. |
| BSP_SECTION_FLASH_GAP void R_BSP_RegisterProtectDisable | ( | bsp_reg_protect_t | regs_to_unprotect | ) |
Disable register protection. Registers that are protected cannot be written to. Register protection is disabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR).
| [in] | regs_to_unprotect | Registers which have write protection disabled. |
| BSP_SECTION_FLASH_GAP void R_BSP_SoftwareDelay | ( | uint32_t | delay, |
| bsp_delay_units_t | units | ||
| ) |
Delay for at least the specified duration in units and return.
| [in] | delay | The number of 'units' to delay. |
| [in] | units | The 'base' (bsp_delay_units_t) for the units specified. Valid values are: BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS, BSP_DELAY_UNITS_MICROSECONDS. For example: At 1 MHz one cycle takes 1 microsecond (.000001 seconds). At 12 MHz one cycle takes 1/12 microsecond or 83 nanoseconds. Therefore one run through bsp_prv_software_delay_loop() takes: ~ (83 * BSP_DELAY_LOOP_CYCLES) or 332 ns. A delay of 2 us therefore requires 2000ns/332ns or 6 loops. |
The 'theoretical' maximum delay that may be obtained is determined by a full 32 bit loop count and the system clock rate. @120MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 120000000) = 143 seconds. @32MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 32000000) = 536 seconds
Note that requests for very large delays will be affected by rounding in the calculations and the actual delay achieved may be slightly longer. @32 MHz, for example, a request for 532 seconds will be closer to 536 seconds.
Note also that if the calculations result in a loop_cnt of zero, the bsp_prv_software_delay_loop() function is not called at all. In this case the requested delay is too small (nanoseconds) to be carried out by the loop itself, and the overhead associated with executing the code to just get to this point has certainly satisfied the requested delay.
| BSP_SECTION_FLASH_GAP fsp_err_t R_BSP_GroupIrqWrite | ( | bsp_grp_irq_t | irq, |
| void(*)(bsp_grp_irq_t irq) | p_callback | ||
| ) |
Register a callback function for supported interrupts. If NULL is passed for the callback argument then any previously registered callbacks are unregistered.
| [in] | irq | Interrupt for which to register a callback. |
| [in] | p_callback | Pointer to function to call when interrupt occurs. |
| FSP_SUCCESS | Callback registered |
| FSP_ERR_ASSERTION | Callback pointer is NULL |
| uint32_t R_BSP_SourceClockHzGet | ( | fsp_priv_source_clock_t | clock | ) |
Gets the frequency of a source clock.
| [in] | clock | Pointer to Octaclk setting structure which provides information regarding Octaclk source and divider settings to be applied. |
| __STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet | ( | void | ) |
Return active interrupt vector number value
| __STATIC_INLINE uint32_t R_FSP_SystemClockHzGet | ( | fsp_priv_clock_t | clock | ) |
Gets the frequency of a system clock.
| __STATIC_INLINE uint32_t R_FSP_ClockDividerGet | ( | uint32_t | ckdivcr | ) |
Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR).
| __STATIC_INLINE bsp_unique_id_t const* R_BSP_UniqueIdGet | ( | void | ) |
Get unique ID for this device.
| __STATIC_INLINE void R_BSP_FlashCacheDisable | ( | void | ) |
Disables the flash cache.
| __STATIC_INLINE void R_BSP_FlashCacheEnable | ( | void | ) |
Enables the flash cache.
| BSP_SECTION_FLASH_GAP void R_BSP_IrqClearPending | ( | IRQn_Type | irq | ) |
Clear the interrupt status flag (IR) for a given interrupt and clear the NVIC pending interrupt.
| [in] | irq | Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers. |
| BSP_SECTION_FLASH_GAP void R_BSP_IrqCfg | ( | IRQn_Type const | irq, |
| uint32_t | priority, | ||
| void * | p_context | ||
| ) |
Sets the interrupt priority and context.
| [in] | irq | The IRQ to configure. |
| [in] | priority | NVIC priority of the interrupt |
| [in] | p_context | The interrupt context is a pointer to data required in the ISR. |
| BSP_SECTION_FLASH_GAP void R_BSP_IrqEnableNoClear | ( | IRQn_Type const | irq | ) |
Enable the IRQ in the NVIC (Without clearing the pending bit).
| [in] | irq | The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers. |
| BSP_SECTION_FLASH_GAP void R_BSP_IrqEnable | ( | IRQn_Type const | irq | ) |
Clears pending interrupts in both ICU and NVIC, then enables the interrupt.
| [in] | irq | Interrupt for which to clear the IR bit and enable in the NVIC. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers. |
| BSP_SECTION_FLASH_GAP void R_BSP_IrqDisable | ( | IRQn_Type const | irq | ) |
Disables interrupts in the NVIC.
| [in] | irq | The IRQ to disable in the NVIC. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers. |
| BSP_SECTION_FLASH_GAP void R_BSP_IrqCfgEnable | ( | IRQn_Type const | irq, |
| uint32_t | priority, | ||
| void * | p_context | ||
| ) |
Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt.
| [in] | irq | Interrupt number. |
| [in] | priority | NVIC priority of the interrupt |
| [in] | p_context | The interrupt context is a pointer to data required in the ISR. |
| uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT |
System Clock Frequency (Core Clock)