RA Flexible Software Package Documentation  Release v4.1.0

 
MCU Board Support Package

Functions

fsp_err_t R_FSP_VersionGet (fsp_pack_version_t *const p_version)
 
void Reset_Handler (void)
 
void Default_Handler (void)
 
void NMI_Handler (void)
 
void SystemInit (void)
 
void R_BSP_WarmStart (bsp_warm_start_event_t event)
 
fsp_err_t R_BSP_GroupIrqWrite (bsp_grp_irq_t irq, void(*p_callback)(bsp_grp_irq_t irq))
 
uint32_t R_BSP_SourceClockHzGet (fsp_priv_source_clock_t clock)
 
__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void)
 
__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
 
__STATIC_INLINE uint32_t R_FSP_ClockDividerGet (uint32_t ckdivcr)
 
__STATIC_INLINE bsp_unique_id_t const * R_BSP_UniqueIdGet (void)
 
__STATIC_INLINE void R_BSP_FlashCacheDisable (void)
 
__STATIC_INLINE void R_BSP_FlashCacheEnable (void)
 
void R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect)
 
void R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect)
 
void R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units)
 
BSP_TFU_INLINE float __sinf (float angle)
 
BSP_TFU_INLINE float __cosf (float angle)
 
BSP_TFU_INLINE void __sincosf (float angle, float *sin, float *cos)
 
BSP_TFU_INLINE float __atan2f (float y_cord, float x_cord)
 
BSP_TFU_INLINE float __hypotf (float x_cord, float y_cord)
 
BSP_TFU_INLINE void __atan2hypotf (float y_cord, float x_cord, float *atan2, float *hypot)
 

Detailed Description

The BSP is responsible for getting the MCU from reset to the user's application. Before reaching the user's application, the BSP sets up the stacks, heap, clocks, interrupts, C runtime environment, and stack monitor.

Overview

BSP Features

BSP Clock Configuration

All system clocks are set up during BSP initialization based on the settings in bsp_clock_cfg.h. These settings are derived from clock configuration information provided from the RA Configuration editor Clocks tab.

System Interrupts

As RA MCUs are based on the Cortex-M ARM architecture, the NVIC Nested Vectored Interrupt Controller (NVIC) handles exceptions and interrupt configuration, prioritization and interrupt masking. In the ARM architecture, the NVIC handles exceptions. Some exceptions are known as System Exceptions. System exceptions are statically located at the "top" of the vector table and occupy vector numbers 1 to 15. Vector zero is reserved for the MSP Main Stack Pointer (MSP). The remaining 15 system exceptions are shown below:

NMI and Hard Fault exceptions are enabled out of reset and have fixed priorities. Other exceptions have configurable priorities and some can be disabled.

Group Interrupts

Group interrupt is the term used to describe the 12 sources that can trigger the Non-Maskable Interrupt (NMI). When an NMI occurs the NMI Handler examines the NMISR (status register) to determine the source of the interrupt. NMI interrupts take precedence over all interrupts, are usable only as CPU interrupts, and cannot activate the RA peripherals Data Transfer Controller (DTC) or Direct Memory Access Controller (DMAC).

Possible group interrupt sources include:

External and Peripheral Interrupts

User configurable interrupts begin with slot 16. These may be external, or peripheral generated interrupts.

Although the number of available slots for the NVIC interrupt vector table may seem small, the BSP defines up to 512 events that are capable of generating an interrupt. By using Event Mapping, the BSP maps user-enabled events to NVIC interrupts. For an RA6M3 MCU, only 96 of these events may be active at any one time, but the user has flexibility by choosing which events generate the active event.

By allowing the user to select only the events they are interested in as interrupt sources, we are able to provide an interrupt service routine that is fast and event specific.

For example, on other microcontrollers a standard NVIC interrupt vector table might contain a single vector entry for the SCI0 (Serial Communications Interface) peripheral. The interrupt service routine for this would have to check a status register for the 'real' source of the interrupt. In the RA implementation there is a vector entry for each of the SCI0 events that we are interested in.

BSP Weak Symbols

You might wonder how the BSP is able to place ISR addresses in the NVIC table without the user having explicitly defined one. All that is required by the BSP is that the interrupt event be given a priority.

This is accomplished through the use of the 'weak' attribute. The weak attribute causes the declaration to be emitted as a weak symbol rather than a global. A weak symbol is one that can be overridden by an accompanying strong reference with the same name. When the BSP declares a function as weak, user code can define the same function and it will be used in place of the BSP function. By defining all possible interrupt sources as weak, the vector table can be built at compile time and any user declarations (strong references) will be used at runtime.

Weak symbols are supported for ELF targets and also for a.out targets when using the GNU assembler and linker.

Note that in CMSIS system.c, there is also a weak definition (and a function body) for the Warm Start callback function R_BSP_WarmStart(). Because this function is defined in the same file as the weak declaration, it will be called as the 'default' implementation. The function may be overridden by the user by copying the body into their user application and modifying it as necessary. The linker identifies this as the 'strong' reference and uses it.

Warm Start Callbacks

As the BSP is in the process of bringing up the board out of reset, there are three points where the user can request a callback. These are defined as the 'Pre Clock Init', 'Post Clock Init' and 'Post C' warm start callbacks.

As described above, this function is already weakly defined as R_BSP_WarmStart(), so it is a simple matter of redefining the function or copying the existing body from CMSIS system.c into the application code to get a callback. R_BSP_WarmStart() takes an event parameter of type bsp_warm_start_event_t which describes the type of warm start callback being made.

This function is not enabled/disabled and is always called for both events as part of the BSP startup. Therefore it needs a function body, which will not be called if the user is overriding it. The function body is located in system.c. To use this function just copy this function into your own code and modify it to meet your needs.

Sub Clock Stabilization Wait Callback

When Sub-Clock oscillator is populated in the application, the BSP startup code waits for some time(sub-clock stabilization time) to allow Sub-clock to stabilize. Enabling the watchdog (IWDT or WDT) timer with Auto start mode in an application using Sub-clock may cause system to generate Reset or NMI interrupt before reaching the application code if watchdog refresh register is not updated in the configured refresh Window. To overcome this problem a weakly defined callback R_BSP_SubClockStabilizeWait() can be overridden. Redefine the callback function in the application code and add code to update the watchdog refresh register. R_BSP_SubClockStabilizeWait() takes a parameter delay of type uint32_t which describes the time in milliseconds required to stabilize the sub-clock.

C Runtime Initialization

This BSP configuration allows the user to skip the FSP C runtime initialization code by setting the "C Runtime Initialization" to "Disabled" on the BSP tab of the RA Configuration editor. Disabling this option is useful in cases where a non-standard linker script is being used or other modifications to the runtime initialization are desired. If this macro is disabled, the user must use the 'Post Clock Init' event from the warm start (described above) to run their own runtime initialization code.

Heap Allocation

The relatively low amount of on-chip SRAM available and lack of memory protection in an MCU means that heap use must be very carefully controlled to avoid memory leaks, overruns and attempted overallocation. Further, many RTOSes provide their own dynamic memory allocation system. For these reasons the default heap size is set at 0 bytes, effectively disabling dynamic memory. If it is required for an application setting a positive value to the "Heap size (bytes)" option in the RA Common configurations on the BSP tab will allocate a heap.

Note
When using printf/sprintf (and other variants) to output floating point numbers a heap is required. A minimum size of 0x1000 (4096) bytes is recommended when starting development in this case.

Error Logging

When error logging is enabled, the error logging function can be redefined on the command line by defining FSP_ERROR_LOG(err) to the desired function call. The default function implementation is FSP_ERROR_LOG(err)=fsp_error_log(err, FILE, LINE). This implementation uses the predefined macros FILE and LINE to help identify the location where the error occurred. Removing the line from the function call can reduce code size when error logging is enabled. Some compilers may support other predefined macros like FUNCTION, which could be helpful for customizing the error logger.

Register Protection

The BSP register protection functions utilize reference counters to ensure that an application which has specified a certain register and subsequently calls another function doesn't have its register protection settings inadvertently modified.

Each time R_BSP_RegisterProtectDisable() is called, the respective reference counter is incremented.

Each time R_BSP_RegisterProtectEnable() is called, the respective reference counter is decremented.

Both functions will only modify the protection state if their reference counter is zero.

/* Enable writing to protected CGC registers */
/* Insert code to modify protected CGC registers. */
/* Disable writing to protected CGC registers */

Option-setting memory

Option-setting memory includes OFS registers OFS0 and OFS1, OSIS debugger ID code, and block protections settings BPS and PBPS. Option-setting memory is MCU specific, and not all MCUs implement all option-setting registers. Option-setting configurations available on the selected device are configurable in the BSP properties. These configurations are placed in sections to be loaded at the required flash address by the linker.

The ID code is a 16-byte value that can be used to protect the MCU from being connected to a debugger or from connecting in Serial Boot Mode. There are different settings that can be set for the ID code; please refer to the hardware manual for your device for available options.

On MCUs that support TrustZone, option-setting registers are placed in a different locations for Non-Secure projects than for Secure or Flat projects. This is handled automatically by the BSP and linker scripts.

All *_SEL registers default to allowing both Secure and Non-Secure access unless otherwise noted here. If block protection is configured in a Secure project, the BSP sets the corresponding configuration to Secure access only by updating the corresponding *_SEL register. Similarly, the LVD related settings in the OFSn_SEL registers are automatically set to Secure if the corresponding LVD monitor is used in the Secure project.

TrustZone Security Attribution Registers

On MCUs that support TrustZone, Security Attribution Registers for modules used in the Secure project are configured to allow Secure access only as part of the startup code of the Secure project. This logic is skipped for Flat projects.

Software Delay

Implements a blocking software delay. A delay can be specified in microseconds, milliseconds or seconds. The delay is implemented based on the system clock rate.

/* Delay at least 1 second. Depending on the number of wait states required for the region of memory
* that the software_delay_loop has been linked in this could take longer. The default is 4 cycles per loop.
* This can be modified by redefining DELAY_LOOP_CYCLES. BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS,
* and BSP_DELAY_UNITS_MICROSECONDS can all be used with R_BSP_SoftwareDelay. */

Trignometric Function

Implements Trignometric math inline functions utilizing TFU hardware. These functions can calculate sine, cosine, arctangent and hypotenuse. The trigonometric library functions sinf(), cosf(), atan2f(), and hypotf() can be mapped to respective TFU functions by enabling TFU Mathlib property in FSP Configuration tool. Extended functions sincosf() and atan2hypotf() are also available when the TFU Mathlib property is enabled in the RA Configuration editor.

TFU functions are not reentrant. Disable the TFU Mathlib property in RA Configuration editor if reentrant access to trigonometric library functions is required.

Note
Refer to the MCU hardware user's manual or datasheet to determine if it has TFU support.

Critical Section Macros

Implements a critical section. Some MCUs (MCUs with the BASEPRI register) support allowing high priority interrupts to execute during critical sections. On these MCUs, interrupts with priority less than or equal to BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION are not serviced in critical sections. Interrupts with higher priority than BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION still execute in critical sections.

FSP_CRITICAL_SECTION_DEFINE;
/* Store the current interrupt posture. */
/* Interrupts cannot run in this section unless their priority is less than BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION. */
/* Restore saved interrupt posture. */

OctaClock Update

Supports changing the Octal-SPI Clock (OCTACLK) during runtime if supported by the MCU. The OCTACLK source and clock divisor can be updated. It is user's responsibility to ensure the selected clock source is running before attempting to update OCTACLK.

Sealing the Main Stack (TrustZone Secure Projects)

In TrustZone secure projects, the BSP seals the main stack by placing the value 0xFEF5EDA5 above the stack top. For more information, refer to section 3.5 "Sealing a Stack" in "Secure software guidelines for ARMv8-M": https://developer.arm.com/documentation/100720/0300.

Board Specific Features

The BSP will call the board's initialization function (bsp_init) which can initialize board specific features. Possible board features are listed below.

Board Feature Description
SDRAM Support The BSP will initialize SDRAM if the board supports it
QSPI Support The BSP will initialize QSPI if the board supports it and put it into ROM mode. Use the R_QSPI module to write and erase the QSPI chip.

Configuration

The BSP is heavily data driven with most features and functionality being configured based on the content from configuration files. Configuration files represent the settings specified by the user and are generated when the project is built and/or when the Generate Project Content button is clicked in the RA Configuration editor.

Build Time Configurations for fsp_common

The following build time configurations are defined in fsp_cfg/bsp/bsp_cfg.h:

ConfigurationOptionsDefaultDescription
Main stack size (bytes)Value must be an integer multiple of 8 and between 8 and 0xFFFFFFFF0x400 Set the size of the main program stack.

NOTE: This entry is for the main stack. When using an RTOS, thread stacks can be configured in the properties for each thread.
Heap size (bytes)Value must be 0 or an integer multiple of 8 between 8 and 0xFFFFFFFF.0 The main heap is disabled by default. Set the heap size to a positive integer divisible by 8 to enable it.

A minimum of 4K (0x1000) is recommended if standard library functions are to be used.
MCU Vcc (mV)Value must between 0 and 5500 (5.5V)3300 Some peripherals require different settings based on the supplied voltage. Entering Vcc here (in mV) allows the relevant driver modules to configure the associated peripherals accordingly.
Parameter checking
  • Enabled
  • Disabled
Disabled When enabled, parameter checking for the BSP is turned on. In addition, any modules whose parameter checking configuration is set to 'Default (BSP)' will perform parameter checking as well.
Assert Failures
  • Return FSP_ERR_ASSERTION
  • Call fsp_error_log then Return FSP_ERR_ASSERTION
  • Use assert() to Halt Execution
  • Disable checks that would return FSP_ERR_ASSERTION
Return FSP_ERR_ASSERTION Define the behavior of the FSP_ASSERT() macro.
Error Log
  • No Error Log
  • Errors Logged via fsp_error_log
No Error Log Specify error logging behavior.
Clock Registers not Reset Values during Startup
  • Disabled
  • Enabled
Disabled If enabled, registers are assumed to be set to their reset value during startup. Enable this if another application such as a bootloader or Secure project has already configured the clocks before the startup code runs.
Main Oscillator Populated
  • Populated
  • Not Populated
Populated Select whether or not there is a main oscillator (XTAL) on the board. This setting can be overridden in board_cfg.h.
PFS Protect
  • Disabled
  • Enabled
Enabled Keep the PFS registers locked when they are not being modified. If disabled they will be unlocked during startup.
C Runtime Initialization
  • Enabled
  • Disabled
Enabled Select if the C runtime initialization in the BSP is to be used. If disabled, use the BSP_WARM_START_POST_CLOCK event to run user defined equivalent.
Early BSP Initialization
  • Enabled
  • Disabled
Disabled Enable this option to use BSP functions before C runtime initialization (BSP_WARM_START_RESET or BSP_WARM_START_POST_CLOCK).
Main Oscillator Clock Source
  • External Oscillator
  • Crystal or Resonator
Crystal or Resonator Select the main oscillator clock source. This setting can be overridden in board_cfg.h
Subclock Populated
  • Populated
  • Not Populated
Populated Select whether or not there is a subclock crystal on the board. This setting can be overridden in board_cfg.h.
Subclock Drive (Drive capacitance availability varies by MCU)
  • Standard/Normal mode
  • Low/Low power mode 1
  • Low power mode 2
  • Low power mode 3
Standard/Normal mode Select the subclock oscillator drive capacitance. This setting can be overridden in board_cfg.h
Subclock Stabilization Time (ms)Value must between 0 and 100001000 Select the subclock oscillator stabilization time. This is only used in the startup code if the subclock is selected as the system clock on the Clocks tab or if the HOCO FLL function is enabled. This setting can be overridden in board_cfg.h

Modules

 RA2A1
 
 RA2E1
 
 RA2E2
 
 RA2L1
 
 RA4E1
 
 RA4M1
 
 RA4M2
 
 RA4M3
 
 RA4W1
 
 RA6E1
 
 RA6M1
 
 RA6M2
 
 RA6M3
 
 RA6M4
 
 RA6M5
 
 RA6T1
 
 RA6T2
 

Macros

#define BSP_IRQ_DISABLED
 
#define FSP_LOG_PRINT(X)
 
#define FSP_RETURN(err)
 
#define FSP_ERROR_LOG(err)
 
#define FSP_ASSERT(a)
 
#define FSP_ERROR_RETURN(a, err)
 
#define FSP_CRITICAL_SECTION_ENTER
 
#define FSP_CRITICAL_SECTION_EXIT
 
#define FSP_INVALID_VECTOR
 
#define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x)
 
#define BSP_STACK_ALIGNMENT
 
#define R_BSP_MODULE_START(ip, channel)
 
#define R_BSP_MODULE_STOP(ip, channel)
 

Enumerations

enum  bsp_grp_irq_t
 
enum  bsp_warm_start_event_t
 
enum  fsp_priv_source_clock_t
 
enum  bsp_reg_protect_t
 
enum  bsp_delay_units_t
 
enum  fsp_ip_t
 
enum  fsp_signal_t
 

Variables

uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT
 

Macro Definition Documentation

◆ BSP_IRQ_DISABLED

#define BSP_IRQ_DISABLED

Used to signify that an ELC event is not able to be used as an interrupt.

◆ FSP_LOG_PRINT

#define FSP_LOG_PRINT (   X)

Macro that can be defined in order to enable logging in FSP modules.

◆ FSP_RETURN

#define FSP_RETURN (   err)

Macro to log and return error without an assertion.

◆ FSP_ERROR_LOG

#define FSP_ERROR_LOG (   err)

This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in user code and do required debugging (breakpoints, stack dump, etc) in this function.

◆ FSP_ASSERT

#define FSP_ASSERT (   a)

Default assertion calls FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP functions.

◆ FSP_ERROR_RETURN

#define FSP_ERROR_RETURN (   a,
  err 
)

All FSP error codes are returned using this macro. Calls FSP_ERROR_LOG function if condition "a" is false. Used to identify runtime errors in FSP functions.

◆ FSP_CRITICAL_SECTION_ENTER

#define FSP_CRITICAL_SECTION_ENTER

This macro temporarily saves the current interrupt state and disables interrupts.

◆ FSP_CRITICAL_SECTION_EXIT

#define FSP_CRITICAL_SECTION_EXIT

This macro restores the previously saved interrupt state, reenabling interrupts.

◆ FSP_INVALID_VECTOR

#define FSP_INVALID_VECTOR

Used to signify that the requested IRQ vector is not defined in this system.

◆ BSP_CFG_HANDLE_UNRECOVERABLE_ERROR

#define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR (   x)

In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will alert the user of the error. The user can override this default behavior by defining their own BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro.

◆ BSP_STACK_ALIGNMENT

#define BSP_STACK_ALIGNMENT

Stacks (and heap) must be sized and aligned to an integer multiple of this number.

◆ R_BSP_MODULE_START

#define R_BSP_MODULE_START (   ip,
  channel 
)

Cancels the module stop state.

Parameters
ipfsp_ip_t enum value for the module to be stopped
channelThe channel. Use channel 0 for modules without channels.

◆ R_BSP_MODULE_STOP

#define R_BSP_MODULE_STOP (   ip,
  channel 
)

Enables the module stop state.

Parameters
ipfsp_ip_t enum value for the module to be stopped
channelThe channel. Use channel 0 for modules without channels.

Enumeration Type Documentation

◆ bsp_grp_irq_t

Which interrupts can have callbacks registered.

Enumerator
BSP_GRP_IRQ_IWDT_ERROR 

IWDT underflow/refresh error has occurred.

BSP_GRP_IRQ_WDT_ERROR 

WDT underflow/refresh error has occurred.

BSP_GRP_IRQ_LVD1 

Voltage monitoring 1 interrupt.

BSP_GRP_IRQ_LVD2 

Voltage monitoring 2 interrupt.

BSP_GRP_IRQ_VBATT 

VBATT monitor interrupt.

BSP_GRP_IRQ_OSC_STOP_DETECT 

Oscillation stop is detected.

BSP_GRP_IRQ_NMI_PIN 

NMI Pin interrupt.

BSP_GRP_IRQ_RAM_PARITY 

RAM Parity Error.

BSP_GRP_IRQ_RAM_ECC 

RAM ECC Error.

BSP_GRP_IRQ_MPU_BUS_SLAVE 

MPU Bus Slave Error.

BSP_GRP_IRQ_MPU_BUS_MASTER 

MPU Bus Master Error.

BSP_GRP_IRQ_MPU_STACK 

MPU Stack Error.

BSP_GRP_IRQ_TRUSTZONE 

MPU Stack Error.

BSP_GRP_IRQ_CACHE_PARITY 

MPU Stack Error.

◆ bsp_warm_start_event_t

Different warm start entry locations in the BSP.

Enumerator
BSP_WARM_START_RESET 

Called almost immediately after reset. No C runtime environment, clocks, or IRQs.

BSP_WARM_START_POST_CLOCK 

Called after clock initialization. No C runtime environment or IRQs.

BSP_WARM_START_POST_C 

Called after clocks and C runtime environment have been set up.

◆ fsp_priv_source_clock_t

Enumerator
FSP_PRIV_CLOCK_HOCO 

The high speed on chip oscillator.

FSP_PRIV_CLOCK_MOCO 

The middle speed on chip oscillator.

FSP_PRIV_CLOCK_LOCO 

The low speed on chip oscillator.

FSP_PRIV_CLOCK_MAIN_OSC 

The main oscillator.

FSP_PRIV_CLOCK_SUBCLOCK 

The subclock oscillator.

FSP_PRIV_CLOCK_PLL 

The PLL oscillator.

FSP_PRIV_CLOCK_PLL2 

The PLL2 oscillator.

◆ bsp_reg_protect_t

The different types of registers that can be protected.

Enumerator
BSP_REG_PROTECT_CGC 

Enables writing to the registers related to the clock generation circuit.

BSP_REG_PROTECT_OM_LPC_BATT 

Enables writing to the registers related to operating modes, low power consumption, and battery backup function.

BSP_REG_PROTECT_LVD 

Enables writing to the registers related to the LVD: LVCMPCR, LVDLVLR, LVD1CR0, LVD1CR1, LVD1SR, LVD2CR0, LVD2CR1, LVD2SR.

BSP_REG_PROTECT_SAR 

Enables writing to the registers related to the security function.

◆ bsp_delay_units_t

Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds

Enumerator
BSP_DELAY_UNITS_SECONDS 

Requested delay amount is in seconds.

BSP_DELAY_UNITS_MILLISECONDS 

Requested delay amount is in milliseconds.

BSP_DELAY_UNITS_MICROSECONDS 

Requested delay amount is in microseconds.

◆ fsp_ip_t

enum fsp_ip_t

Available modules.

Enumerator
FSP_IP_CFLASH 

Code Flash.

FSP_IP_DFLASH 

Data Flash.

FSP_IP_RAM 

RAM.

FSP_IP_LVD 

Low Voltage Detection.

FSP_IP_CGC 

Clock Generation Circuit.

FSP_IP_LPM 

Low Power Modes.

FSP_IP_FCU 

Flash Control Unit.

FSP_IP_ICU 

Interrupt Control Unit.

FSP_IP_DMAC 

DMA Controller.

FSP_IP_DTC 

Data Transfer Controller.

FSP_IP_IOPORT 

I/O Ports.

FSP_IP_PFS 

Pin Function Select.

FSP_IP_ELC 

Event Link Controller.

FSP_IP_MPU 

Memory Protection Unit.

FSP_IP_MSTP 

Module Stop.

FSP_IP_MMF 

Memory Mirror Function.

FSP_IP_KEY 

Key Interrupt Function.

FSP_IP_CAC 

Clock Frequency Accuracy Measurement Circuit.

FSP_IP_DOC 

Data Operation Circuit.

FSP_IP_CRC 

Cyclic Redundancy Check Calculator.

FSP_IP_SCI 

Serial Communications Interface.

FSP_IP_IIC 

I2C Bus Interface.

FSP_IP_SPI 

Serial Peripheral Interface.

FSP_IP_CTSU 

Capacitive Touch Sensing Unit.

FSP_IP_SCE 

Secure Cryptographic Engine.

FSP_IP_SLCDC 

Segment LCD Controller.

FSP_IP_AES 

Advanced Encryption Standard.

FSP_IP_TRNG 

True Random Number Generator.

FSP_IP_FCACHE 

Flash Cache.

FSP_IP_SRAM 

SRAM.

FSP_IP_ADC 

A/D Converter.

FSP_IP_DAC 

12-Bit D/A Converter

FSP_IP_TSN 

Temperature Sensor.

FSP_IP_DAAD 

D/A A/D Synchronous Unit.

FSP_IP_ACMPHS 

High Speed Analog Comparator.

FSP_IP_ACMPLP 

Low Power Analog Comparator.

FSP_IP_OPAMP 

Operational Amplifier.

FSP_IP_SDADC 

Sigma Delta A/D Converter.

FSP_IP_RTC 

Real Time Clock.

FSP_IP_WDT 

Watch Dog Timer.

FSP_IP_IWDT 

Independent Watch Dog Timer.

FSP_IP_GPT 

General PWM Timer.

FSP_IP_POEG 

Port Output Enable for GPT.

FSP_IP_OPS 

Output Phase Switch.

FSP_IP_AGT 

Asynchronous General-Purpose Timer.

FSP_IP_CAN 

Controller Area Network.

FSP_IP_IRDA 

Infrared Data Association.

FSP_IP_QSPI 

Quad Serial Peripheral Interface.

FSP_IP_USBFS 

USB Full Speed.

FSP_IP_SDHI 

SD/MMC Host Interface.

FSP_IP_SRC 

Sampling Rate Converter.

FSP_IP_SSI 

Serial Sound Interface.

FSP_IP_DALI 

Digital Addressable Lighting Interface.

FSP_IP_ETHER 

Ethernet MAC Controller.

FSP_IP_EDMAC 

Ethernet DMA Controller.

FSP_IP_EPTPC 

Ethernet PTP Controller.

FSP_IP_PDC 

Parallel Data Capture Unit.

FSP_IP_GLCDC 

Graphics LCD Controller.

FSP_IP_DRW 

2D Drawing Engine

FSP_IP_JPEG 

JPEG.

FSP_IP_DAC8 

8-Bit D/A Converter

FSP_IP_USBHS 

USB High Speed.

FSP_IP_OSPI 

Octa Serial Peripheral Interface.

FSP_IP_CEC 

HDMI CEC.

FSP_IP_TFU 

Trigonometric Function Unit.

FSP_IP_IIRFA 

IIR Filter Accelerator.

FSP_IP_CANFD 

CAN-FD.

◆ fsp_signal_t

Signals that can be mapped to an interrupt.

Enumerator
FSP_SIGNAL_ADC_COMPARE_MATCH 

ADC COMPARE MATCH.

FSP_SIGNAL_ADC_COMPARE_MISMATCH 

ADC COMPARE MISMATCH.

FSP_SIGNAL_ADC_SCAN_END 

ADC SCAN END.

FSP_SIGNAL_ADC_SCAN_END_B 

ADC SCAN END B.

FSP_SIGNAL_ADC_WINDOW_A 

ADC WINDOW A.

FSP_SIGNAL_ADC_WINDOW_B 

ADC WINDOW B.

FSP_SIGNAL_AES_RDREQ 

AES RDREQ.

FSP_SIGNAL_AES_WRREQ 

AES WRREQ.

FSP_SIGNAL_AGT_COMPARE_A 

AGT COMPARE A.

FSP_SIGNAL_AGT_COMPARE_B 

AGT COMPARE B.

FSP_SIGNAL_AGT_INT 

AGT INT.

FSP_SIGNAL_CAC_FREQUENCY_ERROR 

CAC FREQUENCY ERROR.

FSP_SIGNAL_CAC_MEASUREMENT_END 

CAC MEASUREMENT END.

FSP_SIGNAL_CAC_OVERFLOW 

CAC OVERFLOW.

FSP_SIGNAL_CAN_ERROR 

CAN ERROR.

FSP_SIGNAL_CAN_FIFO_RX 

CAN FIFO RX.

FSP_SIGNAL_CAN_FIFO_TX 

CAN FIFO TX.

FSP_SIGNAL_CAN_MAILBOX_RX 

CAN MAILBOX RX.

FSP_SIGNAL_CAN_MAILBOX_TX 

CAN MAILBOX TX.

FSP_SIGNAL_CGC_MOSC_STOP 

CGC MOSC STOP.

FSP_SIGNAL_LPM_SNOOZE_REQUEST 

LPM SNOOZE REQUEST.

FSP_SIGNAL_LVD_LVD1 

LVD LVD1.

FSP_SIGNAL_LVD_LVD2 

LVD LVD2.

FSP_SIGNAL_VBATT_LVD 

VBATT LVD.

FSP_SIGNAL_LVD_VBATT 

LVD VBATT.

FSP_SIGNAL_ACMPHS_INT 

ACMPHS INT.

FSP_SIGNAL_ACMPLP_INT 

ACMPLP INT.

FSP_SIGNAL_CTSU_END 

CTSU END.

FSP_SIGNAL_CTSU_READ 

CTSU READ.

FSP_SIGNAL_CTSU_WRITE 

CTSU WRITE.

FSP_SIGNAL_DALI_DEI 

DALI DEI.

FSP_SIGNAL_DALI_CLI 

DALI CLI.

FSP_SIGNAL_DALI_SDI 

DALI SDI.

FSP_SIGNAL_DALI_BPI 

DALI BPI.

FSP_SIGNAL_DALI_FEI 

DALI FEI.

FSP_SIGNAL_DALI_SDI_OR_BPI 

DALI SDI OR BPI.

FSP_SIGNAL_DMAC_INT 

DMAC INT.

FSP_SIGNAL_DOC_INT 

DOC INT.

FSP_SIGNAL_DRW_INT 

DRW INT.

FSP_SIGNAL_DTC_COMPLETE 

DTC COMPLETE.

FSP_SIGNAL_DTC_END 

DTC END.

FSP_SIGNAL_EDMAC_EINT 

EDMAC EINT.

FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 

ELC SOFTWARE EVENT 0.

FSP_SIGNAL_ELC_SOFTWARE_EVENT_1 

ELC SOFTWARE EVENT 1.

FSP_SIGNAL_EPTPC_IPLS 

EPTPC IPLS.

FSP_SIGNAL_EPTPC_MINT 

EPTPC MINT.

FSP_SIGNAL_EPTPC_PINT 

EPTPC PINT.

FSP_SIGNAL_EPTPC_TIMER0_FALL 

EPTPC TIMER0 FALL.

FSP_SIGNAL_EPTPC_TIMER0_RISE 

EPTPC TIMER0 RISE.

FSP_SIGNAL_EPTPC_TIMER1_FALL 

EPTPC TIMER1 FALL.

FSP_SIGNAL_EPTPC_TIMER1_RISE 

EPTPC TIMER1 RISE.

FSP_SIGNAL_EPTPC_TIMER2_FALL 

EPTPC TIMER2 FALL.

FSP_SIGNAL_EPTPC_TIMER2_RISE 

EPTPC TIMER2 RISE.

FSP_SIGNAL_EPTPC_TIMER3_FALL 

EPTPC TIMER3 FALL.

FSP_SIGNAL_EPTPC_TIMER3_RISE 

EPTPC TIMER3 RISE.

FSP_SIGNAL_EPTPC_TIMER4_FALL 

EPTPC TIMER4 FALL.

FSP_SIGNAL_EPTPC_TIMER4_RISE 

EPTPC TIMER4 RISE.

FSP_SIGNAL_EPTPC_TIMER5_FALL 

EPTPC TIMER5 FALL.

FSP_SIGNAL_EPTPC_TIMER5_RISE 

EPTPC TIMER5 RISE.

FSP_SIGNAL_FCU_FIFERR 

FCU FIFERR.

FSP_SIGNAL_FCU_FRDYI 

FCU FRDYI.

FSP_SIGNAL_GLCDC_LINE_DETECT 

GLCDC LINE DETECT.

FSP_SIGNAL_GLCDC_UNDERFLOW_1 

GLCDC UNDERFLOW 1.

FSP_SIGNAL_GLCDC_UNDERFLOW_2 

GLCDC UNDERFLOW 2.

FSP_SIGNAL_GPT_CAPTURE_COMPARE_A 

GPT CAPTURE COMPARE A.

FSP_SIGNAL_GPT_CAPTURE_COMPARE_B 

GPT CAPTURE COMPARE B.

FSP_SIGNAL_GPT_COMPARE_C 

GPT COMPARE C.

FSP_SIGNAL_GPT_COMPARE_D 

GPT COMPARE D.

FSP_SIGNAL_GPT_COMPARE_E 

GPT COMPARE E.

FSP_SIGNAL_GPT_COMPARE_F 

GPT COMPARE F.

FSP_SIGNAL_GPT_COUNTER_OVERFLOW 

GPT COUNTER OVERFLOW.

FSP_SIGNAL_GPT_COUNTER_UNDERFLOW 

GPT COUNTER UNDERFLOW.

FSP_SIGNAL_GPT_AD_TRIG_A 

GPT AD TRIG A.

FSP_SIGNAL_GPT_AD_TRIG_B 

GPT AD TRIG B.

FSP_SIGNAL_OPS_UVW_EDGE 

OPS UVW EDGE.

FSP_SIGNAL_ICU_IRQ0 

ICU IRQ0.

FSP_SIGNAL_ICU_IRQ1 

ICU IRQ1.

FSP_SIGNAL_ICU_IRQ2 

ICU IRQ2.

FSP_SIGNAL_ICU_IRQ3 

ICU IRQ3.

FSP_SIGNAL_ICU_IRQ4 

ICU IRQ4.

FSP_SIGNAL_ICU_IRQ5 

ICU IRQ5.

FSP_SIGNAL_ICU_IRQ6 

ICU IRQ6.

FSP_SIGNAL_ICU_IRQ7 

ICU IRQ7.

FSP_SIGNAL_ICU_IRQ8 

ICU IRQ8.

FSP_SIGNAL_ICU_IRQ9 

ICU IRQ9.

FSP_SIGNAL_ICU_IRQ10 

ICU IRQ10.

FSP_SIGNAL_ICU_IRQ11 

ICU IRQ11.

FSP_SIGNAL_ICU_IRQ12 

ICU IRQ12.

FSP_SIGNAL_ICU_IRQ13 

ICU IRQ13.

FSP_SIGNAL_ICU_IRQ14 

ICU IRQ14.

FSP_SIGNAL_ICU_IRQ15 

ICU IRQ15.

FSP_SIGNAL_ICU_SNOOZE_CANCEL 

ICU SNOOZE CANCEL.

FSP_SIGNAL_IIC_ERI 

IIC ERI.

FSP_SIGNAL_IIC_RXI 

IIC RXI.

FSP_SIGNAL_IIC_TEI 

IIC TEI.

FSP_SIGNAL_IIC_TXI 

IIC TXI.

FSP_SIGNAL_IIC_WUI 

IIC WUI.

FSP_SIGNAL_IOPORT_EVENT_1 

IOPORT EVENT 1.

FSP_SIGNAL_IOPORT_EVENT_2 

IOPORT EVENT 2.

FSP_SIGNAL_IOPORT_EVENT_3 

IOPORT EVENT 3.

FSP_SIGNAL_IOPORT_EVENT_4 

IOPORT EVENT 4.

FSP_SIGNAL_IOPORT_EVENT_B 

IOPORT EVENT B.

FSP_SIGNAL_IOPORT_EVENT_C 

IOPORT EVENT C.

FSP_SIGNAL_IOPORT_EVENT_D 

IOPORT EVENT D.

FSP_SIGNAL_IOPORT_EVENT_E 

IOPORT EVENT E.

FSP_SIGNAL_IWDT_UNDERFLOW 

IWDT UNDERFLOW.

FSP_SIGNAL_JPEG_JDTI 

JPEG JDTI.

FSP_SIGNAL_JPEG_JEDI 

JPEG JEDI.

FSP_SIGNAL_KEY_INT 

KEY INT.

FSP_SIGNAL_PDC_FRAME_END 

PDC FRAME END.

FSP_SIGNAL_PDC_INT 

PDC INT.

FSP_SIGNAL_PDC_RECEIVE_DATA_READY 

PDC RECEIVE DATA READY.

FSP_SIGNAL_POEG_EVENT 

POEG EVENT.

FSP_SIGNAL_QSPI_INT 

QSPI INT.

FSP_SIGNAL_RTC_ALARM 

RTC ALARM.

FSP_SIGNAL_RTC_PERIOD 

RTC PERIOD.

FSP_SIGNAL_RTC_CARRY 

RTC CARRY.

FSP_SIGNAL_SCE_INTEGRATE_RDRDY 

SCE INTEGRATE RDRDY.

FSP_SIGNAL_SCE_INTEGRATE_WRRDY 

SCE INTEGRATE WRRDY.

FSP_SIGNAL_SCE_LONG_PLG 

SCE LONG PLG.

FSP_SIGNAL_SCE_PROC_BUSY 

SCE PROC BUSY.

FSP_SIGNAL_SCE_RDRDY_0 

SCE RDRDY 0.

FSP_SIGNAL_SCE_RDRDY_1 

SCE RDRDY 1.

FSP_SIGNAL_SCE_ROMOK 

SCE ROMOK.

FSP_SIGNAL_SCE_TEST_BUSY 

SCE TEST BUSY.

FSP_SIGNAL_SCE_WRRDY_0 

SCE WRRDY 0.

FSP_SIGNAL_SCE_WRRDY_1 

SCE WRRDY 1.

FSP_SIGNAL_SCE_WRRDY_4 

SCE WRRDY 4.

FSP_SIGNAL_SCI_AM 

SCI AM.

FSP_SIGNAL_SCI_ERI 

SCI ERI.

FSP_SIGNAL_SCI_RXI 

SCI RXI.

FSP_SIGNAL_SCI_RXI_OR_ERI 

SCI RXI OR ERI.

FSP_SIGNAL_SCI_TEI 

SCI TEI.

FSP_SIGNAL_SCI_TXI 

SCI TXI.

FSP_SIGNAL_SDADC_ADI 

SDADC ADI.

FSP_SIGNAL_SDADC_SCANEND 

SDADC SCANEND.

FSP_SIGNAL_SDADC_CALIEND 

SDADC CALIEND.

FSP_SIGNAL_SDHIMMC_ACCS 

SDHIMMC ACCS.

FSP_SIGNAL_SDHIMMC_CARD 

SDHIMMC CARD.

FSP_SIGNAL_SDHIMMC_DMA_REQ 

SDHIMMC DMA REQ.

FSP_SIGNAL_SDHIMMC_SDIO 

SDHIMMC SDIO.

FSP_SIGNAL_SPI_ERI 

SPI ERI.

FSP_SIGNAL_SPI_IDLE 

SPI IDLE.

FSP_SIGNAL_SPI_RXI 

SPI RXI.

FSP_SIGNAL_SPI_TEI 

SPI TEI.

FSP_SIGNAL_SPI_TXI 

SPI TXI.

FSP_SIGNAL_SRC_CONVERSION_END 

SRC CONVERSION END.

FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY 

SRC INPUT FIFO EMPTY.

FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL 

SRC OUTPUT FIFO FULL.

FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW 

SRC OUTPUT FIFO OVERFLOW.

FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW 

SRC OUTPUT FIFO UNDERFLOW.

FSP_SIGNAL_SSI_INT 

SSI INT.

FSP_SIGNAL_SSI_RXI 

SSI RXI.

FSP_SIGNAL_SSI_TXI 

SSI TXI.

FSP_SIGNAL_SSI_TXI_RXI 

SSI TXI RXI.

FSP_SIGNAL_TRNG_RDREQ 

TRNG RDREQ.

FSP_SIGNAL_USB_FIFO_0 

USB FIFO 0.

FSP_SIGNAL_USB_FIFO_1 

USB FIFO 1.

FSP_SIGNAL_USB_INT 

USB INT.

FSP_SIGNAL_USB_RESUME 

USB RESUME.

FSP_SIGNAL_USB_USB_INT_RESUME 

USB USB INT RESUME.

FSP_SIGNAL_WDT_UNDERFLOW 

WDT UNDERFLOW.

Function Documentation

◆ R_FSP_VersionGet()

fsp_err_t R_FSP_VersionGet ( fsp_pack_version_t *const  p_version)

Get the FSP version based on compile time macros.

Parameters
[out]p_versionMemory address to return version information to.
Return values
FSP_SUCCESSVersion information stored.
FSP_ERR_ASSERTIONThe parameter p_version is NULL.

◆ Reset_Handler()

void Reset_Handler ( void  )

MCU starts executing here out of reset. Main stack pointer is set up already.

◆ Default_Handler()

void Default_Handler ( void  )

Default exception handler.

◆ NMI_Handler()

void NMI_Handler ( void  )

Non-maskable interrupt handler. This exception is defined by the BSP, unlike other system exceptions, because there are many sources that map to the NMI exception.

◆ SystemInit()

void SystemInit ( void  )

Initialize the MCU and the runtime environment.

◆ R_BSP_WarmStart()

void R_BSP_WarmStart ( bsp_warm_start_event_t  event)

This function is called at various points during the startup process. This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user implemented version. One of the main uses for this function is to call functional safety code during the startup process. To use this function just copy this function into your own code and modify it to meet your needs.

Parameters
[in]eventWhere the code currently is in the start up process

This function is called at various points during the startup process. This implementation uses the event that is called right before main() to set up the pins.

Parameters
[in]eventWhere at in the start up process the code is currently at

◆ R_BSP_GroupIrqWrite()

fsp_err_t R_BSP_GroupIrqWrite ( bsp_grp_irq_t  irq,
void(*)(bsp_grp_irq_t irq)  p_callback 
)

Register a callback function for supported interrupts. If NULL is passed for the callback argument then any previously registered callbacks are unregistered.

Parameters
[in]irqInterrupt for which to register a callback.
[in]p_callbackPointer to function to call when interrupt occurs.
Return values
FSP_SUCCESSCallback registered
FSP_ERR_ASSERTIONCallback pointer is NULL

◆ R_BSP_SourceClockHzGet()

uint32_t R_BSP_SourceClockHzGet ( fsp_priv_source_clock_t  clock)

Gets the frequency of a source clock.

Parameters
[in]clockPointer to Octaclk setting structure which provides information regarding Octaclk source and divider settings to be applied.
Returns
Frequency of requested clock in Hertz.

◆ R_FSP_CurrentIrqGet()

__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet ( void  )

Return active interrupt vector number value

Returns
Active interrupt vector number value

◆ R_FSP_SystemClockHzGet()

__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet ( fsp_priv_clock_t  clock)

Gets the frequency of a system clock.

Returns
Frequency of requested clock in Hertz.

◆ R_FSP_ClockDividerGet()

__STATIC_INLINE uint32_t R_FSP_ClockDividerGet ( uint32_t  ckdivcr)

Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR).

Returns
Clock Divider

◆ R_BSP_UniqueIdGet()

__STATIC_INLINE bsp_unique_id_t const* R_BSP_UniqueIdGet ( void  )

Get unique ID for this device.

Returns
A pointer to the unique identifier structure

◆ R_BSP_FlashCacheDisable()

__STATIC_INLINE void R_BSP_FlashCacheDisable ( void  )

Disables the flash cache.

◆ R_BSP_FlashCacheEnable()

__STATIC_INLINE void R_BSP_FlashCacheEnable ( void  )

Enables the flash cache.

◆ R_BSP_RegisterProtectEnable()

void R_BSP_RegisterProtectEnable ( bsp_reg_protect_t  regs_to_protect)

Enable register protection. Registers that are protected cannot be written to. Register protection is enabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR).

Parameters
[in]regs_to_protectRegisters which have write protection enabled.

◆ R_BSP_RegisterProtectDisable()

void R_BSP_RegisterProtectDisable ( bsp_reg_protect_t  regs_to_unprotect)

Disable register protection. Registers that are protected cannot be written to. Register protection is disabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR).

Parameters
[in]regs_to_unprotectRegisters which have write protection disabled.

◆ R_BSP_SoftwareDelay()

void R_BSP_SoftwareDelay ( uint32_t  delay,
bsp_delay_units_t  units 
)

Delay for at least the specified duration in units and return.

Parameters
[in]delayThe number of 'units' to delay.
[in]unitsThe 'base' (bsp_delay_units_t) for the units specified. Valid values are: BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS, BSP_DELAY_UNITS_MICROSECONDS.
For example:
At 1 MHz one cycle takes 1 microsecond (.000001 seconds).
At 12 MHz one cycle takes 1/12 microsecond or 83 nanoseconds.
Therefore one run through bsp_prv_software_delay_loop() takes: ~ (83 * BSP_DELAY_LOOP_CYCLES) or 332 ns. A delay of 2 us therefore requires 2000ns/332ns or 6 loops.

The 'theoretical' maximum delay that may be obtained is determined by a full 32 bit loop count and the system clock rate. @120MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 120000000) = 143 seconds. @32MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 32000000) = 536 seconds

Note that requests for very large delays will be affected by rounding in the calculations and the actual delay achieved may be slightly longer. @32 MHz, for example, a request for 532 seconds will be closer to 536 seconds.

Note also that if the calculations result in a loop_cnt of zero, the bsp_prv_software_delay_loop() function is not called at all. In this case the requested delay is too small (nanoseconds) to be carried out by the loop itself, and the overhead associated with executing the code to just get to this point has certainly satisfied the requested delay.

Note
This function calls bsp_cpu_clock_get() which ultimately calls R_CGC_SystemClockFreqGet() and therefore requires that the BSP has already initialized the CGC (which it does as part of the Sysinit). Care should be taken to ensure this remains the case if in the future this function were to be called as part of the BSP initialization.
This function will delay for at least the specified duration. Due to overhead in calculating the correct number of loops to delay, very small delay values (generally 1-5 microseconds) may be significantly longer than specified. Approximate overhead for this function is as follows:
  • CM4: 20-50 cycles
  • CM33: 10-60 cycles
  • CM23: 75-200 cycles
If more accurate microsecond timing must be performed in software it is recommended to use bsp_prv_software_delay_loop() directly. In this case, use BSP_DELAY_LOOP_CYCLES or BSP_DELAY_LOOPS_CALCULATE() to convert a calculated delay cycle count to a number of software delay loops.
Delays may be longer than expected when compiler optimization is turned off.
Warning
The delay will be longer than specified on CM23 devices when the core clock is greater than 32 MHz. Setting BSP_DELAY_LOOP_CYCLES to 6 will improve accuracy at 48 MHz but will result in shorter than expected delays at lower speeds.

◆ __sinf()

BSP_TFU_INLINE float __sinf ( float  angle)

Calculates sine of the given angle.

Parameters
[in]angleThe value of an angle in radian.
Return values
Sinevalue of an angle.

◆ __cosf()

BSP_TFU_INLINE float __cosf ( float  angle)

Calculates cosine of the given angle.

Parameters
[in]angleThe value of an angle in radian.
Return values
Cosinevalue of an angle.

◆ __sincosf()

BSP_TFU_INLINE void __sincosf ( float  angle,
float *  sin,
float *  cos 
)

Calculates sine and cosine of the given angle.

Parameters
[in]angleThe value of an angle in radian.
[out]sinSine value of an angle.
[out]cosCosine value of an angle.

◆ __atan2f()

BSP_TFU_INLINE float __atan2f ( float  y_cord,
float  x_cord 
)

Calculates the arc tangent based on given X-cordinate and Y-cordinate values.

Parameters
[in]y_cordY-Axis cordinate value.
[in]x_cordX-Axis cordinate value.
Return values
Arctangent for given values.

◆ __hypotf()

BSP_TFU_INLINE float __hypotf ( float  x_cord,
float  y_cord 
)

Calculates the hypotenuse based on given X-cordinate and Y-cordinate values.

Parameters
[in]y_cordY-cordinate value.
[in]x_cordX-cordinate value.
Return values
Hypotenusefor given values.

◆ __atan2hypotf()

BSP_TFU_INLINE void __atan2hypotf ( float  y_cord,
float  x_cord,
float *  atan2,
float *  hypot 
)

Calculates the arc tangent and hypotenuse based on given X-cordinate and Y-cordinate values.

Parameters
[in]y_cordY-cordinate value.
[in]x_cordX-cordinate value.
[out]atan2Arc tangent for given values.
[out]hypotHypotenuse for given values.

Variable Documentation

◆ BSP_SECTION_EARLY_INIT

uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT

System Clock Frequency (Core Clock)