Detailed Description

Build Time Configurations for ra0e3_fsp

The following build time configurations are defined in fsp_cfg/bsp/bsp_mcu_family_cfg.h:

Configuration	Options	Default	Description
Enable inline BSP IRQ functions	Enabled Disabled	Disabled	Using static inline functions will slightly increase code size, but will slightly decrease cycles taken in ISRs in return.
Use Low Voltage Mode	Not Supported	Not Supported	Use the low voltage mode. This limits the ICLK operating frequency to 4 MHz and requires all clock dividers to be at least 4 when oscillation stop detection is used.

Groups	Modules
Analog	ADC (r_adc_d)
Connectivity	I2C Master (r_sau_i2c) IICA Master (r_iica_master) IICA Slave (r_iica_slave) LIN (r_sau_lin) SPI (r_sau_spi) UART (r_sau_uart)
Input	External IRQ (r_icu)
Monitoring	CRC (r_crc) Independent Watchdog (r_iwdt) Low/Programmable Voltage Detection (r_lvd)
Power	Low Power Modes (r_lpm)
Storage	Flash (r_flash_lp)
System	Clock Generation Circuit (r_cgc) I/O Port (r_ioport)
Timers	32-bit Interval Timer (r_tml) Timer, Independent Channel, 16-bit and 8-bit Timer Operation (r_tau) Timer, Simultaneous Channel Operation (r_tau_pwm)
Transfer	Transfer (r_dtc)

Fixed vector enumeration