RA Flexible Software Package Documentation  Release v5.7.0

 
Macros | Enumerations
RA6T3
BSP » MCU Board Support Package

Detailed Description

Build Time Configurations for ra6t3_fsp

The following build time configurations are defined in fsp_cfg/bsp/bsp_mcu_family_cfg.h:

ConfigurationOptionsDefaultDescription
Security
Security > Exceptions
Exception Response
  • Non-Maskable Interrupt
  • Reset
Non-Maskable Interrupt Configure the result of a TrustZone Filter exception. This exception is generated when the TrustZone Filter detects access to a protected region.

This setting is only valid when building projects with TrustZone.
BusFault, HardFault, and NMI Target
  • Non-Secure State
  • Secure State
Secure State Value for SCB->AIRCR register bit BFHFNMINS. Defines whether BusFault and NMI exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception.

This setting is only valid when building projects with TrustZone.
Prioritize Secure Exceptions
  • Enabled
  • Disabled
Disabled Value for SCB->AIRCR register bit PRIS. When enabled, all Non-secure interrupt priorities are automatically demoted by right shifting their priority by one then setting the most significant bit. As there is effectively one less bit care must be taken to ensure the prioritization of non-secure interrupts is correct.

This setting is only valid when building projects with TrustZone.
Security > SRAM Accessibility
SRAM Protection
  • Both Secure and Non-Secure State
  • Secure State
Both Secure and Non-Secure State Defines whether SRAMPRCR is write accessible for the Non-secure application.

This setting is only valid when building projects with TrustZone.
SRAM ECC
  • Both Secure and Non-Secure State
  • Secure State
Both Secure and Non-Secure State Defines whether SRAM ECC registers are write accessible for the Non-secure application.

This setting is only valid when building projects with TrustZone.
Security > BUS Accessibility
Bus Security Attribution Register A
  • Both Secure and Non-Secure State
  • Secure State
Both Secure and Non-Secure State Defines whether the Slave Bus Control Registers (BUSSCNT<slave>) are write accessible for the Non-secure application.

This setting is only valid when building projects with TrustZone.
Bus Security Attribution Register B
  • Both Secure and Non-Secure State
  • Secure State
Both Secure and Non-Secure State Defines whether the Bus and DMAC/DTC Error Clear Registers are write accessible for the Non-secure application.

This setting is only valid when building projects with TrustZone.
System Reset Request Accessibility
  • Both Secure and Non-Secure State
  • Secure State
Secure State Value for SCB->AIRCR register bit SYSRESETREQS. Defines whether the SYSRESETREQ bit is functional for Non-secure use.

This setting is only valid when building projects with TrustZone.
Cache Accessibility
  • Both Secure and Non-Secure State
  • Secure State
Both Secure and Non-Secure State Defines whether the Cache registers are write accessible for the Non-secure application.

This setting is only valid when building protjects with TrustZone.
System Reset Status Accessibility
  • Both Secure and Non-Secure State
  • Secure State
Both Secure and Non-Secure State Defines whether the reset status registers (RSTSRn) can be cleared from the Non-secure application.

This setting is only valid when building projects with TrustZone.
Uninitialized Non-Secure Application Fallback
  • Enable Uninitialized Non-Secure Application Fallback
  • Disable Uninitialized Non-Secure Application Fallback
Enable Uninitialized Non-Secure Application Fallback If enabled, the secure application checks if the non-secure application has been programmed in non-secure flash before branching. If the non-secure application has not been programmed, then the secure application branches to an infinite loop in non-secure RAM. This prevents an issue where the debugger may not connect if the MCU is configured in the NSECSD lifecycle state.
OFS0 register settings
OFS0 register settings > Independent WDT
Start Mode
  • IWDT is stopped after a reset
  • IWDT is automatically activated after a reset (Autostart mode)
IWDT is stopped after a reset
Timeout Period
  • 128 cycles
  • 512 cycles
  • 1024 cycles
  • 2048 cycles
2048 cycles
Dedicated Clock Frequency Divisor
  • 1
  • 16
  • 32
  • 64
  • 128
  • 256
128
Window End Position
  • 75%
  • 50%
  • 25%
  • 0% (no window end position)
0% (no window end position)
Window Start Position
  • 25%
  • 50%
  • 75%
  • 100% (no window start position)
100% (no window start position)
Reset Interrupt Request Select
  • NMI request or interrupt request is enabled
  • Reset is enabled
Reset is enabled
Stop Control
  • Counting continues (Note: Device will not enter Deep Standby Mode when selected. Device will enter Software Standby Mode)
  • Stop counting when in Sleep, Snooze mode, or Software Standby
Stop counting when in Sleep, Snooze mode, or Software Standby
OFS0 register settings > WDT
Start Mode Select
  • Automatically activate WDT after a reset (auto-start mode)
  • Stop WDT after a reset (register-start mode)
Stop WDT after a reset (register-start mode)
Timeout Period
  • 1024 cycles
  • 4096 cycles
  • 8192 cycles
  • 16384 cycles
16384 cycles
Clock Frequency Division Ratio
  • 4
  • 64
  • 128
  • 512
  • 2048
  • 8192
128
Window End Position
  • 75%
  • 50%
  • 25%
  • 0% (no window end position)
0% (no window end position)
Window Start Position
  • 25%
  • 50%
  • 75%
  • 100% (no window start position)
100% (no window start position)
Reset Interrupt Request
  • NMI
  • Reset
Reset
Stop Control
  • Counting continues
  • Stop counting when entering Sleep mode
Stop counting when entering Sleep mode
OFS1 register settings
Voltage Detection 0 Circuit Start
  • Voltage monitor 0 reset is enabled after reset
  • Voltage monitor 0 reset is disabled after reset
Voltage monitor 0 reset is disabled after reset
Voltage Detection 0 Level
  • 2.94 V
  • 2.87 V
  • 2.80 V
2.80 V
HOCO Oscillation Enable
  • HOCO oscillation is enabled after reset
  • HOCO oscillation is disabled after reset
HOCO oscillation is disabled after reset
Block Protection Settings (BPS)
BPS0Refer to the RA Configuration tool for available options.0U Configure Block Protection Register 0
Permanent Block Protection Settings (PBPS)
PBPS0Refer to the RA Configuration tool for available options.0U Configure Permanent Block Protection Register 0
Clocks
HOCO FLL Function
  • Enabled
  • Disabled
Disabled Setting this option to Enabled improves HOCO accuracy significantly by using the subclock, but incurs certain restrictions.

The FLL function requires the subclock oscillator to be running and stabilized. When enabled and running the PLL or system clock from HOCO, the BSP will wait for both the Subclock Stabilization Time as well as the FLL Stabilization Time when setting up clocks at startup.

When FLL is enabled Software Standby and Deep Software Standby modes are not available.
Enable inline BSP IRQ functions
  • Enabled
  • Disabled
Enabled Using static inline functions will slightly increase code size, but will slightly decrease cycles taken in ISRs in return.
Startup C-Cache Line Size
  • 32 Bytes
  • 64 Bytes
32 Bytes Set the C-Cache line size configured during startup.
TFU Mathlib
  • Disabled
  • Enabled
Enabled If enabled, trigonometric library functions sinf, cosf, atan2f, and hypotf are replaced with hardware accelerated TFU functions. Disable this if reentrant access to these functions is required.
Main Oscillator Wait Time
  • 3 cycles
  • 35 cycles
  • 67 cycles
  • 131 cycles
  • 259 cycles
  • 547 cycles
  • 1059 cycles
  • 2147 cycles
  • 4291 cycles
  • 8163 cycles
8163 cycles Number of cycles to wait for the main oscillator clock to stabilize.
ID Code Mode
  • Unlocked (Ignore ID)
  • Locked with All Erase support
  • Locked
Unlocked (Ignore ID) When set to 'Locked with All Erase support', the ID Code must be set in the debugger to read or write data to the MCU, but the All Erase command is still accepted regardless. When set to 'Locked', all erase/download/debug access is disabled unless the ID Code is provided.
ID Code (32 Hex Characters)Value must be a 32 character long hex stringFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF Set the ID Code for locking debug access. This setting is only used when the ID Code Mode is not set to Unlocked.

Macros

#define BSP_ELC_PERIPHERAL_MASK
 

Enumerations

enum  elc_event_t
 
enum  elc_peripheral_t
 

Macro Definition Documentation

◆ BSP_ELC_PERIPHERAL_MASK

#define BSP_ELC_PERIPHERAL_MASK

Positions of event link set registers (ELSRs) available on this MCU

Enumeration Type Documentation

◆ elc_event_t

enum elc_event_t

Sources of event signals to be linked to other peripherals or the CPU

Note
This list is device specific.

◆ elc_peripheral_t

enum elc_peripheral_t

Possible peripherals to be linked to event signals

Note
This list is device specific.