RA Flexible Software Package Documentation  Release v4.0.0

 
Clock Generation Circuit (r_cgc)

Functions

fsp_err_t R_CGC_Open (cgc_ctrl_t *const p_ctrl, cgc_cfg_t const *const p_cfg)
 
fsp_err_t R_CGC_ClocksCfg (cgc_ctrl_t *const p_ctrl, cgc_clocks_cfg_t const *const p_clock_cfg)
 
fsp_err_t R_CGC_ClockStart (cgc_ctrl_t *const p_ctrl, cgc_clock_t clock_source, cgc_pll_cfg_t const *const p_pll_cfg)
 
fsp_err_t R_CGC_ClockStop (cgc_ctrl_t *const p_ctrl, cgc_clock_t clock_source)
 
fsp_err_t R_CGC_SystemClockSet (cgc_ctrl_t *const p_ctrl, cgc_clock_t clock_source, cgc_divider_cfg_t const *const p_divider_cfg)
 
fsp_err_t R_CGC_SystemClockGet (cgc_ctrl_t *const p_ctrl, cgc_clock_t *const p_clock_source, cgc_divider_cfg_t *const p_divider_cfg)
 
fsp_err_t R_CGC_ClockCheck (cgc_ctrl_t *const p_ctrl, cgc_clock_t clock_source)
 
fsp_err_t R_CGC_OscStopDetectEnable (cgc_ctrl_t *const p_ctrl)
 
fsp_err_t R_CGC_OscStopDetectDisable (cgc_ctrl_t *const p_ctrl)
 
fsp_err_t R_CGC_OscStopStatusClear (cgc_ctrl_t *const p_ctrl)
 
fsp_err_t R_CGC_CallbackSet (cgc_ctrl_t *const p_api_ctrl, void(*p_callback)(cgc_callback_args_t *), void const *const p_context, cgc_callback_args_t *const p_callback_memory)
 
fsp_err_t R_CGC_Close (cgc_ctrl_t *const p_ctrl)
 

Detailed Description

Driver for the CGC peripheral on RA MCUs. This module implements the CGC Interface.

Note
This module is not required for the initial clock configuration. Initial clock settings are configurable on the **Clocks tab of the RA Configuration editor. The initial clock settings are applied by the BSP during the startup process before main.**

Overview

Features

The CGC module supports runtime modifications of clock settings. Key features include the following:

Internal Clocks

The RA microcontrollers have up to seven internal clocks. Not all internal clocks exist on all MCUs. Each clock domain has its own divider that can be updated in R_CGC_SystemClockSet(). The dividers are subject to constraints described in the footnote of the table "Specifications of the Clock Generation Circuit for the internal clocks" in the hardware manual.

The internal clocks include:

Configuration

Note
The initial clock settings are configurable on the Clocks tab of the RA Configuration editor.
There is a configuration to enable the HOCO on reset in the OFS1 settings on the BSP tab.
The following clock related settings are configurable in the RA Common section on the BSP tab:
  • Main Oscillator Wait Time
  • Main Oscillator Clock Source (external oscillator or crystal/resonator)
  • Subclock Populated
  • Subclock Drive
  • Subclock Stabilization Time (ms)
The default stabilization times are determined based on development boards provided by Renesas, but are generally valid for most designs. Depending on the target board hardware configuration and requirements these values may need to be adjusted for reliability or startup speed.

Build Time Configurations for r_cgc

The following build time configurations are defined in fsp_cfg/r_cgc_cfg.h:

ConfigurationOptionsDefaultDescription
Parameter Checking
  • Default (BSP)
  • Enabled
  • Disabled
Default (BSP) If selected code for parameter checking is included in the build.

Configurations for System > Clock Generation Circuit (r_cgc)

This module can be added to the Stacks tab via New Stack > System > Clock Generation Circuit (r_cgc). Non-secure callable guard functions can be generated for this module by right clicking the module in the RA Configuration tool and checking the "Non-secure Callable" box.

ConfigurationOptionsDefaultDescription
NameName must be a valid C symbolg_cgc0 Module name.
NMI CallbackName must be a valid C symbolNULL A user callback function must be provided if oscillation stop detection is used. If this callback function is provided, it is called from the NMI handler if the main oscillator stops.

Clock Configuration

This module is used to configure the system clocks. There are no module specific clock configurations required to use it.

Pin Configuration

The CGC module controls the output of the CLOCKOUT signal.

If an external oscillator is used the XTAL and EXTAL pins must be configured accordingly. When running from an on chip oscillator there is no requirement for the main clock external oscillator. In this case, the XTAL and EXTAL pins can be set to a different function in the RA Configuration editor.

The functionality of the subclock external oscillator pins XCIN and XCOUT is fixed.

Usage Notes

NMI Interrupt

The CGC timer uses the NMI for oscillation stop detection of the main oscillator after R_CGC_OscStopDetectEnable is called. The NMI is enabled by default. No special configuration is required. When the NMI is triggered, the callback function registered during R_CGC_Open() is called.

Starting or Stopping the Subclock

If the Subclock Populated property is set to Populated on the BSP configuration tab, then the subclock is started in the BSP startup routine. Otherwise, it is stopped in the BSP startup routine. Starting and stopping the subclock at runtime is not recommended since the stabilization requirements typically negate the negligible power savings.

The application is responsible for ensuring required clocks are started and stable before accessing MCU peripheral registers.

Warning
The subclock can take up to several seconds to stabilize. RA startup code does not wait for subclock stabilization unless the subclock is the main clock source. In this case the default wait time is 1000ms (1 second). When running AGT or RTC off the subclock, the application must ensure the subclock is stable before starting operation. Because there is no hardware stabilization status bit for the subclock R_CGC_ClockCheck cannot be used to optimize this wait.

Changing the subclock state during R_CGC_ClocksCfg() is not supported.

Low Power Operation

If "Use Low Voltage Mode" is enabled in the BSP MCU specific properties (not available on all MCUs), the MCU is always in low voltage mode and no other power modes are considered. The following conditions must be met for the MCU to run in low voltage mode:

If "Use Low Voltage Mode" is not enabled, the MCU applies the lowest power mode by searching through the following list in order and applying the first power mode that is supported under the current conditions:

Refer to the section "Function for Lower Operating Power Consumption" in the "Low Power Modes" chapter of the hardware manual for MCU specific information about operating power control modes.

Note
The DCDC regulator (if present) is only available in Middle- and High-speed modes. The BSP will automatically switch between DCDC and LDO when switching between compatible and incompatible modes if the DCDC regulator is in use. Switching to the LDO incurs a 60 microsecond critical section wherein all interrupts AND peripherals are stopped. Switching back to DCDC from the LDO incurs an additional 22 microsecond critical section (peripherals running).

When low voltage mode is not used, the following functions adjust the operating power control mode to ensure it remains within the hardware specification and to ensure the MCU is running at the optimal operating power control mode:

Note
FSP APIs, including these APIs, are not thread safe. These APIs and any other user code that modifies the operating power control mode must not be allowed to interrupt each other. Proper care must be taken during application design if these APIs are used in threads or interrupts to ensure this constraint is met.

No action is required by the user of these APIs. This section is provided for informational purposes only.

Examples

Basic Example

This is a basic example of minimal use of the CGC in an application.

void cgc_basic_example (void)
{
fsp_err_t err = FSP_SUCCESS;
/* Initializes the CGC module. */
err = R_CGC_Open(&g_cgc0_ctrl, &g_cgc0_cfg);
/* Handle any errors. This function should be defined by the user. */
assert(FSP_SUCCESS == err);
/* Change the system clock to LOCO for power saving. */
/* Start the LOCO. */
err = R_CGC_ClockStart(&g_cgc0_ctrl, CGC_CLOCK_LOCO, NULL);
assert(FSP_SUCCESS == err);
/* Wait for the LOCO stabilization wait time.
*
* NOTE: The MOCO, LOCO and subclock do not have stabilization status bits, so any stabilization time must be
* performed via a software wait when starting these oscillators. For all other oscillators, R_CGC_ClockCheck can
* be used to verify stabilization status.
*/
R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS);
/* Set divisors. Divisors for clocks that don't exist on the MCU are ignored. */
cgc_divider_cfg_t dividers =
{
/* PCLKB is not used in this application, so select the maximum divisor for lowest power. */
.sckdivcr_b.pclkb_div = CGC_SYS_CLOCK_DIV_64,
/* PCLKD is not used in this application, so select the maximum divisor for lowest power. */
.sckdivcr_b.pclkd_div = CGC_SYS_CLOCK_DIV_64,
/* ICLK is the MCU clock, allow it to run as fast as the LOCO is capable. */
.sckdivcr_b.iclk_div = CGC_SYS_CLOCK_DIV_1,
/* These clocks do not exist on some devices. If any clocks don't exist, set the divider to 1. */
.sckdivcr_b.pclka_div = CGC_SYS_CLOCK_DIV_1,
.sckdivcr_b.pclkc_div = CGC_SYS_CLOCK_DIV_1,
.sckdivcr_b.fclk_div = CGC_SYS_CLOCK_DIV_1,
.sckdivcr_b.bclk_div = CGC_SYS_CLOCK_DIV_1,
};
/* Switch the system clock to LOCO. */
err = R_CGC_SystemClockSet(&g_cgc0_ctrl, CGC_CLOCK_LOCO, &dividers);
assert(FSP_SUCCESS == err);
}

Configuring Multiple Clocks

This example demonstrates switching to a new source clock and stopping the previous source clock in a single function call using R_CGC_ClocksCfg().

void cgc_clocks_cfg_example (void)
{
fsp_err_t err = FSP_SUCCESS;
/* Initializes the CGC module. */
err = R_CGC_Open(&g_cgc0_ctrl, &g_cgc0_cfg);
/* Handle any errors. This function should be defined by the user. */
assert(FSP_SUCCESS == err);
/* Change the system clock to PLL running from the main oscillator. */
/* Assuming the system clock is MOCO, switch to HOCO. */
cgc_clocks_cfg_t clocks_cfg;
clocks_cfg.pll_cfg.source_clock = CGC_CLOCK_MAIN_OSC; // unused
clocks_cfg.pll_cfg.multiplier = CGC_PLL_MUL_10_0; // unused
clocks_cfg.pll_cfg.divider = CGC_PLL_DIV_2; // unused
clocks_cfg.divider_cfg.sckdivcr_b.iclk_div = CGC_SYS_CLOCK_DIV_1;
clocks_cfg.divider_cfg.sckdivcr_b.pclka_div = CGC_SYS_CLOCK_DIV_4;
clocks_cfg.divider_cfg.sckdivcr_b.pclkb_div = CGC_SYS_CLOCK_DIV_4;
clocks_cfg.divider_cfg.sckdivcr_b.pclkc_div = CGC_SYS_CLOCK_DIV_4;
clocks_cfg.divider_cfg.sckdivcr_b.pclkd_div = CGC_SYS_CLOCK_DIV_4;
clocks_cfg.divider_cfg.sckdivcr_b.bclk_div = CGC_SYS_CLOCK_DIV_4;
clocks_cfg.divider_cfg.sckdivcr_b.fclk_div = CGC_SYS_CLOCK_DIV_4;
err = R_CGC_ClocksCfg(&g_cgc0_ctrl, &clocks_cfg);
assert(FSP_SUCCESS == err);
#if BSP_FEATURE_CGC_HAS_PLL
/* Assuming the system clock is HOCO, switch to PLL running from main oscillator and stop MOCO. */
clocks_cfg.pll_cfg.multiplier = (cgc_pll_mul_t) BSP_CFG_PLL_MUL;
clocks_cfg.pll_cfg.divider = (cgc_pll_div_t) BSP_CFG_PLL_DIV;
clocks_cfg.divider_cfg.sckdivcr_b.iclk_div = CGC_SYS_CLOCK_DIV_1;
clocks_cfg.divider_cfg.sckdivcr_b.pclka_div = CGC_SYS_CLOCK_DIV_4;
clocks_cfg.divider_cfg.sckdivcr_b.pclkb_div = CGC_SYS_CLOCK_DIV_4;
clocks_cfg.divider_cfg.sckdivcr_b.pclkc_div = CGC_SYS_CLOCK_DIV_4;
clocks_cfg.divider_cfg.sckdivcr_b.pclkd_div = CGC_SYS_CLOCK_DIV_4;
clocks_cfg.divider_cfg.sckdivcr_b.bclk_div = CGC_SYS_CLOCK_DIV_4;
clocks_cfg.divider_cfg.sckdivcr_b.fclk_div = CGC_SYS_CLOCK_DIV_4;
err = R_CGC_ClocksCfg(&g_cgc0_ctrl, &clocks_cfg);
assert(FSP_SUCCESS == err);
#endif
}

Oscillation Stop Detection

This example demonstrates registering a callback for oscillation stop detection of the main oscillator.

/* Example callback called when oscillation stop is detected. */
void oscillation_stop_callback (cgc_callback_args_t * p_args)
{
fsp_err_t err = FSP_SUCCESS;
/* (Optional) If the MCU was running on the main oscillator, the MCU is now running on MOCO. Switch clocks if
* desired. This example shows switching to HOCO. */
err = R_CGC_ClockStart(&g_cgc0_ctrl, CGC_CLOCK_HOCO, NULL);
assert(FSP_SUCCESS == err);
do
{
/* Wait for HOCO to stabilize. */
err = R_CGC_ClockCheck(&g_cgc0_ctrl, CGC_CLOCK_HOCO);
} while (FSP_SUCCESS != err);
cgc_divider_cfg_t dividers =
{
.sckdivcr_b.pclkb_div = CGC_SYS_CLOCK_DIV_4,
.sckdivcr_b.pclkd_div = CGC_SYS_CLOCK_DIV_4,
.sckdivcr_b.iclk_div = CGC_SYS_CLOCK_DIV_1,
.sckdivcr_b.pclka_div = CGC_SYS_CLOCK_DIV_4,
.sckdivcr_b.pclkc_div = CGC_SYS_CLOCK_DIV_4,
.sckdivcr_b.fclk_div = CGC_SYS_CLOCK_DIV_4,
.sckdivcr_b.bclk_div = CGC_SYS_CLOCK_DIV_4,
};
err = R_CGC_SystemClockSet(&g_cgc0_ctrl, CGC_CLOCK_HOCO, &dividers);
assert(FSP_SUCCESS == err);
#if BSP_FEATURE_CGC_HAS_PLL
/* (Optional) If the MCU was running on the PLL, the PLL is now in free-running mode. Switch clocks if
* desired. This example shows switching to the PLL running on HOCO. */
err = R_CGC_ClockStart(&g_cgc0_ctrl, CGC_CLOCK_HOCO, NULL);
assert(FSP_SUCCESS == err);
do
{
/* Wait for HOCO to stabilize. */
err = R_CGC_ClockCheck(&g_cgc0_ctrl, CGC_CLOCK_HOCO);
} while (FSP_SUCCESS != err);
cgc_pll_cfg_t pll_cfg =
{
.multiplier = (cgc_pll_mul_t) BSP_CFG_PLL_MUL,
.divider = (cgc_pll_div_t) BSP_CFG_PLL_DIV,
};
err = R_CGC_ClockStart(&g_cgc0_ctrl, CGC_CLOCK_PLL, &pll_cfg);
assert(FSP_SUCCESS == err);
do
{
/* Wait for PLL to stabilize. */
err = R_CGC_ClockCheck(&g_cgc0_ctrl, CGC_CLOCK_PLL);
} while (FSP_SUCCESS != err);
cgc_divider_cfg_t pll_dividers =
{
.sckdivcr_b.pclkb_div = CGC_SYS_CLOCK_DIV_4,
.sckdivcr_b.pclkd_div = CGC_SYS_CLOCK_DIV_4,
.sckdivcr_b.iclk_div = CGC_SYS_CLOCK_DIV_1,
.sckdivcr_b.pclka_div = CGC_SYS_CLOCK_DIV_4,
.sckdivcr_b.pclkc_div = CGC_SYS_CLOCK_DIV_4,
.sckdivcr_b.fclk_div = CGC_SYS_CLOCK_DIV_4,
.sckdivcr_b.bclk_div = CGC_SYS_CLOCK_DIV_4,
};
err = R_CGC_SystemClockSet(&g_cgc0_ctrl, CGC_CLOCK_PLL, &pll_dividers);
assert(FSP_SUCCESS == err);
#endif
/* (Optional) Clear the error flag. Only clear this flag after switching the MCU clock source away from the main
* oscillator and if the main oscillator is stable again. */
err = R_CGC_OscStopStatusClear(&g_cgc0_ctrl);
assert(FSP_SUCCESS == err);
}
void cgc_osc_stop_example (void)
{
fsp_err_t err = FSP_SUCCESS;
/* Open the module. */
err = R_CGC_Open(&g_cgc0_ctrl, &g_cgc0_cfg);
/* Handle any errors. This function should be defined by the user. */
assert(FSP_SUCCESS == err);
/* Enable oscillation stop detection. The main oscillator must be running at this point. */
err = R_CGC_OscStopDetectEnable(&g_cgc0_ctrl);
assert(FSP_SUCCESS == err);
/* (Optional) Oscillation stop detection must be disabled before entering any low power mode. */
err = R_CGC_OscStopDetectDisable(&g_cgc0_ctrl);
assert(FSP_SUCCESS == err);
__WFI();
/* (Optional) Reenable oscillation stop detection after waking from low power mode. */
err = R_CGC_OscStopDetectEnable(&g_cgc0_ctrl);
assert(FSP_SUCCESS == err);
}

Data Structures

struct  cgc_instance_ctrl_t
 

Data Structure Documentation

◆ cgc_instance_ctrl_t

struct cgc_instance_ctrl_t

CGC private control block. DO NOT MODIFY. Initialization occurs when R_CGC_Open() is called.

Data Fields

void const * p_context
 

Field Documentation

◆ p_context

void const* cgc_instance_ctrl_t::p_context

Placeholder for user data. Passed to the user callback in cgc_callback_args_t.

Function Documentation

◆ R_CGC_Open()

fsp_err_t R_CGC_Open ( cgc_ctrl_t *const  p_ctrl,
cgc_cfg_t const *const  p_cfg 
)

Initialize the CGC API. Implements cgc_api_t::open.

Example:

/* Initializes the CGC module. */
err = R_CGC_Open(&g_cgc0_ctrl, &g_cgc0_cfg);
Return values
FSP_SUCCESSCGC successfully initialized.
FSP_ERR_ASSERTIONInvalid input argument.
FSP_ERR_ALREADY_OPENModule is already open.

◆ R_CGC_ClocksCfg()

fsp_err_t R_CGC_ClocksCfg ( cgc_ctrl_t *const  p_ctrl,
cgc_clocks_cfg_t const *const  p_clock_cfg 
)

Reconfigures all main system clocks. This API can be used for any of the following purposes:

  • start or stop clocks
  • change the system clock source
  • configure the PLL/PLL2 multiplication and division ratios when starting the PLL
  • change the system dividers

If the requested system clock source has a stabilization flag, this function blocks waiting for the stabilization flag of the requested system clock source to be set. If the requested system clock source was just started and it has no stabilization flag, this function blocks for the stabilization time required by the requested system clock source according to the Electrical Characteristics section of the hardware manual. If the requested system clock source has no stabilization flag and it is already running, it is assumed to be stable and this function will not block. If the requested system clock is the subclock, the subclock must be stable prior to calling this function.

The internal dividers (cgc_clocks_cfg_t::divider_cfg) are subject to constraints described in footnotes of the hardware manual table detailing specifications for the clock generation circuit for the internal clocks for the MCU. For example:

  • RA6M3: see footnotes of Table 9.2 "Specifications of the clock generation circuit for the internal clocks" in the RA6M3 manual R01UH0886EJ0100
  • RA2A1: see footnotes of Table 9.2 "Clock generation circuit specifications for the internal clocks" in the RA2A1 manual R01UH0888EJ0100

Do not attempt to stop the requested clock source or the source of a PLL if the PLL will be running after this operation completes.

Implements cgc_api_t::clocksCfg.

Example:

/* Assuming the system clock is MOCO, switch to HOCO. */
cgc_clocks_cfg_t clocks_cfg;
clocks_cfg.pll_cfg.source_clock = CGC_CLOCK_MAIN_OSC; // unused
clocks_cfg.pll_cfg.multiplier = CGC_PLL_MUL_10_0; // unused
clocks_cfg.pll_cfg.divider = CGC_PLL_DIV_2; // unused
clocks_cfg.divider_cfg.sckdivcr_b.iclk_div = CGC_SYS_CLOCK_DIV_1;
clocks_cfg.divider_cfg.sckdivcr_b.pclka_div = CGC_SYS_CLOCK_DIV_4;
clocks_cfg.divider_cfg.sckdivcr_b.pclkb_div = CGC_SYS_CLOCK_DIV_4;
clocks_cfg.divider_cfg.sckdivcr_b.pclkc_div = CGC_SYS_CLOCK_DIV_4;
clocks_cfg.divider_cfg.sckdivcr_b.pclkd_div = CGC_SYS_CLOCK_DIV_4;
clocks_cfg.divider_cfg.sckdivcr_b.bclk_div = CGC_SYS_CLOCK_DIV_4;
clocks_cfg.divider_cfg.sckdivcr_b.fclk_div = CGC_SYS_CLOCK_DIV_4;
err = R_CGC_ClocksCfg(&g_cgc0_ctrl, &clocks_cfg);
assert(FSP_SUCCESS == err);
Return values
FSP_SUCCESSClock configuration applied successfully.
FSP_ERR_ASSERTIONInvalid input argument.
FSP_ERR_NOT_OPENModule is not open.
FSP_ERR_IN_USEAttempt to stop the current system clock or the PLL source clock.
FSP_ERR_CLOCK_ACTIVEPLL configuration cannot be changed while PLL is running.
FSP_ERR_OSC_STOP_DET_ENABLEDPLL multiplier must be less than 20 if oscillation stop detect is enabled and the input frequency is less than 12.5 MHz.
FSP_ERR_NOT_STABILIZEDPLL clock source is not stable.
FSP_ERR_PLL_SRC_INACTIVEPLL clock source is not running.
FSP_ERR_INVALID_STATEThe subclock must be running before activating HOCO with FLL.

◆ R_CGC_ClockStart()

fsp_err_t R_CGC_ClockStart ( cgc_ctrl_t *const  p_ctrl,
cgc_clock_t  clock_source,
cgc_pll_cfg_t const *const  p_pll_cfg 
)

Start the specified clock if it is not currently active. The PLL configuration cannot be changed while the PLL is running. Implements cgc_api_t::clockStart.

The PLL source clock must be operating and stable prior to starting the PLL.

Example:

/* Start the LOCO. */
err = R_CGC_ClockStart(&g_cgc0_ctrl, CGC_CLOCK_LOCO, NULL);
assert(FSP_SUCCESS == err);
Return values
FSP_SUCCESSClock initialized successfully.
FSP_ERR_ASSERTIONInvalid input argument.
FSP_ERR_NOT_OPENModule is not open.
FSP_ERR_NOT_STABILIZEDThe clock source is not stabilized after being turned off or PLL clock source is not stable.
FSP_ERR_PLL_SRC_INACTIVEPLL clock source is not running.
FSP_ERR_CLOCK_ACTIVEPLL configuration cannot be changed while PLL is running.
FSP_ERR_OSC_STOP_DET_ENABLEDPLL multiplier must be less than 20 if oscillation stop detect is enabled and the input frequency is less than 12.5 MHz.
FSP_ERR_INVALID_STATEThe subclock must be running before activating HOCO with FLL.

◆ R_CGC_ClockStop()

fsp_err_t R_CGC_ClockStop ( cgc_ctrl_t *const  p_ctrl,
cgc_clock_t  clock_source 
)

Stop the specified clock if it is active. Implements cgc_api_t::clockStop.

Do not attempt to stop the current system clock source. Do not attempt to stop the source clock of a PLL if the PLL is running.

Return values
FSP_SUCCESSClock stopped successfully.
FSP_ERR_ASSERTIONInvalid input argument.
FSP_ERR_NOT_OPENModule is not open.
FSP_ERR_IN_USEAttempt to stop the current system clock or the PLL source clock.
FSP_ERR_OSC_STOP_DET_ENABLEDAttempt to stop MOCO when Oscillation stop is enabled.
FSP_ERR_NOT_STABILIZEDClock not stabilized after starting.

◆ R_CGC_SystemClockSet()

fsp_err_t R_CGC_SystemClockSet ( cgc_ctrl_t *const  p_ctrl,
cgc_clock_t  clock_source,
cgc_divider_cfg_t const *const  p_divider_cfg 
)

Set the specified clock as the system clock and configure the internal dividers for ICLK, PCLKA, PCLKB, PCLKC, PCLKD, BCLK, and FCLK. Implements cgc_api_t::systemClockSet.

The requested clock source must be running and stable prior to calling this function. The internal dividers are subject to constraints described in the hardware manual table "Specifications of the Clock Generation Circuit for the internal clocks".

The internal dividers (p_divider_cfg) are subject to constraints described in footnotes of the hardware manual table detailing specifications for the clock generation circuit for the internal clocks for the MCU. For example:

  • RA6M3: see footnotes of Table 9.2 "Specifications of the clock generation circuit for the internal clocks" in the RA6M3 manual R01UH0886EJ0100
  • RA2A1: see footnotes of Table 9.2 "Clock generation circuit specifications for the internal clocks" in the RA2A1 manual R01UH0888EJ0100

This function also updates the RAM and ROM wait states, the operating power control mode, and the SystemCoreClock CMSIS global variable.

Example:

/* Set divisors. Divisors for clocks that don't exist on the MCU are ignored. */
cgc_divider_cfg_t dividers =
{
/* PCLKB is not used in this application, so select the maximum divisor for lowest power. */
.sckdivcr_b.pclkb_div = CGC_SYS_CLOCK_DIV_64,
/* PCLKD is not used in this application, so select the maximum divisor for lowest power. */
.sckdivcr_b.pclkd_div = CGC_SYS_CLOCK_DIV_64,
/* ICLK is the MCU clock, allow it to run as fast as the LOCO is capable. */
.sckdivcr_b.iclk_div = CGC_SYS_CLOCK_DIV_1,
/* These clocks do not exist on some devices. If any clocks don't exist, set the divider to 1. */
.sckdivcr_b.pclka_div = CGC_SYS_CLOCK_DIV_1,
.sckdivcr_b.pclkc_div = CGC_SYS_CLOCK_DIV_1,
.sckdivcr_b.fclk_div = CGC_SYS_CLOCK_DIV_1,
.sckdivcr_b.bclk_div = CGC_SYS_CLOCK_DIV_1,
};
/* Switch the system clock to LOCO. */
err = R_CGC_SystemClockSet(&g_cgc0_ctrl, CGC_CLOCK_LOCO, &dividers);
assert(FSP_SUCCESS == err);
Return values
FSP_SUCCESSOperation performed successfully.
FSP_ERR_ASSERTIONInvalid input argument.
FSP_ERR_NOT_OPENModule is not open.
FSP_ERR_CLOCK_INACTIVEThe specified clock source is inactive.
FSP_ERR_NOT_STABILIZEDThe clock source has not stabilized

◆ R_CGC_SystemClockGet()

fsp_err_t R_CGC_SystemClockGet ( cgc_ctrl_t *const  p_ctrl,
cgc_clock_t *const  p_clock_source,
cgc_divider_cfg_t *const  p_divider_cfg 
)

Return the current system clock source and configuration. Implements cgc_api_t::systemClockGet.

Return values
FSP_SUCCESSParameters returned successfully.
FSP_ERR_ASSERTIONInvalid input argument.
FSP_ERR_NOT_OPENModule is not open.

◆ R_CGC_ClockCheck()

fsp_err_t R_CGC_ClockCheck ( cgc_ctrl_t *const  p_ctrl,
cgc_clock_t  clock_source 
)

Check the specified clock for stability. Implements cgc_api_t::clockCheck.

Return values
FSP_SUCCESSClock is running and stable.
FSP_ERR_ASSERTIONInvalid input argument.
FSP_ERR_NOT_OPENModule is not open.
FSP_ERR_NOT_STABILIZEDClock not stabilized.
FSP_ERR_CLOCK_INACTIVEClock not turned on.

◆ R_CGC_OscStopDetectEnable()

fsp_err_t R_CGC_OscStopDetectEnable ( cgc_ctrl_t *const  p_ctrl)

Enable the oscillation stop detection for the main clock. Implements cgc_api_t::oscStopDetectEnable.

The MCU will automatically switch the system clock to MOCO when a stop is detected if Main Clock is the system clock. If the system clock is the PLL, then the clock source will not be changed and the PLL free running frequency will be the system clock frequency.

Example:

/* Enable oscillation stop detection. The main oscillator must be running at this point. */
err = R_CGC_OscStopDetectEnable(&g_cgc0_ctrl);
assert(FSP_SUCCESS == err);
Return values
FSP_SUCCESSOperation performed successfully.
FSP_ERR_ASSERTIONInvalid input argument.
FSP_ERR_NOT_OPENModule is not open.
FSP_ERR_LOW_VOLTAGE_MODESettings not allowed in low voltage mode.

◆ R_CGC_OscStopDetectDisable()

fsp_err_t R_CGC_OscStopDetectDisable ( cgc_ctrl_t *const  p_ctrl)

Disable the oscillation stop detection for the main clock. Implements cgc_api_t::oscStopDetectDisable.

Example:

/* (Optional) Oscillation stop detection must be disabled before entering any low power mode. */
err = R_CGC_OscStopDetectDisable(&g_cgc0_ctrl);
assert(FSP_SUCCESS == err);
__WFI();
Return values
FSP_SUCCESSOperation performed successfully.
FSP_ERR_ASSERTIONInvalid input argument.
FSP_ERR_NOT_OPENModule is not open.
FSP_ERR_OSC_STOP_DETECTEDThe Oscillation stop detect status flag is set. Under this condition it is not possible to disable the Oscillation stop detection function.

◆ R_CGC_OscStopStatusClear()

fsp_err_t R_CGC_OscStopStatusClear ( cgc_ctrl_t *const  p_ctrl)

Clear the Oscillation Stop Detection Status register. This register is not cleared automatically if the stopped clock is restarted. Implements cgc_api_t::oscStopStatusClear.

After clearing the status, oscillation stop detection is no longer enabled.

This register cannot be cleared while the main oscillator is the system clock or the PLL source clock.

Example:

/* (Optional) Clear the error flag. Only clear this flag after switching the MCU clock source away from the main
* oscillator and if the main oscillator is stable again. */
err = R_CGC_OscStopStatusClear(&g_cgc0_ctrl);
assert(FSP_SUCCESS == err);
Return values
FSP_SUCCESSOperation performed successfully.
FSP_ERR_ASSERTIONInvalid input argument.
FSP_ERR_NOT_OPENModule is not open.
FSP_ERR_CLOCK_INACTIVEMain oscillator must be running to clear the oscillation stop detection flag.
FSP_ERR_OSC_STOP_CLOCK_ACTIVEThe Oscillation Detect Status flag cannot be cleared if the Main Osc or PLL is set as the system clock. Change the system clock before attempting to clear this bit.
FSP_ERR_INVALID_HW_CONDITIONOscillation stop status was not cleared. Check preconditions and try again.

◆ R_CGC_CallbackSet()

fsp_err_t R_CGC_CallbackSet ( cgc_ctrl_t *const  p_api_ctrl,
void(*)(cgc_callback_args_t *)  p_callback,
void const *const  p_context,
cgc_callback_args_t *const  p_callback_memory 
)

Updates the user callback and has option of providing memory for callback structure. Implements cgc_api_t::callbackSet

Return values
FSP_SUCCESSCallback updated successfully.
FSP_ERR_ASSERTIONA required pointer is NULL.
FSP_ERR_NOT_OPENThe control block has not been opened.
FSP_ERR_NO_CALLBACK_MEMORYp_callback is non-secure and p_callback_memory is either secure or NULL.

◆ R_CGC_Close()

fsp_err_t R_CGC_Close ( cgc_ctrl_t *const  p_ctrl)

Closes the CGC module. Implements cgc_api_t::close.

Return values
FSP_SUCCESSThe module is successfully closed.
FSP_ERR_ASSERTIONInvalid input argument.
FSP_ERR_NOT_OPENModule is not open.