Functions
fsp_err_t	R_GPT_Open (timer_ctrl_t const p_ctrl, timer_cfg_t const const p_cfg)

fsp_err_t	R_GPT_Stop (timer_ctrl_t *const p_ctrl)

fsp_err_t	R_GPT_Start (timer_ctrl_t *const p_ctrl)

fsp_err_t	R_GPT_Reset (timer_ctrl_t *const p_ctrl)

fsp_err_t	R_GPT_Enable (timer_ctrl_t *const p_ctrl)

fsp_err_t	R_GPT_Disable (timer_ctrl_t *const p_ctrl)

fsp_err_t	R_GPT_PeriodSet (timer_ctrl_t *const p_ctrl, uint32_t const period_counts)

fsp_err_t	R_GPT_DutyCycleSet (timer_ctrl_t *const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin)

fsp_err_t	R_GPT_CompareMatchSet (timer_ctrl_t *const p_ctrl, uint32_t const compare_match_value, timer_compare_match_t const match_channel)

fsp_err_t	R_GPT_InfoGet (timer_ctrl_t const p_ctrl, timer_info_t const p_info)

fsp_err_t	R_GPT_StatusGet (timer_ctrl_t const p_ctrl, timer_status_t const p_status)

fsp_err_t	R_GPT_CounterSet (timer_ctrl_t *const p_ctrl, uint32_t counter)

fsp_err_t	R_GPT_OutputEnable (timer_ctrl_t *const p_ctrl, gpt_io_pin_t pin)

fsp_err_t	R_GPT_OutputDisable (timer_ctrl_t *const p_ctrl, gpt_io_pin_t pin)

fsp_err_t	R_GPT_AdcTriggerSet (timer_ctrl_t *const p_ctrl, gpt_adc_compare_match_t which_compare_match, uint32_t compare_match_value)

fsp_err_t	R_GPT_PwmOutputDelaySet (timer_ctrl_t *const p_ctrl, gpt_pwm_output_delay_edge_t edge, gpt_pwm_output_delay_setting_t delay_setting, uint32_t const pin)

fsp_err_t	R_GPT_CallbackSet (timer_ctrl_t const p_api_ctrl, void(p_callback)(timer_callback_args_t ), void const const p_context, timer_callback_args_t *const p_callback_memory)

fsp_err_t	R_GPT_Close (timer_ctrl_t *const p_ctrl)

fsp_err_t	R_GPT_PwmOutputDelayInitialize ()

Detailed Description

Driver for the GPT32 and GPT16 peripherals on RA MCUs. This module implements the Timer Interface.

Overview

The GPT module can be used to count events, measure external input signals, generate a periodic interrupt, or output a periodic or PWM signal to a GTIOC pin.

This module supports the GPT peripherals GPT32EH, GPT32E, GPT32, and GPT16. GPT16 is a 16-bit timer. The other peripherals (GPT32EH, GPT32E, and GPT32) are 32-bit timers. The 32-bit timers are all treated the same in this module from the API perspective.

Features

The GPT module has the following features:

Supports periodic mode, one-shot mode, and PWM mode.
Supports count source of PCLK, GTETRG pins, GTIOC pins, or ELC events.
Supports debounce filter on GTIOC pins.
Signal can be output to a pin.
Configurable period (counts per timer cycle).
Configurable duty cycle in PWM mode.
Supports runtime reconfiguration of period.
Supports runtime reconfiguration of duty cycle in PWM mode.
Supports runtime reconfiguration of compare match value.
APIs are provided to start, stop, and reset the counter.
APIs are provided to get the current period, source clock frequency, and count direction.
APIs are provided to get the current timer status and counter value.
Supports start, stop, clear, count up, count down, and capture by external sources from GTETRG pins, GTIOC pins, or ELC events.
Supports symmetric and asymmetric PWM waveform generation.
Supports One shot synchronous pulse waveform generation.
Supports automatic addition of dead time.
Supports generating ELC events to start an ADC scan at a compare match value (see Event Link Controller (r_elc)) and updating the compare match value.
Supports linking with a POEG channel to automatically disable GPT output when an error condition is detected.
Supports setting the counter value while the timer is stopped.
Supports enabling and disabling output pins.
Supports skipping up to seven overflow/underflow (crest/trough) interrupts at a time
Supports generating custom PWM waveforms by configuring the pin's output level at each compare match and cycle end.

Selecting a Timer

RA MCUs have two timer peripherals: the General PWM Timer (GPT) and the Asynchronous General Purpose Timer (AGT). When selecting between them, consider these factors:

	GPT	AGT
Low Power Modes	The GPT can operate in sleep mode.	The AGT can operate in all low power modes.
Available Channels	The number of GPT channels is device specific. All currently supported MCUs have at least 7 GPT channels.	All MCUs have 2 AGT channels.
Timer Resolution	All MCUs have at least one 32-bit GPT timer.	The AGT timers are 16-bit timers.
Clock Source	The GPT runs off PCLKD with a configurable divider up to 1024. It can also be configured to count ELC events or external pulses.	The AGT runs off PCLKB, LOCO, or subclock.

Configuration

Build Time Configurations for r_gpt

The following build time configurations are defined in fsp_cfg/r_gpt_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Pin Output Support	Disabled Enabled Enabled with Extra Features	Disabled	Enables or disables support for outputting PWM waveforms on GTIOCx pins. The "Enabled with Extra Features" option enables support for Triangle wave modes and also enables the features located in the "Extra Features" section of each module instance.
Write Protect Enable	Enabled Disabled	Disabled	If selected write protection is applied to all GPT channels.

Configurations for Timers > Timer, General PWM (r_gpt)

This module can be added to the Stacks tab via New Stack > Timers > Timer, General PWM (r_gpt). Non-secure callable guard functions can be generated for this module by right clicking the module in the RA Configuration tool and checking the "Non-secure Callable" box.

Configuration	Options	Default	Description
General
General > Compare Match
General > Compare Match > Compare Match A
Status	Enabled Disabled	Disabled
Compare match value	Value must be a non-negative integer less than or equal to 0x40000000000	0	Specify the compare match A value in units that selected in Period Unit section.
General > Compare Match > Compare Match B
Status	Enabled Disabled	Disabled
Compare match value	Value must be a non-negative integer less than or equal to 0x40000000000	0	Specify the compare match B value in units that selected in Period Unit section.
Name	Name must be a valid C symbol	g_timer0	Module name.
Channel	Enter the supported Channel number	0	Specify the hardware channel.
Mode	Periodic One-Shot One-Shot Pulse Saw-wave PWM Triangle-wave PWM (symmetric, Mode 1) Triangle-wave PWM (asymmetric, Mode 2) Triangle-wave PWM (asymmetric, Mode 3)	Periodic	Mode selection. Periodic: Generates periodic interrupts or square waves. One-shot: Generate a single interrupt or a pulse wave. Note: One-shot mode is implemented in software. ISRs must be enabled for one-shot even if callback is unused. One-Shot Pulse: Counter performs saw-wave operation with fixed buffer operation. Saw-wave PWM: Generates basic saw-wave PWM waveforms. Triangle-wave PWM (symmetric, Mode 1): Generates symmetric PWM waveforms with duty cycle determined by compare match set with 32-bit transfer during a crest event and updated at the next trough with single or double buffer operation. Triangle-wave PWM (asymmetric, Mode 2): Generates asymmetric PWM waveforms with duty cycle determined by compare match set with 32-bit transfer during a crest/trough event and updated at the next trough/crest. Triangle-wave PWM (asymmetric, Mode 3): Generates PWM waveforms with duty cycle determined by compare match set with 64-bit transfer during a crest interrupt and updated at the next trough with fixed buffer operation.
Period	Value must be a non-negative integer less than or equal to 0x40000000000	0x10000	Specify the timer period in units selected below. Set the period to 0x100000000 (32-bit) or 0x10000 (16-bit) raw counts for a free running timer or an input capture configuration. The period can be set up to 0x40000000000 (32-bit) or 0x4000000 (16-bit) which will use a divider of 1024 with the maximum period. If the requested period cannot be achieved, the settings with the largest possible period that is less than or equal to the requested period are used. The theoretical calculated period is printed in a comment in the generated timer_cfg_t structure.
Period Unit	Raw Counts Nanoseconds Microseconds Milliseconds Seconds Hertz Kilohertz	Raw Counts	Unit of the period specified above
Output
Output > Custom Waveform
Output > Custom Waveform > GTIOA
Initial Output Level	Pin Level Low Pin Level High	Pin Level Low	Set the initial output level of GTIOCxA.
Cycle End Output Level	Pin Level Retain Pin Level Low Pin Level High Pin Level Toggle	Pin Level Retain	Set the output level of GTIOCxA at cycle end.
Compare Match Output Level	Pin Level Retain Pin Level Low Pin Level High Pin Level Toggle	Pin Level Retain	Set the output level of GTIOCxA at compare match.
Retain Output Level at Count Stop	Disabled Enabled	Disabled	Retain the current GTIOxA output level when counting is stopped.
Output > Custom Waveform > GTIOB
Initial Output Level	Pin Level Low Pin Level High	Pin Level Low	Set the initial output level of GTIOCxB.
Cycle End Output Level	Pin Level Retain Pin Level Low Pin Level High Pin Level Toggle	Pin Level Retain	Set the output level of GTIOCxB at cycle end.
Compare Match Output Level	Pin Level Retain Pin Level Low Pin Level High Pin Level Toggle	Pin Level Retain	Set the output level of GTIOCxB at compare match.
Retain Output Level at Count Stop	Disabled Enabled	Disabled	Retain the current GTIOxB output level when counting is stopped.
Custom Waveform Enable	Disabled Enabled	Disabled	Enable custom waveform configuration.
Duty Cycle Percent (only applicable in PWM mode)	Value must be between 0 and 100	50	Specify the timer duty cycle percent. Only used in PWM mode.
GTIOCA Output Enabled	True False	False	Enable the output of GTIOCA on a pin.
GTIOCA Stop Level	Pin Level Low Pin Level High	Pin Level Low	Select the behavior of the output pin when the timer is stopped.
GTIOCB Output Enabled	True False	False	Enable the output of GTIOCB on a pin.
GTIOCB Stop Level	Pin Level Low Pin Level High	Pin Level Low	Select the behavior of the output pin when the timer is stopped.
Input
Count Up Source	MCU Specific Options		Select external source that will increment the counter. If any count up source is selected, the timer will count the external sources only. It will not count PCLKD cycles.
Count Down Source	MCU Specific Options		Select external source that will decrement the counter. If any count down source is selected, the timer will count the external sources only. It will not count PCLKD cycles.
Start Source	MCU Specific Options		Select external source that will start the timer. For pulse width measurement, set the Start Source and the Clear Source to the trigger edge (the edge to start the measurement), and set the Stop Source and Capture Source (either A or B) to the opposite edge (the edge to stop the measurement). For pulse period measurement, set the Start Source, the Clear Source, and the Capture Source (either A or B) to the trigger edge (the edge to start the measurement).
Stop Source	MCU Specific Options		Select external source that will stop the timer.
Clear Source	MCU Specific Options		Select external source that will clear the timer.
Capture A Source	MCU Specific Options		Select external source that will trigger a capture A event.
Capture B Source	MCU Specific Options		Select external source that will trigger a capture B event.
Noise Filter A Sampling Clock Select	No Filter Filter PCLKD / 1 Filter PCLKD / 4 Filter PCLKD / 16 Filter PCLKD / 64	No Filter	Select the input filter for GTIOCA.
Noise Filter B Sampling Clock Select	No Filter Filter PCLKD / 1 Filter PCLKD / 4 Filter PCLKD / 16 Filter PCLKD / 64	No Filter	Select the input filter for GTIOCB.
Interrupts
Callback	Name must be a valid C symbol	NULL	A user callback function can be specified here. If this callback function is provided, it will be called from the interrupt service routine (ISR) each time the timer period elapses
Overflow/Crest Interrupt Priority	MCU Specific Options		Select the overflow interrupt priority. This is the crest interrupt for triangle-wave PWM.
Capture/Compare match A Interrupt Priority	MCU Specific Options		Select the interrupt priority for Capture/Compare match A.
Capture/Compare match B Interrupt Priority	MCU Specific Options		Select the interrupt priority for Capture/Compare match B.
Underflow/Trough Interrupt Priority	MCU Specific Options		Select the interrupt priority for the trough interrupt (triangle-wave PWM only).
Extra Features
Extra Features > Output Disable
POEG Link	MCU Specific Options		Select which POEG to link this GPT channel to.
Output Disable POEG Trigger	Dead Time Error GTIOCA and GTIOCB High Level GTIOCA and GTIOCB Low Level		Select which errors send an output disable trigger to POEG. Dead time error is only available GPT channels that have GTINTAD.GRPDTE.
GTIOCA Disable Setting	Disable Prohibited Set Hi Z Level Low Level High	Disable Prohibited	Select the disable setting for GTIOCA.
GTIOCB Disable Setting	Disable Prohibited Set Hi Z Level Low Level High	Disable Prohibited	Select the disable setting for GTIOCB.
Extra Features > ADC Trigger
Start Event Trigger (Channels with GTINTAD only)	Trigger Event A/D Converter Start Request A During Up Counting Trigger Event A/D Converter Start Request A During Down Counting Trigger Event A/D Converter Start Request B During Up Counting Trigger Event A/D Converter Start Request B During Down Counting		Select which A/D converter start request interrupts to generate and at which point in the cycle to generate them.
ADC A Compare Match (Raw Counts)	Must be a valid non-negative integer with a maximum configurable value of 4294967295 (0xffffffff).	0	Select the compare match value that generates a GPTn AD TRIG A event.
ADC B Compare Match (Raw Counts)	Must be a valid non-negative integer with a maximum configurable value of 4294967295 (0xffffffff).	0	Select the compare match value that generates a GPTn AD TRIG B event.
Extra Features > Dead Time (Value range varies with Channel)
Dead Time Count Up (Raw Counts)	Must be a valid non-negative integer with a maximum configurable value of 4294967295 (0xffffffff).	0	Select the dead time to apply during up counting. This value also applies during down counting for channels that do not have GTDVD. The dead time count up value can be set up to 0xffffffff (32-bit) or 0xffff (16-bit).
Dead Time Count Down (Raw Counts) (Channels with GTDVD only)	Must be a valid non-negative integer with a maximum configurable value of 4294967295 (0xffffffff).	0	Select the dead time to apply during down counting. The dead time count down value can be set up to 0xffffffff (32-bit) or 0xffff (16-bit).
Extra Features > Interrupt Skipping (Channels with GTITC only)
Interrupt to Count	None Overflow and Underflow (sawtooth) Crest (triangle) Trough (triangle)	None	Select the count source for interrupt skipping. The interrupt skip counter increments after each source event. All crest/overflow and trough/underflow interrupts are skipped when the interrupt skip counter is non-zero.
Interrupt Skip Count	0 1 2 3 4 5 6 7	0	Select the number of interrupts to skip.
Skip ADC Events	None ADC A Compare Match ADC B Compare Match ADC A and B Compare Match	None	Select ADC events to suppress when the interrupt skip count is not zero.
Extra Features	Enabled Disabled	Disabled	Select whether to enable extra features on this channel.

Clock Configuration

The GPT clock is based on the PCLKD frequency. You can set the PCLKD frequency using the Clocks tab of the RA Configuration editor or by using the CGC Interface at run-time.

Pin Configuration

This module can use GTETRGA, GTETRGB, GTETRGC, GTETRGD, GTIOCA and GTIOCB pins as count sources.

This module can use GTIOCA and GTIOCB pins as output pins for periodic or PWM signals.

This module can use GTIOCA and GTIOCB as input pins to measure input signals.

Usage Notes

Maximum Period

The RA Configuration editor will automatically calculate the period count value and source clock divider based on the selected period time, units and clock speed.

When the selected period unit is "Raw counts", the maximum period setting is 0x40000000000 on a 32-bit timer or 0x4000000 on a 16-bit timer. This will configure the timer with the maximum period and a count clock divisor of 1024.

Note: 16-bit channels inherently have a reduced maximum period compared to 32-bit channels. When setting period values of hundreds of milliseconds or more on 16-bit channels be sure to check the generated output to confirm the actual configured value as it will clip much earlier than 32-bit channels. In general, it is recommended to use a lower-power timer like AGT or RTC if long hardware delays are required.

Updating Period and Duty Cycle

The period and duty cycle are updated after the next counter overflow after calling R_GPT_PeriodSet() or R_GPT_DutyCycleSet(). To force them to update before the next counter overflow, call R_GPT_Reset() while the counter is running.

Note: When manually changing the timer period counts the maximum value for a 32-bit GPT is 0x100000000. This number overflows the 32-bit value for timer_cfg_t::period_counts. To configure the timer for the maximum period, set timer_cfg_t::period_counts to 0.

One-Shot Mode

The GPT timer does not support one-shot mode natively. One-shot mode is achieved by stopping the timer in the interrupt service routine before the callback is called. If the interrupt is not serviced before the timer period expires again, the timer generates more than one event. The callback is only called once in this case, but multiple events may be generated if the timer is linked to the Transfer (r_dtc).

One-Shot Mode Output

The output waveform in one-shot mode is one PCLKD cycle less than the configured period. The configured period must be at least 2 counts to generate an output pulse.

Examples of one-shot signals that can be generated by this module are shown below:

GPT One-Shot Output

One-Shot Pulse Mode

The one-shot pulse mode is an asymmetric PWM mode that provides more control over the rising and falling edges of the output. The user provides a period and initial output level and controls the signal by specifying compare match values for the leading and trailing edges each period.

Note: Despite its name, the One-Shot Pulse Mode operates continuously and does not stop after the first period.

One-Shot Pulse Mode Output

Examples of PWM signals that can be generated by this module are shown below. The leading and trailing edge match values can be modified using R_GPT_DutyCycleSet() in the overflow interrupt.

GPT One-Shot Pulse Output (without dead time)

If dead time is enabled only match values for GTIOCnA need to be set; the match values for GTIOCnB will be automatically configured in hardware.

GPT One-Shot Pulse Output (with dead time)

Periodic Output

The GTIOC pin toggles twice each time the timer expires in periodic mode. This is achieved by defining a PWM wave at a 50 percent duty cycle so that the period of the resulting square wave (from rising edge to rising edge) matches the period of the GPT timer. Since the periodic output is actually a PWM output, the time at the stop level is one cycle shorter than the time opposite the stop level for odd period values.

Examples of periodic signals that can be generated by this module are shown below:

GPT Periodic Output

PWM Output

The PWM output signal is high at the beginning of the cycle and low at the end of the cycle.

Examples of PWM signals that can be generated by this module are shown below:

GPT PWM Output

Triangle-Wave PWM Output

Examples of PWM signals that can be generated by this module are shown below. The duty_cycle_counts can be modified using R_GPT_DutyCycleSet() in the crest interrupt and updated at the following trough for symmetric PWM or modified in both the crest/trough interrupts and updated at the following trough/crest for asymmetric PWM.

GPT Triangle-Wave PWM Output

PWM Output Delay Circuit

On select MCUs, an additional PWM output delay circuit can be configured in order to fine tune the rising and falling edge delays in increments of 1/32 times the period of the GPT core clock. The PWM output delay function must be configured prior to initializing the GPT channels using R_GPT_PwmOutputDelayInitialize.

Note: 1. In Saw-wave PWM mode, the output delay setting cannot be changed while the capture compare setting (GTCCRn) is greater than or equal the period setting (GTPR) - 2.; 2. In Triangle PWM modes, the output delay setting cannot be changed while the counter is counting down, and the capture compare setting (GTCCRn) is less than or equal to 2.; 3. When the PWM Output Delay Circuit is enabled, the PWM signal is delayed by 3 GPT core clock cycles.; 4. When the GPTCLK is used as the GPT core clock, the following delay is required between writes to the rising or falling edge output delay setting for a given pin: Write_Interval[ns] = Period_of_PCLKA [ns] × 6 + Period_of_GPTCLK [ns] × 4).

Event Counting

Event counting can be done by selecting up or down counting sources from GTETRG pins, ELC events, or GTIOC pins. In event counting mode, the GPT counter is not affected by PCLKD.

Note: In event counting mode, the application must call R_GPT_Start() to enable event counting. The counter will not change after calling R_GPT_Start() until an event occurs.

Pulse Measurement

If the capture edge occurs before the start edge in pulse measurement, the first capture is invalid (0).

Controlling GPT with GTETRG Edges

The GPT timer can be configured to stop, start, clear, count up, or count down when a GTETRG rising or falling edge occurs.

Note: The GTETRG pins are shared by all GPT channels.; GTETRG pins require POEG to be on (example code for this is provided in GPT Free Running Counter Example). If input filtering is required on the GTETRG pins, that must also be handled outside this module.

Controlling GPT with ELC Events

The GPT timer can be configured to stop, start, clear, count up, or count down when an ELC event occurs.

Note: The configurable ELC GPT sources are shared by all GPT channels.; The event links for the ELC must be configured outside this module.

Triggering ELC Events with GPT

The GPT timer can trigger the start of other peripherals. The Event Link Controller (r_elc) guide provides a list of all available peripherals.

Enabling External Sources for Start, Stop, Clear, or Capture

R_GPT_Enable() must be called when external sources are used for start, stop, clear, or capture.

Interrupt Skipping

When an interrupt skipping source is selected a hardware counter will increment each time the selected event occurs. Each interrupt past the first (up to the specified skip count) will be suppressed. If ADC events are selected for skipping they will also be suppressed except during the timer period leading to the selected interrupt skipping event (see below diagram).

Crest interrupt skipping in triangle-wave PWM modes (skip count 2)

Complementary Output

By using the Custom Waveform option the output pins can be made to output complementary waveforms. To ensure these waveforms stay in sync, the duty cycle for both pins can be set simultaneously by calling R_GPT_DutyCycleSet once with a pin parameter of GPT_IO_PIN_GTIOCA_AND_GTIOCB.

Note: The pin level for 0% and 100% duty cycle is determined by the Cycle End Output Level in normal PWM mode and the Initial Output Level in triangle PWM modes. 100% duty will output the configured level and 0% will output the opposite. Do not use Pin Level Toggle or Pin Level Retain for the Cycle End Output Level if normal PWM waveforms are desired.

Examples

GPT Basic Example

This is a basic example of minimal use of the GPT in an application.

void gpt_basic_example (void)
{
    fsp_err_t err = FSP_SUCCESS;
    /* Initializes the module. */
    err = R_GPT_Open(&g_timer0_ctrl, &g_timer0_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
    /* Start the timer. */
    (void) R_GPT_Start(&g_timer0_ctrl);
}

GPT Callback Example

This is an example of a timer callback.

/* Example callback called when timer expires. */
void timer_callback (timer_callback_args_t * p_args)
{
    if (TIMER_EVENT_CYCLE_END == p_args->event)
    {
        /* Add application code to be called periodically here. */
    }
}

GPT Free Running Counter Example

To use the GPT as a free running counter, select periodic mode and set the the Period to 0xFFFFFFFF for a 32-bit timer or 0xFFFF for a 16-bit timer.

void gpt_counter_example (void)
{
    fsp_err_t err = FSP_SUCCESS;
    /* (Optional) If event count mode is used to count edges on a GTETRG pin, POEG must be started to use GTETRG.
     * Reference Note 1 of Table 23.2 "GPT functions" in the RA6M3 manual R01UH0886EJ0100. */
    R_BSP_MODULE_START(FSP_IP_POEG, 0U);
    /* Initializes the module. */
    err = R_GPT_Open(&g_timer0_ctrl, &g_timer0_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
    /* Start the timer. */
    (void) R_GPT_Start(&g_timer0_ctrl);
    /* (Optional) Stop the timer. */
    (void) R_GPT_Stop(&g_timer0_ctrl);
    /* Read the current counter value. Counter value is in status.counter. */
    timer_status_t status;
    (void) R_GPT_StatusGet(&g_timer0_ctrl, &status);
}

GPT Input Capture Example

This is an example of using the GPT to capture pulse width or pulse period measurements.

/* Example callback called when a capture occurs. */
uint64_t g_captured_time     = 0U;
uint32_t g_capture_overflows = 0U;
void timer_capture_callback (timer_callback_args_t * p_args)
{
    if ((TIMER_EVENT_CAPTURE_A == p_args->event) || (TIMER_EVENT_CAPTURE_B == p_args->event))
    {
        /* (Optional) Get the current period if not known. */
        timer_info_t info;
        (void) R_GPT_InfoGet(&g_timer0_ctrl, &info);
        uint64_t period = info.period_counts;
        /* The maximum period is one more than the maximum 32-bit number, but will be reflected as 0 in
         * timer_info_t::period_counts. */
        if (0U == period)
        {
            period = UINT32_MAX + 1U;
        }
        g_captured_time     = (period * g_capture_overflows) + p_args->capture;
        g_capture_overflows = 0U;
    }
    if (TIMER_EVENT_CYCLE_END == p_args->event)
    {
        /* An overflow occurred during capture. This must be accounted for at the application layer. */
        g_capture_overflows++;
    }
}
void gpt_capture_example (void)
{
    fsp_err_t err = FSP_SUCCESS;
    /* Initializes the module. */
    err = R_GPT_Open(&g_timer0_ctrl, &g_timer0_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
    /* Enable captures. Captured values arrive in the interrupt. */
    (void) R_GPT_Enable(&g_timer0_ctrl);
    /* (Optional) Disable captures. */
    (void) R_GPT_Disable(&g_timer0_ctrl);
}

GPT Period Update Example

This an example of updating the period.

#define GPT_EXAMPLE_MSEC_PER_SEC           (1000)
#define GPT_EXAMPLE_DESIRED_PERIOD_MSEC    (20)
/* This example shows how to calculate a new period value at runtime. */
void gpt_period_calculation_example (void)
{
    fsp_err_t err = FSP_SUCCESS;
    /* Initializes the module. */
    err = R_GPT_Open(&g_timer0_ctrl, &g_timer0_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
    /* Start the timer. */
    (void) R_GPT_Start(&g_timer0_ctrl);
    /* Get the source clock frequency (in Hz). There are 3 ways to do this in FSP:
     *  - If the PCLKD frequency has not changed since reset, the source clock frequency is
     *    BSP_STARTUP_PCLKD_HZ >> timer_cfg_t::source_div
     *  - Use the R_GPT_InfoGet function (it accounts for the divider).
     *  - Calculate the current PCLKD frequency using R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) and right shift
     *    by timer_cfg_t::source_div.
     *
     * This example uses the 3rd option (R_FSP_SystemClockHzGet).
     */
    uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) >> g_timer0_cfg.source_div;
    /* Calculate the desired period based on the current clock. Note that this calculation could overflow if the
     * desired period is larger than UINT32_MAX / pclkd_freq_hz. A cast to uint64_t is used to prevent this. */
    uint32_t period_counts =
        (uint32_t) (((uint64_t) pclkd_freq_hz * GPT_EXAMPLE_DESIRED_PERIOD_MSEC) / GPT_EXAMPLE_MSEC_PER_SEC);
    /* Set the calculated period. */
    err = R_GPT_PeriodSet(&g_timer0_ctrl, period_counts);
    assert(FSP_SUCCESS == err);
}

GPT Duty Cycle Update Example

This an example of updating the duty cycle.

#define GPT_EXAMPLE_DESIRED_DUTY_CYCLE_PERCENT    (25)
#define GPT_EXAMPLE_MAX_PERCENT                   (100)
/* This example shows how to calculate a new duty cycle value at runtime. */
void gpt_duty_cycle_calculation_example (void)
{
    fsp_err_t err = FSP_SUCCESS;
    /* Initializes the module. */
    err = R_GPT_Open(&g_timer0_ctrl, &g_timer0_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
    /* Start the timer. */
    (void) R_GPT_Start(&g_timer0_ctrl);
    /* Get the current period setting. */
    timer_info_t info;
    (void) R_GPT_InfoGet(&g_timer0_ctrl, &info);
    uint32_t current_period_counts = info.period_counts;
    /* Calculate the desired duty cycle based on the current period. Note that if the period could be larger than
     * UINT32_MAX / 100, this calculation could overflow. A cast to uint64_t is used to prevent this. The cast is
     * not required for 16-bit timers. */
    uint32_t duty_cycle_counts =
        (uint32_t) (((uint64_t) current_period_counts * GPT_EXAMPLE_DESIRED_DUTY_CYCLE_PERCENT) /
                    GPT_EXAMPLE_MAX_PERCENT);
    /* Set the calculated duty cycle. */
    err = R_GPT_DutyCycleSet(&g_timer0_ctrl, duty_cycle_counts, GPT_IO_PIN_GTIOCB);
    assert(FSP_SUCCESS == err);
}

GPT A/D Converter Start Request Example

This is an example of using the GPT to start the ADC at a configurable A/D converter compare match value.

#if ((1U << GPT_EXAMPLE_CHANNEL) & (BSP_FEATURE_GPT_GPTE_CHANNEL_MASK | BSP_FEATURE_GPT_GPTEH_CHANNEL_MASK | \
                                    BSP_FEATURE_GPT_AD_DIRECT_START_CHANNEL_MASK))
/* This example shows how to configure the GPT to generate an A/D start request at an A/D start request compare
 * match value. This example can only be used with GPTE or GPTEH variants. */
void gpt_adc_start_request_example (void)
{
    fsp_err_t err = FSP_SUCCESS;
 #if ((BSP_FEATURE_GPT_GPTE_SUPPORTED | BSP_FEATURE_GPT_GPTEH_SUPPORTED) && !BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED)
    /* Initialize and configure the ELC. */
    err = R_ELC_Open(&g_elc_ctrl, &g_elc_cfg);
    assert(FSP_SUCCESS == err);
    /* Configure the ELC to start a scan on ADC unit 0 when GPT channel 0. Note: This is typically configured in
     * g_elc_cfg and already set during R_ELC_Open. */
    err = R_ELC_LinkSet(&g_elc_ctrl, ELC_PERIPHERAL_ADC0, ELC_EVENT_GPT0_AD_TRIG_A);
    assert(FSP_SUCCESS == err);
    /* Globally enable ELC events. */
    err = R_ELC_Enable(&g_elc_ctrl);
    assert(FSP_SUCCESS == err);
 #else                                 /* BSP_FEATURE_GPT_AD_DIRECT_START_SUPPORTED */
    /* Do not configure AD ELC trigger for devices with GPT ADC direct-start support */
 #endif
    /* Initialize the ADC to start a scan based on an GPT compare-match event trigger. Set adc_cfg_t::trigger to
     * ADC_TRIGGER_SYNC_ELC.  */
    err = R_ADC_Open(&g_adc0_ctrl, &g_adc0_cfg);
    assert(FSP_SUCCESS == err);
    err = R_ADC_ScanCfg(&g_adc0_ctrl, &g_adc0_channel_cfg);
    assert(FSP_SUCCESS == err);
    /* Enable synchronous triggers by calling R_ADC_ScanStart(). */
    (void) R_ADC_ScanStart(&g_adc0_ctrl);
    /* Initializes the GPT module. Configure gpt_extended_pwm_cfg_t::adc_trigger to set when the A/D start request
     * is generated. Set gpt_extended_pwm_cfg_t::adc_a_compare_match to set the desired compare match value. */
    err = R_GPT_Open(&g_timer0_ctrl, &g_timer0_cfg);
    assert(FSP_SUCCESS == err);
    /* Start the timer. A/D converter start request events are generated each time the counter is equal to the
     * A/D start request compare match value. */
    (void) R_GPT_Start(&g_timer0_ctrl);
}
#endif

GPT One-Shot Pulse Mode Example

This example demonstrates the configuration and use of one-shot pulse mode with GPT timer.

/* Example callback called when timer overflows. */
void gpt_overflow_callback (timer_callback_args_t * p_args)
{
    if (TIMER_EVENT_CYCLE_END == p_args->event)
    {
        g_timer_cycle_end_counter++;
        /* Use R_GPT_DutyCycleSet() API to set new values for each cycle.
         * - Use GPT_IO_PIN_ONE_SHOT_LEADING_EDGE to set the leading edge transition match value (GTCCRC or GTCCRE register).
         * - Use GPT_IO_PIN_ONE_SHOT_TRAILING_EDGE to set the trailing edge transition match value (GTCCRD or GTCCRF register).
         */
    }
}
/* GTIOCA (configured for active-high) first and second pulse will be:
 * - 1/2 period, offset by 3/8 period
 * - 1/4 period, offset by 1/4 period */
#define GPT_ONE_SHOT_EXAMPLE_FIRST_EDGE_PIN_A     ((g_timer0_cfg.period_counts * 3) / 8)
#define GPT_ONE_SHOT_EXAMPLE_SECOND_EDGE_PIN_A    ((g_timer0_cfg.period_counts * 7) / 8)
#define GPT_ONE_SHOT_EXAMPLE_THIRD_EDGE_PIN_A     ((g_timer0_cfg.period_counts * 1) / 4)
#define GPT_ONE_SHOT_EXAMPLE_FOURTH_EDGE_PIN_A    ((g_timer0_cfg.period_counts * 2) / 4)
/* GTIOCB (configured for active-low) first and second pulse will be:
 * - 1/2 period, offset by 1/4 period
 * - 1/4 period, offset by 1/2 period */
#define GPT_ONE_SHOT_EXAMPLE_FIRST_EDGE_PIN_B     ((g_timer0_cfg.period_counts * 1) / 4)
#define GPT_ONE_SHOT_EXAMPLE_SECOND_EDGE_PIN_B    ((g_timer0_cfg.period_counts * 3) / 4)
#define GPT_ONE_SHOT_EXAMPLE_THIRD_EDGE_PIN_B     ((g_timer0_cfg.period_counts * 2) / 4)
#define GPT_ONE_SHOT_EXAMPLE_FOURTH_EDGE_PIN_B    ((g_timer0_cfg.period_counts * 3) / 4)
/* Configure and output a one-shot pulse that resembles what is shown in the example above. */
void gpt_one_shot_pulse_mode_example (void)
{
    fsp_err_t err = FSP_SUCCESS;
    /* Initializes the module. */
    err = R_GPT_Open(&g_timer0_ctrl, &g_timer0_cfg);
    assert(FSP_SUCCESS == err);
    /* Set first edge transition count for GTIOCA and GTIOCB.
     *
     * Notes:
     *  - Two temporary registers (A and B) are used for the second edge.
     *  - Temporary register A and Temporary register B may only be loaded by shifting from GTCCRD and GTCCRF, which is why the GPT_BUFFER_FORCE_PUSH is necessary
     *  - If GPT_BUFFER_FORCE_PUSH is not used, timing for the first pulse will be undefined.
     *  - For more information, see "Example setting for saw-wave one-shot pulse mode" in the UM for your MCU. */
    err = R_GPT_DutyCycleSet(&g_timer0_ctrl,
                             GPT_ONE_SHOT_EXAMPLE_FIRST_EDGE_PIN_A,
                             GPT_IO_PIN_GTIOCA | GPT_IO_PIN_ONE_SHOT_LEADING_EDGE);
    assert(FSP_SUCCESS == err);
    err = R_GPT_DutyCycleSet(&g_timer0_ctrl,
                             GPT_ONE_SHOT_EXAMPLE_FIRST_EDGE_PIN_B,
                             GPT_IO_PIN_GTIOCB | GPT_IO_PIN_ONE_SHOT_LEADING_EDGE);
    assert(FSP_SUCCESS == err);
    /* Set third edge transition count for GTIOCA and GTIOCB
     * Also force-push to shift all four counts into active buffer locations. */
    err = R_GPT_DutyCycleSet(&g_timer0_ctrl,
                             GPT_ONE_SHOT_EXAMPLE_SECOND_EDGE_PIN_A,
                             GPT_IO_PIN_GTIOCA | GPT_IO_PIN_ONE_SHOT_TRAILING_EDGE);
    assert(FSP_SUCCESS == err);
    err = R_GPT_DutyCycleSet(&g_timer0_ctrl,
                             GPT_ONE_SHOT_EXAMPLE_SECOND_EDGE_PIN_B,
                             GPT_IO_PIN_GTIOCB | GPT_IO_PIN_ONE_SHOT_TRAILING_EDGE | GPT_BUFFER_FORCE_PUSH);
    assert(FSP_SUCCESS == err);
    /* Set third leading edge transition count for GTIOCA and GTIOCB.
     * Note: It is not necessary to set third and fourth transition edges if it is not required by the application. */
    err = R_GPT_DutyCycleSet(&g_timer0_ctrl,
                             GPT_ONE_SHOT_EXAMPLE_THIRD_EDGE_PIN_A,
                             GPT_IO_PIN_GTIOCA | GPT_IO_PIN_ONE_SHOT_LEADING_EDGE);
    assert(FSP_SUCCESS == err);
    err = R_GPT_DutyCycleSet(&g_timer0_ctrl,
                             GPT_ONE_SHOT_EXAMPLE_THIRD_EDGE_PIN_B,
                             GPT_IO_PIN_GTIOCB | GPT_IO_PIN_ONE_SHOT_LEADING_EDGE);
    assert(FSP_SUCCESS == err);
    /* Set fourth edge transition count for GTIOCA and GTIOCB
     * Do not force-push, shifting third and fourth edges would overwrite active buffer locations (first and second edge counts). */
    err = R_GPT_DutyCycleSet(&g_timer0_ctrl,
                             GPT_ONE_SHOT_EXAMPLE_FOURTH_EDGE_PIN_A,
                             GPT_IO_PIN_GTIOCA | GPT_IO_PIN_ONE_SHOT_TRAILING_EDGE);
    assert(FSP_SUCCESS == err);
    err = R_GPT_DutyCycleSet(&g_timer0_ctrl,
                             GPT_ONE_SHOT_EXAMPLE_FOURTH_EDGE_PIN_B,
                             GPT_IO_PIN_GTIOCB | GPT_IO_PIN_ONE_SHOT_TRAILING_EDGE);
    assert(FSP_SUCCESS == err);
    /* Start the timer. */
    R_GPT_Start(&g_timer0_ctrl);
    assert(FSP_SUCCESS == err);
    /* Wait for the one-shot pulse output to complete then stop GPT
     *
     * Notes:
     *  - FSP driver does not currently support automatically stopping one-shot pulse. If GPT is not stopped the last waveform timing will be repeated indefinitely.
     *  - Some (more recent) MCUs added a new register (GTPC) that could be used to automatically stop GPT after a set number of periods. Software driver support for this is scheduled to be added in the future.
     *  - The last transition edge timings will continue to be used indefinitely until the user application stops GPT operation. */
    while (g_timer_cycle_end_counter < 2)
    {
        /* Wait for one-shot pulse output to complete (two pulses) */
    }
    /* (Optional) Stop the timer. */
    err = R_GPT_Stop(&g_timer0_ctrl);
    assert(FSP_SUCCESS == err);
}

GPT Compare Match Set Example

This example demonstrates the configuration and use of compare match with GPT timer.

/* Example callback called when compare match occurs. */
void gpt_compare_match_callback (timer_callback_args_t * p_args)
{
    if (TIMER_EVENT_COMPARE_A == p_args->event)
    {
        /* Add application code to be called periodically here. */
    }
}
#define GPT_COMPARE_MATCH_EXAMPLE_VALUE    (0x2000U)
void gpt_compare_match_set_example (void)
{
    fsp_err_t err = FSP_SUCCESS;
    /* Initializes the module. */
    err = R_GPT_Open(&g_timer0_ctrl, &g_timer0_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
    /* Set the compare match value (GPT_COMPARE_MATCH_EXAMPLE_VALUE). This value must be less than or equal to period value. */
    err = R_GPT_CompareMatchSet(&g_timer0_ctrl, GPT_COMPARE_MATCH_EXAMPLE_VALUE, TIMER_COMPARE_MATCH_A);
    assert(FSP_SUCCESS == err);
    /* Start the timer. */
    (void) R_GPT_Start(&g_timer0_ctrl);
    /* (Optional) Stop the timer. */
    (void) R_GPT_Stop(&g_timer0_ctrl);
}

Data Structures
struct	gpt_output_pin_t

struct	gpt_gtior_setting_t

struct	gpt_instance_ctrl_t

struct	gpt_extended_pwm_cfg_t

struct	gpt_extended_cfg_t

Enumerations
enum	gpt_io_pin_t

enum	gpt_buffer_force_push

enum	gpt_pin_level_t

enum	gpt_source_t

enum	gpt_capture_filter_t

enum	gpt_adc_trigger_t

enum	gpt_poeg_link_t

enum	gpt_output_disable_t

enum	gpt_gtioc_disable_t

enum	gpt_adc_compare_match_t

enum	gpt_interrupt_skip_source_t

enum	gpt_interrupt_skip_count_t

enum	gpt_interrupt_skip_adc_t

enum	gpt_pwm_output_delay_setting_t

enum	gpt_pwm_output_delay_edge_t

Data Structure Documentation

◆ gpt_output_pin_t

struct gpt_output_pin_t

Configurations for output pins.

Data Fields
bool	output_enabled	Set to true to enable output, false to disable output.
gpt_pin_level_t	stop_level	Select a stop level from gpt_pin_level_t.

◆ gpt_gtior_setting_t

struct gpt_gtior_setting_t

Custom GTIOR settings used for configuring GTIOCxA and GTIOCxB pins.

◆ gpt_instance_ctrl_t

struct gpt_instance_ctrl_t

Channel control block. DO NOT INITIALIZE. Initialization occurs when timer_api_t::open is called.

◆ gpt_extended_pwm_cfg_t

struct gpt_extended_pwm_cfg_t

GPT extension for advanced PWM features.

Data Fields
uint8_t	trough_ipl	Trough interrupt priority.
IRQn_Type	trough_irq	Trough interrupt.
gpt_poeg_link_t	poeg_link	Select which POEG channel controls output disable for this GPT channel.
gpt_output_disable_t	output_disable	Select which trigger sources request output disable from POEG.
gpt_adc_trigger_t	adc_trigger	Select trigger sources to start A/D conversion.
uint32_t	dead_time_count_up	Set a dead time value for counting up.
uint32_t	dead_time_count_down	Set a dead time value for counting down (available on GPT32E and GPT32EH only)
uint32_t	adc_a_compare_match	Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT<channel>_AD_TRIG_A.
uint32_t	adc_b_compare_match	Select the compare match value used to trigger an A/D conversion start request using ELC_EVENT_GPT<channel>_AD_TRIG_B.
gpt_interrupt_skip_source_t	interrupt_skip_source	Interrupt source to count for interrupt skipping.
gpt_interrupt_skip_count_t	interrupt_skip_count	Number of interrupts to skip between events.
gpt_interrupt_skip_adc_t	interrupt_skip_adc	ADC events to skip when interrupt skipping is enabled.
gpt_gtioc_disable_t	gtioca_disable_setting	Select how to configure GTIOCA when output is disabled.
gpt_gtioc_disable_t	gtiocb_disable_setting	Select how to configure GTIOCB when output is disabled.

◆ gpt_extended_cfg_t

struct gpt_extended_cfg_t

GPT extension configures the output pins for GPT.

Data Fields
gpt_output_pin_t	gtioca	Configuration for GPT I/O pin A.
gpt_output_pin_t	gtiocb	Configuration for GPT I/O pin B.
gpt_source_t	start_source	Event sources that trigger the timer to start.
gpt_source_t	stop_source	Event sources that trigger the timer to stop.
gpt_source_t	clear_source	Event sources that trigger the timer to clear.
gpt_source_t	capture_a_source	Event sources that trigger capture of GTIOCA.
gpt_source_t	capture_b_source	Event sources that trigger capture of GTIOCB.
gpt_source_t	count_up_source	Event sources that trigger a single up count. If GPT_SOURCE_NONE is selected for both count_up_source and count_down_source, then the timer count source is PCLK.
gpt_source_t	count_down_source	Event sources that trigger a single down count. If GPT_SOURCE_NONE is selected for both count_up_source and count_down_source, then the timer count source is PCLK.
gpt_capture_filter_t	capture_filter_gtioca
gpt_capture_filter_t	capture_filter_gtiocb
uint8_t	capture_a_ipl	Capture A interrupt priority.
uint8_t	capture_b_ipl	Capture B interrupt priority.
IRQn_Type	capture_a_irq	Capture A interrupt.
IRQn_Type	capture_b_irq	Capture B interrupt.
uint32_t	compare_match_value[2]	Storing compare match value for channels.
uint8_t	compare_match_status	Storing the compare match register status.
gpt_extended_pwm_cfg_t const *	p_pwm_cfg	Advanced PWM features, optional.
gpt_gtior_setting_t	gtior_setting	Custom GTIOR settings used for configuring GTIOCxA and GTIOCxB pins.

Enumeration Type Documentation

◆ gpt_io_pin_t

enum gpt_io_pin_t

Input/Output pins, used to select which duty cycle to update in R_GPT_DutyCycleSet().

Enumerator
GPT_IO_PIN_GTIOCA	GTIOCA.
GPT_IO_PIN_GTIOCB	GTIOCB.
GPT_IO_PIN_GTIOCA_AND_GTIOCB	GTIOCA and GTIOCB.
GPT_IO_PIN_TROUGH	Used in R_GPT_DutyCycleSet when Triangle-wave PWM Mode 3 is selected.
GPT_IO_PIN_CREST	Used in R_GPT_DutyCycleSet when Triangle-wave PWM Mode 3 is selected.
GPT_IO_PIN_ONE_SHOT_LEADING_EDGE	Used in R_GPT_DutyCycleSet to set GTCCRC and GTCCRE registers when One-Shot Pulse mode is selected.
GPT_IO_PIN_ONE_SHOT_TRAILING_EDGE	Used in R_GPT_DutyCycleSet to set GTCCRD and GTCCRF registers when One-Shot Pulse mode is selected.

◆ gpt_buffer_force_push

enum gpt_buffer_force_push

Forced buffer push operation used in One-Sot Pulse mode with R_GPT_DutyCycleSet().

Enumerator
GPT_BUFFER_FORCE_PUSH	Used in R_GPT_DutyCycleSet to force push the data from GTCCRn registers to temporary buffer A or B when One-Shot Pulse mode is selected.

◆ gpt_pin_level_t

enum gpt_pin_level_t

Level of GPT pin

Enumerator
GPT_PIN_LEVEL_LOW	Pin level low.
GPT_PIN_LEVEL_HIGH	Pin level high.

◆ gpt_source_t

enum gpt_source_t

Sources can be used to start the timer, stop the timer, count up, or count down. These enumerations represent a bitmask. Multiple sources can be ORed together.

Enumerator
GPT_SOURCE_NONE	No active event sources.
GPT_SOURCE_GTETRGA_RISING	Action performed on GTETRGA rising edge.
GPT_SOURCE_GTETRGA_FALLING	Action performed on GTETRGA falling edge.
GPT_SOURCE_GTETRGB_RISING	Action performed on GTETRGB rising edge.
GPT_SOURCE_GTETRGB_FALLING	Action performed on GTETRGB falling edge.
GPT_SOURCE_GTETRGC_RISING	Action performed on GTETRGC rising edge.
GPT_SOURCE_GTETRGC_FALLING	Action performed on GTETRGC falling edge.
GPT_SOURCE_GTETRGD_RISING	Action performed on GTETRGB rising edge.
GPT_SOURCE_GTETRGD_FALLING	Action performed on GTETRGB falling edge.
GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW	Action performed when GTIOCA input rises while GTIOCB is low.
GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH	Action performed when GTIOCA input rises while GTIOCB is high.
GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW	Action performed when GTIOCA input falls while GTIOCB is low.
GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH	Action performed when GTIOCA input falls while GTIOCB is high.
GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_LOW	Action performed when GTIOCB input rises while GTIOCA is low.
GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_HIGH	Action performed when GTIOCB input rises while GTIOCA is high.
GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_LOW	Action performed when GTIOCB input falls while GTIOCA is low.
GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_HIGH	Action performed when GTIOCB input falls while GTIOCA is high.
GPT_SOURCE_GPT_A	Action performed on ELC GPTA event.
GPT_SOURCE_GPT_B	Action performed on ELC GPTB event.
GPT_SOURCE_GPT_C	Action performed on ELC GPTC event.
GPT_SOURCE_GPT_D	Action performed on ELC GPTD event.
GPT_SOURCE_GPT_E	Action performed on ELC GPTE event.
GPT_SOURCE_GPT_F	Action performed on ELC GPTF event.
GPT_SOURCE_GPT_G	Action performed on ELC GPTG event.
GPT_SOURCE_GPT_H	Action performed on ELC GPTH event.

◆ gpt_capture_filter_t

enum gpt_capture_filter_t

Input capture signal noise filter (debounce) setting. Only available for input signals GTIOCxA and GTIOCxB. The noise filter samples the external signal at intervals of the PCLK divided by one of the values. When 3 consecutive samples are at the same level (high or low), then that level is passed on as the observed state of the signal. See "Noise Filter Function" in the hardware manual, GPT section.

Enumerator
GPT_CAPTURE_FILTER_NONE	None - no filtering.
GPT_CAPTURE_FILTER_PCLKD_DIV_1	PCLK/1 - fast sampling.
GPT_CAPTURE_FILTER_PCLKD_DIV_4	PCLK/4.
GPT_CAPTURE_FILTER_PCLKD_DIV_16	PCLK/16.
GPT_CAPTURE_FILTER_PCLKD_DIV_64	PCLK/64 - slow sampling.

◆ gpt_adc_trigger_t

enum gpt_adc_trigger_t

Trigger options to start A/D conversion.

Enumerator
GPT_ADC_TRIGGER_NONE	None - no output disable request.
GPT_ADC_TRIGGER_UP_COUNT_START_ADC_A	Request A/D conversion from ADC unit 0 at up counting compare match of gpt_extended_pwm_cfg_t::adc_a_compare_match.
GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_A	Request A/D conversion from ADC unit 0 at down counting compare match of gpt_extended_pwm_cfg_t::adc_a_compare_match.
GPT_ADC_TRIGGER_UP_COUNT_START_ADC_B	Request A/D conversion from ADC unit 1 at up counting compare match of gpt_extended_pwm_cfg_t::adc_b_compare_match.
GPT_ADC_TRIGGER_DOWN_COUNT_START_ADC_B	Request A/D conversion from ADC unit 1 at down counting compare match of gpt_extended_pwm_cfg_t::adc_b_compare_match.

◆ gpt_poeg_link_t

enum gpt_poeg_link_t

POEG channel to link to this channel.

Enumerator
GPT_POEG_LINK_POEG0	Link this GPT channel to POEG channel 0 (GTETRGA)
GPT_POEG_LINK_POEG1	Link this GPT channel to POEG channel 1 (GTETRGB)
GPT_POEG_LINK_POEG2	Link this GPT channel to POEG channel 2 (GTETRGC)
GPT_POEG_LINK_POEG3	Link this GPT channel to POEG channel 3 (GTETRGD)

◆ gpt_output_disable_t

enum gpt_output_disable_t

Select trigger to send output disable request to POEG.

Enumerator
GPT_OUTPUT_DISABLE_NONE	None - no output disable request.
GPT_OUTPUT_DISABLE_DEAD_TIME_ERROR	Request output disable if a dead time error occurs.
GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_HIGH	Request output disable if GTIOCA and GTIOCB are high at the same time.
GPT_OUTPUT_DISABLE_GTIOCA_GTIOCB_LOW	Request output disable if GTIOCA and GTIOCB are low at the same time.

◆ gpt_gtioc_disable_t

enum gpt_gtioc_disable_t

Disable level options for GTIOC pins.

Enumerator
GPT_GTIOC_DISABLE_PROHIBITED	Do not allow output disable.
GPT_GTIOC_DISABLE_SET_HI_Z	Set GTIOC to high impedance when output is disabled.
GPT_GTIOC_DISABLE_LEVEL_LOW	Set GTIOC level low when output is disabled.
GPT_GTIOC_DISABLE_LEVEL_HIGH	Set GTIOC level high when output is disabled.

◆ gpt_adc_compare_match_t

enum gpt_adc_compare_match_t

Trigger options to start A/D conversion.

Enumerator
GPT_ADC_COMPARE_MATCH_ADC_A	Set A/D conversion start request value for GPT A/D converter start request A.
GPT_ADC_COMPARE_MATCH_ADC_B	Set A/D conversion start request value for GPT A/D converter start request B.

◆ gpt_interrupt_skip_source_t

enum gpt_interrupt_skip_source_t

Interrupt skipping modes

Enumerator
GPT_INTERRUPT_SKIP_SOURCE_NONE	Do not skip interrupts.
GPT_INTERRUPT_SKIP_SOURCE_OVERFLOW_UNDERFLOW	Count and skip overflow and underflow interrupts.
GPT_INTERRUPT_SKIP_SOURCE_CREST	Count crest interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in gpt_interrupt_skip_count_t. When the interrupt does fire, the trough interrupt fires before the crest interrupt.
GPT_INTERRUPT_SKIP_SOURCE_TROUGH	Count trough interrupts for interrupt skipping. Skip the number of crest and trough interrupts configured in gpt_interrupt_skip_count_t. When the interrupt does fire, the crest interrupt fires before the trough interrupt.

◆ gpt_interrupt_skip_count_t

enum gpt_interrupt_skip_count_t

Number of interrupts to skip between events

Enumerator
GPT_INTERRUPT_SKIP_COUNT_0	Do not skip interrupts.
GPT_INTERRUPT_SKIP_COUNT_1	Skip one interrupt.
GPT_INTERRUPT_SKIP_COUNT_2	Skip two interrupts.
GPT_INTERRUPT_SKIP_COUNT_3	Skip three interrupts.
GPT_INTERRUPT_SKIP_COUNT_4	Skip four interrupts.
GPT_INTERRUPT_SKIP_COUNT_5	Skip five interrupts.
GPT_INTERRUPT_SKIP_COUNT_6	Skip six interrupts.
GPT_INTERRUPT_SKIP_COUNT_7	Skip seven interrupts.

◆ gpt_interrupt_skip_adc_t

enum gpt_interrupt_skip_adc_t

ADC events to skip during interrupt skipping

Enumerator
GPT_INTERRUPT_SKIP_ADC_NONE	Do not skip ADC events.
GPT_INTERRUPT_SKIP_ADC_A	Skip ADC A events.
GPT_INTERRUPT_SKIP_ADC_B	Skip ADC B events.
GPT_INTERRUPT_SKIP_ADC_A_AND_B	Skip ADC A and B events.

◆ gpt_pwm_output_delay_setting_t

enum gpt_pwm_output_delay_setting_t

Delay setting for the PWM Delay Generation Circuit (PDG).

Enumerator
GPT_PWM_OUTPUT_DELAY_SETTING_0_32	Delay is not applied.
GPT_PWM_OUTPUT_DELAY_SETTING_1_32	Delay of 1 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_2_32	Delay of 2 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_3_32	Delay of 3 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_4_32	Delay of 4 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_5_32	Delay of 5 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_6_32	Delay of 6 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_7_32	Delay of 7 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_8_32	Delay of 8 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_9_32	Delay of 9 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_10_32	Delay of 10 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_11_32	Delay of 11 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_12_32	Delay of 12 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_13_32	Delay of 13 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_14_32	Delay of 14 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_15_32	Delay of 15 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_16_32	Delay of 16 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_17_32	Delay of 17 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_18_32	Delay of 18 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_19_32	Delay of 19 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_20_32	Delay of 20 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_21_32	Delay of 21 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_22_32	Delay of 22 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_23_32	Delay of 23 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_24_32	Delay of 24 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_25_32	Delay of 25 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_26_32	Delay of 26 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_27_32	Delay of 27 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_28_32	Delay of 28 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_29_32	Delay of 29 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_30_32	Delay of 30 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_31_32	Delay of 31 / 32 GTCLK period applied.
GPT_PWM_OUTPUT_DELAY_SETTING_BYPASS	Bypass the PWM Output Delay Circuit.

◆ gpt_pwm_output_delay_edge_t

enum gpt_pwm_output_delay_edge_t

Select which PWM Output Delay setting to apply.

Enumerator
GPT_PWM_OUTPUT_DELAY_EDGE_RISING	Configure the PWM Output Delay setting for rising edge.
GPT_PWM_OUTPUT_DELAY_EDGE_FALLING	Configure the PWM Output Delay setting for falling edge.

Function Documentation

◆ R_GPT_Open()

fsp_err_t R_GPT_Open	(	timer_ctrl_t *const	p_ctrl,
		timer_cfg_t const *const	p_cfg
	)

Initializes the timer module and applies configurations. Implements timer_api_t::open.

GPT hardware does not support one-shot functionality natively. When using one-shot mode, the timer will be stopped in an ISR after the requested period has elapsed.

The GPT implementation of the general timer can accept a gpt_extended_cfg_t extension parameter.

Example:

    /* Initializes the module. */
    err = R_GPT_Open(&g_timer0_ctrl, &g_timer0_cfg);

Return values

FSP_SUCCESS	Initialization was successful and timer has started.
FSP_ERR_ASSERTION	A required input pointer is NULL or the source divider is invalid.
FSP_ERR_ALREADY_OPEN	Module is already open.
FSP_ERR_IRQ_BSP_DISABLED	timer_cfg_t::mode is TIMER_MODE_ONE_SHOT or timer_cfg_t::p_callback is not NULL, but ISR is not enabled. ISR must be enabled to use one-shot mode or callback.
FSP_ERR_INVALID_MODE	Triangle wave PWM is only supported if GPT_CFG_OUTPUT_SUPPORT_ENABLE is 2. Selected channel does not support external count sources. External and event count sources not are available in this mode.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	The channel requested in the p_cfg parameter is not available on this device.

◆ R_GPT_Stop()

fsp_err_t R_GPT_Stop ( timer_ctrl_t *const p_ctrl )

Stops timer. Implements timer_api_t::stop.

Example:

    /* (Optional) Stop the timer. */
    (void) R_GPT_Stop(&g_timer0_ctrl);

Return values

FSP_SUCCESS	Timer successfully stopped.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

◆ R_GPT_Start()

fsp_err_t R_GPT_Start ( timer_ctrl_t *const p_ctrl )

Starts timer. Implements timer_api_t::start.

Example:

    /* Start the timer. */
    (void) R_GPT_Start(&g_timer0_ctrl);

Return values

FSP_SUCCESS	Timer successfully started.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

◆ R_GPT_Reset()

fsp_err_t R_GPT_Reset ( timer_ctrl_t *const p_ctrl )

Resets the counter value to 0. Implements timer_api_t::reset.

Note: This function also updates to the new period if no counter overflow has occurred since the last call to R_GPT_PeriodSet().

Return values

FSP_SUCCESS	Counter value written successfully.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

◆ R_GPT_Enable()

fsp_err_t R_GPT_Enable ( timer_ctrl_t *const p_ctrl )

Enables external event triggers that start, stop, clear, or capture the counter. Implements timer_api_t::enable.

Example:

    /* Enable captures. Captured values arrive in the interrupt. */
    (void) R_GPT_Enable(&g_timer0_ctrl);

Return values

FSP_SUCCESS	External events successfully enabled.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

◆ R_GPT_Disable()

fsp_err_t R_GPT_Disable ( timer_ctrl_t *const p_ctrl )

Disables external event triggers that start, stop, clear, or capture the counter. Implements timer_api_t::disable.

Note: The timer could be running after R_GPT_Disable(). To ensure it is stopped, call R_GPT_Stop().

Example:

    /* (Optional) Disable captures. */
    (void) R_GPT_Disable(&g_timer0_ctrl);

Return values

FSP_SUCCESS	External events successfully disabled.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

◆ R_GPT_PeriodSet()

fsp_err_t R_GPT_PeriodSet	(	timer_ctrl_t *const	p_ctrl,
		uint32_t const	period_counts
	)

Sets period value provided. If the timer is running, the period will be updated after the next counter overflow. If the timer is stopped, this function resets the counter and updates the period. Implements timer_api_t::periodSet.

Warning: If periodic output is used, the duty cycle buffer registers are updated after the period buffer register. If this function is called while the timer is running and a GPT overflow occurs during processing, the duty cycle will not be the desired 50% duty cycle until the counter overflow after processing completes.

Example:

    /* Get the source clock frequency (in Hz). There are 3 ways to do this in FSP:
     *  - If the PCLKD frequency has not changed since reset, the source clock frequency is
     *    BSP_STARTUP_PCLKD_HZ >> timer_cfg_t::source_div
     *  - Use the R_GPT_InfoGet function (it accounts for the divider).
     *  - Calculate the current PCLKD frequency using R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) and right shift
     *    by timer_cfg_t::source_div.
     *
     * This example uses the 3rd option (R_FSP_SystemClockHzGet).
     */
    uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) >> g_timer0_cfg.source_div;
    /* Calculate the desired period based on the current clock. Note that this calculation could overflow if the
     * desired period is larger than UINT32_MAX / pclkd_freq_hz. A cast to uint64_t is used to prevent this. */
    uint32_t period_counts =
        (uint32_t) (((uint64_t) pclkd_freq_hz * GPT_EXAMPLE_DESIRED_PERIOD_MSEC) / GPT_EXAMPLE_MSEC_PER_SEC);
    /* Set the calculated period. */
    err = R_GPT_PeriodSet(&g_timer0_ctrl, period_counts);
    assert(FSP_SUCCESS == err);

Return values

FSP_SUCCESS	Period value written successfully.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

◆ R_GPT_DutyCycleSet()

fsp_err_t R_GPT_DutyCycleSet	(	timer_ctrl_t *const	p_ctrl,
		uint32_t const	duty_cycle_counts,
		uint32_t const	pin
	)

Sets duty cycle on requested pin. Implements timer_api_t::dutyCycleSet.

Duty cycle is updated in the buffer register. The updated duty cycle is reflected after the next cycle end (counter overflow).

Example:

    /* Get the current period setting. */
    timer_info_t info;
    (void) R_GPT_InfoGet(&g_timer0_ctrl, &info);
    uint32_t current_period_counts = info.period_counts;
    /* Calculate the desired duty cycle based on the current period. Note that if the period could be larger than
     * UINT32_MAX / 100, this calculation could overflow. A cast to uint64_t is used to prevent this. The cast is
     * not required for 16-bit timers. */
    uint32_t duty_cycle_counts =
        (uint32_t) (((uint64_t) current_period_counts * GPT_EXAMPLE_DESIRED_DUTY_CYCLE_PERCENT) /
                    GPT_EXAMPLE_MAX_PERCENT);
    /* Set the calculated duty cycle. */
    err = R_GPT_DutyCycleSet(&g_timer0_ctrl, duty_cycle_counts, GPT_IO_PIN_GTIOCB);
    assert(FSP_SUCCESS == err);

Parameters

[in]	p_ctrl	Pointer to instance control block.
[in]	duty_cycle_counts	Duty cycle to set in counts.
[in]	pin	Use gpt_io_pin_t to select GPT_IO_PIN_GTIOCA or GPT_IO_PIN_GTIOCB

Return values

FSP_SUCCESS	Duty cycle updated successfully.
FSP_ERR_ASSERTION	p_ctrl was NULL or the pin is not one of gpt_io_pin_t
FSP_ERR_NOT_OPEN	The instance is not opened.
FSP_ERR_INVALID_ARGUMENT	Duty cycle is larger than period.
FSP_ERR_INVALID_MODE	GPT_IO_PIN_TROUGH, and GPT_IO_PIN_CREST settings are invalid in the this mode.
FSP_ERR_UNSUPPORTED	GPT_CFG_OUTPUT_SUPPORT_ENABLE is 0.

◆ R_GPT_CompareMatchSet()

fsp_err_t R_GPT_CompareMatchSet	(	timer_ctrl_t *const	p_ctrl,
		uint32_t const	compare_match_value,
		timer_compare_match_t const	match_channel
	)

Set value for compare match feature. Implements timer_api_t::compareMatchSet.

Note: This API should be used when timer is stop counting. And shall not be used along with PWM operation.

Example:

    /* Set the compare match value (GPT_COMPARE_MATCH_EXAMPLE_VALUE). This value must be less than or equal to period value. */
    err = R_GPT_CompareMatchSet(&g_timer0_ctrl, GPT_COMPARE_MATCH_EXAMPLE_VALUE, TIMER_COMPARE_MATCH_A);
    assert(FSP_SUCCESS == err);

Return values

FSP_SUCCESS	Set the compare match value successfully.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.
FSP_ERR_NOT_ENABLED	Requested compare channel is disabled.

◆ R_GPT_InfoGet()

fsp_err_t R_GPT_InfoGet	(	timer_ctrl_t *const	p_ctrl,
		timer_info_t *const	p_info
	)

Get timer information and store it in provided pointer p_info. Implements timer_api_t::infoGet.

Example:

        /* (Optional) Get the current period if not known. */
        timer_info_t info;
        (void) R_GPT_InfoGet(&g_timer0_ctrl, &info);
        uint64_t period = info.period_counts;
        /* The maximum period is one more than the maximum 32-bit number, but will be reflected as 0 in
         * timer_info_t::period_counts. */
        if (0U == period)
        {
            period = UINT32_MAX + 1U;
        }

Return values

FSP_SUCCESS	Period, count direction, frequency, and ELC event written to caller's structure successfully.
FSP_ERR_ASSERTION	p_ctrl or p_info was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

◆ R_GPT_StatusGet()

fsp_err_t R_GPT_StatusGet	(	timer_ctrl_t *const	p_ctrl,
		timer_status_t *const	p_status
	)

Get current timer status and store it in provided pointer p_status. Implements timer_api_t::statusGet.

Example:

    /* Read the current counter value. Counter value is in status.counter. */
    timer_status_t status;
    (void) R_GPT_StatusGet(&g_timer0_ctrl, &status);

Return values

FSP_SUCCESS	Current timer state and counter value set successfully.
FSP_ERR_ASSERTION	p_ctrl or p_status was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

◆ R_GPT_CounterSet()

fsp_err_t R_GPT_CounterSet	(	timer_ctrl_t *const	p_ctrl,
		uint32_t	counter
	)

Set counter value.

Note: Do not call this API while the counter is counting. The counter value can only be updated while the counter is stopped.

Return values

FSP_SUCCESS	Counter value updated.
FSP_ERR_ASSERTION	p_ctrl or p_status was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.
FSP_ERR_IN_USE	The timer is running. Stop the timer before calling this function.

◆ R_GPT_OutputEnable()

fsp_err_t R_GPT_OutputEnable	(	timer_ctrl_t *const	p_ctrl,
		gpt_io_pin_t	pin
	)

Enable output for GTIOCA and/or GTIOCB.

Return values

FSP_SUCCESS	Output is enabled.
FSP_ERR_ASSERTION	p_ctrl or p_status was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

◆ R_GPT_OutputDisable()

fsp_err_t R_GPT_OutputDisable	(	timer_ctrl_t *const	p_ctrl,
		gpt_io_pin_t	pin
	)

Disable output for GTIOCA and/or GTIOCB.

Return values

FSP_SUCCESS	Output is disabled.
FSP_ERR_ASSERTION	p_ctrl or p_status was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

◆ R_GPT_AdcTriggerSet()

fsp_err_t R_GPT_AdcTriggerSet	(	timer_ctrl_t *const	p_ctrl,
		gpt_adc_compare_match_t	which_compare_match,
		uint32_t	compare_match_value
	)

Set A/D converter start request compare match value.

Return values

FSP_SUCCESS	Counter value updated.
FSP_ERR_ASSERTION	p_ctrl or p_status was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

◆ R_GPT_PwmOutputDelaySet()

fsp_err_t R_GPT_PwmOutputDelaySet	(	timer_ctrl_t *const	p_ctrl,
		gpt_pwm_output_delay_edge_t	edge,
		gpt_pwm_output_delay_setting_t	delay_setting,
		uint32_t const	pin
	)

Set the Output Delay setting for the PWM output pin.

Return values

FSP_SUCCESS	The output delay was set.
FSP_ERR_ASSERTION	An input parameter was invalid.
FSP_ERR_NOT_OPEN	The instance is not opened.
FSP_ERR_INVALID_CHANNEL	The channel does not support this feature.
FSP_ERR_NOT_INITIALIZED	The PWM Output Delay Circuit has not been initialized.
FSP_ERR_INVALID_STATE	The PWM Output Delay setting cannot be updated in the current state.
FSP_ERR_UNSUPPORTED	This feature is not supported on this MCU.

◆ R_GPT_CallbackSet()

fsp_err_t R_GPT_CallbackSet	(	timer_ctrl_t *const	p_api_ctrl,
		void()(timer_callback_args_t )	p_callback,
		void const *const	p_context,
		timer_callback_args_t *const	p_callback_memory
	)

Updates the user callback with the option to provide memory for the callback argument structure. Implements timer_api_t::callbackSet.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_NO_CALLBACK_MEMORY	p_callback is non-secure and p_callback_memory is either secure or NULL.

◆ R_GPT_Close()

fsp_err_t R_GPT_Close ( timer_ctrl_t *const p_ctrl )

Stops counter, disables output pins, and clears internal driver data. Implements timer_api_t::close.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

◆ R_GPT_PwmOutputDelayInitialize()

fsp_err_t R_GPT_PwmOutputDelayInitialize ( )

Initialize the PWM Delay Generation Circuit (PDG). This function must be called before calling R_GPT_PwmOutputDelaySet.

Note: This function will delay for 20 microseconds.

Return values

FSP_SUCCESS	Initialization sequence completed successfully.
FSP_ERR_INVALID_STATE	The source clock frequnecy is out of the required range for the PDG.
FSP_ERR_UNSUPPORTED	This feature is not supported.

Functions

Detailed Description

Overview

Features

Selecting a Timer

Configuration

Build Time Configurations for r_gpt

Configurations for Timers > Timer, General PWM (r_gpt)

Clock Configuration

Pin Configuration

Usage Notes

Maximum Period

Updating Period and Duty Cycle

One-Shot Mode

One-Shot Mode Output

One-Shot Pulse Mode

One-Shot Pulse Mode Output

Periodic Output

PWM Output

Triangle-Wave PWM Output

PWM Output Delay Circuit

Event Counting

Pulse Measurement

Controlling GPT with GTETRG Edges

Controlling GPT with ELC Events

Triggering ELC Events with GPT

Enabling External Sources for Start, Stop, Clear, or Capture

Interrupt Skipping

Complementary Output

Examples

GPT Basic Example

GPT Callback Example

GPT Free Running Counter Example

GPT Input Capture Example

GPT Period Update Example

GPT Duty Cycle Update Example

GPT A/D Converter Start Request Example

GPT One-Shot Pulse Mode Example

GPT Compare Match Set Example

Data Structures

Enumerations

Data Structure Documentation

◆ gpt_output_pin_t

◆ gpt_gtior_setting_t

◆ gpt_instance_ctrl_t

◆ gpt_extended_pwm_cfg_t

◆ gpt_extended_cfg_t

Enumeration Type Documentation

◆ gpt_io_pin_t

◆ gpt_buffer_force_push

◆ gpt_pin_level_t

◆ gpt_source_t

◆ gpt_capture_filter_t

◆ gpt_adc_trigger_t

◆ gpt_poeg_link_t

◆ gpt_output_disable_t

◆ gpt_gtioc_disable_t

◆ gpt_adc_compare_match_t

◆ gpt_interrupt_skip_source_t

◆ gpt_interrupt_skip_count_t

◆ gpt_interrupt_skip_adc_t

◆ gpt_pwm_output_delay_setting_t

◆ gpt_pwm_output_delay_edge_t

Function Documentation

◆ R_GPT_Open()

◆ R_GPT_Stop()

◆ R_GPT_Start()

◆ R_GPT_Reset()

◆ R_GPT_Enable()

◆ R_GPT_Disable()

◆ R_GPT_PeriodSet()

◆ R_GPT_DutyCycleSet()

◆ R_GPT_CompareMatchSet()

◆ R_GPT_InfoGet()

◆ R_GPT_StatusGet()

◆ R_GPT_CounterSet()

◆ R_GPT_OutputEnable()

◆ R_GPT_OutputDisable()

◆ R_GPT_AdcTriggerSet()

◆ R_GPT_PwmOutputDelaySet()