Functions
fsp_err_t	R_SCI_SPI_Open (spi_ctrl_t p_api_ctrl, spi_cfg_t const const p_cfg)

fsp_err_t	R_SCI_SPI_Read (spi_ctrl_t const p_api_ctrl, void p_dest, uint32_t const length, spi_bit_width_t const bit_width)

fsp_err_t	R_SCI_SPI_Write (spi_ctrl_t const p_api_ctrl, void const p_src, uint32_t const length, spi_bit_width_t const bit_width)

fsp_err_t	R_SCI_SPI_WriteRead (spi_ctrl_t const p_api_ctrl, void const p_src, void *p_dest, uint32_t const length, spi_bit_width_t const bit_width)

fsp_err_t	R_SCI_SPI_CallbackSet (spi_ctrl_t const p_api_ctrl, void(p_callback)(spi_callback_args_t ), void const const p_context, spi_callback_args_t *const p_callback_memory)

fsp_err_t	R_SCI_SPI_Close (spi_ctrl_t *const p_api_ctrl)

fsp_err_t	R_SCI_SPI_CalculateBitrate (uint32_t bitrate, sci_spi_div_setting_t *sclk_div, bool use_mddr)

Detailed Description

Driver for the SCI peripheral on RA MCUs. This module implements the SPI Interface.

Overview

Features

Standard SPI Modes
- Master or Slave Mode
- Clock Polarity (CPOL)
  - CPOL=0 SCLK is low when idle
  - CPOL=1 SCLK is high when idle
- Clock Phase (CPHA)
  - CPHA=0 Select data sampling on leading edge, data change on trailing edge
  - CPHA=1 Select data change on leading edge, data sampling on trailing edge
- MSB/LSB first
Configurable bit rate
DTC Support
Callback Events
- Transfer Complete
- RX Overflow Error (The SCI shift register is copied to the data register before previous data was read)

Configuration

Build Time Configurations for r_sci_spi

The following build time configurations are defined in fsp_cfg/r_sci_spi_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
DTC Support	Enabled Disabled	Enabled	If support for transfering data using the DTC will be compiled in.

Configurations for Connectivity > SPI (r_sci_spi)

This module can be added to the Stacks tab via New Stack > Connectivity > SPI (r_sci_spi). Non-secure callable guard functions can be generated for this module by right clicking the module in the RA Configuration tool and checking the "Non-secure Callable" box.

Configuration	Options	Default	Description
Name	Name must be a valid C symbol	g_spi0	Module name.
Channel	Value must be a non-negative integer	0	Select the SCI channel.
Operating Mode	Master Slave	Master	Select the SPI operating mode.
Clock Phase	Data sampling on odd edge, data variation on even edge Data sampling on even edge, data variation on odd edge	Data sampling on odd edge, data variation on even edge	Select the clock edge to sample data.
Clock Polarity	Low when idle High when idle	Low when idle	Select clock level when idle.
Mode Fault Error	Enable Disable	Disable	Detect master/slave mode conflicts.
Bit Order	MSB First LSB First	MSB First	Select the data bit order.
Callback	Name must be a valid C symbol	sci_spi_callback	A user callback function that is called from the sci spi interrupts when a transfer is completed or an error has occurred.
Receive Interrupt Priority	MCU Specific Options		Select the receive interrupt priority.
Transmit Interrupt Priority	MCU Specific Options		Select the transmit interrupt priority.
Transmit End Interrupt Priority	MCU Specific Options		Select the transmit end interrupt priority.
Error Interrupt Priority	MCU Specific Options		Select the error interrupt priority.
Bitrate	Value must be an integer greater than 0	8000000	Enter the desired bitrate. If the requested bitrate cannot be achieved, the settings with the largest possible value that is less than or equal to the requested bitrate is used. The theoretical bitrate is printed in a comment in the generated sci_spi_extended_cfg_t structure.
Bitrate Modulation	Disabled Enabled	Disabled	Enabling bitrate modulation reduces the percent error of the actual bitrate with respect to the requested baud rate. It does this by modulating the number of cycles per clock output pulse, so the clock is no longer a square wave.

Clock Configuration

The clock for this module is derived from the following peripheral clock for each MCU group:

MCU Group	Peripheral Clock
RA2A1	PCLKB
RA2A2	PCLKB
RA2E1	PCLKB
RA2E2	PCLKB
RA2E3	PCLKB
RA2L1	PCLKB
RA4E1	PCLKA
RA4E2	PCLKA
RA4M1	PCLKA
RA4M2	PCLKA
RA4M3	PCLKA
RA4T1	PCLKA
RA4W1	PCLKA
RA6E1	PCLKA
RA6E2	PCLKA
RA6M1	PCLKA
RA6M2	PCLKA
RA6M3	PCLKA
RA6M4	PCLKA
RA6M5	PCLKA
RA6T1	PCLKA
RA6T3	PCLKA

Pin Configuration

This module uses SCIn_MOSI, SCIn_MISO, SCIn_SPCK, and SCIn_SS pins to communicate with on board devices.

Note: At high bit rates, it might be necessary to configure the pins with IOPORT_CFG_DRIVE_HIGH.

Usage Notes

Transfer Complete Event

The transfer complete event is triggered when all of the data has been transfered. In slave mode if the SS pin is de-asserted then no transfer complete event is generated until the SS pin is asserted and the remaining data is transferred.

Performance

At high bit rates, interrupts may not be able to service transfers fast enough. In master mode this means there will be a delay between each data frame. In slave mode this could result in RX Overflow errors. In order to improve performance at high bit rates, it is recommended that the instance be configured to service transfers using the DTC.

Also note when using DTC for data transfer, SCI SPI can experience overrun error if the application makes heavy use of DMAC and/or another DTC instance. This is because DMAC has a higher priority over DTC in arbitration for the mastership of the DMA bus, and the arbitration between different triggers/transfers in DTC is done based on interrupt/trigger priority. Overrun error can be averted with one of the following options:

If SCI SPI uses DTC for data transfer, avoid the use of DMAC or another DTC instance in an application.
If DMAC/DTC is a must for other data transfers, avoid the use of DTC with SCI SPI.
Use the RSPI instead of SCI SPI. The RSPI hardware can handle overrun conditions.

Transmit From RXI Interrupt

After every byte, the SCI SPI peripheral generates a transmit buffer empty interrupt and a receive buffer full interrupt. Whenever possible, the SCI_SPI module handles both interrupts in the receive buffer full interrupt. This improves performance when the DTC is not being used.

Slave Select Pin

In master mode the slave select pin must be driven in software.
In slave mode the hardware handles the slave select pin and will only transfer data when the SS pin is low.

Bit Rate Modulation

Depending on the peripheral clock frequency, the desired bit rate may not be achievable. With bit rate modulation, the device can remove a configurable number of input clock pulses to the internal bit rate counter in order to create the desired bit rate. This has the effect of changing the period of individual bits in order to achieve the desired average bit rate. For more information see section 34.9 Bit Rate Modulation Function in the RA6M3 manual.

Examples

Basic Example

This is a basic example of minimal use of the SCI_SPI in an application.

static volatile bool g_transfer_complete = false;
static void r_sci_spi_callback (spi_callback_args_t * p_args)
{
    if (SPI_EVENT_TRANSFER_COMPLETE == p_args->event)
    {
        g_transfer_complete = true;
    }
}
void sci_spi_basic_example (void)
{
    uint8_t tx_buffer[TRANSFER_SIZE];
    uint8_t rx_buffer[TRANSFER_SIZE];
    /* Configure Slave Select Line 1 */
    R_BSP_PinWrite(SLAVE_SELECT_LINE_1, BSP_IO_LEVEL_HIGH);
    /* Configure Slave Select Line 2 */
    R_BSP_PinWrite(SLAVE_SELECT_LINE_2, BSP_IO_LEVEL_HIGH);
    fsp_err_t err = FSP_SUCCESS;
    /* Initialize the SPI module. */
    err = R_SCI_SPI_Open(&g_spi_ctrl, &g_spi_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
    /* Assert Slave Select Line 1 */
    R_BSP_PinWrite(SLAVE_SELECT_LINE_1, BSP_IO_LEVEL_LOW);
    /* Start a write/read transfer */
    g_transfer_complete = false;
    err = R_SCI_SPI_WriteRead(&g_spi_ctrl, tx_buffer, rx_buffer, TRANSFER_SIZE, SPI_BIT_WIDTH_8_BITS);
    assert(FSP_SUCCESS == err);
    /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
    while (false == g_transfer_complete)
    {
        ;
    }
    /* De-assert Slave Select Line 1 */
    R_BSP_PinWrite(SLAVE_SELECT_LINE_1, BSP_IO_LEVEL_HIGH);
    /* Wait for minimum time required between transfers. */
    R_BSP_SoftwareDelay(SSL_NEXT_ACCESS_DELAY, BSP_DELAY_UNITS_MICROSECONDS);
    /* Assert Slave Select Line 2 */
    R_BSP_PinWrite(SLAVE_SELECT_LINE_2, BSP_IO_LEVEL_LOW);
    /* Start a write/read transfer */
    g_transfer_complete = false;
    err = R_SCI_SPI_WriteRead(&g_spi_ctrl, tx_buffer, rx_buffer, TRANSFER_SIZE, SPI_BIT_WIDTH_8_BITS);
    assert(FSP_SUCCESS == err);
    /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
    while (false == g_transfer_complete)
    {
        ;
    }
    /* De-assert Slave Select Line 2 */
    R_BSP_PinWrite(SLAVE_SELECT_LINE_2, BSP_IO_LEVEL_HIGH);
}

Data Structures
struct	sci_spi_div_setting_t

Data Structure Documentation

◆ sci_spi_div_setting_t

struct sci_spi_div_setting_t

Settings for adjusting the SPI CLK.

Data Fields
uint8_t	brr
uint8_t	cks: 2
uint8_t	mddr	Set to 0 to disable MDDR.

Function Documentation

◆ R_SCI_SPI_Open()

fsp_err_t R_SCI_SPI_Open	(	spi_ctrl_t *	p_api_ctrl,
		spi_cfg_t const *const	p_cfg
	)

Initialize a channel for SPI communication mode. Implements spi_api_t::open.

This function performs the following tasks:

Performs parameter checking and processes error conditions.
Enables the clock for the SCI channel.
Initializes the associated registers with default value and the user-configurable options.
Provides the channel handle for use with other API functions.

Parameters

p_api_ctrl	Pointer to the control structure.
p_cfg	Pointer to a configuration structure.

Return values

FSP_SUCCESS	Channel initialized successfully.
FSP_ERR_ASSERTION	An input parameter is invalid or NULL.
FSP_ERR_ALREADY_OPEN	The instance has already been opened.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	The channel number is invalid.

◆ R_SCI_SPI_Read()

fsp_err_t R_SCI_SPI_Read	(	spi_ctrl_t *const	p_api_ctrl,
		void *	p_dest,
		uint32_t const	length,
		spi_bit_width_t const	bit_width
	)

Receive data from an SPI device. Implements spi_api_t::read.

The function performs the following tasks:

Performs parameter checking and processes error conditions.
Enable transmitter.
Enable receiver.
Enable interrupts.
Start data transmission by writing data to the TXD register.
Receive data from receive buffer full interrupt occurs and copy data to the buffer of destination.
Complete data reception via receive buffer full interrupt and transmitting dummy data.
Disable transmitter.
Disable receiver.
Disable interrupts.

Parameters

	p_api_ctrl	Pointer to the control structure.
	p_dest	Pointer to the destination buffer.
[in]	length	The number of bytes to transfer.
[in]	bit_width	Invalid for SCI_SPI (Set to SPI_BIT_WIDTH_8_BITS).

Return values

FSP_SUCCESS	Read operation successfully completed.
FSP_ERR_ASSERTION	One of the following invalid parameters passed: Pointer p_api_ctrl is NULL Bit width is not 8 bits Length is equal to 0 Pointer to destination is NULL
FSP_ERR_NOT_OPEN	The channel has not been opened. Open the channel first.
FSP_ERR_UNSUPPORTED	The given bit_width is not supported.
FSP_ERR_IN_USE	A transfer is already in progress.

Returns

See Common Error Codes or functions called by this function for other possible return codes. This function calls:

transfer_api_t::reconfigure

◆ R_SCI_SPI_Write()

fsp_err_t R_SCI_SPI_Write	(	spi_ctrl_t *const	p_api_ctrl,
		void const *	p_src,
		uint32_t const	length,
		spi_bit_width_t const	bit_width
	)

Transmit data to a SPI device. Implements spi_api_t::write.

The function performs the following tasks:

Performs parameter checking and processes error conditions.
Enable transmitter.
Enable interrupts.
Start data transmission with data via transmit buffer empty interrupt.
Copy data from source buffer to the SPI data register for transmission.
Complete data transmission via transmit buffer empty interrupt.
Disable transmitter.
Disable receiver.
Disable interrupts.

Parameters

	p_api_ctrl	Pointer to the control structure.
	p_src	Pointer to the source buffer.
[in]	length	The number of bytes to transfer.
[in]	bit_width	Invalid for SCI_SPI (Set to SPI_BIT_WIDTH_8_BITS).

Return values

FSP_SUCCESS	Write operation successfully completed.
FSP_ERR_ASSERTION	One of the following invalid parameters passed: Pointer p_api_ctrl is NULL Pointer to source is NULL Length is equal to 0 Bit width is not equal to 8 bits
FSP_ERR_NOT_OPEN	The channel has not been opened. Open the channel first.
FSP_ERR_UNSUPPORTED	The given bit_width is not supported.
FSP_ERR_IN_USE	A transfer is already in progress.

Returns

See Common Error Codes or functions called by this function for other possible return codes. This function calls:

transfer_api_t::reconfigure

◆ R_SCI_SPI_WriteRead()

fsp_err_t R_SCI_SPI_WriteRead	(	spi_ctrl_t *const	p_api_ctrl,
		void const *	p_src,
		void *	p_dest,
		uint32_t const	length,
		spi_bit_width_t const	bit_width
	)

Simultaneously transmit data to SPI device while receiving data from SPI device (full duplex). Implements spi_api_t::writeRead.

The function performs the following tasks:

Performs parameter checking and processes error conditions.
Enable transmitter.
Enable receiver.
Enable interrupts.
Start data transmission using transmit buffer empty interrupt (or by writing to the TDR register).
Copy data from source buffer to the SPI data register for transmission.
Receive data from receive buffer full interrupt and copy data to the destination buffer.
Complete data transmission and reception via transmit end interrupt.
Disable transmitter.
Disable receiver.
Disable interrupts.

Parameters

	p_api_ctrl	Pointer to the control structure.
	p_src	Pointer to the source buffer.
	p_dest	Pointer to the destination buffer.
[in]	length	The number of bytes to transfer.
[in]	bit_width	Invalid for SCI_SPI (Set to SPI_BIT_WIDTH_8_BITS).

Return values

FSP_SUCCESS	Write operation successfully completed.
FSP_ERR_ASSERTION	One of the following invalid parameters passed: Pointer p_api_ctrl is NULL Pointer to source is NULL Pointer to destination is NULL Length is equal to 0 Bit width is not equal to 8 bits
FSP_ERR_NOT_OPEN	The channel has not been opened. Open the channel first.
FSP_ERR_UNSUPPORTED	The given bit_width is not supported.
FSP_ERR_IN_USE	A transfer is already in progress.

Returns

See Common Error Codes or functions called by this function for other possible return codes. This function calls:

transfer_api_t::reconfigure

◆ R_SCI_SPI_CallbackSet()

fsp_err_t R_SCI_SPI_CallbackSet	(	spi_ctrl_t *const	p_api_ctrl,
		void()(spi_callback_args_t )	p_callback,
		void const *const	p_context,
		spi_callback_args_t *const	p_callback_memory
	)

Updates the user callback and has option of providing memory for callback structure. Implements spi_api_t::callbackSet

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_NO_CALLBACK_MEMORY	p_callback is non-secure and p_callback_memory is either secure or NULL.

◆ R_SCI_SPI_Close()

fsp_err_t R_SCI_SPI_Close ( spi_ctrl_t *const p_api_ctrl )

Disable the SCI channel and set the instance as not open. Implements spi_api_t::close.

Parameters

p_api_ctrl Pointer to an opened instance.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	The parameter p_api_ctrl is NULL.
FSP_ERR_NOT_OPEN	The channel has not been opened. Open the channel first.

◆ R_SCI_SPI_CalculateBitrate()

fsp_err_t R_SCI_SPI_CalculateBitrate	(	uint32_t	bitrate,
		sci_spi_div_setting_t *	sclk_div,
		bool	use_mddr
	)

Calculate the register settings required to achieve the desired bitrate.

Parameters

[in]	bitrate	bitrate [bps]. For example, 250,000; 500,00; 2,500,000 (max), etc.
	sclk_div	Pointer to sci_spi_div_setting_t used to configure baudrate settings.
[in]	use_mddr	Calculate the divider settings for use with MDDR.

Return values

FSP_SUCCESS	Baud rate is set successfully.
FSP_ERR_ASSERTION	Baud rate is not achievable.

Note: The application must pause for 1 bit time after the BRR register is loaded before transmitting/receiving to allow time for the clock to settle.

Functions

Detailed Description

Overview

Features

Configuration

Build Time Configurations for r_sci_spi

Configurations for Connectivity > SPI (r_sci_spi)

Clock Configuration

Pin Configuration

Usage Notes

Transfer Complete Event

Performance

Transmit From RXI Interrupt

Slave Select Pin

Bit Rate Modulation

Examples

Basic Example

Data Structures

Data Structure Documentation

◆ sci_spi_div_setting_t

Function Documentation

◆ R_SCI_SPI_Open()

◆ R_SCI_SPI_Read()

◆ R_SCI_SPI_Write()

◆ R_SCI_SPI_WriteRead()

◆ R_SCI_SPI_CallbackSet()

◆ R_SCI_SPI_Close()

◆ R_SCI_SPI_CalculateBitrate()