MCU Board Support Package

Functions
fsp_err_t	R_FSP_VersionGet (fsp_pack_version_t *const p_version)
void	Reset_Handler (void)
void	Default_Handler (void)
BSP_WEAK_REFERENCE void	R_BSP_WarmStart (bsp_warm_start_event_t event) __attribute__((noinline))
void	SystemInit (void)
void	R_BSP_CacheEnable (void)
	Enable caches. More...
void	R_BSP_CacheDisable (void)
	Disable caches. More...
void	R_BSP_CacheClean (void)
	Clean caches. More...
void	R_BSP_CacheInvalidate (void)
	Flush caches. More...
void	R_BSP_CacheCleanInvalidate (void)
	Clean and flush caches. More...
__STATIC_INLINE void	bsp_cache_operate_all (uint8_t operate)
__STATIC_INLINE void	R_BSP_CacheEnableData (void)
__STATIC_INLINE void	R_BSP_CacheDisableData (void)
__STATIC_INLINE void	R_BSP_CacheCleanAllData (void)
__STATIC_INLINE void	R_BSP_CacheInvalidateAllData (void)
__STATIC_INLINE void	R_BSP_CacheCleanInvalidateAllData (void)
uint32_t	R_BSP_SourceClockHzGet (fsp_priv_source_clock_t clock)
__STATIC_INLINE IRQn_Type	R_FSP_CurrentIrqGet (void)
__STATIC_INLINE uint32_t	R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
__STATIC_INLINE uint32_t	R_FSP_ClockDividerGet (uint32_t ckdivcr)
__STATIC_INLINE bsp_unique_id_t const *	R_BSP_UniqueIdGet (void)
__STATIC_INLINE fsp_err_t	R_BSP_PartNumberGet (bsp_part_number_t *const p_part_number)
void	R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units)
fsp_err_t	R_BSP_GroupIrqWrite (bsp_grp_irq_nmi_t irq, void(*p_callback)(bsp_grp_irq_nmi_t irq))
void	bsp_nmi_handler (void)
bool	R_BSP_GroupIrqCheck (uint8_t irq)
uint32_t	R_BSP_GetCurrentIFlagState (void)
	Provides the current I flag state on PSW register. More...
void	R_BSP_SetIFlagState (uint32_t interrupt_mask)
	Set I flag state on PSW register. If this flag is 0, all interrupts are disabled. More...
uint32_t	R_BSP_GetCurrentIpl (void)
	Get current interrupt priority level from PSW register. More...
void	R_BSP_SetIpl (uint32_t interrupt_mask_level)
	Set IPL state on PSW register. If the passed interrupt priority level (IPL) is maximum, all interrupts are disabled. If the passed IPL is less than the maximum, interrupts which IPL is above the set value will be processed. More...
uint32_t	R_BSP_IrqIsEnabled (IRQn_Type const irq)
void	R_BSP_IrqStatusClear (IRQn_Type irq)
void	R_BSP_IrqClearPending (IRQn_Type irq)
void	R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void *p_context)
void	R_BSP_IrqEnableNoClear (IRQn_Type const irq)
void	R_BSP_IrqEnable (IRQn_Type const irq)
void	R_BSP_IrqDisable (IRQn_Type const irq)
void	R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void *p_context)
void	R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect)
void	R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect)

Detailed Description

The BSP is responsible for getting the MCU from reset to the user's application. Before reaching the user's application, the BSP sets up the stacks, heap, clocks, interrupts, C runtime environment, and stack monitor.

• BSP Features
• BSP Clock Configuration
• System Interrupts
• Group Interrupts
• External and Peripheral Interrupts
• Error Logging
• BSP Weak Symbols
• Warm Start Callbacks
• Sub Clock Stabilization Wait Callback
• SDRAM Initialization
• C Runtime Initialization
• Register Protection
• Software Delay
• Endian
• Limited D-Cache and I-Cache Support
• Cacheable Buffer Placement Example
• Non-Cacheable Buffer Placement Example
• Configuration
• Limitation

Overview

BSP Features

BSP Clock Configuration

All system clocks are set up during BSP initialization based on the settings in bsp_clock_cfg.h. These settings are derived from clock configuration information provided from the FSP Configuration editor Clocks tab.

• Clock configuration is performed prior to initializing the C runtime environment to speed up the startup process, as it is possible to start up on a relatively slow (that is, 32 kHz) clock.
• The BSP implements the required delays to allow the selected clock to stabilize.
• The BSP will configure the CMSIS SystemCoreClock variable after clock initialization with the current system clock frequency.

System Interrupts

As RX MCUs are based on the RXv3 architecture, the Interrupt Controller Unit (ICU) handles exceptions and interrupt configuration, prioritization and interrupt masking using the interrupt vector table (INTB) in CPU. In the exception vector table, the individual vectors are allocated to in a 124-byte area where the value indicated by the exception table register (EXTB) is used as the starting address (ExtBase). The reset vector is always allocated to FFFFFFFCh, regardless of the value of the exception vector table. The exceptions except nomal non-maskable interrupt are shown below:

• Undefined instruction exception
• Privileged instruction exception
• Access exception
• Secure exception
• Address exception
• Single-precision floating-point exception
• Reset
• Non-maskable interrupt
• Interrupt
• Unconditional trap

Group Interrupts

Group interrupt is the term used to describe the 13 sources that can trigger the Non-Maskable Interrupt (NMI). When an NMI occurs the NMI Handler examines the NMISR (status register) to determine the source of the interrupt. NMI interrupts take precedence over all interrupts, are usable only as CPU interrupts, and cannot activate the RX peripherals Data Transfer Controller (DTC) or Direct Memory Access Controller (DMAC).

Possible group interrupt sources include:

• IWDT Underflow/Refresh Error
• WDT Underflow/Refresh Error
• Voltage-Monitoring 1 Interrupt
• Voltage-Monitoring 2 Interrupt
• Main Oscillation Stop Detection
• NMI pin Interrupt
• Common Memory Error Interrupt
• Bus Error Interrupt
• Sub Oscillation Stop Detection
• Local Memory Error Interrupt
• Double-precision Floating-point Exception
• Code MRAM Read Error Interrupt
• Extra MRAM Read Error Interrupt

A user may enable notification for one or NMI interrupts by registering a callback using the BSP API function R_BSP_GroupIrqWrite(). When an NMI interrupt occurs, the NMI handler checks to see if there is a callback registered for the cause of the interrupt and if so calls the registered callback function.

External and Peripheral Interrupts

Maskable interrupts are Peripheral interrupts, Software interrupts, Group interrupts, External pin interrupts. User unconfigurable interrupts (software interrupts, group interrupts, external interrupts, peripheral-generated interrupts) are assigned to vector numbers 0 to 127, and user configurable interrupts (software configurable interrupts) are assigned to vector numbers 128 to 255.

By allowing the user to select only the software configurable interrupts they are interested in as interrupt sources, we are able to provide an interrupt service routine that is fast and software configurable interrupt specific.

For example, on other microcontrollers an interrupt vector table might contain a single vector entry for the SCI0 (Serial Communications Interface) peripheral. The interrupt service routine for this would have to check a status register for the 'real' source of the interrupt. In the RX implementation there is a vector entry for each of the SCI0 events that we are interested in.

Nested interrupts are explicitly enabled by setting the PSW.I bit when entering a maskable interrupt handler.

Note: RX MCUs disable nested interrupts by default. RX FSP enables nested interrupts in software.`

BSP Weak Symbols

You might wonder how the BSP is able to place ISR addresses in the interrupt table without the user having explicitly defined one. All that is required by the BSP is that the interrupt event be given a priority.

This is accomplished through the use of the 'weak' attribute. The weak attribute causes the declaration to be emitted as a weak symbol rather than a global. A weak symbol is one that can be overridden by an accompanying strong reference with the same name. When the BSP declares a function as weak, user code can define the same function and it will be used in place of the BSP function. By defining all possible interrupt sources as weak, the vector table can be built at compile time and any user declarations (strong references) will be used at runtime.

Weak symbols are supported for ELF targets and also for a.out targets when using the GNU assembler and linker.

Note that in CMSIS system.c, there is also a weak definition (and a function body) for the Warm Start callback function R_BSP_WarmStart(). Because this function is defined in the same file as the weak declaration, it will be called as the 'default' implementation. The function may be overridden by the user by copying the body into their user application and modifying it as necessary. The linker identifies this as the 'strong' reference and uses it.

Warm Start Callbacks

As the BSP is in the process of bringing up the board out of reset, there are three points where the user can request a callback. These are defined as the 'Pre Clock Init', 'Post Clock Init' and 'Post C' warm start callbacks.

As described above, this function is already weakly defined as R_BSP_WarmStart(), so it is a simple matter of redefining the function or copying the existing body from CMSIS system.c into the application code to get a callback. R_BSP_WarmStart() takes an event parameter of type bsp_warm_start_event_t which describes the type of warm start callback being made.

This function is not enabled/disabled and is always called for both events as part of the BSP startup. Therefore it needs a function body, which will not be called if the user is overriding it. The function body is located in system.c. To use this function just copy this function into your own code and modify it to meet your needs.

Sub Clock Stabilization Wait Callback

When Sub-Clock oscillator is populated in the application, the BSP startup code waits for some time(sub-clock stabilization time) to allow Sub-clock to stabilize. Enabling the watchdog (IWDT or WDT) timer with Auto start mode in an application using Sub-clock may cause system to generate Reset or NMI interrupt before reaching the application code if watchdog refresh register is not updated in the configured refresh Window. To overcome this problem a weakly defined callback R_BSP_SubClockStabilizeWait() can be overridden. Redefine the callback function in the application code and add code to update the watchdog refresh register. R_BSP_SubClockStabilizeWait() takes a parameter delay of type uint32_t which describes the time in milliseconds required to stabilize the sub-clock.

Sub Clock Stabilization Wait After Reset callback

After Power-On-Reset, the BSP startup code may have to wait for some time(sub-clock stabilization time) to allow Sub-clock to stabilize. This can cause problem to RTC in case device is to be reset frequently. If Sub-Clock registers are not initialized during a reset, BSP actually does not have to wait for Sub-clock to stabilize. To overcome this problem, a weakly defined callback R_BSP_SubClockStabilizeWaitAfterReset() is provided. Reimplement the callback function in the application code to determine whether BSP has to wait for stabilization time based on the current reset type. R_BSP_SubClockStabilizeWaitAfterReset() takes a parameter delay of type uint32_t which describes the time in milliseconds required to stabilize the sub-clock.

SDRAM Initialization

The BSP provides support for usage of external SDRAM modules on MCUs with SDRAM support. SDRAM is enabled and configured in the BSP tab of the FSP configuration editor. The default location for initialization is in the 'Post C' warm start callback. If required, the call to R_BSP_SdramInit() can be moved anywhere after clock and pin initialization, but it must only be called once after reset.

Before entering Software Standby or Deep Software Standby, the user must call R_BSP_SdramSelfRefreshEnable() to change from Auto-Refresh to Self-Refresh in order to preserve data during the low power state. No SDRAM access is allowed after this function is called. The user must not place FSP code or data or their wakeup interrupt handling functions into SDRAM to ensure there are no issues around transitions into and out of Software Standby since SDRAM access will be disabled then and trigger a fault if access is requested.

When resuming from Software Standby, the user must call R_BSP_SdramSelfRefreshDisable() to change from Self-Refresh to Auto-Refresh and restore SDRAM access.

When resuming operation after Deep Software Standby or another situation where there is already data present in the SDRAM modules that must be preserved, the user must call R_BSP_SdramInit(false) before pin initialization and then call R_BSP_SdramSelfRefreshDisable() after pins have been configured in order to resume operations with the SDRAM.

C Runtime Initialization

This BSP configuration allows the user to skip the FSP C runtime initialization code by setting the "C Runtime Initialization" to "Disabled" on the BSP tab of the FSP Configuration editor. Disabling this option is useful in cases where a non-standard linker script is being used or other modifications to the runtime initialization are desired. If this macro is disabled, the user must use the 'Post Clock Init' event from the warm start (described above) to run their own runtime initialization code.

Heap Allocation

The relatively low amount of on-chip SRAM available and lack of memory protection in an MCU means that heap use must be very carefully controlled to avoid memory leaks, overruns and attempted overallocation. Further, many RTOSes provide their own dynamic memory allocation system. For these reasons the default heap size is set at 0 bytes, effectively disabling dynamic memory. If it is required for an application setting a positive value to the "Heap size (bytes)" option in the RX Common configurations on the BSP tab will allocate a heap.

Note

When using printf/sprintf (and other variants) to output floating point numbers a heap is required. A minimum size of 0x1000 (4096) bytes is recommended when starting development in this case.

Error Logging

When error logging is enabled, the error logging function can be redefined on the command line by defining FSP_ERROR_LOG(err) to the desired function call. The default function implementation is FSP_ERROR_LOG(err)=fsp_error_log(err, FILE, LINE). This implementation uses the predefined macros FILE and LINE to help identify the location where the error occurred. Removing the line from the function call can reduce code size when error logging is enabled. Some compilers may support other predefined macros like FUNCTION, which could be helpful for customizing the error logger.

Register Protection

The BSP register protection functions utilize reference counters to ensure that an application which has specified a certain register and subsequently calls another function doesn't have its register protection settings inadvertently modified.

Each time R_BSP_RegisterProtectDisable() is called, the respective reference counter is incremented.

Each time R_BSP_RegisterProtectEnable() is called, the respective reference counter is decremented.

Both functions will only modify the protection state if their reference counter is zero.

    /* Enable writing to protected CGC registers */
    R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC);

    /* Insert code to modify protected CGC registers. */

    /* Disable writing to protected CGC registers */
    R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_CGC);

Option-Setting Memory

Option-setting memory includes OFS registers (e.g. OFS1), block protections settings (BPS/PBPS), and other device-dependent non-volatile options. Option-setting memory is MCU specific, and not all MCUs implement all option-setting registers. Option-setting configurations available on the selected device are configurable in the BSP properties. These configurations are placed in sections to be loaded at the required flash address by the linker.

OFS registers can be individually enabled or disabled. When an OFS register is disabled, its flash address will not be erased or programmed. The existing settings on the device will not be changed. For safety purpose, OFS registers that could limit or disable debug or ROM write access (like BANKSEL, BPS, PBPS etc.) are disabled by default. Please note:

• Secure OFS registers can only be set by Secure/Flat projects. Secure OFS register settings are ignored in Non-Secure projects.
• For MCUBoot use case, OFS registers will only be set by bootloader projects.

All *_SEL registers default to allowing both Secure and Non-Secure access unless otherwise noted here. If block protection is configured in a Secure project, the BSP sets the corresponding configuration to Secure access only by updating the corresponding *_SEL register. Similarly, the PVD related settings in the OFSn_SEL registers are automatically set to Secure if the corresponding PVD monitor is used in the Secure project.

Software Delay

Implements a blocking software delay. A delay can be specified in microseconds, milliseconds or seconds. The delay is implemented based on the system clock rate.

    /* Delay at least 1 second. Depending on the number of wait states required for the region of memory
     * that the software_delay_loop has been linked in this could take longer. The default is 4 cycles per loop.
     * This can be modified by redefining DELAY_LOOP_CYCLES. BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS,
     * and BSP_DELAY_UNITS_MICROSECONDS can all be used with R_BSP_SoftwareDelay. */
    R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_SECONDS);

Trignometric Function

To utilize the TFU hardware for trigonometric math functions, please use the functions provided by each compiler. The CCRX, GCC, and IAR compilers offer options related to TFU. These compilers provide an option to replace calls to the following mathematical library functions with TFU-enabled code. By modifying the compiler options, the trigonometric library functions sinf(), cosf(), atan2f(), hypotf() and more can be mapped to their respective TFU functions. Extended functions sincosf() and atan2hypotf() are also available when the compiler option is enabled in project settings.

Note

Refer to the MCU hardware user's manual or datasheet to determine if it has TFU support.

Critical Section Macros

Implements a critical section. Some MCUs (MCUs with the BASEPRI register) support allowing high priority interrupts to execute during critical sections. On these MCUs, interrupts with priority less than or equal to BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION are not serviced in critical sections. Interrupts with higher priority than BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION still execute in critical sections.

    FSP_CRITICAL_SECTION_DEFINE;

    /* Store the current interrupt posture. */
    FSP_CRITICAL_SECTION_ENTER;

    /* Interrupts cannot run in this section unless their priority is less than BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION. */

    /* Restore saved interrupt posture. */
    FSP_CRITICAL_SECTION_EXIT;

XSPIClock Update

Supports changing the XSPI Clock (XSPICLK) during runtime if supported by the MCU. The XSPICLK source and clock divisor can be updated. It is user's responsibility to ensure the selected clock source is running before attempting to update XSPICLK.

Endian

The BSP supports both big-endian and little-endian. Users can configure the MCU endian through the compiler settings.

Devices with LVOCR

By default, FSP disables I/O port low voltage mode for devices with the LVOCR register. Presently, RX74M and RX74N devices configure I/O ports based on VCC and VCC2 voltage levels. For cases where VCC and/or VCC2 will be less than 2.7 V for these devices, the I/O port low voltage mode should be enabled for VCC.

Note

If the I/O port low voltage mode is not enabled for VCC when less than 2.7 V, device electrical characteristics cannot be guaranteed. Do not enable I/O port low voltage mode for VCC when they are greater than or equal to 2.7 V.

Limited D-Cache and I-Cache Support

For MCUs with D-Cache and I-Cache, limited support is available for enabling the caches and automatically configuring predefined non-cacheable and cacheable regions via the MPU during BSP initialization.

For these MCUs, D-Cache is disabled by default because certain existing drivers do not support data coherency with D-Cache enabled. Enabling the D-Cache requires that data coherency be considered in any circumstance where a core interacts with other bus members.

For these MCUs, I-Cache is also disabled by default to maintain compatibility with existing applications. Users can enable I-Cache separately if the performance benefits are desired and the application has been validated accordingly.

Cacheable Buffer Placement Example

The predefined cacheable regions configured by the MPU when D-Cache is enabled can be used to contain data that should be cached. To use the predefined cacheable regions, place the data into the corresponding cacheable section defined by the linker script for the chosen toolchain.

Below is an example of placing buffers in cacheable regions:

uint8_t cached_uninitialized_buffer_sram[1024] BSP_PLACE_IN_SECTION(".ram_noinit");

Note

The .ram_noinit and .sdram_noinit sections were treated as uninitialized sections.

Non-Cacheable Buffer Placement Example

The predefined non-cacheable regions configured by the MPU when D-Cache is enabled can be used to contain data that should not be cached, ensuring data coherency for that data. To use the predefined non-cacheable regions, place the data into the corresponding non-cacheable section defined by the linker script for the chosen toolchain. The predefined non-cacheable regions are not initialized by the BSP.

Below is an example of placing buffers in non-cacheable regions:

uint8_t uncached_uninitialized_buffer_sram[1024] BSP_PLACE_IN_SECTION(".ram_noinit_nocache");

Note

The .ram_noinit_nocache and .sdram_noinit_nocache sections were treated as uninitialized sections.

Configuration

The BSP is heavily data driven with most features and functionality being configured based on the content from configuration files. Configuration files represent the settings specified by the user and are generated when the project is built and/or when the Generate Project Content button is clicked in the FSP Configuration editor.

Build Time Configurations for fsp_common

The following build time configurations are defined in fsp_cfg/bsp/bsp_cfg.h:

Configuration	Options	Default	Description
Main stack size (bytes)	Value must be an integer multiple of 8 and between 8 and 0xFFFFFFFF	0x400	Set the size of the main program stack. NOTE: This entry is for the main stack. When using an RTOS, thread stacks can be configured in the properties for each thread.
Heap size (bytes)	Value must be 0 or an integer multiple of 8 between 8 and 0xFFFFFFFF.	0	The main heap is disabled by default. Set the heap size to a positive integer divisible by 8 to enable it. A minimum of 4K (0x1000) is recommended if standard library functions are to be used.
Protect zone root stack size (bytes)	Value must be 0 or an integer multiple of 8 between 8 and 0xFFFFFFFF.	0x800	The number of root interrupt stacks used by the ProtectZone hypervisor.
MCU Vcc (mV)	Value must between 0 and 5500 (5.5V)	3300	Some peripherals require different settings based on the supplied voltage. Entering Vcc here (in mV) allows the relevant driver modules to configure the associated peripherals accordingly.
Parameter checking	Enabled Disabled	Disabled	When enabled, parameter checking for the BSP is turned on. In addition, any modules whose parameter checking configuration is set to 'Default (BSP)' will perform parameter checking as well.
Assert Failures	Return FSP_ERR_ASSERTION Call fsp_error_log then Return FSP_ERR_ASSERTION Use assert() to Halt Execution Disable checks that would return FSP_ERR_ASSERTION	Return FSP_ERR_ASSERTION	Define the behavior of the FSP_ASSERT() macro.
Clock Registers not Reset Values during Startup	Disabled Enabled	Disabled	If enabled, registers are assumed to be set to their reset value during startup. Enable this if another application such as a bootloader or Secure project has already configured the clocks before the startup code runs.
Main Oscillator Populated	Populated Not Populated	Populated	Select whether or not there is a main oscillator (XTAL) on the board. This setting can be overridden in board_cfg.h.
PFS Protect	Disabled Enabled	Enabled	Keep the PFS registers locked when they are not being modified. If disabled they will be unlocked during startup.
C Runtime Initialization	Enabled Disabled	Enabled	Select if the C runtime initialization in the BSP is to be used. If disabled, use the BSP_WARM_START_POST_CLOCK event to run user defined equivalent.
Early BSP Initialization	Enabled Disabled	Disabled	Enable this option to use BSP functions before C runtime initialization (BSP_WARM_START_RESET or BSP_WARM_START_POST_CLOCK).
Main Oscillator Clock Source	External Oscillator Crystal or Resonator	Crystal or Resonator	Select the main oscillator clock source. This setting can be overridden in board_cfg.h
Subclock Populated	Populated Not Populated	Populated	Select whether or not there is a subclock crystal on the board. This setting can be overridden in board_cfg.h.
Subclock Drive (Drive capacitance availability varies by MCU)	Standard/Normal mode Low/Low power mode 1 Low power mode 2 Low power mode 3	Standard/Normal mode	Select the subclock oscillator drive capacitance. This setting can be overridden in board_cfg.h
Subclock Stabilization Time (ms)	Value must between 0 and 10000	1000	Select the subclock oscillator stabilization time. This is only used in the startup code if the subclock is selected as the system clock on the Clocks tab or if the HOCO FLL function is enabled. This setting can be overridden in board_cfg.h

Usage Notes

Limitation

The BSP will not initialize any memory sections in the SDRAM. The user is responsible for initializing any code or data stored in SDRAM.

FSP C++ projects are not supported with the CC-RX compiler because it does not support the C++ 11 features, which is required for C++ project. Use a C project when building with CC-RX.

ProtectZone

Secure World Project Preparation

Secure Service Call

Secure Service Call (SSC) to retrieve clock information from the Non-Secure world. Users can add their corresponding processing as required.

ProtectZone Limitations

Secure Execution Blocks Non-Secure Execution

Non-Secure interrupts that occur during Secure execution are pended.

This BSP does not support hypervisor calls that invoke Non-Secure functions from the Secure world.

Secure Interrupt Priority

In ProtectZone Secure projects, Secure interrupt priorities must be higher than 15 to prevent Non-Secure interrupts from preempting Secure execution.

Secure Floating-Point Registers Not Cleared

Secure floating-point registers are not cleared when transitioning from the Secure to the Non-Secure world.

CCRX Secure Project Setting

When building a secure application with the CC-RX compiler, define the _RX_PZ_SECURE assembler symbol as follows:

1. From the Project menu, select C/C++ Project Settings.
   

   Project Settings
2. Select Paths and Symbols, then open the Symbols tab. Under Languages, select Assembly and click Add.
   

   Project Settings path_and_symbols
3. Enter _RX_PZ_SECURE in the Name field and 1 in the Value field, then click OK.
   

   Project Settings asm symbol Settings

Modules
	RX74M
	RX74N

Data Structures
struct	transfer_info_t

Macros
#define	BSP_IRQ_DISABLED
#define	FSP_LOG_PRINT(X)
#define	FSP_RETURN(err)
#define	FSP_ERROR_LOG(err)
#define	FSP_ASSERT(a)
#define	FSP_ERROR_RETURN(a, err)
#define	FSP_CRITICAL_SECTION_ENTER
#define	FSP_CRITICAL_SECTION_EXIT
#define	FSP_INVALID_VECTOR
#define	BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x)
#define	BSP_STACK_ALIGNMENT
#define	R_BSP_MODULE_START(ip, channel)
#define	R_BSP_MODULE_STOP(ip, channel)

Enumerations
enum	fsp_ip_t
enum	fsp_signal_t
enum	bsp_warm_start_event_t
enum	fsp_priv_clock_t
enum	fsp_priv_source_clock_t
enum	bsp_delay_units_t
enum	bsp_grp_irq_nmi_t
enum	bsp_reg_protect_t
enum	transfer_mode_t
enum	transfer_size_t
enum	transfer_addr_mode_t
enum	transfer_repeat_area_t
enum	transfer_chain_mode_t
enum	transfer_irq_t

Variables
uint32_t SystemCoreClock	BSP_SECTION_EARLY_INIT

---

Data Structure Documentation

transfer_info_t

struct transfer_info_t

This structure specifies the properties of the transfer.

Warning

When using DTC, this structure corresponds to the descriptor block registers required by the DTC. The following components may be modified by the driver: p_src, p_dest, num_blocks, and length.

When using DTC, do NOT reuse this structure to configure multiple transfers. Each transfer must have a unique transfer_info_t.

When using DTC, this structure must not be allocated in a temporary location. Any instance of this structure must remain in scope until the transfer it is used for is closed.

Note

When using DTC, consider placing instances of this structure in a protected section of memory.

Data Fields
union transfer_info_t	transfer_settings_u
void const *volatile	p_src	Source pointer.
void *volatile	p_dest	Destination pointer.
volatile uint16_t	num_blocks	Number of blocks to transfer when using TRANSFER_MODE_BLOCK (DTC, DMAC and EXDMAC) or TRANSFER_MODE_REPEAT (DMAC and EXDMAC only) or TRANSFER_MODE_REPEAT_BLOCK (DMAC and EXDMAC only), unused in other modes. Number of blocks to transfer when using TRANSFER_MODE_BLOCK (DTC, DMAC or EXDMAC) or TRANSFER_MODE_REPEAT (DMAC and EXDMAC only) or TRANSFER_MODE_REPEAT_BLOCK (DMAC and EXDMAC only), unused in other modes.
volatile uint16_t	length	Length of each transfer. Range limited for TRANSFER_MODE_BLOCK, TRANSFER_MODE_REPEAT, and TRANSFER_MODE_REPEAT_BLOCK see HAL driver for details.
union transfer_info_t	transfer_settings_u

Macro Definition Documentation

BSP_IRQ_DISABLED

#define BSP_IRQ_DISABLED

Used to configure the interrupt priority level into level 0 for disabling the interrupt.

FSP_LOG_PRINT

#define FSP_LOG_PRINT

(

X

)

Macro that can be defined in order to enable logging in FSP modules.

FSP_RETURN

#define FSP_RETURN

(

err

)

Macro to log and return error without an assertion.

FSP_ERROR_LOG

#define FSP_ERROR_LOG

(

err

)

This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in user code and do required debugging (breakpoints, stack dump, etc) in this function.

FSP_ASSERT

#define FSP_ASSERT

(

a

)

Default assertion calls FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP functions.

FSP_ERROR_RETURN

#define FSP_ERROR_RETURN	(		a,
			err
	)

All FSP error codes are returned using this macro. Calls FSP_ERROR_LOG function if condition "a" is false. Used to identify runtime errors in FSP functions.

FSP_CRITICAL_SECTION_ENTER

#define FSP_CRITICAL_SECTION_ENTER

This macro temporarily saves the current interrupt state and disables interrupts.

FSP_CRITICAL_SECTION_EXIT

#define FSP_CRITICAL_SECTION_EXIT

This macro restores the previously saved interrupt state, reenabling interrupts.

FSP_INVALID_VECTOR

#define FSP_INVALID_VECTOR

Used to signify that the requested IRQ vector is not defined in this system.

BSP_CFG_HANDLE_UNRECOVERABLE_ERROR

#define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR

(

x

)

In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will alert the user of the error. The user can override this default behavior by defining their own BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro.

BSP_STACK_ALIGNMENT

#define BSP_STACK_ALIGNMENT

Stacks (and heap) must be sized and aligned to an integer multiple of this number.

R_BSP_MODULE_START

#define R_BSP_MODULE_START	(		ip,
			channel
	)

Cancels the module stop state.

Parameters

ip	fsp_ip_t enum value for the module to be stopped
channel	The channel. Use channel 0 for modules without channels.

R_BSP_MODULE_STOP

#define R_BSP_MODULE_STOP	(		ip,
			channel
	)

Enables the module stop state.

Parameters

ip	fsp_ip_t enum value for the module to be stopped
channel	The channel. Use channel 0 for modules without channels.

Enumeration Type Documentation

fsp_ip_t

enum fsp_ip_t

Available modules.

Enumerator
FSP_IP_CFLASH	Code Flash.
FSP_IP_DFLASH	Data Flash.
FSP_IP_RAM	RAM.
FSP_IP_LVD	Low Voltage Detection.
FSP_IP_CGC	Clock Generation Circuit.
FSP_IP_LPM	Low Power Modes.
FSP_IP_FCU	Flash Control Unit.
FSP_IP_ICU	Interrupt Control Unit.
FSP_IP_DMAC	DMA Controller.
FSP_IP_DTC	Data Transfer Controller.
FSP_IP_IOPORT	I/O Ports.
FSP_IP_PFS	Pin Function Select.
FSP_IP_ELC	Event Link Controller.
FSP_IP_MPU	Memory Protection Unit.
FSP_IP_MSTP	Module Stop.
FSP_IP_MMF	Memory Mirror Function.
FSP_IP_KEY	Key Interrupt Function.
FSP_IP_CAC	Clock Frequency Accuracy Measurement Circuit.
FSP_IP_DOC	Data Operation Circuit.
FSP_IP_CRC	Cyclic Redundancy Check Calculator.
FSP_IP_SCI	Serial Communications Interface.
FSP_IP_IIC	I2C Bus Interface.
FSP_IP_SPI	Serial Peripheral Interface.
FSP_IP_CTSU	Capacitive Touch Sensing Unit.
FSP_IP_SCE	Secure Cryptographic Engine.
FSP_IP_SLCDC	Segment LCD Controller.
FSP_IP_AES	Advanced Encryption Standard.
FSP_IP_TRNG	True Random Number Generator.
FSP_IP_FCACHE	Flash Cache.
FSP_IP_SRAM	SRAM.
FSP_IP_ADC	A/D Converter.
FSP_IP_DAC	12-Bit D/A Converter
FSP_IP_TSN	Temperature Sensor.
FSP_IP_DAAD	D/A A/D Synchronous Unit.
FSP_IP_ACMPHS	High Speed Analog Comparator.
FSP_IP_ACMPLP	Low Power Analog Comparator.
FSP_IP_OPAMP	Operational Amplifier.
FSP_IP_SDADC	Sigma Delta A/D Converter.
FSP_IP_RTC	Real Time Clock.
FSP_IP_WDT	Watch Dog Timer.
FSP_IP_IWDT	Independent Watch Dog Timer.
FSP_IP_GPT	General PWM Timer.
FSP_IP_POEG	Port Output Enable for GPT.
FSP_IP_OPS	Output Phase Switch.
FSP_IP_AGT	Asynchronous General-Purpose Timer.
FSP_IP_CAN	Controller Area Network.
FSP_IP_IRDA	Infrared Data Association.
FSP_IP_QSPI	Quad Serial Peripheral Interface.
FSP_IP_USBFS	USB Full Speed.
FSP_IP_SDHI	SD Host Interface.
FSP_IP_SRC	Sampling Rate Converter.
FSP_IP_SSI	Serial Sound Interface.
FSP_IP_DALI	Digital Addressable Lighting Interface.
FSP_IP_ETHER	Ethernet MAC Controller.
FSP_IP_EDMAC	Ethernet DMA Controller.
FSP_IP_EPTPC	Ethernet PTP Controller.
FSP_IP_PDC	Parallel Data Capture Unit.
FSP_IP_GLCDC	Graphics LCD Controller.
FSP_IP_DRW	2D Drawing Engine
FSP_IP_JPEG	JPEG.
FSP_IP_DAC8	8-Bit D/A Converter
FSP_IP_USBHS	USB High Speed.
FSP_IP_OSPI	Octa Serial Peripheral Interface.
FSP_IP_CEC	HDMI CEC.
FSP_IP_TFU	Trigonometric Function Unit.
FSP_IP_IIRFA	IIR Filter Accelerator.
FSP_IP_CANFD	CAN-FD.
FSP_IP_EXDMAC	EXDMA Controller.
FSP_IP_ACSE	All-Module Clock Stop Mode Enable.
FSP_IP_EXPANSIONRAM	Expansion RAM.
FSP_IP_ECCRAM	ECCRAM.
FSP_IP_STANDBYRAM	Standby RAM.
FSP_IP_MMCIF	MMC Host Interface.
FSP_IP_TSIP	Trusted Secure IP.
FSP_IP_TPU	16-Bit Timer Pulse Unit
FSP_IP_CMT	Compare Match Timer.
FSP_IP_CMTW	Compare Match Timer W.
FSP_IP_TMR	8-Bit Timer
FSP_IP_MTU	Multifunction Timer Pulse Unit.
FSP_IP_PPG	Programmable Pulse Generator.
FSP_IP_HRPWM	High Resolution PWM Waveform Generation Circuit.
FSP_IP_CMPC	Comparator C.
FSP_IP_SCI_B	Serial Communications Interface.
FSP_IP_I3C	I3C Bus Interface.
FSP_IP_SPI_B	Serial Peripheral Interface.
FSP_IP_ENDAT	EnDat 2.2.
FSP_IP_ENDAT3	EnDat 3.
FSP_IP_BISS	BiSS-C.
FSP_IP_BISSL	BiSS-Line.
FSP_IP_HDSL	HIPERFACE DSL.
FSP_IP_AFMT	A-format.
FSP_IP_FFT	FFT Accelerator.

fsp_signal_t

enum fsp_signal_t

Signals that can be mapped to an interrupt.

Enumerator
FSP_SIGNAL_ADC_COMPARE_MATCH	ADC COMPARE MATCH.
FSP_SIGNAL_ADC_COMPARE_MISMATCH	ADC COMPARE MISMATCH.
FSP_SIGNAL_ADC_SCAN_END	ADC SCAN END.
FSP_SIGNAL_ADC_SCAN_END_B	ADC SCAN END B.
FSP_SIGNAL_ADC_WINDOW_A	ADC WINDOW A.
FSP_SIGNAL_ADC_WINDOW_B	ADC WINDOW B.
FSP_SIGNAL_AES_RDREQ	AES RDREQ.
FSP_SIGNAL_AES_WRREQ	AES WRREQ.
FSP_SIGNAL_AGT_COMPARE_A	AGT COMPARE A.
FSP_SIGNAL_AGT_COMPARE_B	AGT COMPARE B.
FSP_SIGNAL_AGT_INT	AGT INT.
FSP_SIGNAL_CAC_FREQUENCY_ERROR	CAC FREQUENCY ERROR.
FSP_SIGNAL_CAC_MEASUREMENT_END	CAC MEASUREMENT END.
FSP_SIGNAL_CAC_OVERFLOW	CAC OVERFLOW.
FSP_SIGNAL_CAN_ERROR	CAN ERROR.
FSP_SIGNAL_CAN_FIFO_RX	CAN FIFO RX.
FSP_SIGNAL_CAN_FIFO_TX	CAN FIFO TX.
FSP_SIGNAL_CAN_MAILBOX_RX	CAN MAILBOX RX.
FSP_SIGNAL_CAN_MAILBOX_TX	CAN MAILBOX TX.
FSP_SIGNAL_CGC_MOSC_STOP	CGC MOSC STOP.
FSP_SIGNAL_LPM_SNOOZE_REQUEST	LPM SNOOZE REQUEST.
FSP_SIGNAL_LVD_LVD1	LVD LVD1.
FSP_SIGNAL_LVD_LVD2	LVD LVD2.
FSP_SIGNAL_VBATT_LVD	VBATT LVD.
FSP_SIGNAL_LVD_VBATT	LVD VBATT.
FSP_SIGNAL_ACMPHS_INT	ACMPHS INT.
FSP_SIGNAL_ACMPLP_INT	ACMPLP INT.
FSP_SIGNAL_CTSU_END	CTSU END.
FSP_SIGNAL_CTSU_READ	CTSU READ.
FSP_SIGNAL_CTSU_WRITE	CTSU WRITE.
FSP_SIGNAL_DALI_DEI	DALI DEI.
FSP_SIGNAL_DALI_CLI	DALI CLI.
FSP_SIGNAL_DALI_SDI	DALI SDI.
FSP_SIGNAL_DALI_BPI	DALI BPI.
FSP_SIGNAL_DALI_FEI	DALI FEI.
FSP_SIGNAL_DALI_SDI_OR_BPI	DALI SDI OR BPI.
FSP_SIGNAL_DMAC_INT	DMAC INT.
FSP_SIGNAL_DOC_INT	DOC INT.
FSP_SIGNAL_DRW_INT	DRW INT.
FSP_SIGNAL_DTC_COMPLETE	DTC COMPLETE.
FSP_SIGNAL_DTC_END	DTC END.
FSP_SIGNAL_EDMAC_EINT	EDMAC EINT.
FSP_SIGNAL_ELC_SOFTWARE_EVENT_0	ELC SOFTWARE EVENT 0.
FSP_SIGNAL_ELC_SOFTWARE_EVENT_1	ELC SOFTWARE EVENT 1.
FSP_SIGNAL_EPTPC_IPLS	EPTPC IPLS.
FSP_SIGNAL_EPTPC_MINT	EPTPC MINT.
FSP_SIGNAL_EPTPC_PINT	EPTPC PINT.
FSP_SIGNAL_EPTPC_TIMER0_FALL	EPTPC TIMER0 FALL.
FSP_SIGNAL_EPTPC_TIMER0_RISE	EPTPC TIMER0 RISE.
FSP_SIGNAL_EPTPC_TIMER1_FALL	EPTPC TIMER1 FALL.
FSP_SIGNAL_EPTPC_TIMER1_RISE	EPTPC TIMER1 RISE.
FSP_SIGNAL_EPTPC_TIMER2_FALL	EPTPC TIMER2 FALL.
FSP_SIGNAL_EPTPC_TIMER2_RISE	EPTPC TIMER2 RISE.
FSP_SIGNAL_EPTPC_TIMER3_FALL	EPTPC TIMER3 FALL.
FSP_SIGNAL_EPTPC_TIMER3_RISE	EPTPC TIMER3 RISE.
FSP_SIGNAL_EPTPC_TIMER4_FALL	EPTPC TIMER4 FALL.
FSP_SIGNAL_EPTPC_TIMER4_RISE	EPTPC TIMER4 RISE.
FSP_SIGNAL_EPTPC_TIMER5_FALL	EPTPC TIMER5 FALL.
FSP_SIGNAL_EPTPC_TIMER5_RISE	EPTPC TIMER5 RISE.
FSP_SIGNAL_FCU_FIFERR	FCU FIFERR.
FSP_SIGNAL_FCU_FRDYI	FCU FRDYI.
FSP_SIGNAL_GLCDC_LINE_DETECT	GLCDC LINE DETECT.
FSP_SIGNAL_GLCDC_UNDERFLOW_1	GLCDC UNDERFLOW 1.
FSP_SIGNAL_GLCDC_UNDERFLOW_2	GLCDC UNDERFLOW 2.
FSP_SIGNAL_GPT_CAPTURE_COMPARE_A	GPT CAPTURE COMPARE A.
FSP_SIGNAL_GPT_CAPTURE_COMPARE_B	GPT CAPTURE COMPARE B.
FSP_SIGNAL_GPT_COMPARE_C	GPT COMPARE C.
FSP_SIGNAL_GPT_COMPARE_D	GPT COMPARE D.
FSP_SIGNAL_GPT_COMPARE_E	GPT COMPARE E.
FSP_SIGNAL_GPT_COMPARE_F	GPT COMPARE F.
FSP_SIGNAL_GPT_COUNTER_OVERFLOW	GPT COUNTER OVERFLOW.
FSP_SIGNAL_GPT_COUNTER_UNDERFLOW	GPT COUNTER UNDERFLOW.
FSP_SIGNAL_GPT_AD_TRIG_A	GPT AD TRIG A.
FSP_SIGNAL_GPT_AD_TRIG_B	GPT AD TRIG B.
FSP_SIGNAL_OPS_UVW_EDGE	OPS UVW EDGE.
FSP_SIGNAL_ICU_IRQ0	ICU IRQ0.
FSP_SIGNAL_ICU_IRQ1	ICU IRQ1.
FSP_SIGNAL_ICU_IRQ2	ICU IRQ2.
FSP_SIGNAL_ICU_IRQ3	ICU IRQ3.
FSP_SIGNAL_ICU_IRQ4	ICU IRQ4.
FSP_SIGNAL_ICU_IRQ5	ICU IRQ5.
FSP_SIGNAL_ICU_IRQ6	ICU IRQ6.
FSP_SIGNAL_ICU_IRQ7	ICU IRQ7.
FSP_SIGNAL_ICU_IRQ8	ICU IRQ8.
FSP_SIGNAL_ICU_IRQ9	ICU IRQ9.
FSP_SIGNAL_ICU_IRQ10	ICU IRQ10.
FSP_SIGNAL_ICU_IRQ11	ICU IRQ11.
FSP_SIGNAL_ICU_IRQ12	ICU IRQ12.
FSP_SIGNAL_ICU_IRQ13	ICU IRQ13.
FSP_SIGNAL_ICU_IRQ14	ICU IRQ14.
FSP_SIGNAL_ICU_IRQ15	ICU IRQ15.
FSP_SIGNAL_ICU_SNOOZE_CANCEL	ICU SNOOZE CANCEL.
FSP_SIGNAL_IIC_ERI	IIC ERI.
FSP_SIGNAL_IIC_RXI	IIC RXI.
FSP_SIGNAL_IIC_TEI	IIC TEI.
FSP_SIGNAL_IIC_TXI	IIC TXI.
FSP_SIGNAL_IIC_WUI	IIC WUI.
FSP_SIGNAL_IOPORT_EVENT_1	IOPORT EVENT 1.
FSP_SIGNAL_IOPORT_EVENT_2	IOPORT EVENT 2.
FSP_SIGNAL_IOPORT_EVENT_3	IOPORT EVENT 3.
FSP_SIGNAL_IOPORT_EVENT_4	IOPORT EVENT 4.
FSP_SIGNAL_IOPORT_EVENT_B	IOPORT EVENT B.
FSP_SIGNAL_IOPORT_EVENT_C	IOPORT EVENT C.
FSP_SIGNAL_IOPORT_EVENT_D	IOPORT EVENT D.
FSP_SIGNAL_IOPORT_EVENT_E	IOPORT EVENT E.
FSP_SIGNAL_IWDT_UNDERFLOW	IWDT UNDERFLOW.
FSP_SIGNAL_JPEG_JDTI	JPEG JDTI.
FSP_SIGNAL_JPEG_JEDI	JPEG JEDI.
FSP_SIGNAL_KEY_INT	KEY INT.
FSP_SIGNAL_PDC_FRAME_END	PDC FRAME END.
FSP_SIGNAL_PDC_INT	PDC INT.
FSP_SIGNAL_PDC_RECEIVE_DATA_READY	PDC RECEIVE DATA READY.
FSP_SIGNAL_POEG_EVENT	POEG EVENT.
FSP_SIGNAL_QSPI_INT	QSPI INT.
FSP_SIGNAL_RTC_ALARM	RTC ALARM.
FSP_SIGNAL_RTC_PERIOD	RTC PERIOD.
FSP_SIGNAL_RTC_CARRY	RTC CARRY.
FSP_SIGNAL_SCE_INTEGRATE_RDRDY	SCE INTEGRATE RDRDY.
FSP_SIGNAL_SCE_INTEGRATE_WRRDY	SCE INTEGRATE WRRDY.
FSP_SIGNAL_SCE_LONG_PLG	SCE LONG PLG.
FSP_SIGNAL_SCE_PROC_BUSY	SCE PROC BUSY.
FSP_SIGNAL_SCE_RDRDY_0	SCE RDRDY 0.
FSP_SIGNAL_SCE_RDRDY_1	SCE RDRDY 1.
FSP_SIGNAL_SCE_ROMOK	SCE ROMOK.
FSP_SIGNAL_SCE_TEST_BUSY	SCE TEST BUSY.
FSP_SIGNAL_SCE_WRRDY_0	SCE WRRDY 0.
FSP_SIGNAL_SCE_WRRDY_1	SCE WRRDY 1.
FSP_SIGNAL_SCE_WRRDY_4	SCE WRRDY 4.
FSP_SIGNAL_SCI_AM	SCI AM.
FSP_SIGNAL_SCI_ERI	SCI ERI.
FSP_SIGNAL_SCI_RXI	SCI RXI.
FSP_SIGNAL_SCI_RXI_OR_ERI	SCI RXI OR ERI.
FSP_SIGNAL_SCI_TEI	SCI TEI.
FSP_SIGNAL_SCI_TXI	SCI TXI.
FSP_SIGNAL_SDADC_ADI	SDADC ADI.
FSP_SIGNAL_SDADC_SCANEND	SDADC SCANEND.
FSP_SIGNAL_SDADC_CALIEND	SDADC CALIEND.
FSP_SIGNAL_SDHIMMC_ACCS	SDHIMMC ACCS.
FSP_SIGNAL_SDHIMMC_CARD	SDHIMMC CARD.
FSP_SIGNAL_SDHIMMC_DMA_REQ	SDHIMMC DMA REQ.
FSP_SIGNAL_SDHIMMC_SDIO	SDHIMMC SDIO.
FSP_SIGNAL_SPI_ERI	SPI ERI.
FSP_SIGNAL_SPI_IDLE	SPI IDLE.
FSP_SIGNAL_SPI_RXI	SPI RXI.
FSP_SIGNAL_SPI_TEI	SPI TEI.
FSP_SIGNAL_SPI_TXI	SPI TXI.
FSP_SIGNAL_SRC_CONVERSION_END	SRC CONVERSION END.
FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY	SRC INPUT FIFO EMPTY.
FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL	SRC OUTPUT FIFO FULL.
FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW	SRC OUTPUT FIFO OVERFLOW.
FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW	SRC OUTPUT FIFO UNDERFLOW.
FSP_SIGNAL_SSI_INT	SSI INT.
FSP_SIGNAL_SSI_RXI	SSI RXI.
FSP_SIGNAL_SSI_TXI	SSI TXI.
FSP_SIGNAL_SSI_TXI_RXI	SSI TXI RXI.
FSP_SIGNAL_TRNG_RDREQ	TRNG RDREQ.
FSP_SIGNAL_USB_FIFO_0	USB FIFO 0.
FSP_SIGNAL_USB_FIFO_1	USB FIFO 1.
FSP_SIGNAL_USB_INT	USB INT.
FSP_SIGNAL_USB_RESUME	USB RESUME.
FSP_SIGNAL_USB_USB_INT_RESUME	USB USB INT RESUME.
FSP_SIGNAL_WDT_UNDERFLOW	WDT UNDERFLOW.
FSP_SIGNAL_ULPT_COMPARE_A	ULPT COMPARE A.
FSP_SIGNAL_ULPT_COMPARE_B	ULPT COMPARE B.
FSP_SIGNAL_ULPT_INT	ULPT INT.

bsp_warm_start_event_t

enum bsp_warm_start_event_t

Different warm start entry locations in the BSP.

Enumerator
BSP_WARM_START_RESET	Called almost immediately after reset. No C runtime environment, clocks, or IRQs.
BSP_WARM_START_POST_CLOCK	Called after clock initialization. No C runtime environment or IRQs.
BSP_WARM_START_POST_C	Called after clocks and C runtime environment have been set up.

fsp_priv_clock_t

enum fsp_priv_clock_t

Enumerator
FSP_PRIV_CLOCK_UNUSED	Sentinel value for unused clock.

fsp_priv_source_clock_t

enum fsp_priv_source_clock_t

Enumerator
FSP_PRIV_CLOCK_HOCO	The high speed on chip oscillator.
FSP_PRIV_CLOCK_MOCO	The middle speed on chip oscillator.
FSP_PRIV_CLOCK_LOCO	The low speed on chip oscillator.
FSP_PRIV_CLOCK_MAIN_OSC	The main oscillator.
FSP_PRIV_CLOCK_SUBCLOCK	The subclock oscillator.
FSP_PRIV_CLOCK_PLL	The PLL output.
FSP_PRIV_CLOCK_PLL1P	The PLL1P output.
FSP_PRIV_CLOCK_PLL2	The PLL2 output.
FSP_PRIV_CLOCK_PLL2P	The PLL2P output.
FSP_PRIV_CLOCK_PLL1Q	The PLL1Q output.
FSP_PRIV_CLOCK_PLL1R	The PLL1R output.
FSP_PRIV_CLOCK_PLL2Q	The PLL2Q output.
FSP_PRIV_CLOCK_PLL2R	The PLL2R output.

bsp_delay_units_t

enum bsp_delay_units_t

Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds

Enumerator
BSP_DELAY_UNITS_SECONDS	Requested delay amount is in seconds.
BSP_DELAY_UNITS_MILLISECONDS	Requested delay amount is in milliseconds.
BSP_DELAY_UNITS_MICROSECONDS	Requested delay amount is in microseconds.

bsp_grp_irq_nmi_t

enum bsp_grp_irq_nmi_t

Which interrupts can have callbacks registered.

Enumerator
BSP_GRP_IRQ_IWDT_ERROR	IWDT underflow/refresh error has occurred.
BSP_GRP_IRQ_WDT_ERROR	WDT underflow/refresh error has occurred.
BSP_GRP_IRQ_PVD1	Voltage monitoring 1 interrupt.
BSP_GRP_IRQ_PVD2	Voltage monitoring 2 interrupt.
BSP_GRP_IRQ_SOSC_STOP_DETECT	Sub-clock oscillation stop detection interrupt.
BSP_GRP_IRQ_OSC_STOP_DETECT	Main clock oscillation stop detection interrupt.
BSP_GRP_IRQ_NMI_PIN	NMI pin interrupt.
BSP_GRP_IRQ_BUS	Bus error interrupt.
BSP_GRP_IRQ_CM_ERROR	Common memory error interrupt.
BSP_GRP_IRQ_LM_ERROR	Local memory error interrupt.
BSP_GRP_IRQ_DPFPU	Double-precision floating-point exception.
BSP_GRP_IRQ_MRC_READ_DETECT	Code MRAM read access error interrupt.
BSP_GRP_IRQ_MRE_READ_DETECT	Extra MRAM read access error interrupt.

bsp_reg_protect_t

enum bsp_reg_protect_t

The different types of registers that can be protected.

Enumerator
BSP_REG_PROTECT_CGC	Enables writing to the registers related to the clock generation circuit.
BSP_REG_PROTECT_OM_LPC_BATT_SWR	Enables writing to the registers related to operating modes, low power consumption, battery backup function, and software reset function.
BSP_REG_PROTECT_PVD	Enables writing to the registers related to the PVD.
BSP_REG_PROTECT_SAR	Enables writing to the registers related to the security function.
BSP_REG_PROTECT_RST	Enables writing to the registers related to the Reset.

transfer_mode_t

enum transfer_mode_t

Transfer mode describes what will happen when a transfer request occurs.

Enumerator
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers.
TRANSFER_MODE_REPEAT	Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the repeat area and the transfer length will be reset to their initial values. If DMAC or EXDMAC is used, the transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is used, the transfer repeats continuously (no limit to the number of repeat transfers).
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers.
TRANSFER_MODE_REPEAT_BLOCK	In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets within a block (to split blocks into arrays of their first data, second data, etc.)
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers.
TRANSFER_MODE_REPEAT	Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the repeat area and the transfer length will be reset to their initial values. If DMAC or EXDMAC is used, the transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is used, the transfer repeats continuously (no limit to the number of repeat transfers).
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers.
TRANSFER_MODE_REPEAT_BLOCK	In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets within a block (to split blocks into arrays of their first data, second data, etc.)

transfer_size_t

enum transfer_size_t

Transfer size specifies the size of each individual transfer. Total transfer length = transfer_size_t * transfer_length_t

Enumerator
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.

transfer_addr_mode_t

enum transfer_addr_mode_t

Address mode specifies whether to modify (increment or decrement) pointer after each transfer.

Enumerator
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_OFFSET	Offset is added to the address pointer after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_DECREMENTED	Address pointer is decremented by associated transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_OFFSET	Offset is added to the address pointer after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_DECREMENTED	Address pointer is decremented by associated transfer_size_t after each transfer.

transfer_repeat_area_t

enum transfer_repeat_area_t

Repeat area options (source or destination). In TRANSFER_MODE_REPEAT, the selected pointer returns to its original value after transfer_info_t::length transfers. In TRANSFER_MODE_BLOCK and TRANSFER_MODE_REPEAT_BLOCK, the selected pointer returns to its original value after each transfer.

Enumerator
TRANSFER_REPEAT_AREA_DESTINATION	Destination area repeated in TRANSFER_MODE_REPEAT or TRANSFER_MODE_BLOCK or TRANSFER_MODE_REPEAT_BLOCK.
TRANSFER_REPEAT_AREA_SOURCE	Source area repeated in TRANSFER_MODE_REPEAT or TRANSFER_MODE_BLOCK or TRANSFER_MODE_REPEAT_BLOCK.
TRANSFER_REPEAT_AREA_DESTINATION	Destination area repeated in TRANSFER_MODE_REPEAT or TRANSFER_MODE_BLOCK or TRANSFER_MODE_REPEAT_BLOCK.
TRANSFER_REPEAT_AREA_SOURCE	Source area repeated in TRANSFER_MODE_REPEAT or TRANSFER_MODE_BLOCK or TRANSFER_MODE_REPEAT_BLOCK.

transfer_chain_mode_t

enum transfer_chain_mode_t

Chain transfer mode options.

Note

Only applies for DTC.

Enumerator
TRANSFER_CHAIN_MODE_DISABLED	Chain mode not used.
TRANSFER_CHAIN_MODE_EACH	Switch to next transfer after a single transfer from this transfer_info_t.
TRANSFER_CHAIN_MODE_END	Complete the entire transfer defined in this transfer_info_t before chaining to next transfer.
TRANSFER_CHAIN_MODE_DISABLED	Chain mode not used.
TRANSFER_CHAIN_MODE_EACH	Switch to next transfer after a single transfer from this transfer_info_t.
TRANSFER_CHAIN_MODE_END	Complete the entire transfer defined in this transfer_info_t before chaining to next transfer.

transfer_irq_t

enum transfer_irq_t

Interrupt options.

Enumerator
TRANSFER_IRQ_END	Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer, the interrupt will occur only after subsequent chained transfer(s) are complete. Warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will prevent activation source interrupts until the transfer is complete.
TRANSFER_IRQ_EACH	Interrupt occurs after each transfer. Note Not available in all HAL drivers. See HAL driver for details.
TRANSFER_IRQ_END	Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer, the interrupt will occur only after subsequent chained transfer(s) are complete. Warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will prevent activation source interrupts until the transfer is complete.
TRANSFER_IRQ_EACH	Interrupt occurs after each transfer. Note Not available in all HAL drivers. See HAL driver for details.

Function Documentation

R_FSP_VersionGet()

fsp_err_t R_FSP_VersionGet

(

fsp_pack_version_t *const

p_version

)

Get the FSP version based on compile time macros.

Parameters

[out]

p_version

Memory address to return version information to.

Return values

FSP_SUCCESS	Version information stored.
FSP_ERR_ASSERTION	The parameter p_version is NULL.

Reset_Handler()

void Reset_Handler

(

void

)

MCU starts executing here out of reset. Main stack pointer is set up already.

Default_Handler()

void Default_Handler

(

void

)

Default exception handler.

R_BSP_WarmStart()

void R_BSP_WarmStart

(

bsp_warm_start_event_t

event

)

This function is called at various points during the startup process. This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user implemented version. One of the main uses for this function is to call functional safety code during the startup process. To use this function just copy this function into your own code and modify it to meet your needs.

Parameters

[in]

event

Where the code currently is in the start up process

SystemInit()

void SystemInit

(

void

)

Initialize the MCU and the runtime environment.

R_BSP_CacheEnable()

void R_BSP_CacheEnable

(

void

)

Enable caches.

Enables all configured cache regions.

R_BSP_CacheDisable()

void R_BSP_CacheDisable

(

void

)

Disable caches.

Disable all configured cache regions.

R_BSP_CacheClean()

void R_BSP_CacheClean

(

void

)

Clean caches.

Writes back any modified cache contents to memory.

R_BSP_CacheInvalidate()

void R_BSP_CacheInvalidate

(

void

)

Flush caches.

Invalidates all cache entries without writing back cached data to memory. Any modified cache contents that have not been cleaned may be discarded.

R_BSP_CacheCleanInvalidate()

void R_BSP_CacheCleanInvalidate

(

void

)

Clean and flush caches.

Writes back any modified cache contents to memory and invalidates all cache entries.

bsp_cache_operate_all()

__STATIC_INLINE void bsp_cache_operate_all

(

uint8_t

operate

)

Cache operation to all area.

Parameters

[in]

operate

Cache operation. BSP_PRV_DCACHE_INV(0) - Cache invalidate. BSP_PRV_DCACHE_CLEAN(1) - Cache clean. BSP_PRV_DCACHE_CLEAN_INV(2) - Cache clean and invalidate.

R_BSP_CacheEnableData()

__STATIC_INLINE void R_BSP_CacheEnableData

(

void

)

Enable Data cache.

R_BSP_CacheDisableData()

__STATIC_INLINE void R_BSP_CacheDisableData

(

void

)

Disable Data cache.

R_BSP_CacheCleanAllData()

__STATIC_INLINE void R_BSP_CacheCleanAllData

(

void

)

Clean whole of the data cache.

R_BSP_CacheInvalidateAllData()

__STATIC_INLINE void R_BSP_CacheInvalidateAllData

(

void

)

Invalidate whole of the data cache.

R_BSP_CacheCleanInvalidateAllData()

__STATIC_INLINE void R_BSP_CacheCleanInvalidateAllData

(

void

)

Clean and invalidate the whole of data cache.

R_BSP_SourceClockHzGet()

uint32_t R_BSP_SourceClockHzGet

(

fsp_priv_source_clock_t

clock

)

Gets the frequency of a source clock.

Parameters

[in]

clock

Element of clock souce enum which provides clock source.

Returns

Frequency of requested clock in Hertz.

R_FSP_CurrentIrqGet()

__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet

(

void

)

Return active interrupt vector number value

Returns

Active interrupt vector number value

R_FSP_SystemClockHzGet()

__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet

(

fsp_priv_clock_t

clock

)

Gets the frequency of a system clock.

Returns

Frequency of requested clock in Hertz.

R_FSP_ClockDividerGet()

__STATIC_INLINE uint32_t R_FSP_ClockDividerGet

(

uint32_t

ckdivcr

)

Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR).

Returns

Clock Divider

R_BSP_UniqueIdGet()

__STATIC_INLINE bsp_unique_id_t const* R_BSP_UniqueIdGet

(

void

)

Get unique ID for this device.

Returns

A pointer to the unique identifier structure

R_BSP_PartNumberGet()

__STATIC_INLINE fsp_err_t R_BSP_PartNumberGet

(

bsp_part_number_t *const

p_part_number

)

Get part number for this device.

Parameters

[out]

p_part_number

Memory address to return MCU's part number to.

Return values

FSP_SUCCESS	Part number information stored.
FSP_ERR_ASSERTION	The parameter p_part_number is NULL.
FSP_ERR_NOT_FOUND	An error occurred when retrieving data from part number register.

R_BSP_SoftwareDelay()

void R_BSP_SoftwareDelay	(	uint32_t	delay,
		bsp_delay_units_t	units
	)

Delay for at least the specified duration in units and return.

Parameters

[in]	delay	The number of 'units' to delay.
[in]	units	The 'base' (bsp_delay_units_t) for the units specified. Valid values are: BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS, BSP_DELAY_UNITS_MICROSECONDS. For example: At 1 MHz one cycle takes 1 microsecond (.000001 seconds). At 12 MHz one cycle takes 1/12 microsecond or 83 nanoseconds. Therefore one run through bsp_prv_software_delay_loop() takes: ~ (83 * BSP_DELAY_LOOP_CYCLES) or 332 ns. A delay of 2 us therefore requires 2000ns/332ns or 6 loops.

The 'theoretical' maximum delay that may be obtained is determined by a full 32 bit loop count and the system clock rate. @120MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 120000000) = 143 seconds. @32MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 32000000) = 536 seconds

Note that requests for very large delays will be affected by rounding in the calculations and the actual delay achieved may be slightly longer. @32 MHz, for example, a request for 532 seconds will be closer to 536 seconds.

Note also that if the calculations result in a loop_cnt of zero, the bsp_prv_software_delay_loop() function is not called at all. In this case the requested delay is too small (nanoseconds) to be carried out by the loop itself, and the overhead associated with executing the code to just get to this point has certainly satisfied the requested delay.

Note

This function calls bsp_cpu_clock_get() which ultimately calls R_CGC_SystemClockFreqGet() and therefore requires that the BSP has already initialized the CGC (which it does as part of the Sysinit). Care should be taken to ensure this remains the case if in the future this function were to be called as part of the BSP initialization.

This function will delay for at least the specified duration. Due to overhead in calculating the correct number of loops to delay, very small delay values (generally 1-5 microseconds) may be significantly longer than specified. Approximate overhead for this function is as follows:

• RXv3: 35 - 43 cycles

If more accurate microsecond timing must be performed in software it is recommended to use bsp_prv_software_delay_loop() directly. In this case, use BSP_DELAY_LOOP_CYCLES or BSP_DELAY_LOOPS_CALCULATE() to convert a calculated delay cycle count to a number of software delay loops.

Delays may be longer than expected when compiler optimization is turned off.

R_BSP_GroupIrqWrite()

fsp_err_t R_BSP_GroupIrqWrite	(	bsp_grp_irq_nmi_t	irq,
		void(*)(bsp_grp_irq_nmi_t irq)	p_callback
	)

Register a callback function for supported interrupts. If NULL is passed for the callback argument then any previously registered callbacks are unregistered.

Parameters

[in]	irq	Interrupt for which to register a callback.
[in]	p_callback	Pointer to function to call when interrupt occurs.

Return values

FSP_SUCCESS	Callback registered
FSP_ERR_ASSERTION	Callback pointer is NULL

bsp_nmi_handler()

void bsp_nmi_handler

(

void

)

Non-maskable interrupt handler. This exception is defined by the BSP, unlike other system exceptions, because there are many sources that map to the NMI exception.

R_BSP_GroupIrqCheck()

bool R_BSP_GroupIrqCheck

(

uint8_t

irq

)

Non-maskable interrupt handler.

R_BSP_GetCurrentIFlagState()

uint32_t R_BSP_GetCurrentIFlagState

(

void

)

Provides the current I flag state on PSW register.

Return values

0	Disabled interrupts.
1	Enabled interrupts.

R_BSP_SetIFlagState()

void R_BSP_SetIFlagState

(

uint32_t

interrupt_mask

)

Set I flag state on PSW register. If this flag is 0, all interrupts are disabled.

Parameters

[in]

interrupt_mask

Value to set to the I-flag.

R_BSP_GetCurrentIpl()

uint32_t R_BSP_GetCurrentIpl

(

void

)

Get current interrupt priority level from PSW register.

Returns

Returns the value of interrupt priority level (IPL) currently registered in PSW.

R_BSP_SetIpl()

void R_BSP_SetIpl

(

uint32_t

interrupt_mask_level

)

Set IPL state on PSW register. If the passed interrupt priority level (IPL) is maximum, all interrupts are disabled. If the passed IPL is less than the maximum, interrupts which IPL is above the set value will be processed.

Parameters

[in]

interrupt_mask_level

Interrupt priority to be masked.

R_BSP_IrqIsEnabled()

uint32_t R_BSP_IrqIsEnabled

(

IRQn_Type const

irq

)

Get interrupt request enable status.

Parameters

[in]

irq

The IRQ to get interrupt request enable. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.

Return values

0	Interrupt request is disabled.
1	Interrupt request is enabled.

Warning

Do not call this function for system exceptions where the IRQn_Type value is < 0.

R_BSP_IrqStatusClear()

void R_BSP_IrqStatusClear

(

IRQn_Type

irq

)

Clear the interrupt status flag (IR) for a given interrupt. When an interrupt is triggered the IR bit is set. If it is not cleared in the ISR then the interrupt will trigger again immediately.

Parameters

[in]

irq

Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.

Warning

Do not call this function for system exceptions where the IRQn_Type value is < 0.

R_BSP_IrqClearPending()

void R_BSP_IrqClearPending

(

IRQn_Type

irq

)

Clear the interrupt status flag (IR) for a given interrupt and clear the ICU pending interrupt.

Parameters

[in]

irq

Interrupt for which to clear the IR bit. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.

Warning

Do not call this function for system exceptions where the IRQn_Type value is < 0.

R_BSP_IrqCfg()

void R_BSP_IrqCfg	(	IRQn_Type const	irq,
		uint32_t	priority,
		void *	p_context
	)

Sets the interrupt priority and context.

Parameters

[in]	irq	The IRQ to configure.
[in]	priority	ICU priority of the interrupt
[in]	p_context	The interrupt context is a pointer to data required in the ISR.

Warning

Do not call this function for system exceptions where the IRQn_Type value is < 0.

R_BSP_IrqEnableNoClear()

void R_BSP_IrqEnableNoClear

(

IRQn_Type const

irq

)

Enable the IRQ in the ICU (Without clearing the pending bit).

Parameters

[in]

irq

The IRQ to enable. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.

Warning

Do not call this function for system exceptions where the IRQn_Type value is < 0.

R_BSP_IrqEnable()

void R_BSP_IrqEnable

(

IRQn_Type const

irq

)

Clears pending interrupts in the ICU, then enables the interrupt.

Parameters

[in]

irq

Interrupt for which to clear the IR bit and enable in the ICU. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.

Warning

Do not call this function for system exceptions where the IRQn_Type value is < 0.

R_BSP_IrqDisable()

void R_BSP_IrqDisable

(

IRQn_Type const

irq

)

Disables interrupts in the ICU.

Parameters

[in]

irq

The IRQ to disable in the ICU. Note that the enums listed for IRQn_Type are only those for the Cortex Processor Exceptions Numbers.

Warning

Do not call this function for system exceptions where the IRQn_Type value is < 0.

R_BSP_IrqCfgEnable()

void R_BSP_IrqCfgEnable	(	IRQn_Type const	irq,
		uint32_t	priority,
		void *	p_context
	)

Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt.

Parameters

[in]	irq	Interrupt number.
[in]	priority	ICU priority of the interrupt
[in]	p_context	The interrupt context is a pointer to data required in the ISR.

Warning

Do not call this function for system exceptions where the IRQn_Type value is < 0.

R_BSP_RegisterProtectEnable()

void R_BSP_RegisterProtectEnable

(

bsp_reg_protect_t

regs_to_protect

)

Enable register protection. Registers that are protected cannot be written to. Register protection is enabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR).

Parameters

[in]

regs_to_protect

Registers which have write protection enabled.

R_BSP_RegisterProtectDisable()

void R_BSP_RegisterProtectDisable

(

bsp_reg_protect_t

regs_to_unprotect

)

Disable register protection. Registers that are protected cannot be written to. Register protection is disabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR).

Parameters

[in]

regs_to_unprotect

Registers which have write protection disabled.

Variable Documentation

BSP_SECTION_EARLY_INIT

uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT

System Clock Frequency (Core Clock)