RX Flexible Software Package Documentation  Release v1.0.0

 
Functions | Macros | Enumerations
RX74M
BSP » MCU Board Support Package

Functions

void bsp_selectable_irq_cfg (void)
 
__STATIC_INLINE void bsp_set_selectable_irq_cfg (uint16_t *const p_base_addr, bsp_interrupt_event_t const *const p_selectable_irq_table, uint32_t size)
 
__STATIC_INLINE uint8_t bsp_get_interrupt_priority (uint8_t irq)
 Get the interrupt priority register number from the IRQ. More...
 

Detailed Description

Build Time Configurations for rx74m_fsp

The following build time configurations are defined in fsp_cfg/bsp/bsp_mcu_family_cfg.h:

ConfigurationOptionsDefaultDescription
SDRAM > Timings > tRAS (cycles)
  • 1 cycles
  • 2 cycles
  • 3 cycles
  • 4 cycles
  • 5 cycles
  • 6 cycles
  • 7 cycles
6 cycles Row Active Interval
SDRAM > Timings > tRCD (cycles)
  • 1 cycles
  • 2 cycles
  • 3 cycles
  • 4 cycles
2 cycles Row Column Latency
SDRAM > Timings > tRP (cycles)
  • 1 cycles
  • 2 cycles
  • 3 cycles
  • 4 cycles
  • 5 cycles
  • 6 cycles
  • 7 cycles
  • 8 cycles
2 cycles Row Precharge Interval
SDRAM > Timings > tWR (cycles)
  • 1 cycles
  • 2 cycles
2 cycles Write Recovery Interval
SDRAM > Timings > tCL (cycles)
  • 1 cycles
  • 2 cycles
  • 3 cycles
3 cycles Column Latency
SDRAM > Timings > tRFC (cycles)tRFC must be between 2 and 4096 cycles1171 Auto-Refresh Request Interval Setting
SDRAM > Timings > tREFW (cycles)Refer to the RX Configuration tool for available options.5 cycles Auto-Refresh Cycle/Self-Refresh Clearing Cycle Count Setting.
SDRAM > Initialization > Auto-Refresh Interval (ARFI)Refer to the RX Configuration tool for available options.5 cycles Specifies the interval at which the auto-refresh commands are issued in the SDRAM initialization sequence.
SDRAM > Initialization > Auto-Refresh Count (ARFC)Refer to the RX Configuration tool for available options.2 times Specifies the number of times auto-refresh is to be performed in the SDRAM initialization sequence.
SDRAM > Initialization > Precharge Cycle Count (PRC)
  • 3 cycles
  • 4 cycles
  • 5 cycles
  • 6 cycles
  • 7 cycles
  • 8 cycles
  • 9 cycles
  • 10 cycles
3 cycles Specifies the number of precharged cycles in the SDRAM initialization sequence.
SDRAM > SDRAM Support
  • Enabled
  • Disabled
Disabled If enabled, SDRAM will be initialized and configured by the BSP with the provided settings.
SDRAM > Address Multiplex Shift
  • 8-bit shift
  • 9-bit shift
  • 10-bit shift
  • 11-bit shift
8-bit shift Selects the size of the shift towards the lower half of the row address in row address/column address multiplexing.
SDRAM > Endian Mode
  • Endian of SDRAM address space is the same as the endian of operating mode.
  • Endian of SDRAM address space is not the endian of operating mode.
Endian of SDRAM address space is the same as the endian of operating mode. Specifies the endianness of the SDRAM address space. See HWM for full list of constraints when using Big Endian.
SDRAM > Continuous Access Mode
  • Enabled
  • Disabled
Enabled If enabled, SDRAM continuous access mode will be enabled.
SDRAM > Bus Width
  • 8-bit
  • 16-bit
  • 32-bit
16-bit Specifies the data bus width for SDRAM.
Clocks > HOCO FLL Function
  • Enabled
  • Disabled
Disabled Setting this option to Enabled improves HOCO accuracy significantly by using the subclock, but incurs certain restrictions.

The FLL function requires the subclock oscillator to be running and stabilized. When enabled and running the PLL or system clock from HOCO, the BSP will wait for both the Subclock Stabilization Time as well as the FLL Stabilization Time when setting up clocks at startup.

When FLL is enabled Software Standby and Deep Software Standby modes are not available.
Clocks > Clock Settling Delay
  • Enabled
  • Disabled
Enabled Setting this option to Enabled will insert delays for clocking scaling and transitions to ensure voltage supply stability. See the RX74M HWM (R01UH1055) section 9.11.1 for details.
Clocks > Sleep Mode Entry and Exit Delays
  • Enabled
  • Disabled
Enabled Setting this option to Enabled will insert delays before and after entering sleep modes to ensure voltage supply stability.
Clocks > RTOS Sleep Mode Entry and Exit Delays
  • Enabled
  • Disabled
Enabled Setting this option to Enabled will insert delays before and after WFI calls in the RTOS to ensure voltage supply stability.
Clocks > Settling Delay (us)Unit must be a non-negative integer150 Specifies the length of the delay to be used for the Clock settling, Sleep mode, and MSTP change delays.
Clocks > Main Clock Oscillator Drive Capability
  • Auto
  • 8MHz
  • 8MHz to 24MHz
  • 8MHz to 48MHz
Auto Main oscillator drive setting. Auto uses FSP default based on XTAL frequency.
Cache settings > Data cache
  • Enabled
  • Disabled
Disabled Enable limited D-Cache support. See BSP usage notes for limitations.
Cache settings > Instruction cache
  • Enabled
  • Disabled
Disabled Enable limited I-Cache support. See BSP usage notes for limitations.
Security > Exceptions > Exception Response
  • Interrupt
  • Reset
Interrupt Specifies the behavior when an access violation is detected. This exception is generated when an access to a Secure area from a Non-Secure master is detected.
This setting is only valid when building projects with ProtectZone.
Security > Exceptions > NMI Target
  • Secure State
  • Non-Secure State
Non-Secure State Defines the security attributes of the NMI exception.
This setting is only valid when building projects with ProtectZone.
Security > BUS Accessibility > Bus Security Attribution Register A
  • Secure State
  • Non-Secure State
Non-Secure State Defines the security attributes for the arbitration and throughput control registers.
This setting is only valid when building projects with ProtectZone.
Security > BUS Accessibility > Bus Security Attribution Register B
  • Secure State
  • Non-Secure State
Non-Secure State Defines the security attributes of registers related to bus errors.
This setting is only valid when building projects with ProtectZone.
Security > BUS Accessibility > Bus Security Attribution Register C
  • Secure State
  • Non-Secure State
Non-Secure State Defines the security attributes for the SDRAM/CSC control registers.
This setting is only valid when building projects with ProtectZone.
Security > SRAM Accessibility > SRAM0 Protection
  • Secure State
  • Non-Secure State
Non-Secure State Define the security attributes for SRAMCR0, SRAMECCRGN0, SRAMESCLR.CLR00, and SRAMESCLR.CLR01.
This setting is only valid when building projects with ProtectZone.
Security > SRAM Accessibility > SRAM1 Protection
  • Secure State
  • Non-Secure State
Non-Secure State Define the security attributes for SRAMCR1, SRAMECCRGN1, SRAMESCLR.CLR10, and SRAMESCLR.CLR11.
This setting is only valid when building projects with ProtectZone.
Security > LRAM Accessibility > LRAM Protection
  • Secure State
  • Non-Secure State
Non-Secure State Defines the security attributes of LRMCRx and LRMESCLR.
This setting is only valid when building projects with ProtectZone.
Security > Number of SSC Table Entries11 The number of SSC Table Entries used by the ProtectZone hypervisor.
Security > Cache Accessibility
  • Secure State
  • Non-Secure State
Non-Secure State Defines the security attributes of the cash registers.
This setting is only valid when building projects with ProtectZone.
Security > Branch Instruction Processing Accessibility
  • Secure State
  • Non-Secure State
Non-Secure State Defines the security attributes of the Branch Instruction Processing Accelerator registers.
This setting is only valid when building projects with ProtectZone.
Security > System Reset Status Accessibility
  • Secure State
  • Non-Secure State
Non-Secure State Defines the security attributes for the Reset Status Registers (RSTSRn) and Reset Output Status Registers (ROUTSRn).
This setting is only valid when building projects with ProtectZone.
Security > Battery Backup Accessibility
  • Secure State
  • Non-Secure State
Non-Secure State Defines the security attributes of the battery backup register.
This setting is only valid when building projects with ProtectZone.
Security > Uninitialized Non-Secure Application Fallback
  • Enable Uninitialized Non-Secure Application Fallback
  • Disable Uninitialized Non-Secure Application Fallback
Enable Uninitialized Non-Secure Application Fallback If enabled, the secure application checks if the non-secure application has been programmed in non-secure Code MRAM before branching. If the non-secure application has not been programmed, then the secure application branches to an infinite loop in non-secure RAM.
I/O Ports > Voltage Mode > VCC
  • Low (VCC < 2.7 V)
  • High (VCC >= 2.7 V)
High (VCC >= 2.7 V) When VCC is lower than 2.7 V, set VCC I/O Ports Voltage Mode to Low.
Enable inline BSP IRQ functions
  • Enabled
  • Disabled
Enabled Using static inline functions will slightly increase code size, but will slightly decrease cycles taken in ISRs in return.
Main Oscillator Wait Time
  • 3 cycles
  • 35 cycles
  • 67 cycles
  • 131 cycles
  • 259 cycles
  • 547 cycles
  • 1059 cycles
  • 2147 cycles
  • 4291 cycles
  • 8163 cycles
8163 cycles Number of cycles to wait for the main oscillator clock to stabilize.
Prefetch Buffer
  • Enabled
  • Disabled
Disabled Enabling this option enables Prefetch buffer function in the BSP.

Macros

#define BSP_ELC_PERIPHERAL_MASK
 

Enumerations

enum  elc_peripheral_t
 
enum  elc_software_event_t
 
enum  elc_interrupt_t
 
enum  icu_event_t
 
enum  bsp_grp_irq_t
 

Macro Definition Documentation

◆ BSP_ELC_PERIPHERAL_MASK

#define BSP_ELC_PERIPHERAL_MASK

Positions of event link set registers (ELSRs) available on this MCU

Enumeration Type Documentation

◆ elc_peripheral_t

enum elc_peripheral_t

Possible peripherals to be linked to event signals

Note
This list is device specific.

◆ elc_software_event_t

enum elc_software_event_t

Possible software events

Note
This list is device specific.
Enumerator
ELC_SOFTWARE_EVENT_0 

Software event 0.

ELC_SOFTWARE_EVENT_1 

Software event 1.

ELC_SOFTWARE_EVENT_0 

Software event 0.

ELC_SOFTWARE_EVENT_1 

Software event 1.

ELC_SOFTWARE_EVENT_2 

Software event 2.

ELC_SOFTWARE_EVENT_3 

Software event 3.

ELC_SOFTWARE_EVENT_0 

Software event 0.

ELC_SOFTWARE_EVENT_1 

Software event 1.

ELC_SOFTWARE_EVENT_2 

Software event 2.

ELC_SOFTWARE_EVENT_3 

Software event 3.

◆ elc_interrupt_t

enum elc_interrupt_t

Event link possible interrupts

Enumerator
ELC_INTERRUPT_1 

Interrupt 1.

ELC_INTERRUPT_2 

Interrupt 2.

ELC_INTERRUPT_3 

Interrupt 3.

ELC_INTERRUPT_4 

Interrupt 4.

◆ icu_event_t

enum icu_event_t

Events to be used with the IELSR register to link interrupt events to the NVIC

Note
This list is device specific.

◆ bsp_grp_irq_t

enum bsp_grp_irq_t

Which interrupts can have callbacks registered.

Function Documentation

◆ bsp_selectable_irq_cfg()

void bsp_selectable_irq_cfg ( void  )

Configure selectable irq depend on RX MCU. RX74M has three selectable irq register(SLIXR, SLIXR).

◆ bsp_set_selectable_irq_cfg()

__STATIC_INLINE void bsp_set_selectable_irq_cfg ( uint16_t *const  p_base_addr,
bsp_interrupt_event_t const *const  p_selectable_irq_table,
uint32_t  size 
)

Set selectable irq table value that user setting to selectable irq register.

Parameters
[out]p_base_addrThe p_base_addr is write base address of selectable irq register.
[in]p_selectable_irq_tableThe p_selectable_irq_table is uesr setting selectable irq table.
[in]sizeThe size is read range of p_selectable_irq_table array.
Warning
Do not call this function with values where size over p_selectable_irq_table allowd range.

◆ bsp_get_interrupt_priority()

__STATIC_INLINE uint8_t bsp_get_interrupt_priority ( uint8_t  irq)

Get the interrupt priority register number from the IRQ.

Parameters
[in]irqThe IRQ to get the the interrupt priority register number
Returns
interrupt priority register number