Phase Counting Interface (r_pcif)

Functions
fsp_err_t	R_PCIF_Open (pcif_ctrl_t *const p_ctrl, pcif_cfg_t const *const p_cfg)
fsp_err_t	R_PCIF_Stop (pcif_ctrl_t *const p_ctrl, pcif_stop_mode_t stop_mode)
fsp_err_t	R_PCIF_Start (pcif_ctrl_t *const p_ctrl)
fsp_err_t	R_PCIF_SetCounter (pcif_ctrl_t *const p_ctrl, pcif_phc_counter_info_t const *const p_counter_data, bool reset_counter)
fsp_err_t	R_PCIF_StatusGet (pcif_ctrl_t *const p_ctrl, pcif_status_t *const p_status)
fsp_err_t	R_PCIF_SoftwareEventGenerate (pcif_ctrl_t *const p_ctrl)
fsp_err_t	R_PCIF_Close (pcif_ctrl_t *const p_ctrl)

Detailed Description

Driver for the PCIF peripheral on RX MCUs. This module implements the PCIF Interface.

Overview

The Phase Counting Interface (PCIF) outputs A-phase, B-phase, and Z-phase signals for encoder-style motor control systems. The PCIF has two operating modes:

• Phase Counting Mode: Generates ABZ output signals from position data, edge count data, and carrier period events supplied by software or ELC.
• Incremental Mode: Receives external ABZ encoder signals and outputs ABZ signals with a configured resolution ratio.

Features

• Generate ABZ outputs from angle or position information configured by software.
• Output ABZ pulses with reduced resolution from an external encoder signal.
• Provide position feedback information to the host controller.
• Generate ABZ pulses without external components such as an FPGA.
• Support Phase Counting mode.
  • Use internal or ELC carrier period events to update edge data.
  • Update edge data and position data at run time.
  • Notify the user callback when a carrier period occurs or an error is detected.
  • Set position data at run time.
• Support Incremental mode.
  • Configure the output resolution ratio for an external encoder signal.
  • Generate Z-phase output or clear the position counter by software trigger.
  • Use crest/trough ELC events to clear internal counters or generate Z-phase output.
• Support Z-phase generation in both modes.
• Support ABZ-phase output inversion in both modes.
• Start PCIF operation by API.
• Stop PCIF operation immediately or by phase-counting synchronized stop.
• Get current operation state and position monitor information at run time.

Configuration

Build Time Configurations for r_pcif

The following build time configurations are defined in fsp_cfg/r_pcif_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Timer Support	Enabled Disabled	Disabled	If select whether to use Timer module in the build.

Configurations for Motor > Phase-Counting Interface (r_pcif)

This module can be added to the Stacks tab via New Stack > Motor > Phase-Counting Interface (r_pcif).

Configuration	Options	Default	Description
General > Polarity > A-phase	Positive Negative	Positive	Select the polarity for A phase.
General > Polarity > B-phase	Positive Negative	Positive	Select the polarity for B phase.
General > Polarity > Z-phase	Positive Negative	Positive	Select the polarity for Z phase.
General > Name	Name must be a valid C symbol	g_pcif0	Module name.
General > Channel	Value must be an non-negative integer	0	Specify the PCIF channel.
General > Clock Source	MCU Specific Options		Select the clock source for the PCIF module.
General > Mode	Phase Counting Mode Incremental Mode	Phase Counting Mode	Select the clock source for the PCIF module.
General > Maximum Position	Manual Entry	0x10000	Specify The maximum value of the position counter.
Phase Counting Mode > ELC Support > Carrier Period Event Trigger Source	MCU Specific Options		Select external source that triggers the carrier period.
Phase Counting Mode > Initialize Edge Data > Start Position	Value must be a non-negative integer and less than max position	0	Set specify start counter position.
Phase Counting Mode > Initialize Edge Data > Edge Count Data	Value must be a signed 16-bit integer	0	Set the initial edge counter. This value must also be within +/- the generated carrier period count.
Phase Counting Mode > Error Detect > Error Carrier Period Detection	Disable Enable	Disable	Select carrier period error detection.
Phase Counting Mode > Error Detect > Error Edge Unprocessed Detection	Disable Enable	Disable	Select edge unprocessed error detection.
Phase Counting Mode > Error Detect > Error Edge Counting Overflow Detection	Disable Enable	Disable	Select edge counting overflow error detection.
Phase Counting Mode > Error Detect > Error Old Edge Detection	Disable Enable	Disable	Select old edge error detection.
Phase Counting Mode > Carrier Period	Manual Entry	500	Specify the carrier period in microseconds selected.
Phase Counting Mode > Carrier Period Event Difference Threshold	Value must be a non-negative integer in the 16-bit range	0x100	Allowable difference range of carrier period events. This value must be less than the generated carrier period count.
Phase Counting Mode > Carrier Period Adjustment Mode	Event Based Mode Register Based Mode	Register Based Mode	Carrier period adjustment mode selection.
Phase Counting Mode > Z Phase Width	Z-phase Width Disable Z-phase Width 1 Z-phase Width 2 Z-phase Width 3 Z-phase Width 4	Z-phase Width Disable	Select Z-phase width configuration.
Phase Counting Mode > Z Phase Sync	Z-phase Sync A Phase Z-phase Sync B Phase	Z-phase Sync A Phase	Select Z-phase synchronize configuration.
Phase Counting Mode > Edge Counter Clear	Disable Enable	Disable	Select automatic clear edge counter configuration.
Phase Counting Mode > Callback	Name must be a valid C symbol	NULL	A user callback function can be specified here. If this callback function is provided, it will be called from the interrupt service routine (ISR) each time the carrier period elapses
Incremental Mode > ELC Support > Crest Event Trigger Src	MCU Specific Options		Select external source that triggers the crest event.
Incremental Mode > ELC Support > Trough Event Trigger Src	MCU Specific Options		Select external source that triggers the trough event.
Incremental Mode > Downscale Resolution Ratio	Value must be from 1 to 64	1	Specify the downscale resolution ratio.
Incremental Mode > AB-Phase Input Mode	Mode 0 (AB phase pulse) Mode 1 (A phase pulse, B phase rotation direction) Mode 2 (Pulse switching)	Mode 0 (AB phase pulse)	Incremental AB phase input mode selection
Incremental Mode > AB-Phase Output Mode	Same as input AB phase pulse	Same as input	Incremental AB phase output mode selection
Incremental Mode > Z-Phase Output Mode	Immediate output A-phase synchronization B-phase synchronization Pulse synchronization	Immediate output	Incremental Z phase output mode selection
Incremental Mode > Z-Phase Output Minimum Cycle	Value must be from 1 to 256	1	Specify the minimum output cycle.
Incremental Mode > Z Phase Generate Sources	Counter-based Z-Phase Input Crest Event Trigger Trough Event Trigger Software Trigger		Select Z phase generate sources.
Incremental Mode > Clear Counter Sources	Z-Phase Input Crest Event Trigger Trough Event Trigger Software Trigger		Select counter clear sources.

Clock Configuration

PCIF uses CCLK as the core clock and CCLK_DIV as the output synchronization clock. CCLK can be selected from PCLKB or GPTCLK in the RX Configuration editor.

Configure the clocks so all HUM clock conditions are satisfied:

Clock	HUM range or limit
PCLKB	Maximum 75 MHz
CCLK	Maximum 200 MHz
CCLK_DIV	10 MHz to 20 MHz

The following relationships must also be satisfied:

• PCLKB >= 2 * CCLK_DIV
• PCLKB >= CCLK / 8

For example, the HUM maximum-frequency setting is PCLKB = 75 MHz, CCLK = 200 MHz, and CCLK_DIV = 20 MHz.

Pin Configuration

This module can use PCOUTAn, PCOUTBn, and PCOUTZn pins as output pins.

This module can use PCINAn, PCINBn, and PCINZn pins as input pins for encoder signals.

Usage Notes

General Operation

• Stop the PCIF before changing mode, polarity, position maximum, or other configuration registers that the HUM marks as rewrite-prohibited while SR.PCIFPS is 1.
• When using ELC events, start carrier period generation or crest/trough trigger generation only after the PCIF start flow has completed. HUM operation is not guaranteed if these events are input during start processing.
• Output inversion is configured by A/B/Z polarity settings and applies to both phase-counting and incremental modes.
• R_PCIF_StatusGet reports the PCIF operation state, rotation direction, and monitor values. In phase-counting mode, current_position_value is PHCPCMR.PHCPOSCNTM, position_write_value is PHCPCWDR.PHCPOSCNTWD, and input_counter_value is 0. In incremental mode, current_position_value is INCPCMR.INCOCNTM, input_counter_value is INCPCMR.INCICNTM, and position_write_value is 0.

Phase Counting Mode

Position And Edge Settings

• The number of edges per rotation can be set from 16 to 65,536 and must be a multiple of 4.
• The driver max_count_position field is the POSMAX register value. For an encoder with N edges per rotation, configure max_count_position = N - 1.
• The carrier period can be configured from 10 us to 3276 us. The generated carrier period count is expressed in CCLK_DIV cycles.
• The carrier period event difference threshold must be less than the carrier period count.
• The edge count written to PHCECR.PHCEDGCNT must be in the range -carrier_period_counts to +carrier_period_counts.

Carrier Period Control

There are two methods for controlling the carrier period:

• Event-based mode: Carrier period processing is triggered by carrier period event input from ELC.
• Register-based mode: Carrier period processing is generated from the configured PHCPERIODR.PHCPERIOD[15:0] value.

Set PHCPERIODR.PHCPERIOD[15:0] to the mean interval of carrier period events. If the long-term mean event interval differs from the register setting, edges may not be completely processed and may be lost during long-term operation.

Runtime Edge And Position Updates

R_PCIF_SetCounter writes the new edge count and can also write the new position value.

• When the PCIF is stopped, the new position value is reflected immediately.
• When the PCIF is running, the new position value is normally reflected at the next carrier period event.
• position_write_value from R_PCIF_StatusGet can be used to inspect the latest position write value.

Error Detection

Error detection is available only in phase-counting mode and must be enabled per error type in the configuration. If an error specified by PHCSR occurs, HUM operation is not guaranteed. Stop or reset the PCIF according to the phase-counting stop flow, clear the error state, and review the PCIF settings.

Incremental Mode

Input And Output Modes

PCIF supports the following incremental input/output combinations:

Input setting	Output setting	Input protocol mode	Output protocol mode
AB-phase pulse	Same as input	Mode 0	Mode 0
A-phase pulse, B-phase direction	Same as input	Mode 1	Mode 1
A-phase pulse, B-phase direction	AB-phase pulse	Mode 1	Mode 0
Pulse switching	Same as input	Mode 2	Mode 2
Pulse switching	AB-phase pulse	Mode 2	Mode 0

Note:

• Mode 0 uses AB-phase pulses.
• Mode 1 uses A-phase pulse and B-phase rotation direction.
• Mode 2 uses pulse switching, where A-phase toggles for forward rotation and B-phase toggles for reverse rotation.

Resolution And Position Monitor

The incremental resolution setting is encoded as INCRSL = ratio - 1. A setting of 0 outputs the same resolution as the input; a setting of 63 outputs 1/64 of the input resolution.

In incremental mode, the complete input position can be calculated from the monitor values returned by R_PCIF_StatusGet:

input_position = current_position_value * (resolution_ratio_setting + 1U) + input_counter_value;

Z-Phase Generation And Counter Clear

The following HUM restrictions are enforced by the driver:

• Counter-based Z-phase generation and Z-phase input generation cannot be enabled at the same time.
• Clear counter by Z-phase input cannot be enabled when counter-based Z-phase generation is enabled.
• A/B synchronized Z-phase output is valid only when the output protocol is Mode 0.
• Pulse synchronized Z-phase output is valid only when the output protocol is Mode 1 or Mode 2.

z_output_min_cycles extends the Z-phase output assertion period. A configured value of 0 means 1 CCLK_DIV cycle, and 255 means 256 CCLK_DIV cycles. While the Z-phase output assertion period is being extended, other Z-phase output conditions are ignored until the extension completes.

Input Toggle Interval

The input ABZ signal must meet the HUM minimum toggle interval:

Input protocol condition	Minimum required toggle interval
Mode 0	1 CCLK cycle + 1 CCLK_DIV cycle
Mode 1	1 CCLK cycle + 1 CCLK_DIV cycle
Mode 2 with constant rotation direction	1 CCLK cycle + 1 CCLK_DIV cycle
Mode 2 when the rotation direction changes	1 CCLK cycle + 2 CCLK_DIV cycles

If the input signal does not satisfy these intervals, edges may be lost.

Limitations

• Edge count max value setting in PHCECR: According to the HUM, PHCECR.PHCEDGCNT[15:0] can represent values from -PHCPERIOD[15:0] to +PHCPERIOD[15:0]. The FSP API uses int16_t for edge count data, so values outside the signed 16-bit range cannot be passed through the API.

Examples

PCIF Basic Example

This is a basic example of minimal use of the PCIF in an application.

void basic_example (void)
{
    fsp_err_t err;


    /* Initialize the PCIF module */
    err = R_PCIF_Open(&g_pcif0_ctrl, &g_pcif0_cfg);


    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);

    /* Initialize error flag and success flag to false.
     * This gets set to true in PCIF callback upon error occurs. */
    g_error_flag   = false;
    g_success_flag = false;


    /* Start PCIF Operation*/
    err = R_PCIF_Start(&g_pcif0_ctrl);
    assert(FSP_SUCCESS == err);


    uint32_t timeout_ms = PCIF_DELAY_MS;

    /* Since there is nothing else to do, block until Callback triggers*/
    while ((true != g_success_flag) && (true != g_error_flag) && timeout_ms)
    {
        R_BSP_SoftwareDelay(1U, BSP_DELAY_UNITS_MILLISECONDS);
        timeout_ms--;
    }

    if (0U == timeout_ms)
    {
        __BKPT(0);
    }


    /* Stop PCIF Operation*/
    err = R_PCIF_Stop(&g_pcif0_ctrl, PCIF_STOP_MODE_IMMEDIATE);
    assert(FSP_SUCCESS == err);


    err = R_PCIF_Close(&g_pcif0_ctrl);
    assert(FSP_SUCCESS == err);

}

PCIF Callback

This is an example of PCIF callback.

/* Example callback called when pcif carrier period occurs. */
void pcif_callback (pcif_callback_args_t * p_args)
{
    if (PCIF_ERROR_NONE == p_args->error)
    {
        /* User can call R_PCIF_SetCounter to set edge data for next carrier period */
        R_PCIF_SetCounter(&g_pcif0_ctrl, &g_counter_data, true);
        g_success_flag = true;
    }
    else                               /* Error occur */
    {
        g_error_flag = true;
    }

}

PCIF Phase Counting Mode Example

This is an example of PCIF phase counting mode.

/* Example callback called when pcif carrier period occurs. */
void pcif_phase_counting_callback (pcif_callback_args_t * p_args)
{
    if (PCIF_ERROR_NONE == p_args->error)
    {
        g_success_flag = true;

        /* Do something with p_context if any */
    }
    else                               /* Error occur */
    {
        g_error_flag = true;

        /* Can check which type of error here to do something ...*/
    }
}

void pcif_phase_counting_example (void)
{
    fsp_err_t err;

    /* Initialize the PCIF module */
    err = R_PCIF_Open(&g_pcif0_ctrl, &g_pcif0_cfg);
    assert(FSP_SUCCESS == err);

    /* Initialize error flag to false. This gets set to true in PCIF callback upon error occurs. */
    g_error_flag   = false;
    g_success_flag = false;

    /* Start PCIF Operation*/
    err = R_PCIF_Start(&g_pcif0_ctrl);
    assert(FSP_SUCCESS == err);


    /* Set edge */
    for (int i = 0; i < 5; i++)
    {
        err = R_PCIF_SetCounter(&g_pcif0_ctrl, &g_arr_counter_data[i], false);
        assert(FSP_SUCCESS == err);

        uint32_t timeout_ms = PCIF_DELAY_MS;

        /* Since there is nothing else to do, block until Callback triggers*/
        while ((true != g_success_flag) && (true != g_error_flag) && timeout_ms)
        {
            R_BSP_SoftwareDelay(1U, BSP_DELAY_UNITS_MILLISECONDS);
            timeout_ms--;
        }

        /* If timeout */
        if (0U == timeout_ms)
        {
            __BKPT(0);
        }
        else if (true == g_error_flag)
        {
            break;
        }
        else
        {
            /* Do next loop*/
            g_success_flag = false;
            g_error_flag   = false;
        }
    }


    /* If error occurs, PCIF will automatically stop operation */
    if (true != g_error_flag)
    {
        /* Stop PCIF Operation if no error occurs*/
        err = R_PCIF_Stop(&g_pcif0_ctrl, PCIF_STOP_MODE_IMMEDIATE);
        assert(FSP_SUCCESS == err);
    }

    /* Deinitialize the PCIF module */
    err = R_PCIF_Close(&g_pcif0_ctrl);
    assert(FSP_SUCCESS == err);
}

PCIF Edge Data Update Example

This is an example of updating edge data in the PCIF main process.

    if (PCIF_ERROR_NONE == p_args->error)
    {
        /* User can call R_PCIF_SetCounter to set edge data for next carrier period */
        R_PCIF_SetCounter(&g_pcif0_ctrl, &g_counter_data, true);
        g_success_flag = true;
    }
    else                               /* Error occur */
    {
        g_error_flag = true;
    }

PCIF Basic Incremental Mode Example

This is an example of PCIF incremental mode.

void pcif_incremental_example (void)
{
    fsp_err_t err;

    /* Initialize the PCIF module */
    err = R_PCIF_Open(&g_pcif0_ctrl, &g_pcif0_cfg);
    assert(FSP_SUCCESS == err);

    /* Start PCIF Operation*/
    err = R_PCIF_Start(&g_pcif0_ctrl);
    assert(FSP_SUCCESS == err);

    pcif_status_t pcif_status;
    err = R_PCIF_StatusGet(&g_pcif0_ctrl, &pcif_status);
    assert(FSP_SUCCESS == err);

    /* Do something with data in pcif_status.
     * In incremental mode, current_position_value is INCOCNTM and input_counter_value is INCICNTM.
     * In phase-counting mode, current_position_value is PHCPOSCNTM and position_write_value is PHCPCWDR. */



    /* Reset counter or Z phase generate */
    err = R_PCIF_SoftwareEventGenerate(&g_pcif0_ctrl);
    assert(FSP_SUCCESS == err);

    /* Check if the counter is reset? or the Z phase is generated?*/


    /* Stop PCIF Operation */
    /* With incremental mode, stop mode always is PCIF_STOP_MODE_IMMEDIATE */
    err = R_PCIF_Stop(&g_pcif0_ctrl, PCIF_STOP_MODE_IMMEDIATE);
    assert(FSP_SUCCESS == err);

    /* Deinitialize the PCIF module */
    err = R_PCIF_Close(&g_pcif0_ctrl);
    assert(FSP_SUCCESS == err);
}

Data Structures
struct	pcif_extended_cfg_t
struct	pcif_instance_ctrl_t

Macros
#define	PCIF_INC_RESOLUTION_RATIO_SETTING_MAX
#define	PCIF_INC_Z_PHASE_GEN_COUNTER_INPUT_PROHIBITED_MASK
#define	PCIF_INC_COUNTER_CLEAR_Z_GEN_PROHIBITED_MASK

Enumerations
enum	pcif_phc_error_detection_enable_t
enum	pcif_phc_z_phase_width_t
enum	pcif_phc_z_phase_sync_t
enum	pcif_phc_carrier_period_mode_t
enum	pcif_phc_counter_clear_mode_t
enum	pcif_inc_ab_input_mode_t
enum	pcif_inc_ab_output_mode_t
enum	pcif_inc_z_output_mode_t
enum	pcif_inc_z_generate_source_t
enum	pcif_inc_position_counter_clear_t

---

Data Structure Documentation

pcif_extended_cfg_t

struct pcif_extended_cfg_t

Extended configuration structure for PCIF.

Data Fields
pcif_phc_z_phase_width_t	z_width	Set width Z phase. Setting for Phase Counting mode Setting Z phase
pcif_phc_z_phase_sync_t	z_sync	Set phase (A/B) to sync Z phase.
pcif_phc_carrier_period_mode_t	carrier_period_mode	Set carrier period mode. Carrier Period Setting
uint16_t	carrier_period_diff_threshold	Carrier period difference threshold in CCLK_DIV cycles.
uint16_t	carrier_period_counts	Carrier period in CCLK_DIV cycles.
pcif_phc_counter_clear_mode_t	counter_clear_mode	Set automatic clear counter mode. Edge Counter Setting
pcif_phc_counter_info_t *	p_init_counter_data	Set initial counter data.
pcif_phc_error_detection_enable_t	error_carrier_period_enable	Set carrier period error detection enable. Error detection enable setting
pcif_phc_error_detection_enable_t	error_edge_count_enable	Set edge count error detection enable.
pcif_phc_error_detection_enable_t	error_edge_count_overflow_enable	Set edge count overflow error detection enable.
pcif_phc_error_detection_enable_t	error_old_edge_count_enable	Set old edge count error detection enable.
uint8_t	resolution_ratio_setting	Output resolution: 0 = x1/1, N = x1/(N + 1), max 0x3F. Setting for Incremental mode
pcif_inc_ab_input_mode_t	ab_input_mode	Set incremental input mode. Setting A/B phase
pcif_inc_ab_output_mode_t	ab_output_mode	Set incremental output mode.
uint8_t	z_output_min_cycles	Minimum cycle Z output: 0 = 1 CCLK_DIV cycle, 0xFF = 256 cycles. Setting Z Phase
pcif_inc_z_generate_source_t	z_generate_source	Set Z phase generate source.
pcif_inc_z_output_mode_t	z_output_mode	Set incremental Z phase output mode.
pcif_inc_position_counter_clear_t	position_clear_source	Set incremental position counter clear mode.

pcif_instance_ctrl_t

struct pcif_instance_ctrl_t

Control block used by driver. DO NOT INITIALIZE. Initialization occurs when pcif_api_t::open is called.

Macro Definition Documentation

PCIF_INC_RESOLUTION_RATIO_SETTING_MAX

#define PCIF_INC_RESOLUTION_RATIO_SETTING_MAX

Maximum incremental mode resolution ratio setting (INCRSL[5:0]).

PCIF_INC_Z_PHASE_GEN_COUNTER_INPUT_PROHIBITED_MASK

#define PCIF_INC_Z_PHASE_GEN_COUNTER_INPUT_PROHIBITED_MASK

Z phase generation sources that cannot be enabled together.

PCIF_INC_COUNTER_CLEAR_Z_GEN_PROHIBITED_MASK

#define PCIF_INC_COUNTER_CLEAR_Z_GEN_PROHIBITED_MASK

Position clear source prohibited when counter-based Z phase generation is enabled.

Enumeration Type Documentation

pcif_phc_error_detection_enable_t

enum pcif_phc_error_detection_enable_t

Error detection enable setting.

Enumerator
PCIF_PHC_ERROR_DETECTION_DISABLE	error detection disabled
PCIF_PHC_ERROR_DETECTION_ENABLE	error detection enabled

pcif_phc_z_phase_width_t

enum pcif_phc_z_phase_width_t

Z phase width config

Enumerator
PCIF_PHC_Z_WIDTH_DISABLE	Z Width = 0, output Z phase disabled.
PCIF_PHC_Z_WIDTH_1	Z Width = 1.
PCIF_PHC_Z_WIDTH_2	Z Width = 2.
PCIF_PHC_Z_WIDTH_3	Z Width = 3.
PCIF_PHC_Z_WIDTH_4	Z Width = 4.

pcif_phc_z_phase_sync_t

enum pcif_phc_z_phase_sync_t

Phase Counting mode Z phase sync

Enumerator
PCIF_PHC_SYNC_PHASE_A	Z phase sync with A PHASE.
PCIF_PHC_SYNC_PHASE_B	Z phase sync with B PHASE.

pcif_phc_carrier_period_mode_t

enum pcif_phc_carrier_period_mode_t

Phase Counting mode carrier cycle event difference adjustment mode

Enumerator
PCIF_PHC_CARRIER_PERIOD_MODE_EVENT_BASED	Carrier period is generated by ELC.
PCIF_PHC_CARRIER_PERIOD_MODE_REGISTER_BASED	Carrier period is generated by internal counter.

pcif_phc_counter_clear_mode_t

enum pcif_phc_counter_clear_mode_t

Phase Counting mode automatic clear counter mode

Enumerator
PCIF_PHC_COUNTER_CLEAR_DISABLE	Disable automatic clear edge count register.
PCIF_PHC_COUNTER_CLEAR_ENABLE	Enable automatic clear edge count register.

pcif_inc_ab_input_mode_t

enum pcif_inc_ab_input_mode_t

Incremental mode ABZ phase input

Enumerator
PCIF_INC_INPUT_AB_PHASE_PULSE	Input mode 0: AB phase pulse.
PCIF_INC_INPUT_A_PHASE_PULSE	Input mode 1: A phase pulse (B phase rotation direction)
PCIF_INC_INPUT_PULSE_SWITCHING	Input mode 2: Pulse switching.

pcif_inc_ab_output_mode_t

enum pcif_inc_ab_output_mode_t

Incremental mode AB phase output

Enumerator
PCIF_INC_OUTPUT_SAME_AS_INPUT	Output same as input.
PCIF_INC_OUTPUT_AB_PHASE_PULSE	Output AB phase pulse.

pcif_inc_z_output_mode_t

enum pcif_inc_z_output_mode_t

Incremental mode Z phase output

Enumerator
PCIF_INC_Z_OUTPUT_IMMEDIATE	Immediate output.
PCIF_INC_Z_OUTPUT_A_SYNC	A-phase synchronization.
PCIF_INC_Z_OUTPUT_B_SYNC	B-phase synchronization.
PCIF_INC_Z_OUTPUT_PULSE_SYNC	Pulse synchronization.

pcif_inc_z_generate_source_t

enum pcif_inc_z_generate_source_t

Incremental mode Z phase generate source

Enumerator
PCIF_INC_Z_PHASE_GEN_NONE	No generation of Z phase.
PCIF_INC_Z_PHASE_GEN_COUNTER	Generate Z phase from output/internal counter.
PCIF_INC_Z_PHASE_GEN_INPUT	Generate output Z phase from external input signal.
PCIF_INC_Z_PHASE_GEN_CREST	Generate output Z phase from crest event signal.
PCIF_INC_Z_PHASE_GEN_TROUGH	Generate output Z phase from trough event signal.
PCIF_INC_Z_PHASE_GEN_SOFTWARE	Generate output Z phase from software trigger.

pcif_inc_position_counter_clear_t

enum pcif_inc_position_counter_clear_t

Incremental position counter clear enable bit

Enumerator
PCIF_INC_COUNTER_CLEAR_NONE	Disable position counter clear.
PCIF_INC_COUNTER_CLEAR_INPUT	Clear position counter by Z input signal.
PCIF_INC_COUNTER_CLEAR_CREST	Clear position counter by crest event signal.
PCIF_INC_COUNTER_CLEAR_TROUGH	Clear position counter by trough event signal.
PCIF_INC_COUNTER_CLEAR_SOFTWARE	Clear position counter by software trigger.

Function Documentation

R_PCIF_Open()

fsp_err_t R_PCIF_Open	(	pcif_ctrl_t *const	p_ctrl,
		pcif_cfg_t const *const	p_cfg
	)

Initializes the pcif module and applies configurations. Implements pcif_api_t::open.

This function sets this clock divisor and the configurations specified in pcif_cfg_t.

Example:

    /* Initialize the PCIF module */
    err = R_PCIF_Open(&g_pcif0_ctrl, &g_pcif0_cfg);

Return values

FSP_SUCCESS	Successful open.
FSP_ERR_ALREADY_OPEN	The control structure is already opened.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	The channel requested in the p_cfg parameter is not available on this device.
FSP_ERR_ASSERTION	Parameter check failure due to one or more reasons below: Pointer p_api_ctrl or p_cfg is NULL. Extended parameter is NULL. Timer instance in p_cfg is NULL when timer support enabled Callback parameter is NULL when ELC support enabled.
FSP_ERR_INVALID_DATA	Parameter check failure due to one or more reasons below: Max count position does not meet “4 * N – 1" requirement. Value diff threshold is greater than or equal to value carrier period. Initial position is greater than max count position. Initial edge count is outside the carrier period range. Incremental resolution ratio is outside the hardware bit-field range. Prohibited incremental Z generation sources are enabled together. Prohibited incremental position clear source is enabled.

R_PCIF_Stop()

fsp_err_t R_PCIF_Stop	(	pcif_ctrl_t *const	p_ctrl,
		pcif_stop_mode_t	stop_mode
	)

Stop PCIF. Implements pcif_api_t::stop.

Example:

    /* Stop PCIF Operation*/
    err = R_PCIF_Stop(&g_pcif0_ctrl, PCIF_STOP_MODE_IMMEDIATE);
    assert(FSP_SUCCESS == err);

Return values

FSP_SUCCESS	Module successfully stops.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_PCIF_Start()

fsp_err_t R_PCIF_Start

(

pcif_ctrl_t *const

p_ctrl

)

Starts PCIF. Implements pcif_api_t::start.

Example:

    /* Start PCIF Operation*/
    err = R_PCIF_Start(&g_pcif0_ctrl);
    assert(FSP_SUCCESS == err);

Return values

FSP_SUCCESS	Timer successfully started.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.
FSP_ERR_IN_USE	Channel is running.

Returns

See Common Error Codes or lower level drivers for other possible return codes.

R_PCIF_SetCounter()

fsp_err_t R_PCIF_SetCounter	(	pcif_ctrl_t *const	p_ctrl,
		pcif_phc_counter_info_t const *const	p_counter_data,
		bool	reset_counter
	)

Set counter data in phase counting mode. Implements pcif_api_t::setCounter. Only used in phase counting mode. This function returns the PCIF information.

Example:

    /* Set edge */
    for (int i = 0; i < 5; i++)
    {
        err = R_PCIF_SetCounter(&g_pcif0_ctrl, &g_arr_counter_data[i], false);
        assert(FSP_SUCCESS == err);

        uint32_t timeout_ms = PCIF_DELAY_MS;

        /* Since there is nothing else to do, block until Callback triggers*/
        while ((true != g_success_flag) && (true != g_error_flag) && timeout_ms)
        {
            R_BSP_SoftwareDelay(1U, BSP_DELAY_UNITS_MILLISECONDS);
            timeout_ms--;
        }

        /* If timeout */
        if (0U == timeout_ms)
        {
            __BKPT(0);
        }
        else if (true == g_error_flag)
        {
            break;
        }
        else
        {
            /* Do next loop*/
            g_success_flag = false;
            g_error_flag   = false;
        }
    }

Return values

FSP_SUCCESS	Information successfully retrieved.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.
FSP_ERR_INVALID_MODE	The mode is not phase counting.
FSP_ERR_INVALID_DATA	The new position or edge count is invalid.

R_PCIF_StatusGet()

fsp_err_t R_PCIF_StatusGet	(	pcif_ctrl_t *const	p_ctrl,
		pcif_status_t *const	p_status
	)

Get PCIF status. Implements pcif_api_t::statusGet.

This function returns the PCIF status.

Example:

    pcif_status_t pcif_status;
    err = R_PCIF_StatusGet(&g_pcif0_ctrl, &pcif_status);
    assert(FSP_SUCCESS == err);

    /* Do something with data in pcif_status.
     * In incremental mode, current_position_value is INCOCNTM and input_counter_value is INCICNTM.
     * In phase-counting mode, current_position_value is PHCPOSCNTM and position_write_value is PHCPCWDR. */

Return values

FSP_SUCCESS	Status successfully retrieved.
FSP_ERR_ASSERTION	p_ctrl or p_status was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_PCIF_SoftwareEventGenerate()

fsp_err_t R_PCIF_SoftwareEventGenerate

(

pcif_ctrl_t *const

p_ctrl

)

Software reset PCIF. Implements pcif_api_t::softwareEventGenerate.

This function generates a software event to reset the PCIF.

Example:

    /* Reset counter or Z phase generate */
    err = R_PCIF_SoftwareEventGenerate(&g_pcif0_ctrl);
    assert(FSP_SUCCESS == err);

    /* Check if the counter is reset? or the Z phase is generated?*/

Return values

FSP_SUCCESS	Software event successfully generated.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.
FSP_ERR_INVALID_MODE	The mode is not incremental.

R_PCIF_Close()

fsp_err_t R_PCIF_Close

(

pcif_ctrl_t *const

p_ctrl

)

Close PCIF. Implements pcif_api_t::close.

This function powers down the PCIF and closes the lower level timer drivers if they are used.

Example:

    err = R_PCIF_Close(&g_pcif0_ctrl);
    assert(FSP_SUCCESS == err);

Return values

FSP_SUCCESS	Timer successfully started.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.