Functions
fsp_err_t	R_TMR_Open (timer_ctrl_t const p_ctrl, timer_cfg_t const const p_cfg)

fsp_err_t	R_TMR_Start (timer_ctrl_t *const p_ctrl)

fsp_err_t	R_TMR_Stop (timer_ctrl_t *const p_ctrl)

fsp_err_t	R_TMR_Enable (timer_ctrl_t *const p_ctrl)

fsp_err_t	R_TMR_Disable (timer_ctrl_t *const p_ctrl)

fsp_err_t	R_TMR_Reset (timer_ctrl_t *const p_ctrl)

fsp_err_t	R_TMR_PeriodSet (timer_ctrl_t *const p_ctrl, uint32_t const period_counts)

fsp_err_t	R_TMR_DutyCycleSet (timer_ctrl_t *const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin)

fsp_err_t	R_TMR_CompareMatchSet (timer_ctrl_t *const p_ctrl, uint32_t const compare_match_value, timer_compare_match_t const match_channel)

fsp_err_t	R_TMR_InfoGet (timer_ctrl_t const p_ctrl, timer_info_t const p_info)

fsp_err_t	R_TMR_StatusGet (timer_ctrl_t const p_ctrl, timer_status_t const p_status)

fsp_err_t	R_TMR_AdcTriggerSet (timer_ctrl_t *const p_ctrl, tmr_adc_trigger_t adc_request_enable)

fsp_err_t	R_TMR_CallbackSet (timer_ctrl_t const p_api_ctrl, void(p_callback)(timer_callback_args_t ), void const p_context, timer_callback_args_t *const p_callback_memory)

fsp_err_t	R_TMR_Close (timer_ctrl_t *const p_ctrl)

Detailed Description

Driver for the TMR peripheral on RX MCUs. This module implements the Timer Interface.

Overview

Features

The TMR module has the following features:

Supports periodic mode, one-shot mode, and PWM mode.
Signal can be output to a pin.
Configurable period (counts per timer cycle).
Configurable duty cycle in PWM mode.
Configurable clock source, including PCLKB.
Supports runtime reconfiguration of period.
Supports runtime reconfiguration of duty cycle in PWM mode.
APIs are provided to start, stop, and reset the counter.
APIs are provided to get the current period, source clock frequency, and count direction.
APIs are provided to get the current timer status and counter value.
Supports linking to the specified module, TMR count start, event count, or count restart by ELC events.

Selecting a Timer

RX MCUs have four timer peripherals: the General PWM Timer (GPT), the Compare Match Timer (CMT), the Compare Match Timer W (CMTW) and the 8-bit Timer (TMR). When selecting between them, consider these factors:

	GPT	CMT	CMTW	TMR
Low Power Modes	The GPT can operate in sleep mode.	The CMT can operate in sleep mode.	The CMTW can operate in sleep mode.	The TMR can operate in sleep mode.
Available Channels	The number of GPT channels is device specific. All currently supported MCUs have at least 4 GPT channels.	The number of CMT channels is device specific. All MCUs have 4 CMT channels.	The number of CMTW channels is device specific. All MCUs have 2 CMTW channels.	All MCUs have 4 TMR channels.
Timer Resolution	All MCUs have at least one 32-bit GPT timer.	The CMT timers are 16-bit timers.	The CMTW timer have at least one 32-bit CMTW timer	The TMR timers are 8-bit timer or 16-bit timer.
Clock Source	The GPT runs off PCLKA with a configurable divider up to 1024. It can also be configured to count ELC events or external pulses.	The CMT runs off PCLKB.	The CMTW runs off PCLKB.	The TMR runs off PCLKB.

Configuration

Build Time Configurations for r_tmr

The following build time configurations are defined in fsp_cfg/r_tmr_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Pin Output Support	Disabled Enabled	Disabled	If selected code for outputting a waveform to a pin is included in the build.

Configurations for Timers > Timer, 8-bit timer (r_tmr)

This module can be added to the Stacks tab via New Stack > Timers > Timer, 8-bit timer (r_tmr).

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_timer0	Module name.
General > Counter Size	MCU Specific Options		Counter size register bit width (8-bit or 16-bit))
General > Channel	Channel number must be a non-negative integer	0	Physical hardware channel.
General > Mode	Periodic One-Shot PWM	Periodic	Mode selection. Note: One-shot mode is implemented in software. ISR's must be enabled for one shot even if callback is unused.
General > Period	Value must be non-negative	0x100	Specify the timer period based on the selected unit.
General > Period Unit	Raw Counts Nanoseconds Microseconds Milliseconds Seconds Hertz Kilohertz	Raw Counts	Unit of the period specified above
Output > Duty Cycle Percent (only applicable in PWM mode)	Value must be between 0 and 100	50	Specify the timer duty cycle percent. Only used in PWM mode.
Extra Features > ADC Trigger	MCU Specific Options		Select the ADC trigger enable.
Interrupts > Callback	Name must be a valid C symbol	NULL	A user callback function. If this callback function is provided, it is called from the interrupt service routine (ISR) each time the timer period elapses.
Interrupts > Overflow Interrupt Priority	MCU Specific Options		Select the interrupt priority for overflow.
Interrupts > Compare Match Interrupt Priority	MCU Specific Options		Select the interrupt priority for compare match.

Clock Configuration

The TMR clock is based on the PCLKB frequency. You can set the clock frequency using the Clocks tab of the RX Configuration editor or by using the CGC Interface at run-time.

Pin Configuration

This module can use the TMOn pin as output pins for periodic, one-shot, or PWM signals.

Timer Period

The RX Configuration editor will automatically calculate the period count value and source clock divider based on the selected period time, units, and clock speed.

When the selected unit is "Raw counts", the maximum allowed period setting varies depending on the selected clock source:

Clock source	8-bit Timer Maximum period (counts)	16-bit Timer Maximum period (counts)
PCLKB	0xFF	0xFFFF

Usage Notes

One-Shot Mode

The TMR timer does not support one-shot mode natively. One-shot mode is achieved by stopping the timer in the interrupt service routine before the callback is called. If the interrupt is not serviced before the timer period expires again, the timer generates more than one event. The callback is only called once in this case, but multiple events may be generated if the timer is linked to the Transfer (r_dtc).

One-Shot Mode Output

The output waveform in one-shot mode is one TMR clock cycle less than the configured period. The configured period must be at least 2 counts to generate an output pulse.

Examples of one-shot signals that can be generated by this module are shown below:

TMR One-Shot Output

Periodic Output

The TMOn pin toggles twice each time the timer expires in periodic mode. This is achieved by defining a PWM wave at a 50 percent duty cycle so that the period of the resulting square (from rising edge to rising edge) matches the period of the TMR timer. Since the periodic output is actually a PWM output, the time at the stop level is one cycle shorter than the time opposite the stop level for odd period values.

Examples of periodic signals that can be generated by this module are shown below:

TMR Periodic Output

PWM Output

This module does not support in three-phase PWM output. The PWM output signal is low at the beginning of the cycle and high at the end of the cycle.

Examples of PWM signals that can be generated by this module are shown below:

TMR PWM Output

Triggering ADC with TMR

The TMR timer can trigger the start request in response to compare match A This feature not support on MCU RX74M.

Triggering ELC Events with TMR

The TMR timer can trigger the start of other peripherals. The Event Link Controller (r_elc) guide provides a list of all available peripherals.

Event Counting

Event counting can be done by selecting counting sources from TCCR, ELC events.

Note: In event counting mode, the application must call R_TMR_Start() to enable event counting. The counter will not change after calling R_TMR_Start() until an event occurs.

Controlling TMR with ELC Events

The TMR timer can be configured to start, count, and restart when an ELC event occurs.

Note: Event signal input and output are available for TMR channels supported by ELC on the target MCU.

Limitations

Developers should be aware of the following limitations when using the TMR:

TMR operates with 2 units. Each unit has 2 channels with a maximum counter size of 16-bit per unit.
When a channel is configured as a 16-bit timer, the remaining channel in the same unit cannot be used.
When a channel is configured as an 8-bit timer, the remaining channel in the same unit can only be used as an 8-bit timer.

Examples

TMR Basic Example

This is a basic example of minimal use of the TMR in an application.

void tmr_basic_example (void)
{
    fsp_err_t err = FSP_SUCCESS;
    /* Initializes the module. */
    err = R_TMR_Open(&g_timer0_ctrl, &g_timer0_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
    /* Start the timer. */
    (void) R_TMR_Start(&g_timer0_ctrl);
}

TMR Callback Example

This is an example of a timer callback.

/* Example callback called when timer expires. */
void timer_callback (timer_callback_args_t * p_args)
{
    if (TIMER_EVENT_CYCLE_END == p_args->event)
    {
        /* Add application code to be called periodically here. */
    }
}

TMR Free Running Counter Example

To use the TMR as a free running counter, select periodic mode and set the the Period to 0xFF for a 8-bit timer or 0xFFFF for a 16-bit timer.

void tmr_counter_example (void)
{
    fsp_err_t err = FSP_SUCCESS;
    /* Initializes the module. */
    err = R_TMR_Open(&g_timer0_ctrl, &g_timer0_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
    /* Start the timer. */
    (void) R_TMR_Start(&g_timer0_ctrl);
    /* (Optional) Stop the timer. */
    (void) R_TMR_Stop(&g_timer0_ctrl);
    /* Read the current counter value. Counter value is in status.counter. */
    timer_status_t status;
    (void) R_TMR_StatusGet(&g_timer0_ctrl, &status);
}

TMR Period Update Example

This is an example of updating the period.

#define TMR_EXAMPLE_MSEC_PER_SEC           (1000)
#define TMR_EXAMPLE_DESIRED_PERIOD_MSEC    (20)
/* This example shows how to calculate a new period value at runtime. */
void tmr_period_calculation_example (void)
{
    fsp_err_t err = FSP_SUCCESS;
    /* Initializes the module. */
    err = R_TMR_Open(&g_timer0_ctrl, &g_timer0_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
    /* Start the timer. */
    (void) R_TMR_Start(&g_timer0_ctrl);
    /* Get the source clock frequency (in Hz). There are several ways to do this in FSP:
     *  - If LOCO or subclock is chosen in tmr_extended_cfg_t::clock_source
     *      - The source clock frequency is BSP_LOCO_HZ >> timer_cfg_t::source_div
     *  - If PCLKB is chosen in tmr_extended_cfg_t::clock_source and the PCLKB frequency has not changed since reset,
     *      - The source clock frequency is BSP_STARTUP_PCLKB_HZ >> timer_cfg_t::source_div
     *  - Use the R_TMR_InfoGet function (it accounts for the clock source and divider).
     *  - Calculate the current PCLKB frequency using R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB) and right shift
     *    by timer_cfg_t::source_div.
     *
     * This example uses the last option (R_FSP_SystemClockHzGet).
     */
    uint32_t timer_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKB) >> g_timer0_cfg.source_div;
    /* Calculate the desired period based on the current clock. Note that this calculation could overflow if the
     * desired period is larger than UINT32_MAX / pclkb_freq_hz. A cast to uint64_t is used to prevent this. */
    uint32_t period_counts =
        (uint32_t) (((uint64_t) timer_freq_hz * TMR_EXAMPLE_DESIRED_PERIOD_MSEC) / TMR_EXAMPLE_MSEC_PER_SEC);
    /* Set the calculated period. This will return an error if parameter checking is enabled and the calculated
     * period is larger than UINT16_MAX. */
    err = R_TMR_PeriodSet(&g_timer0_ctrl, period_counts);
    assert(FSP_SUCCESS == err);
}

TMR Duty Cycle Update Example

This is an example of updating the duty cycle.

#define TMR_EXAMPLE_DESIRED_DUTY_CYCLE_PERCENT    (25)
#define TMR_EXAMPLE_MAX_PERCENT                   (100)
/* This example shows how to calculate a new duty cycle value at runtime. */
void tmr_duty_cycle_calculation_example (void)
{
    fsp_err_t err = FSP_SUCCESS;
    /* Initializes the module. */
    err = R_TMR_Open(&g_timer0_ctrl, &g_timer0_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
    /* Start the timer. */
    (void) R_TMR_Start(&g_timer0_ctrl);
    /* Get the current period setting. */
    timer_info_t info;
    (void) R_TMR_InfoGet(&g_timer0_ctrl, &info);
    uint32_t current_period_counts = info.period_counts;
    /* Calculate the desired duty cycle based on the current period. */
    uint32_t duty_cycle_counts = (current_period_counts * TMR_EXAMPLE_DESIRED_DUTY_CYCLE_PERCENT) /
                                 TMR_EXAMPLE_MAX_PERCENT;
    /* Set the calculated duty cycle. */
    err = R_TMR_DutyCycleSet(&g_timer0_ctrl, duty_cycle_counts, 0);
    assert(FSP_SUCCESS == err);
}

TMR Cascaded Timers Example

This is an example of using underflow from an even TMR channel as the count source for the next channel (in this case, TMR0 and TMR1).

/* This example shows how use cascaded timers. The count source for TMR channel 1 is set to TMR0 underflow. */
void tmr_cascaded_timers_example (void)
{
    fsp_err_t err = FSP_SUCCESS;
    /* Initialize the timers in any order. */
    err = R_TMR_Open(&g_timer_channel0_ctrl, &g_timer_channel0_cfg);
    assert(FSP_SUCCESS == err);
    err = R_TMR_Open(&g_timer_channel1_ctrl, &g_timer_channel1_cfg);
    assert(FSP_SUCCESS == err);
    /* Start TMR channel 1 first. */
    (void) R_TMR_Start(&g_timer_channel1_ctrl);
    (void) R_TMR_Start(&g_timer_channel0_ctrl);
    /* (Optional) Stop TMR channel 0 first. */
    (void) R_TMR_Stop(&g_timer_channel0_ctrl);
    (void) R_TMR_Stop(&g_timer_channel1_ctrl);
    /* Read the current counter value. Counter value is in status.counter. */
    timer_status_t status;
    (void) R_TMR_StatusGet(&g_timer_channel1_ctrl, &status);
}

Data Structures
struct	tmr_instance_ctrl_t

struct	tmr_extended_cfg_t

Enumerations
enum	tmr_adc_trigger_t

enum	tmr_counter_size_t

Data Structure Documentation

◆ tmr_instance_ctrl_t

struct tmr_instance_ctrl_t

Channel control block. DO NOT INITIALIZE. Initialization occurs when timer_api_t::open is called.

Data Fields
uint32_t	open
	Whether or not channel is open.

const timer_cfg_t *	p_cfg
	Pointer to initial configurations.

R_TMR_Type *	p_reg
	Base register for this channel.

uint32_t	period
	Current timer period (counts)

uint8_t	index
	register array index for this channel.

uint8_t	control_index
	This field indicates the index of the odd-numbered channel that will be used as the lower byte in 16-bit mode.

void(*	p_callback )(timer_callback_args_t *)
	Pointer to callback that is called when a timer_event_t occurs.

timer_callback_args_t *	p_callback_memory
	Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory.

void *	p_context
	Pointer to context to be passed into callback function.

◆ tmr_extended_cfg_t

struct tmr_extended_cfg_t

Optional TMR extension data structure.

Data Fields
tmr_counter_size_t	counter_size	Selected timer 16-bit or 8-bit.
tmr_adc_trigger_t	adc_request_enable	A/D Converter Start Request.
uint8_t	output_compare_ipl	Output Compare match interrupt priority.
IRQn_Type	output_compare_irq	Output Compare match interrupt.

Enumeration Type Documentation

◆ tmr_adc_trigger_t

enum tmr_adc_trigger_t

Trigger options to start A/D conversion.

Enumerator
TMR_ADC_TRIGGER_DISABLE	A/D conversion start request in response to compare match A is disabled.
TMR_ADC_TRIGGER_ENABLE	A/D conversion start request in response to compare match A is enable.

◆ tmr_counter_size_t

enum tmr_counter_size_t

Trigger options to start A/D conversion.

Enumerator
TMR_COUNTER_SIZE_8_BIT	Counter timer 8-bit selected.
TMR_COUNTER_SIZE_16_BIT	Counter timer 16-bit selected.

Function Documentation

◆ R_TMR_Open()

fsp_err_t R_TMR_Open	(	timer_ctrl_t *const	p_ctrl,
		timer_cfg_t const *const	p_cfg
	)

Initializes the timer module and applies configurations. Implements timer_api_t::open.

TMR hardware does not support one-shot functionality natively. When using one-shot mode, the timer will be stopped in an ISR after the requested period has elapsed.

The TMR implementation of the general timer can accept a tmr_extended_cfg_t extension parameter.

Example:

    /* Initializes the module. */
    err = R_TMR_Open(&g_timer0_ctrl, &g_timer0_cfg);

Return values

FSP_SUCCESS	Initialization was successful.
FSP_ERR_ASSERTION	A required input pointer is NULL or the source divider is invalid or channel does not support a 16bit counter size or the period was not in the valid range of 1 to 0xFF in 8bit counter or 1 to 0xFFFF in 16bit counter or an input parameter is invalid.
FSP_ERR_ALREADY_OPEN	Module is already open.
FSP_ERR_IRQ_BSP_DISABLED	timer_cfg_t::mode is TIMER_MODE_ONE_SHOT or timer_cfg_t::p_callback is not NULL, but ISR is not enabled. ISR must be enabled to use one-shot mode or callback. Or a required interrupt has not been enabled in the vector table.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	The channel requested in the p_cfg parameter is not available on this device.

◆ R_TMR_Start()

fsp_err_t R_TMR_Start ( timer_ctrl_t *const p_ctrl )

Starts timer. Implements timer_api_t::start.

Return values

FSP_SUCCESS	Timer successfully started.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

◆ R_TMR_Stop()

fsp_err_t R_TMR_Stop ( timer_ctrl_t *const p_ctrl )

Stops timer. Implements timer_api_t::stop.

Return values

FSP_SUCCESS	Timer successfully stopped.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

◆ R_TMR_Enable()

fsp_err_t R_TMR_Enable ( timer_ctrl_t *const p_ctrl )

Enables external event triggers that start, event count, or restart the counter. Implements timer_api_t::enable.

Return values

FSP_ERR_UNSUPPORTED API not supported by TMR.

◆ R_TMR_Disable()

fsp_err_t R_TMR_Disable ( timer_ctrl_t *const p_ctrl )

Disables external event triggers that start, event count or restart the counter. Implements timer_api_t::disable.

Note: The timer could be running after R_TMR_Disable(). To ensure it is stopped, call R_TMR_Stop().

Return values

FSP_ERR_UNSUPPORTED API not supported by TMR.

◆ R_TMR_Reset()

fsp_err_t R_TMR_Reset ( timer_ctrl_t *const p_ctrl )

Resets the counter value to 0. Implements timer_api_t::reset.

Return values

FSP_SUCCESS	Counter reset.
FSP_ERR_ASSERTION	p_ctrl is NULL
FSP_ERR_NOT_OPEN	The instance control structure is not opened.

◆ R_TMR_PeriodSet()

fsp_err_t R_TMR_PeriodSet	(	timer_ctrl_t *const	p_ctrl,
		uint32_t const	period_counts
	)

Updates period. The new period is updated immediately. Implements timer_api_t::periodSet.

Warning: Stop the timer before calling this function if one-shot output is used.

Return values

FSP_SUCCESS	Period value updated.
FSP_ERR_ASSERTION	A required pointer was NULL, or the period was not in the valid range of 1 to 0xFF in 8bit counter or 1 to 0xFFFF in 16bit counter.
FSP_ERR_NOT_OPEN	The instance control structure is not opened.

◆ R_TMR_DutyCycleSet()

fsp_err_t R_TMR_DutyCycleSet	(	timer_ctrl_t *const	p_ctrl,
		uint32_t const	duty_cycle_counts,
		uint32_t const	pin
	)

Sets duty cycle on requested pin. Implements timer_api_t::dutyCycleSet.

Example:

    /* Get the current period setting. */
    timer_info_t info;
    (void) R_TMR_InfoGet(&g_timer0_ctrl, &info);
    uint32_t current_period_counts = info.period_counts;
    /* Calculate the desired duty cycle based on the current period. */
    uint32_t duty_cycle_counts = (current_period_counts * TMR_EXAMPLE_DESIRED_DUTY_CYCLE_PERCENT) /
                                 TMR_EXAMPLE_MAX_PERCENT;
    /* Set the calculated duty cycle. */
    err = R_TMR_DutyCycleSet(&g_timer0_ctrl, duty_cycle_counts, 0);
    assert(FSP_SUCCESS == err);

Return values

FSP_SUCCESS	Duty cycle updated.
FSP_ERR_ASSERTION	A required pointer was NULL, or the pin was invalid.
FSP_ERR_INVALID_ARGUMENT	Duty cycle was not in the valid range of 0 to period (counts) - 1
FSP_ERR_NOT_OPEN	The instance control structure is not opened.
FSP_ERR_UNSUPPORTED	TMR_CFG_OUTPUT_SUPPORT_ENABLE is 0.

◆ R_TMR_CompareMatchSet()

fsp_err_t R_TMR_CompareMatchSet	(	timer_ctrl_t *const	p_ctrl,
		uint32_t const	compare_match_value,
		timer_compare_match_t const	match_channel
	)

Placeholder for unsupported compareMatch function. Implements timer_api_t::compareMatchSet.

Return values

FSP_ERR_UNSUPPORTED TMR compare match is not supported.

◆ R_TMR_InfoGet()

fsp_err_t R_TMR_InfoGet	(	timer_ctrl_t *const	p_ctrl,
		timer_info_t *const	p_info
	)

Gets timer information and store it in provided pointer p_info. Implements timer_api_t::infoGet.

Return values

FSP_SUCCESS	Period, count direction, and frequency stored in p_info.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The instance control structure is not opened.

◆ R_TMR_StatusGet()

fsp_err_t R_TMR_StatusGet	(	timer_ctrl_t *const	p_ctrl,
		timer_status_t *const	p_status
	)

Get current timer status and store it in provided pointer p_status. Implements timer_api_t::statusGet.

Return values

FSP_SUCCESS	Current timer state and counter value set successfully.
FSP_ERR_ASSERTION	p_ctrl or p_status was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

◆ R_TMR_AdcTriggerSet()

fsp_err_t R_TMR_AdcTriggerSet	(	timer_ctrl_t *const	p_ctrl,
		tmr_adc_trigger_t	adc_request_enable
	)

Set A/D converter start request compare match value.

Return values

FSP_SUCCESS	Counter value updated.
FSP_ERR_ASSERTION	p_ctrl was NULL or channel unsupport Adc trigger.
FSP_ERR_NOT_OPEN	The instance is not opened.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	The channel requested in the p_cfg parameter is not available on this device 16-bit timer.
FSP_ERR_UNSUPPORTED	The feature not available on this device.

◆ R_TMR_CallbackSet()

fsp_err_t R_TMR_CallbackSet	(	timer_ctrl_t *const	p_api_ctrl,
		void()(timer_callback_args_t )	p_callback,
		void *const	p_context,
		timer_callback_args_t *const	p_callback_memory
	)

Updates the user callback with the option to provide memory for the callback argument structure. Implements timer_api_t::callbackSet.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

◆ R_TMR_Close()

fsp_err_t R_TMR_Close ( timer_ctrl_t *const p_ctrl )

Stops counter, clears internal driver data. Implements timer_api_t::close.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

Functions

Detailed Description

Overview

Features

Selecting a Timer

Configuration

Build Time Configurations for r_tmr

Configurations for Timers > Timer, 8-bit timer (r_tmr)

Clock Configuration

Pin Configuration

Timer Period

Usage Notes

One-Shot Mode

One-Shot Mode Output

Periodic Output

PWM Output

Triggering ADC with TMR

Triggering ELC Events with TMR

Event Counting

Controlling TMR with ELC Events

Limitations

Examples

TMR Basic Example

TMR Callback Example

TMR Free Running Counter Example

TMR Period Update Example

TMR Duty Cycle Update Example

TMR Cascaded Timers Example

Data Structures

Enumerations

Data Structure Documentation

◆ tmr_instance_ctrl_t

Data Fields

◆ tmr_extended_cfg_t

Enumeration Type Documentation

◆ tmr_adc_trigger_t

◆ tmr_counter_size_t

Function Documentation

◆ R_TMR_Open()

◆ R_TMR_Start()

◆ R_TMR_Stop()

◆ R_TMR_Enable()

◆ R_TMR_Disable()

◆ R_TMR_Reset()

◆ R_TMR_PeriodSet()

◆ R_TMR_DutyCycleSet()

◆ R_TMR_CompareMatchSet()

◆ R_TMR_InfoGet()

◆ R_TMR_StatusGet()

◆ R_TMR_AdcTriggerSet()

◆ R_TMR_CallbackSet()

◆ R_TMR_Close()