Functions
fsp_err_t	R_SPI_B_Open (spi_ctrl_t p_api_ctrl, spi_cfg_t const const p_cfg)

fsp_err_t	R_SPI_B_Read (spi_ctrl_t const p_api_ctrl, void p_dest, uint32_t const length, spi_bit_width_t const bit_width)

fsp_err_t	R_SPI_B_Write (spi_ctrl_t const p_api_ctrl, void const p_src, uint32_t const length, spi_bit_width_t const bit_width)

fsp_err_t	R_SPI_B_WriteRead (spi_ctrl_t const p_api_ctrl, void const p_src, void *p_dest, uint32_t const length, spi_bit_width_t const bit_width)

fsp_err_t	R_SPI_B_Close (spi_ctrl_t *const p_api_ctrl)

fsp_err_t	R_SPI_B_CalculateBitrate (uint32_t bitrate, spi_b_clock_source_t clock_source, rspck_div_setting_t *spck_div)

fsp_err_t	R_SPI_B_CallbackSet (spi_ctrl_t const p_api_ctrl, void(p_callback)(spi_callback_args_t ), void const p_context, spi_callback_args_t *const p_callback_memory)

Detailed Description

Driver for the SPI peripheral on RZ MPUs. This module implements the SPI Interface.

Overview

Features

Standard SPI Modes
- Master or Slave Mode
- 3-Wire (clock synchronous) or 4-Wire (SPI) Mode
- Clock Polarity (CPOL)
  - CPOL=0 SCLK is low when idle
  - CPOL=1 SCLK is high when idle
- Clock Phase (CPHA)
  - CPHA=0 Data is sampled at an odd edge and changes at an even edge.
  - CPHA=1 Data changes at an odd edge and is sampled at an even edge.
- MSB/LSB first
- 8- to 32-Bit data frames
  - Hardware endian swap in 16-Bit and 32-Bit mode
- SSL level keep (burst transfer) supported
Configurable bitrate
Supports Full Duplex or Transmit Only Mode
FIFO Support
DMAC Support
Callback Events
- Transfer Complete
- RX Overflow Error (The SPI shift register is copied to the data register before previous data was read)
- TX Underrun Error (No data to load into shift register for transmitting)
- Parity Error (When parity is enabled and a parity error is detected)

Configuration

Build Time Configurations for r_spi_b

The following build time configurations are defined in fsp_cfg/r_spi_b_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Enable Support for using DMAC	Enabled Disabled	Enabled	If enabled, DMAC instances will be included in the build for both transmission and reception.
Enable Transmitting from RXI Interrupt	Enabled Disabled	Disabled	If enabled, all operations will be handled from the RX (receive) interrupt. This setting only provides a performance boost when DMAC is not used. In addition, Transmit Only mode is not supported when this configuration is enabled.

Configurations for Connectivity > SPI (r_spi_b)

This module can be added to the Stacks tab via New Stack > Connectivity > SPI (r_spi_b). Non-secure callable guard functions can be generated for this module by right clicking the module in the RA Configuration tool and checking the "Non-secure Callable" box.

Configuration	Options	Default	Description
Name	Name must be a valid C symbol	g_spi0	Module name.
Channel	Value must be a non-negative integer	0	Select the SPI channel.
Receive Interrupt Priority	Value must be an integer between 0 and 255	12	Select the interrupt priority for all SPI interrupts.
Transmit Buffer Empty Interrupt Priority	Value must be an integer between 0 and 255	12	Select the interrupt priority for all SPI interrupts.
Transfer Complete Interrupt Priority	Value must be an integer between 0 and 255	12	Select the interrupt priority for all SPI interrupts.
Error Interrupt Priority	Value must be an integer between 0 and 255	12	Select the interrupt priority for all SPI interrupts.
Operating Mode	Master Slave	Master	Select the SPI operating mode.
Clock Phase	Data sampling on odd edge, data variation on even edge Data sampling on even edge, data variation on odd edge	Data sampling on odd edge, data variation on even edge	Select the clock edge to sample data.
Clock Polarity	Low when idle High when idle	Low when idle	Select clock level when idle.
Mode Fault Error	Enable Disable	Disable	Detect master/slave mode conflicts.
Bit Order	MSB First LSB First	MSB First	Select the data bit order.
Callback	Name must be a valid C symbol	spi_callback	A user callback function can be provided. If this callback function is provided, it will be called from the interrupt service routine (ISR).
SPI Mode	SPI Operation Clock Synchronous Operation	Clock Synchronous Operation	Select the clock sync mode.
Full or Transmit Only Mode	Full Duplex Transmit Only	Full Duplex	Select Full Duplex or Transmit Only Mode.
Slave Select Polarity	Active Low Active High	Active Low	Select the slave select active level.
Select SSL(Slave Select)	SSL0 SSL1 SSL2 SSL3	SSL0	Select which slave to use.
MOSI Idle State	MOSI Idle Value Fixing Disable MOSI Idle Value Fixing Low MOSI Idle Value Fixing High	MOSI Idle Value Fixing Disable	Select the MOSI idle level if MOSI idle is enabled.
Parity Mode	Disabled Odd Even	Disabled	Select the parity mode if parity is enabled.
Byte Swapping	Disable Enable	Disable	Select the byte swap mode for 16/32-Bit Data Frames.
Clock Source	MCU Specific Options		Select the clock source for communication.
Bitrate	Value must be an integer greater than 0	16000000	Enter the desired bitrate, change the bitrate to a value supported by MPU. If the requested bitrate cannot be achieved, the settings with the largest possible value that is less than or equal to the requested bitrate is used. The actual bitrate is printed in a comment in the generated spi_extended_cfg_t structure.
Clock Delay	1 Clock 2 Clocks 3 Clocks 4 Clocks 5 Clocks 6 Clocks 7 Clocks 8 Clocks	1 Clock	Configure the number of SPI clock cycles before each data frame.
SSL Negation Delay	1 Clock 2 Clocks 3 Clocks 4 Clocks 5 Clocks 6 Clocks 7 Clocks 8 Clocks	1 Clock	Configure the number of SPI clock cycles after each data frame.
Next Access Delay	1 Clock 2 Clocks 3 Clocks 4 Clocks 5 Clocks 6 Clocks 7 Clocks 8 Clocks	1 Clock	Configure the number of SPI clock cycles between each data frame.
SSL Level Keep	Disable Enable	Disable	Select whether to negate the SSL level for each frame transfer.
Transmit FIFO Threshold	Value must be an integer between 0 and 15	0	Select the transmit FIFO threshold that is the basis for the transmit buffer empty interrupt generation.
Receive FIFO Threshold	Value must be an integer between 0 and 15	0	Select the receive FIFO threshold that is the basis for the receive buffer empty interrupt generation.
Receive Data Ready Detect Adjustment	Value must be an integer between 0 and 255	0	Configure the timing to detect the received data ready.
Master Receive Clock Delay Adjustment	Adjust with Analog Delay Adjust with Digital Delay	Adjust with Analog Delay	Select the master receive clock.
Max Analog Delay	No delay 1.1 ns 2.2 ns 3.3 ns 4.4 ns 5.5 ns 6.6 ns 7.7 ns	No delay	Select the max analog delay.
Digital Delay	0 Clocks 1 Clock 2 Clocks 3 Clocks 4 Clocks 5 Clocks 6 Clocks 7 Clocks	0 Clocks	Select the digital delay.

Clock Configuration

The SPI peripheral uses the following clock for communication and internal operations.

MPU Group	Peripheral Bus Clock	Communication Operation Clock
RZ/G3E	P4CLK	P4CLK
RZ/G3L	P3CLK	Channel 0: P17CLK Channel 1: P18CLK Channel 2: P19CLK
RZ/G3SE	P3CLK	Channel 0: P17CLK Channel 1: P18CLK Channel 2: P19CLK

Pin Configuration

This module uses MOSI, MISO, RSPCK, and SSL pins to communicate with on board devices.

Note: At high bitrates it may be necessary to configure the pins with IOPORT_CFG_DRIVE_HIGH to maintain signal integrity.

Usage Notes

Performance

At high bitrates, interrupts may not be able to service transfers fast enough. In master mode this means there will be a delay between each data frame. In slave mode this could result in TX Underrun and RX Overflow errors.

In order to improve performance at high bitrates, it is recommended that the instance be configured to service transfers using the DMAC.

Another way to improve performance is to transfer the data in 16/32 bit wide data frames when possible. A typical use-case where this is possible is when reading/writing to a block device.

Transmit From RXI Interrupt

After every data frame the SPI peripheral generates a transmit buffer empty interrupt and a receive buffer full interrupt. It is possible to configure the driver to handle transmit buffer empty interrupts in the receive buffer full ISR. This only improves performance when the DMAC is not being used.

Note: Configuring the module to use RX DMAC instance without also providing a TX DMAC instance results in an invalid configuration when RXI transmit is enabled.; Transmit Only mode is not supported when Transmit from RXI is enabled.

Clock Auto-Stopping

In master mode, if the Receive Buffer Full Interrupts are not handled fast enough, instead of generating a RX Overflow error, the last clock cycle will be stretched until the receive buffer is read.

Parity Mode

When parity mode is configured, the LSB of each data frame is used as a parity bit. When odd parity is selected, the LSB is set such that there are an odd number of ones in the data frame. When even parity is selected, the LSB is set such that there are an even number of ones in the data frame.

Limitations

Developers should be aware of the following limitations when using the SPI:

In master mode, the driver will only configure 4-Wire mode if the device supports SSL Level Keeping (SSLKP bit in SPCMD0) and will return FSP_ERR_UNSUPPORTED if configured for 4-Wire mode on devices without SSL Level Keeping. Without SSL Level Keeping, the SSL pin is toggled after every data frame. In most cases this is not desirable behavior so it is recommended that the SSL pin be driven in software if SSL Level Keeping is not present on the device.
The module does not support communicating with multiple slaves using different SSL pins. In order to achieve this, the module must either be closed and re-opened to change the SSL pin or drive SSL in software. It is recommended that SSL be driven in software when controlling multiple slave devices.
The SPI peripheral has a minimum 3 SPI CLK delay between each data frame.
The behavior for Byte Swap operation is not guaranteed for data frames other than 8-bit, 16-bit and 32bit.

Examples

Basic Example

This is a basic example of minimal use of the SPI in an application.

static volatile bool g_transfer_complete = false;
void spi_basic_example (void)
{
    uint8_t tx_buffer[TRANSFER_SIZE];
    uint8_t rx_buffer[TRANSFER_SIZE];
    fsp_err_t err = FSP_SUCCESS;
    /* Initialize the SPI module. */
    err = R_SPI_B_Open(&g_spi_ctrl, &g_spi_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
    /* Start a write/read transfer */
    err = R_SPI_B_WriteRead(&g_spi_ctrl, tx_buffer, rx_buffer, TRANSFER_SIZE, SPI_BIT_WIDTH_8_BITS);
    assert(FSP_SUCCESS == err);
    /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
    while (false == g_transfer_complete)
    {
        ;
    }
}
static void r_spi_callback (spi_callback_args_t * p_args)
{
    if (SPI_EVENT_TRANSFER_COMPLETE == p_args->event)
    {
        g_transfer_complete = true;
    }
}

Driving Software Slave Select Line

This is an example of communicating with multiple slave devices by asserting SSL in software.

void spi_software_ssl_example (void)
{
    uint8_t tx_buffer[TRANSFER_SIZE];
    uint8_t rx_buffer[TRANSFER_SIZE];
    /* Configure Slave Select Line 1 */
    R_BSP_PinWrite(SLAVE_SELECT_LINE_1, BSP_IO_LEVEL_HIGH);
    /* Configure Slave Select Line 2 */
    R_BSP_PinWrite(SLAVE_SELECT_LINE_2, BSP_IO_LEVEL_HIGH);
    fsp_err_t err = FSP_SUCCESS;
    /* Initialize the SPI module. */
    err = R_SPI_B_Open(&g_spi_ctrl, &g_spi_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
    /* Assert Slave Select Line 1 */
    R_BSP_PinWrite(SLAVE_SELECT_LINE_1, BSP_IO_LEVEL_LOW);
    /* Start a write/read transfer */
    g_transfer_complete = false;
    err                 = R_SPI_B_WriteRead(&g_spi_ctrl, tx_buffer, rx_buffer, TRANSFER_SIZE, SPI_BIT_WIDTH_8_BITS);
    assert(FSP_SUCCESS == err);
    /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
    while (false == g_transfer_complete)
    {
        ;
    }
    /* De-assert Slave Select Line 1 */
    R_BSP_PinWrite(SLAVE_SELECT_LINE_1, BSP_IO_LEVEL_HIGH);
    /* Wait for minimum time required between transfers. */
    R_BSP_SoftwareDelay(SSL_NEXT_ACCESS_DELAY, BSP_DELAY_UNITS_MICROSECONDS);
    /* Assert Slave Select Line 2 */
    R_BSP_PinWrite(SLAVE_SELECT_LINE_2, BSP_IO_LEVEL_LOW);
    /* Start a write/read transfer */
    g_transfer_complete = false;
    err                 = R_SPI_B_WriteRead(&g_spi_ctrl, tx_buffer, rx_buffer, TRANSFER_SIZE, SPI_BIT_WIDTH_8_BITS);
    assert(FSP_SUCCESS == err);
    /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
    while (false == g_transfer_complete)
    {
        ;
    }
    /* De-assert Slave Select Line 2 */
    R_BSP_PinWrite(SLAVE_SELECT_LINE_2, BSP_IO_LEVEL_HIGH);
}

Configuring the SPI Clock Divider Registers

This example demonstrates how to set the SPI clock divisors at runtime.

void spi_bitrate_example (void)
{
    fsp_err_t err = FSP_SUCCESS;
    g_spi_cfg.p_extend = &g_spi_extended_cfg;
    /* Configure SPI Clock divider to achieve largest bitrate less than or equal to the desired bitrate. */
#if BSP_FEATURE_SPI_B_DIFFERENT_TCLK_PATH_EACH_CHANNEL
    err = R_SPI_B_CalculateBitrate(BITRATE, SPI_B_CLOCK_SOURCE_TCLK_CH0, &(g_spi_extended_cfg.spck_div));
#else
    err = R_SPI_B_CalculateBitrate(BITRATE, SPI_B_CLOCK_SOURCE_TCLK, &(g_spi_extended_cfg.spck_div));
#endif
    assert(FSP_SUCCESS == err);
    /* Initialize the SPI module. */
    err = R_SPI_B_Open(&g_spi_ctrl, &g_spi_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
}

Classes
struct	st_rspck_div_setting

struct	st_spi_b_extended_cfg

struct	st_spi_b_instance_ctrl

Typedefs
typedef struct st_rspck_div_setting	rspck_div_setting_t

typedef struct st_spi_b_extended_cfg	spi_b_extended_cfg_t

typedef struct st_spi_b_instance_ctrl	spi_b_instance_ctrl_t

Enumerations
enum	spi_b_ssl_mode_t

enum	spi_b_communication_t

enum	spi_b_ssl_polarity_t

enum	spi_b_ssl_select_t

enum	spi_b_mosi_idle_value_fixing_t

enum	spi_b_parity_t

enum	spi_b_byte_swap_t

enum	spi_b_delay_count_t

enum	spi_b_clock_source_t

enum	spi_b_master_receive_clock_t

enum	spi_b_analog_delay_t

enum	spi_b_digital_delay_t

enum	spi_b_ssl_level_keep_t

Class Documentation

◆ RZG::st_rspck_div_setting

struct RZG::st_rspck_div_setting

SPI Clock Divider settings.

Class Members
uint8_t	spbr	SPBR register setting.
uint8_t	brdv: 2	BRDV setting in SPCMD0.

◆ RZG::st_spi_b_extended_cfg

struct RZG::st_spi_b_extended_cfg

Extended SPI interface configuration

Class Members
spi_b_ssl_mode_t	spi_clksyn	Select SPI or Clock Synchronous mode operation.
spi_b_communication_t	spi_comm	Select full-duplex or transmit-only communication.
spi_b_ssl_polarity_t	ssl_polarity	Select SSLn signal polarity.
spi_b_ssl_select_t	ssl_select	Select which slave to use: 0-SSL0, 1-SSL1, 2-SSL2, 3-SSL3.
spi_b_mosi_idle_value_fixing_t	mosi_idle	Select MOSI idle fixed value and selection.
spi_b_parity_t	parity	Select parity and enable/disable parity.
spi_b_byte_swap_t	byte_swap	Select byte swap mode.
spi_b_clock_source_t	clock_source	Communication clock source (TCLK).
rspck_div_setting_t	spck_div	Register values for configuring the SPI Clock Divider.
spi_b_delay_count_t	spck_delay	SPI Clock Delay Register Setting.
spi_b_delay_count_t	ssl_negation_delay	SPI Slave Select Negation Delay Register Setting.
spi_b_delay_count_t	next_access_delay	SPI Next-Access Delay Register Setting.
spi_b_ssl_level_keep_t	ssl_level_keep	Select SSL signal level keep mode.
uint8_t	transmit_fifo_threshold	Transmit FIFO threshold (0~15)
uint8_t	receive_fifo_threshold	Receive FIFO threshold (0~15)
uint8_t	receive_data_ready_detect_adjustment	Receive data ready detect timing (0~255 counts of operation clock)
spi_b_master_receive_clock_t	master_receive_clock	SPI master receive clock.
spi_b_analog_delay_t	analog_delay	SPI max analog delay.
spi_b_digital_delay_t	digital_delay	SPI digital delay.
void *	p_reg	Register base address for specified channel.

◆ RZG::st_spi_b_instance_ctrl

struct RZG::st_spi_b_instance_ctrl

Channel control block. DO NOT INITIALIZE. Initialization occurs when spi_api_t::open is called.

Public Attributes
uint32_t	open
	Indicates whether the open() API has been successfully called.

spi_cfg_t const *	p_cfg
	Pointer to instance configuration.

R_SPI_B0_Type *	p_regs
	Base register for this channel.

void const *	p_tx_data
	Buffer to transmit.

void *	p_rx_data
	Buffer to receive.

uint32_t	tx_count
	Number of Data Frames to transfer (8-bit, 16-bit, 32-bit)

uint32_t	rx_count
	Number of Data Frames to transfer (8-bit, 16-bit, 32-bit)

uint32_t	count
	Number of Data Frames to transfer (8-bit, 16-bit, 32-bit)

spi_bit_width_t	bit_width
	Bits per Data frame (8-bit, 16-bit, 32-bit)

Typedef Documentation

◆ rspck_div_setting_t

typedef struct st_rspck_div_setting rspck_div_setting_t

SPI Clock Divider settings. Please refer to the struct st_rspck_div_setting.

◆ spi_b_extended_cfg_t

typedef struct st_spi_b_extended_cfg spi_b_extended_cfg_t

Extended SPI interface configuration. Please refer to the struct st_spi_b_extended_cfg.

◆ spi_b_instance_ctrl_t

typedef struct st_spi_b_instance_ctrl spi_b_instance_ctrl_t

Channel control block. DO NOT INITIALIZE. Initialization occurs when spi_api_t::open is called. Please refer to the struct st_spi_b_instance_ctrl.

Enumeration Type Documentation

◆ spi_b_ssl_mode_t

enum spi_b_ssl_mode_t

3-Wire or 4-Wire mode.

Enumerator
SPI_B_SSL_MODE_SPI	SPI operation (4-wire method)
SPI_B_SSL_MODE_CLK_SYN	Clock Synchronous operation (3-wire method)

◆ spi_b_communication_t

enum spi_b_communication_t

Transmit Only (Half Duplex), or Full Duplex.

Enumerator
SPI_B_COMMUNICATION_FULL_DUPLEX	Full-Duplex synchronous serial communication.
SPI_B_COMMUNICATION_TRANSMIT_ONLY	Transit only serial communication.

◆ spi_b_ssl_polarity_t

enum spi_b_ssl_polarity_t

Slave Select Polarity.

Enumerator
SPI_B_SSLP_LOW	SSLP signal polarity active low.
SPI_B_SSLP_HIGH	SSLP signal polarity active high.

◆ spi_b_ssl_select_t

enum spi_b_ssl_select_t

The Slave Select Line

Enumerator
SPI_B_SSL_SELECT_SSL0	Select SSL0.
SPI_B_SSL_SELECT_SSL1	Select SSL1.
SPI_B_SSL_SELECT_SSL2	Select SSL2.
SPI_B_SSL_SELECT_SSL3	Select SSL3.

◆ spi_b_mosi_idle_value_fixing_t

enum spi_b_mosi_idle_value_fixing_t

MOSI Idle Behavior.

Enumerator
SPI_B_MOSI_IDLE_VALUE_FIXING_DISABLE	MOSI output value=value set in MOIFV bit.
SPI_B_MOSI_IDLE_VALUE_FIXING_LOW	MOSIn level low during MOSI idling.
SPI_B_MOSI_IDLE_VALUE_FIXING_HIGH	MOSIn level high during MOSI idling.

◆ spi_b_parity_t

enum spi_b_parity_t

Parity Mode

Enumerator
SPI_B_PARITY_MODE_DISABLE	Disable parity.
SPI_B_PARITY_MODE_ODD	Select even parity.
SPI_B_PARITY_MODE_EVEN	Select odd parity.

◆ spi_b_byte_swap_t

enum spi_b_byte_swap_t

Byte Swapping Enable/Disable.

Enumerator
SPI_B_BYTE_SWAP_DISABLE	Disable Byte swapping for 16/32-Bit transfers.
SPI_B_BYTE_SWAP_ENABLE	Enable Byte swapping for 16/32-Bit transfers.

◆ spi_b_delay_count_t

enum spi_b_delay_count_t

Delay count for SPI delay settings.

Enumerator
SPI_B_DELAY_COUNT_1	Set RSPCK delay count to 1 RSPCK.
SPI_B_DELAY_COUNT_2	Set RSPCK delay count to 2 RSPCK.
SPI_B_DELAY_COUNT_3	Set RSPCK delay count to 3 RSPCK.
SPI_B_DELAY_COUNT_4	Set RSPCK delay count to 4 RSPCK.
SPI_B_DELAY_COUNT_5	Set RSPCK delay count to 5 RSPCK.
SPI_B_DELAY_COUNT_6	Set RSPCK delay count to 6 RSPCK.
SPI_B_DELAY_COUNT_7	Set RSPCK delay count to 7 RSPCK.
SPI_B_DELAY_COUNT_8	Set RSPCK delay count to 8 RSPCK.

◆ spi_b_clock_source_t

enum spi_b_clock_source_t

SPI communication clock source.

◆ spi_b_master_receive_clock_t

enum spi_b_master_receive_clock_t

SPI master receive clock.

Enumerator
SPI_B_MASTER_RECEIVE_CLOCK_ANALOG_DELAY	SPI Master Receive Clock with Analog Delay.
SPI_B_MASTER_RECEIVE_CLOCK_DEGITAL_DELAY	SPI Master Receive Clock with Digital Delay.

◆ spi_b_analog_delay_t

enum spi_b_analog_delay_t

SPI max analog delay.

Enumerator
SPI_B_ANALOG_DELAY_NODELAY	No delay.
SPI_B_ANALOG_DELAY_1_1_NS	1.1 ns (max)
SPI_B_ANALOG_DELAY_2_2_NS	2.2 ns (max)
SPI_B_ANALOG_DELAY_3_3_NS	3.3 ns (max)
SPI_B_ANALOG_DELAY_4_4_NS	4.4 ns (max)
SPI_B_ANALOG_DELAY_5_5_NS	5.5 ns (max)
SPI_B_ANALOG_DELAY_6_6_NS	6.6 ns (max)
SPI_B_ANALOG_DELAY_7_7_NS	7.7 ns (max)

◆ spi_b_digital_delay_t

enum spi_b_digital_delay_t

SPI digital delay.

Enumerator
SPI_B_DIGITAL_DELAY_CLOCK_0	0 PCLKSPIn
SPI_B_DIGITAL_DELAY_CLOCK_1	1 PCLKSPIn
SPI_B_DIGITAL_DELAY_CLOCK_2	2 PCLKSPIn
SPI_B_DIGITAL_DELAY_CLOCK_3	3 PCLKSPIn
SPI_B_DIGITAL_DELAY_CLOCK_4	4 PCLKSPIn
SPI_B_DIGITAL_DELAY_CLOCK_5	5 PCLKSPIn
SPI_B_DIGITAL_DELAY_CLOCK_6	6 PCLKSPIn
SPI_B_DIGITAL_DELAY_CLOCK_7	7 PCLKSPIn

◆ spi_b_ssl_level_keep_t

enum spi_b_ssl_level_keep_t

SSL Signal Level Keeping Enable/Disable.

Enumerator
SPI_B_SSL_LEVEL_KEEP_DISABLE	Disable SSL Level Keep Mode.
SPI_B_SSL_LEVEL_KEEP_ENABLE	Enable SSL Level Keep Mode.

Function Documentation

◆ R_SPI_B_Open()

fsp_err_t R_SPI_B_Open	(	spi_ctrl_t *	p_api_ctrl,
		spi_cfg_t const *const	p_cfg
	)

This functions initializes a channel for SPI communication mode. Implements spi_api_t::open.

This function performs the following tasks:

Performs parameter checking and processes error conditions.
Configures the peripheral registers according to the configuration.
Initialize the control structure for use in other SPI Interface functions.

Return values

FSP_SUCCESS	Channel initialized successfully.
FSP_ERR_ALREADY_OPEN	Instance was already initialized.
FSP_ERR_ASSERTION	An invalid argument was given in the configuration structure.
FSP_ERR_UNSUPPORTED	A requested setting is not possible on this device with the current build configuration.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	The channel number is invalid.

Returns: See Common Error Codes or functions called by this function for other possible return codes. This function calls: transfer_api_t::open

Note: This function is reentrant.

◆ R_SPI_B_Read()

fsp_err_t R_SPI_B_Read	(	spi_ctrl_t *const	p_api_ctrl,
		void *	p_dest,
		uint32_t const	length,
		spi_bit_width_t const	bit_width
	)

This function receives data from a SPI device. Implements spi_api_t::read.

The function performs the following tasks:

Performs parameter checking and processes error conditions.
Sets up the instance to complete a SPI read operation.

Return values

FSP_SUCCESS	Read operation successfully completed.
FSP_ERR_ASSERTION	NULL pointer to control or destination parameters or transfer length is zero.
FSP_ERR_NOT_OPEN	The channel has not been opened. Open channel first.
FSP_ERR_IN_USE	A transfer is already in progress.

◆ R_SPI_B_Write()

fsp_err_t R_SPI_B_Write	(	spi_ctrl_t *const	p_api_ctrl,
		void const *	p_src,
		uint32_t const	length,
		spi_bit_width_t const	bit_width
	)

This function transmits data to a SPI device using the TX Only Communications Operation Mode. Implements spi_api_t::write.

The function performs the following tasks:

Performs parameter checking and processes error conditions.
Sets up the instance to complete a SPI write operation.

Return values

FSP_SUCCESS	Write operation successfully completed.
FSP_ERR_ASSERTION	NULL pointer to control or source parameters or transfer length is zero.
FSP_ERR_NOT_OPEN	The channel has not been opened. Open the channel first.
FSP_ERR_IN_USE	A transfer is already in progress.

◆ R_SPI_B_WriteRead()

fsp_err_t R_SPI_B_WriteRead	(	spi_ctrl_t *const	p_api_ctrl,
		void const *	p_src,
		void *	p_dest,
		uint32_t const	length,
		spi_bit_width_t const	bit_width
	)

This function simultaneously transmits and receive data. Implements spi_api_t::writeRead.

The function performs the following tasks:

Performs parameter checking and processes error conditions.
Sets up the instance to complete a SPI writeRead operation.

Return values

FSP_SUCCESS	Write operation successfully completed.
FSP_ERR_ASSERTION	NULL pointer to control, source or destination parameters or transfer length is zero.
FSP_ERR_NOT_OPEN	The channel has not been opened. Open the channel first.
FSP_ERR_IN_USE	A transfer is already in progress.

◆ R_SPI_B_Close()

fsp_err_t R_SPI_B_Close ( spi_ctrl_t *const p_api_ctrl )

This function manages the closing of a channel by the following task. Implements spi_api_t::close.

Disables SPI operations by disabling the SPI bus.

Disables the SPI peripheral.
Disables all the associated interrupts.
Update control structure so it will not work with SPI Interface functions.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	A required pointer argument is NULL.
FSP_ERR_NOT_OPEN	The channel has not been opened. Open the channel first.

◆ R_SPI_B_CalculateBitrate()

fsp_err_t R_SPI_B_CalculateBitrate	(	uint32_t	bitrate,
		spi_b_clock_source_t	clock_source,
		rspck_div_setting_t *	spck_div
	)

Calculates the SPBR register value and the BRDV bits for a desired bitrate. If the desired bitrate is faster than the maximum bitrate, than the bitrate is set to the maximum bitrate. If the desired bitrate is slower than the minimum bitrate, than an error is returned.

Parameters

[in]	bitrate	Desired bitrate
[in]	clock_source	SPI communication clock source to be used
[out]	spck_div	Memory location to store bitrate register settings.

Return values

FSP_SUCCESS	Valid spbr and brdv values were calculated
FSP_ERR_UNSUPPORTED	Bitrate is not achievable

◆ R_SPI_B_CallbackSet()

fsp_err_t R_SPI_B_CallbackSet	(	spi_ctrl_t *const	p_api_ctrl,
		void()(spi_callback_args_t )	p_callback,
		void *const	p_context,
		spi_callback_args_t *const	p_callback_memory
	)

Updates the user callback and has option of providing memory for callback structure. Implements spi_api_t::callbackSet

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_NO_CALLBACK_MEMORY	p_callback is non-secure and p_callback_memory is either secure or NULL.

Functions

Detailed Description

Overview

Features

Configuration

Build Time Configurations for r_spi_b

Configurations for Connectivity > SPI (r_spi_b)

Clock Configuration

Pin Configuration

Usage Notes

Performance

Transmit From RXI Interrupt

Clock Auto-Stopping

Parity Mode

Limitations

Examples

Basic Example

Driving Software Slave Select Line

Configuring the SPI Clock Divider Registers

Classes

Typedefs

Enumerations

Class Documentation

◆ RZG::st_rspck_div_setting

◆ RZG::st_spi_b_extended_cfg

◆ RZG::st_spi_b_instance_ctrl

Public Attributes

Typedef Documentation

◆ rspck_div_setting_t

◆ spi_b_extended_cfg_t

◆ spi_b_instance_ctrl_t

Enumeration Type Documentation

◆ spi_b_ssl_mode_t

◆ spi_b_communication_t

◆ spi_b_ssl_polarity_t

◆ spi_b_ssl_select_t

◆ spi_b_mosi_idle_value_fixing_t

◆ spi_b_parity_t

◆ spi_b_byte_swap_t

◆ spi_b_delay_count_t

◆ spi_b_clock_source_t

◆ spi_b_master_receive_clock_t

◆ spi_b_analog_delay_t

◆ spi_b_digital_delay_t

◆ spi_b_ssl_level_keep_t

Function Documentation

◆ R_SPI_B_Open()

◆ R_SPI_B_Read()

◆ R_SPI_B_Write()

◆ R_SPI_B_WriteRead()

◆ R_SPI_B_Close()

◆ R_SPI_B_CalculateBitrate()

◆ R_SPI_B_CallbackSet()