RZN Namespace Reference

Default initialization function. More...

Classes
struct	cgc_api_t
union	ethsw_tdma_callback_data_t
struct	iic_master_clock_settings
struct	iic_slave_clock_settings
struct	s_ether_phy_extend_cfg
struct	s_ethercat_ssc_port_extend_cfg
struct	s_gpt_gtior_setting
struct	s_gpt_output_pin
struct	s_sdmmc_device
struct	s_sdmmc_status
struct	st_adc_api
struct	st_adc_callback_args
struct	st_adc_cfg
struct	st_adc_info
struct	st_adc_instance
struct	st_adc_instance_ctrl
struct	st_adc_status
struct	st_bsc_callback_args
struct	st_bsc_extended_cfg
struct	st_bsc_instance_ctrl
struct	st_bsc_nor_extended_cfg
struct	st_bsc_nor_instance_ctrl
struct	st_bsc_nor_region_info
struct	st_bsc_sdram_callback_args
struct	st_bsc_sdram_cs2_settings
struct	st_bsc_sdram_extended_cfg
struct	st_bsc_sdram_instance_ctrl
struct	st_can_api
struct	st_can_bit_timing_cfg
struct	st_can_callback_args
struct	st_can_cfg
struct	st_can_frame
struct	st_can_info
struct	st_can_instance
struct	st_canfd_afl_entry_t
struct	st_canfd_extended_cfg
struct	st_canfd_global_cfg
struct	st_canfd_instance_ctrl
struct	st_cgc_callback_args
struct	st_cgc_cfg
struct	st_cgc_clocks_cfg
struct	st_cgc_divider_cfg
struct	st_cgc_instance
struct	st_cgc_instance_ctrl
struct	st_cgc_pll_cfg
struct	st_cmt_instance_ctrl
struct	st_cmtw_extended_cfg
struct	st_cmtw_instance_ctrl
struct	st_crc_api
struct	st_crc_cfg
struct	st_crc_extended_cfg
struct	st_crc_input_t
struct	st_crc_instance
struct	st_crc_instance_ctrl
struct	st_display_api
struct	st_display_brightness
struct	st_display_callback_args
struct	st_display_cfg
struct	st_display_clut
struct	st_display_clut_cfg
struct	st_display_color
struct	st_display_colorkeying_cfg
struct	st_display_colorkeying_layer
struct	st_display_contrast
struct	st_display_coordinate
struct	st_display_correction
struct	st_display_ctrl
struct	st_display_gamma_correction
struct	st_display_input_cfg
struct	st_display_instance
struct	st_display_layer
struct	st_display_output_cfg
struct	st_display_runtime_cfg
struct	st_display_status
struct	st_display_timing
struct	st_dmac_extended_cfg
struct	st_dmac_instance_ctrl
struct	st_dmac_link_cfg
struct	st_doc_api
struct	st_doc_callback_args
struct	st_doc_cfg
struct	st_doc_instance
struct	st_dsmif_error_status
struct	st_dsmif_extended_cfg
struct	st_dsmif_instance_ctrl
struct	st_elc_api
struct	st_elc_cfg
struct	st_elc_instance
struct	st_elc_instance_ctrl
struct	st_error_api
struct	st_error_callback_args
struct	st_error_cfg
struct	st_error_instance
struct	st_ether_api
struct	st_ether_callback_args
struct	st_ether_cfg
struct	st_ether_instance
struct	st_ether_nic_info
struct	st_ether_phy_api
struct	st_ether_phy_cfg
struct	st_ether_phy_instance
struct	st_ether_phy_instance_ctrl
struct	st_ether_phy_lsi_cfg
struct	st_ether_selector_api
struct	st_ether_selector_cfg
struct	st_ether_selector_instance
struct	st_ether_selector_instance_ctrl
struct	st_ether_switch_api
struct	st_ether_switch_callback_args
struct	st_ether_switch_cfg
struct	st_ether_switch_instance
struct	st_ethercat_ssc_port_api
struct	st_ethercat_ssc_port_callback_args
struct	st_ethercat_ssc_port_cfg
struct	st_ethercat_ssc_port_instance
struct	st_ethercat_ssc_port_instance_ctrl
struct	st_ethsw_cqf_enable
struct	st_ethsw_dlr_init
struct	st_ethsw_eee
struct	st_ethsw_extend_cfg
struct	st_ethsw_flood_unknown_config
struct	st_ethsw_instance_ctrl
struct	st_ethsw_mac_table_config
struct	st_ethsw_mac_table_entry_addr
struct	st_ethsw_mac_table_entry_info
struct	st_ethsw_mirror_conf
struct	st_ethsw_mmctl_pool_size
struct	st_ethsw_mmctl_qgate
struct	st_ethsw_mmctl_queue_assign
struct	st_ethsw_port_mask
struct	st_ethsw_preempt_port_ctrl_config
struct	st_ethsw_preempt_queue
struct	st_ethsw_preempt_status
struct	st_ethsw_qos_mode
struct	st_ethsw_qos_prio_ip
struct	st_ethsw_qos_prio_type
struct	st_ethsw_queue_flush_event
struct	st_ethsw_rx_pattern_ctrl
struct	st_ethsw_rx_pattern_event_data
struct	st_ethsw_rx_pattern_matcher
struct	st_ethsw_snoop_arith_config
struct	st_ethsw_snoop_parser_config
struct	st_ethsw_statistic_mac
struct	st_ethsw_statistic_switch_base
struct	st_ethsw_statistics_8023br
struct	st_ethsw_statistics_dlr
struct	st_ethsw_tdma_counter1
struct	st_ethsw_tdma_enable
struct	st_ethsw_tdma_schedule_entry
struct	st_ethsw_time_domain
struct	st_ethsw_time_enable
struct	st_ethsw_time_offset_correction
struct	st_ethsw_time_peerdelay
struct	st_ethsw_time_rate_correction
struct	st_ethsw_time_transmit
struct	st_ethsw_timestamp
struct	st_ethsw_ts_pulse_generator
struct	st_ethsw_yellow_length
struct	st_external_bus_api
struct	st_external_bus_cfg
struct	st_external_irq_api
struct	st_external_irq_callback_args
struct	st_external_irq_cfg
struct	st_external_irq_instance
union	st_fsp_pack_version
struct	st_gamma_correction
struct	st_gmac_b_instance_ctrl
struct	st_gmac_b_instance_descriptor
struct	st_gmac_b_pause_resolution
struct	st_gmac_instance_ctrl
struct	st_gmac_instance_descriptor
struct	st_gpt_extended_cfg
struct	st_gpt_extended_pwm_cfg
struct	st_gpt_instance_ctrl
struct	st_gpt_three_phase_instance
struct	st_gpt_three_phase_instance_ctrl
struct	st_hyper_address_space
struct	st_hyper_cs_timing_setting
struct	st_hyperbus_api
struct	st_hyperbus_cfg
struct	st_hyperbus_command_address
struct	st_hyperbus_direct_transfer
struct	st_hyperbus_instance
struct	st_hyperbus_status
struct	st_i2c_master_api
struct	st_i2c_master_callback_args
struct	st_i2c_master_cfg
struct	st_i2c_master_instance
struct	st_i2c_master_status
struct	st_i2c_slave_api
struct	st_i2c_slave_callback_args
struct	st_i2c_slave_cfg
struct	st_i2c_slave_instance
struct	st_icu_instance_ctrl
struct	st_icu_inter_cpu_irq_api
struct	st_icu_inter_cpu_irq_callback_args
struct	st_icu_inter_cpu_irq_cfg
struct	st_icu_inter_cpu_irq_instance
struct	st_icu_inter_cpu_irq_instance_ctrl
struct	st_iic_master_extended_cfg
struct	st_iic_master_instance_ctrl
struct	st_iic_slave_extended_cfg
struct	st_iic_slave_instance_ctrl
struct	st_ioport_api
struct	st_ioport_cfg
struct	st_ioport_event_group_input
struct	st_ioport_event_group_output
struct	st_ioport_event_single
struct	st_ioport_extend_cfg
struct	st_ioport_instance
struct	st_ioport_instance_ctrl
struct	st_ioport_pin_cfg
struct	st_lcdc_extended_cfg
struct	st_lcdc_instance_ctrl
struct	st_mtu3_elc_operation
struct	st_mtu3_extended_cfg
struct	st_mtu3_extended_pwm_cfg
struct	st_mtu3_instance_ctrl
struct	st_mtu3_output_pin
struct	st_mtu3_three_phase_extend_cfg
struct	st_mtu3_three_phase_instance_ctrl
struct	st_nor_flash_api
struct	st_nor_flash_cfg
struct	st_nor_flash_status
struct	st_ospi_address_space
struct	st_pci_api
struct	st_pci_callback_args
struct	st_pci_cfg
struct	st_pci_configuration_register_init
struct	st_pci_configuration_register_transfer
struct	st_pci_instance
struct	st_pci_io_register_transfer
struct	st_pci_message_transfer
struct	st_pci_status
struct	st_pcie_ep_extended_cfg
struct	st_pcie_ep_instance_ctrl
struct	st_pcie_ep_window_settings
struct	st_pcie_rc_extended_cfg
struct	st_pcie_rc_instance_ctrl
struct	st_pcie_rc_msi_window_settings
struct	st_pcie_rc_window_settings
struct	st_poe3_api
struct	st_poe3_callback_args
struct	st_poe3_cfg
struct	st_poe3_complementary_pwm_pin_setting
struct	st_poe3_complementary_pwm_setting_t
struct	st_poe3_extended_cfg
struct	st_poe3_instance
struct	st_poe3_instance_ctrl
struct	st_poe3_output_short_circuit_setting
struct	st_poe3_poe_input_setting
struct	st_poe3_pwm_pin_setting
struct	st_poe3_status
struct	st_poeg_api
struct	st_poeg_callback_args
struct	st_poeg_cfg
struct	st_poeg_extended_cfg
struct	st_poeg_instance
struct	st_poeg_instance_ctrl
struct	st_poeg_status
struct	st_qspi_address_space
struct	st_qspi_timing_setting
struct	st_rm_block_media_api
struct	st_rm_block_media_callback_args
struct	st_rm_block_media_cfg
struct	st_rm_block_media_info
struct	st_rm_block_media_instance
struct	st_rm_block_media_sdmmc_extended_cfg
struct	st_rm_block_media_sdmmc_instance_ctrl
struct	st_rm_block_media_status
struct	st_rm_block_media_usb_extended_cfg
struct	st_rm_block_media_usb_instance_ctrl
struct	st_rm_freertos_plus_fat_api
struct	st_rm_freertos_plus_fat_callback_args
struct	st_rm_freertos_plus_fat_cfg
struct	st_rm_freertos_plus_fat_device
struct	st_rm_freertos_plus_fat_disk_cfg
struct	st_rm_freertos_plus_fat_info
struct	st_rm_freertos_plus_fat_instance
struct	st_rm_freertos_plus_fat_instance_ctrl
struct	st_rsip_api
struct	st_rsip_cfg
struct	st_rsip_instance
struct	st_rsip_wrapped_dkm
struct	st_rsip_wrapped_key
struct	st_rspck_div_setting
struct	st_rtc_alarm_time
struct	st_rtc_api
struct	st_rtc_callback_args
struct	st_rtc_cfg
struct	st_rtc_error_adjustment_cfg
struct	st_rtc_info
struct	st_rtc_instance
struct	st_rtc_instance_ctrl
struct	st_rtc_time_capture
struct	st_sci_baud_setting_t
struct	st_sci_i2c_clock_settings
struct	st_sci_i2c_extended_cfg
struct	st_sci_i2c_instance_ctrl
struct	st_sci_smci_baud_setting_t
struct	st_sci_smci_extended_cfg
struct	st_sci_smci_instance_ctrl
struct	st_sci_spi_div_setting
struct	st_sci_spi_extended_cfg
struct	st_sci_spi_instance_ctrl
struct	st_sci_uart_baud_calculation
struct	st_sci_uart_extended_cfg
struct	st_sci_uart_instance_ctrl
struct	st_sci_uart_rs485_setting
struct	st_sdhi_extended_cfg
struct	st_sdmmc_api
struct	st_sdmmc_callback_args
struct	st_sdmmc_cfg
struct	st_sdmmc_instance
struct	st_sdmmc_instance_ctrl
struct	st_sdmmc_read_io_ext_args_t
struct	st_sdmmc_write_io_args_t
struct	st_sdmmc_write_io_ext_args_t
struct	st_sdram_api
struct	st_sdram_cfg
struct	st_sdram_instance
struct	st_shared_memory_api
struct	st_shared_memory_callback_args
struct	st_shared_memory_cfg
struct	st_shared_memory_extended_cfg
struct	st_shared_memory_instance
struct	st_shared_memory_instance_ctrl
struct	st_shared_memory_status
struct	st_smci_api
struct	st_smci_callback_args
struct	st_smci_cfg
struct	st_smci_instance
struct	st_smci_speed_params
struct	st_smci_status
struct	st_smci_transfer_mode
struct	st_spi_api
struct	st_spi_callback_args
struct	st_spi_cfg
struct	st_spi_extended_cfg
struct	st_spi_flash_api
struct	st_spi_flash_cfg
struct	st_spi_flash_direct_transfer
struct	st_spi_flash_erase_command
struct	st_spi_flash_instance
struct	st_spi_flash_status
struct	st_spi_instance
struct	st_spi_instance_ctrl
struct	st_spi_write_read_guard_args
struct	st_three_phase_api
struct	st_three_phase_cfg
struct	st_three_phase_duty_cycle
struct	st_timer_api
struct	st_timer_callback_args
struct	st_timer_cfg
struct	st_timer_info
struct	st_timer_instance
struct	st_timer_status
struct	st_transfer_api
struct	st_transfer_callback_args_t
struct	st_transfer_cfg
struct	st_transfer_info
struct	st_transfer_instance
struct	st_transfer_properties
struct	st_tsu_b_extended_cfg
struct	st_tsu_b_instance_ctrl
struct	st_tsu_instance_ctrl
struct	st_uart_api
struct	st_uart_callback_arg
struct	st_uart_cfg
struct	st_uart_info
struct	st_uart_instance
struct	st_usb_api
struct	st_usb_cfg
struct	st_usb_hcdc_api
struct	st_usb_hcdc_instance
struct	st_usb_hhid_api
struct	st_usb_hhid_instance
struct	st_usb_hmsc_api
struct	st_usb_instance
struct	st_wdt_api
struct	st_wdt_callback_args
struct	st_wdt_cfg
struct	st_wdt_instance
struct	st_wdt_instance_ctrl
struct	st_wdt_timeout_values
struct	st_xspi_hyper_extended_cfg
struct	st_xspi_hyper_instance_ctrl
struct	st_xspi_ospi_extended_cfg
struct	st_xspi_ospi_instance_ctrl
struct	st_xspi_ospi_opi_command_set
struct	st_xspi_ospi_timing_setting
struct	st_xspi_qspi_extended_cfg
struct	st_xspi_qspi_instance_ctrl
struct	usb_hcdc_abstractstate_t
struct	usb_hcdc_breakduration_t
union	usb_hcdc_commfeature_t
struct	usb_hcdc_controllinestate_t
struct	usb_hcdc_countrysetting_t
struct	usb_hcdc_device_info_t
struct	usb_hcdc_encapsulated_t
struct	usb_hcdc_linecoding_t
struct	usb_hcdc_serialstate_t
struct	usb_pcdc_ctrllinestate_t
struct	usb_pcdc_linecoding_t
union	usb_sci_serialstate_t
struct	usb_serial_state_bitmap_t

Typedefs
typedef struct st_adc_status	adc_status_t
typedef struct st_adc_callback_args	adc_callback_args_t
typedef struct st_adc_info	adc_info_t
typedef struct st_adc_cfg	adc_cfg_t
typedef void	adc_ctrl_t
typedef struct st_adc_api	adc_api_t
typedef struct st_adc_instance	adc_instance_t
typedef struct st_can_info	can_info_t
typedef struct st_can_bit_timing_cfg	can_bit_timing_cfg_t
typedef struct st_can_frame	can_frame_t
typedef struct st_can_callback_args	can_callback_args_t
typedef struct st_can_cfg	can_cfg_t
typedef void	can_ctrl_t
typedef struct st_can_api	can_api_t
typedef struct st_can_instance	can_instance_t
typedef struct st_cgc_callback_args	cgc_callback_args_t
typedef struct st_cgc_pll_cfg	cgc_pll_cfg_t
typedef struct st_cgc_divider_cfg	cgc_divider_cfg_t
typedef void	cgc_ctrl_t
typedef struct st_cgc_cfg	cgc_cfg_t
typedef struct st_cgc_clocks_cfg	cgc_clocks_cfg_t
typedef struct st_cgc_instance	cgc_instance_t
typedef struct st_crc_input_t	crc_input_t
typedef void	crc_ctrl_t
typedef struct st_crc_cfg	crc_cfg_t
typedef struct st_crc_api	crc_api_t
typedef struct st_crc_instance	crc_instance_t
typedef struct st_display_timing	display_timing_t
typedef struct st_display_color	display_color_t
typedef struct st_display_coordinate	display_coordinate_t
typedef struct st_display_brightness	display_brightness_t
typedef struct st_display_contrast	display_contrast_t
typedef struct st_display_correction	display_correction_t
typedef struct st_gamma_correction	gamma_correction_t
typedef struct st_display_gamma_correction	display_gamma_correction_t
typedef struct st_display_clut	display_clut_t
typedef struct st_display_colorkeying_cfg	display_colorkeying_cfg_t
typedef struct st_display_colorkeying_layer	display_colorkeying_layer_t
typedef struct st_display_input_cfg	display_input_cfg_t
typedef struct st_display_output_cfg	display_output_cfg_t
typedef struct st_display_layer	display_layer_t
typedef struct st_display_callback_args	display_callback_args_t
typedef struct st_display_cfg	display_cfg_t
typedef struct st_display_runtime_cfg	display_runtime_cfg_t
typedef struct st_display_clut_cfg	display_clut_cfg_t
typedef void	display_ctrl_t
typedef struct st_display_status	display_status_t
typedef struct st_display_api	display_api_t
typedef struct st_display_instance	display_instance_t
typedef struct st_doc_callback_args	doc_callback_args_t
typedef void	doc_ctrl_t
typedef struct st_doc_cfg	doc_cfg_t
typedef struct st_doc_api	doc_api_t
typedef struct st_doc_instance	doc_instance_t
typedef void	elc_ctrl_t
typedef struct st_elc_cfg	elc_cfg_t
typedef struct st_elc_api	elc_api_t
typedef struct st_elc_instance	elc_instance_t
typedef struct st_error_callback_args	error_callback_args_t
typedef void	error_ctrl_t
typedef struct st_error_cfg	error_cfg_t
typedef struct st_error_api	error_api_t
typedef struct st_error_instance	error_instance_t
typedef struct st_ether_nic_info	ether_nic_info_t
typedef struct st_ether_callback_args	ether_callback_args_t
typedef void	ether_ctrl_t
typedef struct st_ether_cfg	ether_cfg_t
typedef struct st_ether_api	ether_api_t
typedef struct st_ether_instance	ether_instance_t
typedef void	ether_phy_ctrl_t
typedef struct st_ether_phy_cfg	ether_phy_cfg_t
typedef struct st_ether_phy_lsi_cfg	ether_phy_lsi_cfg_t
typedef struct st_ether_phy_api	ether_phy_api_t
typedef struct st_ether_phy_instance	ether_phy_instance_t
typedef void	ether_selector_ctrl_t
typedef struct st_ether_selector_cfg	ether_selector_cfg_t
typedef struct st_ether_selector_api	ether_selector_api_t
typedef struct st_ether_selector_instance	ether_selector_instance_t
typedef struct st_ether_switch_callback_args	ether_switch_callback_args_t
typedef void	ether_switch_ctrl_t
typedef struct st_ether_switch_cfg	ether_switch_cfg_t
typedef struct st_ether_switch_api	ether_switch_api_t
typedef struct st_ether_switch_instance	ether_switch_instance_t
typedef struct st_external_bus_cfg	external_bus_cfg_t
typedef void	external_bus_ctrl_t
typedef struct st_external_bus_api	external_bus_api_t
typedef struct st_external_bus_instance	external_bus_instance_t
typedef struct st_external_irq_callback_args	external_irq_callback_args_t
typedef struct st_external_irq_cfg	external_irq_cfg_t
typedef void	external_irq_ctrl_t
typedef struct st_external_irq_api	external_irq_api_t
typedef struct st_external_irq_instance	external_irq_instance_t
typedef struct st_hyperbus_command_address	hyperbus_command_address_t
typedef struct st_hyperbus_direct_transfer	hyperbus_direct_transfer_t
typedef struct st_hyperbus_status	hyperbus_status_t
typedef struct st_hyperbus_cfg	hyperbus_cfg_t
typedef void	hyperbus_ctrl_t
typedef struct st_hyperbus_api	hyperbus_api_t
typedef struct st_hyperbus_instance	hyperbus_instance_t
typedef struct st_i2c_master_callback_args	i2c_master_callback_args_t
typedef struct st_i2c_master_status	i2c_master_status_t
typedef struct st_i2c_master_cfg	i2c_master_cfg_t
typedef void	i2c_master_ctrl_t
typedef struct st_i2c_master_api	i2c_master_api_t
typedef struct st_i2c_master_instance	i2c_master_instance_t
typedef struct st_i2c_slave_callback_args	i2c_slave_callback_args_t
typedef struct st_i2c_slave_cfg	i2c_slave_cfg_t
typedef void	i2c_slave_ctrl_t
typedef struct st_i2c_slave_api	i2c_slave_api_t
typedef struct st_i2c_slave_instance	i2c_slave_instance_t
typedef struct st_icu_inter_cpu_irq_callback_args	icu_inter_cpu_irq_callback_args_t
typedef struct st_icu_inter_cpu_irq_cfg	icu_inter_cpu_irq_cfg_t
typedef void	icu_inter_cpu_irq_ctrl_t
typedef struct st_icu_inter_cpu_irq_api	icu_inter_cpu_irq_api_t
typedef struct st_icu_inter_cpu_irq_instance	icu_inter_cpu_irq_instance_t
typedef uint16_t	ioport_size_t
	IO port size. More...
typedef struct st_ioport_pin_cfg	ioport_pin_cfg_t
typedef struct st_ioport_cfg	ioport_cfg_t
typedef void	ioport_ctrl_t
typedef struct st_ioport_api	ioport_api_t
typedef struct st_ioport_instance	ioport_instance_t
typedef struct st_nor_flash_cfg	nor_flash_cfg_t
typedef struct st_nor_flash_status	nor_flash_status_t
typedef void	nor_flash_ctrl_t
typedef struct st_nor_flash_api	nor_flash_api_t
typedef struct st_nor_flash_instance	nor_flash_instance_t
typedef struct st_pci_configuration_register_init	pci_configuration_register_init_t
typedef struct st_pci_configuration_register_transfer	pci_configuration_register_transfer_t
typedef struct st_pci_io_register_transfer	pci_io_register_transfer_t
typedef struct st_pci_message_transfer	pci_message_transfer_t
typedef struct st_pci_status	pci_status_t
typedef struct st_pci_callback_args	pci_callback_args_t
typedef void	pci_ctrl_t
typedef struct st_pci_cfg	pci_cfg_t
typedef struct st_pci_api	pci_api_t
typedef struct st_pci_instance	pci_instance_t
typedef struct st_poe3_pwm_pin_setting	poe3_pwm_pin_setting_t
typedef struct st_poe3_complementary_pwm_pin_setting	poe3_complementary_pwm_pin_setting_t
typedef struct st_poe3_complementary_pwm_setting_t	poe3_complementary_pwm_setting_t
typedef struct st_poe3_output_short_circuit_setting	poe3_output_short_circuit_setting_t
typedef struct st_poe3_status	poe3_status_t
typedef struct st_poe3_callback_args	poe3_callback_args_t
typedef void	poe3_ctrl_t
typedef struct st_poe3_cfg	poe3_cfg_t
typedef struct st_poe3_api	poe3_api_t
typedef struct st_poe3_instance	poe3_instance_t
typedef struct st_poeg_status	poeg_status_t
typedef struct st_poeg_callback_args	poeg_callback_args_t
typedef void	poeg_ctrl_t
typedef struct st_poeg_cfg	poeg_cfg_t
typedef struct st_poeg_api	poeg_api_t
typedef struct st_poeg_instance	poeg_instance_t
typedef struct st_rtc_callback_args	rtc_callback_args_t
typedef struct st_rtc_error_adjustment_cfg	rtc_error_adjustment_cfg_t
typedef struct tm	rtc_time_t
typedef struct st_rtc_alarm_time	rtc_alarm_time_t
typedef struct st_rtc_time_capture	rtc_time_capture_t
typedef struct st_rtc_info	rtc_info_t
typedef struct st_rtc_cfg	rtc_cfg_t
typedef void	rtc_ctrl_t
typedef struct st_rtc_api	rtc_api_t
typedef struct st_rtc_instance	rtc_instance_t
typedef struct s_sdmmc_status	sdmmc_status_t
typedef struct s_sdmmc_device	sdmmc_device_t
typedef struct st_sdmmc_callback_args	sdmmc_callback_args_t
typedef struct st_sdmmc_write_io_args_t	sdmmc_write_io_args_t
typedef struct st_sdmmc_read_io_ext_args_t	sdmmc_read_io_ext_args_t
typedef struct st_sdmmc_write_io_ext_args_t	sdmmc_write_io_ext_args_t
typedef struct st_sdmmc_cfg	sdmmc_cfg_t
typedef void	sdmmc_ctrl_t
typedef struct st_sdmmc_api	sdmmc_api_t
typedef struct st_sdmmc_instance	sdmmc_instance_t
typedef struct st_sdram_cfg	sdram_cfg_t
typedef void	sdram_ctrl_t
typedef struct st_sdram_api	sdram_api_t
typedef struct st_sdram_instance	sdram_instance_t
typedef struct st_shared_memory_callback_args	shared_memory_callback_args_t
typedef struct st_shared_memory_status	shared_memory_status_t
typedef struct st_shared_memory_cfg	shared_memory_cfg_t
typedef void	shared_memory_ctrl_t
typedef struct st_shared_memory_api	shared_memory_api_t
typedef struct st_shared_memory_instance	shared_memory_instance_t
typedef struct st_smci_status	smci_status_t
typedef struct st_smci_transfer_mode	smci_transfer_mode_t
typedef struct st_smci_speed_params	smci_speed_params_t
typedef struct st_smci_callback_args	smci_callback_args_t
typedef struct st_smci_cfg	smci_cfg_t
typedef void	smci_ctrl_t
typedef struct st_smci_api	smci_api_t
typedef struct st_smci_instance	smci_instance_t
typedef struct st_spi_callback_args	spi_callback_args_t
typedef struct st_spi_write_read_guard_args	spi_write_read_guard_args_t
typedef struct st_spi_cfg	spi_cfg_t
typedef void	spi_ctrl_t
typedef struct st_spi_api	spi_api_t
typedef struct st_spi_instance	spi_instance_t
typedef struct st_spi_flash_erase_command	spi_flash_erase_command_t
typedef struct st_spi_flash_direct_transfer	spi_flash_direct_transfer_t
typedef struct st_spi_flash_cfg	spi_flash_cfg_t
typedef void	spi_flash_ctrl_t
typedef struct st_spi_flash_status	spi_flash_status_t
typedef struct st_spi_flash_api	spi_flash_api_t
typedef struct st_spi_flash_instance	spi_flash_instance_t
typedef struct st_three_phase_duty_cycle	three_phase_duty_cycle_t
typedef void	three_phase_ctrl_t
typedef struct st_three_phase_cfg	three_phase_cfg_t
typedef struct st_three_phase_api	three_phase_api_t
typedef struct st_gpt_three_phase_instance	three_phase_instance_t
typedef struct st_timer_callback_args	timer_callback_args_t
typedef void	timer_ctrl_t
typedef struct st_timer_info	timer_info_t
typedef struct st_timer_status	timer_status_t
typedef struct st_timer_cfg	timer_cfg_t
typedef struct st_timer_api	timer_api_t
typedef struct st_timer_instance	timer_instance_t
typedef void	transfer_ctrl_t
typedef struct st_transfer_callback_args_t	transfer_callback_args_t
typedef struct st_transfer_properties	transfer_properties_t
typedef struct st_transfer_info	transfer_info_t
typedef struct st_transfer_cfg	transfer_cfg_t
typedef struct st_transfer_api	transfer_api_t
typedef struct st_transfer_instance	transfer_instance_t
typedef struct st_uart_info	uart_info_t
typedef struct st_uart_callback_arg	uart_callback_args_t
typedef struct st_uart_cfg	uart_cfg_t
typedef void	uart_ctrl_t
typedef struct st_uart_api	uart_api_t
typedef struct st_uart_instance	uart_instance_t
typedef void	usb_ctrl_t
typedef struct st_usb_descriptor	usb_descriptor_t
typedef struct st_usb_setup	usb_setup_t
typedef struct st_usb_pipe	usb_pipe_t
typedef struct st_usb_info	usb_info_t
typedef struct st_usb_compliance	usb_compliance_t
typedef struct st_usb_event_info	usb_event_info_t
typedef struct st_usb_cfg	usb_cfg_t
typedef struct st_usb_api	usb_api_t
typedef struct st_usb_instance	usb_instance_t
typedef struct st_usb_hcdc_api	usb_hcdc_api_t
typedef struct st_usb_hcdc_instance	usb_hcdc_instance_t
typedef struct st_usb_hhid_api	usb_hhid_api_t
typedef struct st_usb_hhid_instance	usb_hhid_instance_t
typedef struct st_usb_hmsc_api	usb_hmsc_api_t
typedef struct st_wdt_callback_args	wdt_callback_args_t
typedef struct st_wdt_timeout_values	wdt_timeout_values_t
typedef void	wdt_ctrl_t
typedef struct st_wdt_cfg	wdt_cfg_t
typedef struct st_wdt_api	wdt_api_t
typedef struct st_wdt_instance	wdt_instance_t
typedef struct st_rm_block_media_info	rm_block_media_info_t
typedef struct st_rm_block_media_callback_args	rm_block_media_callback_args_t
typedef struct st_rm_block_media_cfg	rm_block_media_cfg_t
typedef struct st_rm_block_media_status	rm_block_media_status_t
typedef void	rm_block_media_ctrl_t
typedef struct st_rm_block_media_api	rm_block_media_api_t
typedef struct st_rm_block_media_instance	rm_block_media_instance_t
typedef struct st_ethercat_ssc_port_callback_args	ethercat_ssc_port_callback_args_t
typedef void	ethercat_ssc_port_ctrl_t
typedef struct st_ethercat_ssc_port_cfg	ethercat_ssc_port_cfg_t
typedef struct st_ethercat_ssc_port_api	ethercat_ssc_port_api_t
typedef struct st_ethercat_ssc_port_instance	ethercat_ssc_port_instance_t
typedef struct st_rm_freertos_plus_fat_callback_args	rm_freertos_plus_fat_callback_args_t
typedef struct st_rm_freertos_plus_fat_device	rm_freertos_plus_fat_device_t
typedef struct st_rm_freertos_plus_fat_info	rm_freertos_plus_fat_info_t
typedef struct st_rm_freertos_plus_fat_cfg	rm_freertos_plus_fat_cfg_t
typedef struct st_rm_freertos_plus_fat_disk_cfg	rm_freertos_plus_fat_disk_cfg_t
typedef void	rm_freertos_plus_fat_ctrl_t
typedef struct st_rm_freertos_plus_fat_api	rm_freertos_plus_fat_api_t
typedef struct st_rm_freertos_plus_fat_instance	rm_freertos_plus_fat_instance_t
typedef union st_fsp_pack_version	fsp_pack_version_t
typedef struct st_adc_instance_ctrl	adc_instance_ctrl_t
typedef struct st_bsc_callback_args	bsc_callback_args_t
typedef struct st_bsc_extended_cfg	bsc_extended_cfg_t
typedef struct st_bsc_instance_ctrl	bsc_instance_ctrl_t
typedef struct st_bsc_nor_region_info	bsc_nor_block_info_t
typedef struct st_bsc_nor_extended_cfg	bsc_nor_extended_cfg_t
typedef struct st_bsc_nor_instance_ctrl	bsc_nor_instance_ctrl_t
typedef struct st_bsc_sdram_callback_args	bsc_sdram_callback_args_t
typedef struct st_bsc_sdram_cs2_settings	bsc_sdram_cs2_settings_t
typedef struct st_bsc_sdram_extended_cfg	bsc_sdram_extended_cfg_t
typedef struct st_bsc_sdram_instance_ctrl	bsc_sdram_instance_ctrl_t
typedef struct st_canfd_instance_ctrl	canfd_instance_ctrl_t
typedef struct st_canfd_afl_entry_t	canfd_afl_entry_t
typedef struct st_canfd_global_cfg	canfd_global_cfg_t
typedef struct st_canfd_extended_cfg	canfd_extended_cfg_t
typedef struct st_cgc_instance_ctrl	cgc_instance_ctrl_t
typedef struct st_cmt_instance_ctrl	cmt_instance_ctrl_t
typedef struct st_cmtw_instance_ctrl	cmtw_instance_ctrl_t
typedef struct st_cmtw_extended_cfg	cmtw_extended_cfg_t
typedef struct st_crc_extended_cfg	crc_extended_cfg_t
typedef struct st_crc_instance_ctrl	crc_instance_ctrl_t
typedef struct st_dmac_link_cfg	dmac_link_cfg_t
typedef struct st_dmac_instance_ctrl	dmac_instance_ctrl_t
typedef struct st_dmac_extended_cfg	dmac_extended_cfg_t
typedef struct st_dsmif_extended_cfg	dsmif_extended_cfg_t
typedef struct st_dsmif_instance_ctrl	dsmif_instance_ctrl_t
typedef struct st_dsmif_error_status	dsmif_error_status_t
typedef struct st_elc_instance_ctrl	elc_instance_ctrl_t
typedef struct st_ether_phy_instance_ctrl	ether_phy_instance_ctrl_t
typedef struct s_ether_phy_extend_cfg	ether_phy_extend_cfg_t
typedef struct st_ether_selector_instance_ctrl	ether_selector_instance_ctrl_t
typedef struct st_ethsw_instance_ctrl	ethsw_instance_ctrl_t
typedef struct st_ethsw_extend_cfg	ethsw_extend_cfg_t
typedef struct st_ethsw_port_mask	ethsw_port_mask_t
typedef uint8_t	ethsw_mac_addr_t[ETHSW_MAC_ADDR_LENGTH]
typedef struct st_ethsw_mac_table_entry_addr	ethsw_mac_table_entry_addr_t
typedef struct st_ethsw_mac_table_entry_info	ethsw_mac_table_entry_info_t
typedef struct st_ethsw_mac_table_config	ethsw_mac_table_config_t
typedef struct st_ethsw_flood_unknown_config	ethsw_flood_unknown_config_t
typedef struct st_ethsw_dlr_init	ethsw_dlr_init_t
typedef struct st_ethsw_rx_pattern_ctrl	ethsw_rx_pattern_ctrl_t
typedef struct st_ethsw_rx_pattern_matcher	ethsw_rx_pattern_matcher_t
typedef struct st_ethsw_rx_pattern_event_data	ethsw_rx_pattern_event_data_t
typedef struct st_ethsw_preempt_queue	ethsw_preempt_queue_t
typedef struct st_ethsw_preempt_port_ctrl_config	ethsw_preempt_port_ctrl_config_t
typedef struct st_ethsw_preempt_status	ethsw_preempt_status_t
typedef struct st_ethsw_mmctl_qgate	ethsw_mmclt_qgate_t
typedef struct st_ethsw_mmctl_pool_size	ethsw_mmctl_pool_size_t
typedef struct st_ethsw_mmctl_queue_assign	ethsw_mmctl_queue_assign_t
typedef struct st_ethsw_yellow_length	ethsw_yellow_length_t
typedef struct st_ethsw_queue_flush_event	ethsw_queue_flush_event_t
typedef uint8_t	ethsw_mmctl_qclosed_nonempty_t[4]
typedef struct st_ethsw_statistic_switch_base	ethsw_statistics_switch_base_t
typedef struct st_ethsw_statistic_mac	ethsw_statistics_mac_t
typedef struct st_ethsw_statistics_8023br	ethsw_statistics_8023br_t
typedef struct st_ethsw_statistics_dlr	ethsw_statistics_dlr_t
typedef struct st_ethsw_cqf_enable	ethsw_cqf_enable_t
typedef struct st_ethsw_snoop_parser_config	ethsw_snoop_parser_config_t
typedef struct st_ethsw_snoop_arith_config	ethsw_snoop_arith_config_t
typedef struct st_ethsw_eee	ethsw_eee_t
typedef struct st_ethsw_qos_mode	ethsw_qos_mode_t
typedef struct st_ethsw_qos_prio_ip	ethsw_qos_prio_ip_t
typedef struct st_ethsw_qos_prio_type	ethsw_qos_prio_type_t
typedef struct st_ethsw_mirror_conf	ethsw_mirror_conf_t
typedef struct st_ethsw_ts_pulse_generator	ethsw_ts_pulse_generator_t
typedef struct st_ethsw_tdma_enable	ethsw_tdma_enable_t
typedef struct st_ethsw_tdma_schedule_entry	ethsw_tdma_schedule_entry_t
typedef struct st_ethsw_tdma_counter1	ethsw_tdma_counter1_t
typedef struct st_ethsw_time_enable	ethsw_time_enable_t
typedef struct st_ethsw_timestamp	ethsw_timestamp_t
typedef struct st_ethsw_time_transmit	ethsw_time_transmit_t
typedef struct st_ethsw_time_peerdelay	ethsw_time_peerdelay_t
typedef struct st_ethsw_time_offset_correction	ethsw_time_offset_correction_t
typedef struct st_ethsw_time_rate_correction	ethsw_time_rate_correction_t
typedef struct st_ethsw_time_domain	ethsw_time_domain_t
typedef struct st_gmac_instance_descriptor	gmac_instance_descriptor_t
typedef struct st_gmac_instance_ctrl	gmac_instance_ctrl_t
typedef struct st_gmac_b_instance_descriptor	gmac_b_instance_descriptor_t
typedef struct st_gmac_b_instance_ctrl	gmac_b_instance_ctrl_t
typedef struct st_gmac_b_pause_resolution	gmac_b_pause_resolution_t
typedef struct s_gpt_output_pin	gpt_output_pin_t
typedef struct s_gpt_gtior_setting	gpt_gtior_setting_t
typedef struct st_gpt_instance_ctrl	gpt_instance_ctrl_t
typedef struct st_gpt_extended_pwm_cfg	gpt_extended_pwm_cfg_t
typedef struct st_gpt_extended_cfg	gpt_extended_cfg_t
typedef struct st_gpt_three_phase_instance_ctrl	gpt_three_phase_instance_ctrl_t
typedef struct st_icu_instance_ctrl	icu_instance_ctrl_t
typedef struct st_icu_inter_cpu_irq_instance_ctrl	icu_inter_cpu_irq_instance_ctrl_t
typedef struct iic_master_clock_settings	iic_master_clock_settings_t
typedef struct st_iic_master_instance_ctrl	iic_master_instance_ctrl_t
typedef struct st_iic_master_extended_cfg	iic_master_extended_cfg_t
typedef struct iic_slave_clock_settings	iic_slave_clock_settings_t
typedef struct st_iic_slave_instance_ctrl	iic_slave_instance_ctrl_t
typedef struct st_iic_slave_extended_cfg	iic_slave_extended_cfg_t
typedef struct st_ioport_event_single	ioport_event_single_t
typedef struct st_ioport_event_group_output	ioport_event_group_output_t
typedef struct st_ioport_event_group_input	ioport_event_group_input_t
typedef struct st_ioport_extend_cfg	ioport_extend_cfg_t
typedef struct st_ioport_instance_ctrl	ioport_instance_ctrl_t
typedef struct st_lcdc_extended_cfg	lcdc_extended_cfg_t
typedef struct st_display_ctrl	lcdc_ctrl_t
typedef struct st_lcdc_instance_ctrl	lcdc_instance_ctrl_t
typedef struct st_mtu3_output_pin	mtu3_output_pin_t
typedef struct st_mtu3_elc_operation	mtu3_elc_operation_t
typedef struct st_mtu3_instance_ctrl	mtu3_instance_ctrl_t
typedef struct st_mtu3_extended_pwm_cfg	mtu3_extended_pwm_cfg_t
typedef struct st_mtu3_extended_cfg	mtu3_extended_cfg_t
typedef struct st_mtu3_three_phase_extend_cfg	mtu3_three_phase_extended_cfg_t
typedef struct st_mtu3_three_phase_instance_ctrl	mtu3_three_phase_instance_ctrl_t
typedef struct st_pcie_ep_window_settings	pcie_ep_window_settings_t
typedef struct st_pcie_ep_instance_ctrl	pcie_ep_instance_ctrl_t
typedef struct st_pcie_ep_extended_cfg	pcie_ep_extended_cfg_t
typedef struct st_pcie_rc_window_settings	pcie_rc_window_settings_t
typedef struct st_pcie_rc_msi_window_settings	pcie_rc_msi_window_settings_t
typedef struct st_pcie_rc_instance_ctrl	pcie_rc_instance_ctrl_t
typedef struct st_pcie_rc_extended_cfg	pcie_rc_extended_cfg_t
typedef struct st_poe3_poe_input_setting	poe3_poe_input_setting_t
typedef struct st_poe3_extended_cfg	poe3_extended_cfg_t
typedef struct st_poe3_instance_ctrl	poe3_instance_ctrl_t
typedef struct st_poeg_instance_ctrl	poeg_instance_ctrl_t
typedef struct st_poeg_extended_cfg	poeg_extended_cfg_t
typedef struct st_rtc_instance_ctrl	rtc_instance_ctrl_t
typedef struct st_sci_i2c_clock_settings	sci_i2c_clock_settings_t
typedef struct st_sci_i2c_instance_ctrl	sci_i2c_instance_ctrl_t
typedef struct st_sci_i2c_extended_cfg	sci_i2c_extended_cfg_t
typedef struct st_sci_smci_instance_ctrl	sci_smci_instance_ctrl_t
typedef struct st_sci_smci_baud_setting_t	sci_smci_baud_setting_t
typedef struct st_sci_smci_extended_cfg	sci_smci_extended_cfg_t
typedef struct st_sci_spi_div_setting	sci_spi_div_setting_t
typedef struct st_sci_spi_extended_cfg	sci_spi_extended_cfg_t
typedef struct st_sci_spi_instance_ctrl	sci_spi_instance_ctrl_t
typedef struct st_sci_uart_instance_ctrl	sci_uart_instance_ctrl_t
typedef struct st_sci_uart_baud_calculation	sci_uart_baud_calculation_t
typedef struct st_sci_baud_setting_t	sci_baud_setting_t
typedef struct st_sci_uart_rs485_setting	sci_uart_rs485_setting_t
typedef struct st_sci_uart_extended_cfg	sci_uart_extended_cfg_t
typedef struct st_sdmmc_instance_ctrl	sdhi_instance_ctrl_t
typedef struct st_sdhi_extended_cfg	sdhi_extended_cfg_t
typedef struct st_shared_memory_extended_cfg	shared_memory_extended_cfg_t
typedef struct st_shared_memory_instance_ctrl	shared_memory_instance_ctrl_t
typedef struct st_rspck_div_setting	rspck_div_setting_t
typedef struct st_spi_extended_cfg	spi_extended_cfg_t
typedef struct st_spi_instance_ctrl	spi_instance_ctrl_t
typedef struct st_tsu_instance_ctrl	tsu_instance_ctrl_t
typedef struct st_tsu_b_extended_cfg	tsu_b_extended_cfg_t
typedef struct st_tsu_b_instance_ctrl	tsu_b_instance_ctrl_t
typedef usb_event_info_t	usb_instance_ctrl_t
typedef struct st_wdt_instance_ctrl	wdt_instance_ctrl_t
typedef struct st_hyper_cs_timing_setting	xspi_hyper_cs_timing_setting_t
typedef struct st_hyper_address_space	xspi_hyper_address_space_t
typedef struct st_xspi_hyper_extended_cfg	xspi_hyper_extended_cfg_t
typedef struct st_xspi_hyper_instance_ctrl	xspi_hyper_instance_ctrl_t
typedef struct st_xspi_ospi_timing_setting	xspi_ospi_timing_setting_t
typedef struct st_xspi_ospi_opi_command_set	xspi_ospi_opi_command_set_t
typedef struct st_ospi_address_space	xspi_ospi_address_space_t
typedef struct st_xspi_ospi_extended_cfg	xspi_ospi_extended_cfg_t
typedef struct st_xspi_ospi_instance_ctrl	xspi_ospi_instance_ctrl_t
typedef struct st_qspi_timing_setting	xspi_qspi_timing_setting_t
typedef struct st_qspi_address_space	xspi_qspi_address_space_t
typedef struct st_xspi_qspi_extended_cfg	xspi_qspi_extended_cfg_t
typedef struct st_xspi_qspi_instance_ctrl	xspi_qspi_instance_ctrl_t
typedef struct st_rm_block_media_sdmmc_extended_cfg	rm_block_media_sdmmc_extended_cfg_t
typedef struct st_rm_block_media_sdmmc_instance_ctrl	rm_block_media_sdmmc_instance_ctrl_t
typedef struct st_rm_block_media_usb_extended_cfg	rm_block_media_usb_extended_cfg_t
typedef struct st_rm_block_media_usb_instance_ctrl	rm_block_media_usb_instance_ctrl_t
typedef struct st_ethercat_ssc_port_instance_ctrl	ethercat_ssc_port_instance_ctrl_t
typedef struct s_ethercat_ssc_port_extend_cfg	ethercat_ssc_port_extend_cfg_t
typedef struct st_rm_freertos_plus_fat_instance_ctrl	rm_freertos_plus_fat_instance_ctrl_t
typedef enum e_rsip_key_type	rsip_key_type_t
typedef enum e_rsip_aes_cipher_mode	rsip_aes_cipher_mode_t
typedef enum e_rsip_aes_aead_mode	rsip_aes_aead_mode_t
typedef enum e_rsip_chacha_poly_mode	rsip_chacha_poly_mode_t
typedef enum e_rsip_aes_mac_mode	rsip_aes_mac_mode_t
typedef enum e_rsip_hash_type	rsip_hash_type_t
typedef enum e_rsip_mgf_type	rsip_mgf_type_t
typedef enum e_rsip_rsa_salt_length	rsip_rsa_salt_length_t
typedef enum e_rsip_initial_vector_type	rsip_initial_vector_type_t
typedef enum e_rsip_otf_channel	rsip_otf_channel_t
typedef struct st_rsip_wrapped_key	rsip_wrapped_key_t
typedef struct st_rsip_wrapped_dkm	rsip_wrapped_dkm_t
typedef void	rsip_sha_handle_abstractor_t
typedef void	rsip_hmac_handle_abstractor_t
typedef void	rsip_kdf_sha_handle_abstractor_t
typedef void	rsip_kdf_hmac_handle_abstractor_t
typedef void	rsip_wrapped_secret_abstractor_t
typedef void	rsip_verified_cert_info_abstractor_t
typedef void	rsip_ctrl_t
typedef struct st_rsip_cfg	rsip_cfg_t
typedef struct st_rsip_api	rsip_api_t
typedef struct st_rsip_instance	rsip_instance_t

Enumerations
enum	fsp_err_t
enum	adc_mode_t
enum	adc_resolution_t
enum	adc_alignment_t
enum	adc_trigger_t
enum	adc_event_t
enum	adc_channel_t
enum	adc_group_id_t
enum	adc_group_mask_t
enum	adc_state_t
enum	can_event_t
enum	can_operation_mode_t
enum	can_test_mode_t
enum	can_id_mode_t
enum	can_frame_type_t
enum	cgc_event_t
enum	cgc_clock_t
enum	cgc_pll_div_t
enum	cgc_pll_out_div_t
enum	cgc_sys_clock_div_t
enum	cgc_pin_output_control_t
enum	cgc_usb_clock_div_t
enum	cgc_clock_change_t
enum	crc_polynomial_t
enum	crc_bit_order_t
enum	crc_snoop_direction_t
enum	display_frame_layer_t
enum	display_state_t
enum	display_event_t
enum	display_in_format_t
enum	display_out_format_t
enum	display_endian_t
enum	display_color_order_t
enum	display_signal_polarity_t
enum	display_sync_edge_t
enum	display_fade_control_t
enum	display_fade_status_t
enum	display_color_keying_t
enum	display_data_swap_t
enum	doc_event_t
enum	doc_bit_width_t
enum	elc_peripheral_t
enum	elc_software_event_t
enum	error_event_t
enum	ether_wake_on_lan_t
enum	ether_flow_control_t
enum	ether_multicast_t
enum	ether_promiscuous_t
enum	ether_zerocopy_t
enum	ether_event_t
enum	ether_phy_lsi_type_t
enum	ether_phy_flow_control_t
enum	ether_phy_link_speed_t
enum	ether_phy_mii_type_t
enum	ether_selector_phylink_polarity_t
enum	ether_selector_interface_t
enum	ether_selector_speed_t
enum	ether_selector_duplex_t
enum	ether_selector_ref_clock_t
enum	ether_switch_event_t
enum	external_bus_chip_select_t
enum	external_bus_data_bus_width_t
enum	external_bus_external_wait_t
enum	external_irq_trigger_t
enum	external_irq_clock_source_div_t
enum	hyperbus_burst_type_t
enum	hyperbus_space_select_t
enum	hyperbus_latency_count_t
enum	i2c_master_rate_t
enum	i2c_master_addr_mode_t
enum	i2c_master_event_t
enum	i2c_slave_rate_t
enum	i2c_slave_addr_mode_t
enum	i2c_slave_event_t
enum	nor_flash_chip_select_t
enum	nor_flash_data_bus_width_t
enum	pci_event_t
enum	pci_configuration_write_type_t
enum	pci_configuration_read_type_t
enum	pci_link_speed_t
enum	pci_ltssm_state_t
enum	poe3_state_t
enum	poe3_active_level_t
enum	poe3_pin_select_t
enum	poeg_state_t
enum	poeg_trigger_t
enum	poeg_gtetrg_polarity_t
enum	poeg_gtetrg_noise_filter_t
enum	rtc_event_t
enum	rtc_alarm_channel_t
enum	rtc_clock_source_t
enum	rtc_status_t
enum	rtc_error_adjustment_t
enum	rtc_error_adjustment_mode_t
enum	rtc_error_adjustment_period_t
enum	rtc_periodic_irq_select_t
enum	rtc_time_capture_source_t
enum	rtc_time_capture_mode_t
enum	rtc_time_capture_noise_filter_t
enum	sdmmc_card_type_t
enum	sdmmc_bus_width_t
enum	sdmmc_io_transfer_mode_t
enum	sdmmc_io_address_mode_t
enum	sdmmc_io_write_mode_t
enum	sdmmc_event_t
enum	sdmmc_card_detect_t
enum	sdmmc_write_protect_t
enum	sdmmc_r1_state_t
enum	sdram_data_bus_width_t
enum	sdram_address_bus_width_t
enum	sdram_write_burst_mode_t
enum	sdram_refresh_cycle_source_div_t
enum	shared_memory_state_t
enum	smci_state_t
enum	smci_event_t
enum	smci_convention_type_t
enum	smci_clock_conversion_integer_t
enum	smci_baudrate_adjustment_integer_t
enum	smci_protocol_type_t
enum	spi_bit_width_t
enum	spi_mode_t
enum	spi_clk_phase_t
enum	spi_clk_polarity_t
enum	spi_mode_fault_t
enum	spi_bit_order_t
enum	spi_event_t
enum	spi_flash_read_mode_t
enum	spi_flash_protocol_t
enum	spi_flash_address_bytes_t
enum	spi_flash_data_lines_t
enum	spi_flash_dummy_clocks_t
enum	spi_flash_direct_transfer_dir_t
enum	three_phase_channel_t
enum	three_phase_buffer_mode_t
enum	timer_event_t
enum	timer_variant_t
enum	timer_compare_match_t
enum	timer_state_t
enum	timer_mode_t
enum	timer_direction_t
enum	timer_source_div_t
enum	transfer_mode_t
enum	transfer_size_t
enum	transfer_addr_mode_t
enum	transfer_repeat_area_t
enum	transfer_chain_mode_t
enum	transfer_irq_t
enum	transfer_start_mode_t
enum	uart_event_t
enum	uart_data_bits_t
enum	uart_parity_t
enum	uart_stop_bits_t
enum	uart_dir_t
enum	usb_speed_t
enum	usb_setup_status_t
enum	usb_status_t
enum	usb_class_t
enum	usb_bcport_t
enum	usb_onoff_t
enum	usb_transfer_t
enum	usb_transfer_type_t
enum	usb_mode_t
enum	usb_compliancetest_status_t
enum	usb_hcdc_data_bit_t
enum	usb_hcdc_stop_bit_t
enum	usb_hcdc_parity_bit_t
enum	usb_hcdc_line_speed_t
enum	usb_hcdc_feature_selector_t
enum	usb_atapi_t
enum	usb_csw_result_t
enum	wdt_timeout_t
enum	wdt_clock_division_t
enum	wdt_window_start_t
enum	wdt_window_end_t
enum	wdt_reset_control_t
enum	wdt_stop_control_t
enum	wdt_status_t
enum	rm_block_media_event_t
enum	ethercat_ssc_port_event_t
enum	rm_freertos_plus_fat_event_t
enum	rm_freertos_plus_fat_type_t
enum	fsp_ip_t
enum	fsp_signal_t
enum	bsc_event_t
enum	bsc_memory_type_t
enum	bsc_idle_cycle_t
enum	bsc_access_wait_cycle_t
enum	bsc_cs_wait_cycle_t
enum	bsc_external_wait_timeout_t
enum	bsc_nor_idle_cycle_t
enum	bsc_nor_access_wait_cycle_t
enum	bsc_nor_cs_wait_cycle_t
enum	bsc_nor_memory_space_t
enum	bsc_sdram_chip_select_t
enum	bsc_sdram_idle_cycle_t
enum	bsc_sdram_command_t
enum	canfd_status_t
enum	canfd_error_t
enum	canfd_tx_buffer_t
enum	canfd_tx_mb_t
enum	canfd_rx_buffer_t
enum	canfd_rx_mb_t
enum	canfd_rx_fifo_t
enum	canfd_minimum_dlc_t
enum	canfd_frame_options_t
enum	cmtw_source_edge_t
enum	cmtw_output_pin_t
enum	cmtw_clear_source_t
enum	cmtw_io_pin_t
enum	cmtw_output_control_t
enum	cmtw_input_control_t
enum	dmac_link_valid_t
enum	dmac_link_end_t
enum	dmac_link_write_back_t
enum	dmac_link_interrupt_mask_t
enum	dmac_register_select_reverse_t
enum	dmac_ack_mode_t
enum	dmac_detection_t
enum	dmac_request_direction_t
enum	dmac_channel_scheduling_t
enum	dmac_mode_select_t
enum	dmac_external_output_signal_active_level_t
enum	dsmif_sum_err_detect_channel_t
enum	dsmif_clock_ctrl_t
enum	dsmif_clock_edge_t
enum	dsmif_filter_order_t
enum	dsmif_data_shift_t
enum	dsmif_capture_trigger_t
enum	dsmif_counter_init_trigger_t
enum	dsmif_current_data_t
enum	dsmif_channel_mask_t
enum	dsmif_channel_overcurrent_status_t
enum	dsmif_channel_short_circuit_status_t
enum	dsmif_overcurrent_sum_status_t
enum	elc_gpt_event_mask_t
enum	ether_phy_port_type_t
enum	ether_phy_mdio_t
enum	ether_phy_speed_t
enum	ether_phy_duplex_t
enum	ether_phy_auto_negotiation_t
enum	ethsw_specific_tag_t
enum	ethsw_phylink_t
enum	ethsw_link_speed_t
enum	ethsw_mac_table_clear_mode_t
enum	ethsw_link_status_t
enum	ethsw_dlr_event_t
enum	ethsw_dlr_beacon_state_t
enum	ethsw_dlr_node_state_t
enum	ethsw_rx_pattern_mode_t
enum	ethsw_rx_pattern_event_t
enum	ethsw_preempt_verify_status_t
enum	ethsw_mmctl_qgate_action_t
enum	ethsw_mmctl_pool_id_t
enum	ethsw_queu_flush_action_t
enum	ethsw_snoop_offset_type_t
enum	ethsw_snoop_comp_type_t
enum	ethsw_snoop_action_t
enum	ethsw_snoop_operat_t
enum	ethsw_mirr_mode_t
enum	ethsw_vlan_in_mode_t
enum	ethsw_vlan_out_mode_t
enum	ethsw_tdma_event_t
enum	ethsw_tdma_gpio_mode_t
enum	ethsw_time_event_t
enum	gmac_link_change_t
enum	gmac_magic_packet_t
enum	gmac_phylink_t
enum	gmac_link_status_t
enum	gmac_b_port_mask_t
enum	gmac_b_link_change_t
enum	gmac_b_magic_packet_t
enum	gmac_b_phylink_t
enum	gmac_b_pause_mask_t
enum	gmac_b_pause_val_t
enum	gmac_b_link_status_t
enum	gpt_io_pin_t
enum	gpt_buffer_force_push_t
enum	gpt_pin_level_t
enum	gpt_source_t
enum	gpt_capture_filter_t
enum	gpt_adc_trigger_t
enum	gpt_poeg_link_t
enum	gpt_output_disable_t
enum	gpt_gtioc_disable_t
enum	gpt_adc_compare_match_t
enum	gpt_interrupt_skip_source_t
enum	gpt_interrupt_skip_count_t
enum	gpt_interrupt_skip_adc_t
enum	gpt_interrupt_skip_select_t
enum	iic_master_timeout_mode_t
enum	iic_master_timeout_scl_low_t
enum	ioport_event_pin_selection_t
enum	ioport_event_output_operation_t
enum	ioport_event_control_t
enum	ioport_event_direction_t
enum	ioport_event_detection_t
enum	ioport_event_initial_buffer_value_t
enum	mtu3_io_pin_level_t
enum	mtu3_clock_edge_t
enum	mtu3_clock_div_t
enum	mtu3_tcnt_clear_t
enum	mtu3_io_pin_t
enum	mtu3_elc_operation_option_t
enum	mtu3_pin_level_t
enum	mtu3_noise_filter_setting_t
enum	mtu3_noise_filter_mtclk_setting_t
enum	mtu3_noise_filter_clock_t
enum	mtu3_noise_filter_external_clock_t
enum	mtu3_interrupt_skip_mode_t
enum	mtu3_interrupt_skip_count_t
enum	mtu3_adc_compare_match_t
enum	mtu3_phase_counting_mode_t
enum	mtu3_bit_mode_t
enum	mtu3_external_clock_t
enum	mtu3_compare_match_status_t
enum	mtu3_buffer_mode_t
enum	mtu3_three_phase_pwm_mode_t
enum	mtu3_three_phase_psye_t
enum	mtu3_three_phase_output_level_t
enum	mtu3_three_phase_synchronous_channel_t
enum	pcie_ep_link_mode_t
enum	pcie_rc_link_mode_t
enum	poe3_hiz_mode_t
enum	sci_i2c_clock_source_t
enum	sci_smci_clock_source_t
enum	sci_spi_clock_source_t
enum	sci_uart_clock_t
enum	sci_uart_flow_control_t
enum	sci_uart_rx_fifo_trigger_t
enum	sci_uart_start_bit_t
enum	sci_uart_noise_cancellation_t
enum	sci_uart_rs485_enable_t
enum	sci_uart_rs485_de_polarity_t
enum	sci_uart_clock_source_t
enum	spi_ssl_mode_t
enum	spi_communication_t
enum	spi_ssl_polarity_t
enum	spi_ssl_select_t
enum	spi_mosi_idle_value_fixing_t
enum	spi_parity_t
enum	spi_byte_swap_t
enum	spi_delay_count_t
enum	spi_clock_source_t
enum	spi_master_receive_clock_t
enum	spi_mrioclk_analog_delay_t
enum	spi_mrclk_digital_delay_t
enum	tsu_b_average_t
enum	tsu_b_compare_cfg_t
enum	xspi_hyper_chip_select_t
enum	xspi_hyper_device_type_t
enum	xspi_hyper_memory_size_t
enum	xspi_hyper_transaction_interval_clocks_t
enum	xspi_hyper_cs_pulldown_clocks_t
enum	xspi_hyper_cs_pullup_clocks_t
enum	xspi_hyper_prefetch_function_t
enum	xspi_hyper_io_voltage_t
enum	xspi_ospi_chip_select_t
enum	xspi_ospi_memory_size_t
enum	xspi_ospi_command_interval_clocks_t
enum	xspi_ospi_cs_pullup_clocks_t
enum	xspi_ospi_cs_pulldown_clocks_t
enum	xspi_ospi_prefetch_function_t
enum	xspi_ospi_io_voltage_t
enum	xspi_ospi_byte_order_t
enum	xspi_qspi_chip_select_t
enum	xspi_qspi_memory_size_t
enum	xspi_qspi_command_interval_clocks_t
enum	xspi_qspi_cs_pullup_clocks_t
enum	xspi_qspi_cs_pulldown_clocks_t
enum	xspi_qspi_prefetch_function_t
enum	xspi_qspi_io_voltage_t
enum	ethercat_ssc_port_eeprom_size_t
enum	ethercat_ssc_port_txc_delay_t
enum	bsp_warm_start_event_t
enum	bsp_delay_units_t
enum	bsp_io_level_t
enum	bsp_io_direction_t
enum	bsp_io_port_t
enum	bsp_io_port_pin_t
enum	bsp_io_region_t
enum	bsp_reg_protect_t
enum	bsp_reset_t
enum	bsp_cluster_reset_auto_release_t
enum	bsp_module_reset_t
enum	bsp_resource_state_t
enum	bsp_resource_num_t
enum	bsp_grp_irq_t
enum	elc_event_t
enum	adc_channel_t
enum	cgc_fsel_xspi_clock_div_t
enum	cgc_divsel_xspi_clock_div_t
enum	cgc_clock_out_clock_div_t
enum	cgc_canfd_clock_div_t
enum	cgc_phy_clock_t
enum	cgc_spi_async_clock_t
enum	cgc_sci_async_clock_t
enum	cgc_lcdc_div_t
enum	cgc_scie_async_clock_t
enum	cgc_encout_clock_t
enum	cgc_cpu_clock_div_t
enum	cgc_clock_t
enum	cgc_clock_change_t
enum	display_in_format_t
enum	elc_peripheral_t
enum	error_event_t
enum	ioport_pin_pfc_t
enum	ioport_cfg_options_t
enum	ether_event_t
enum	ether_switch_event_t
enum	ether_phy_lsi_type_t
enum	poe3_active_level_t
enum	poeg_state_t
enum	poeg_trigger_t
enum	poe3_state_t
enum	transfer_event_t
enum	transfer_mode_t
enum	transfer_size_t
enum	transfer_addr_mode_t
enum	elc_event_t
enum	adc_channel_t
enum	cgc_fsel_xspi_clock_div_t
enum	cgc_divsel_xspi_clock_div_t
enum	cgc_clock_out_clock_div_t
enum	cgc_canfd_clock_div_t
enum	cgc_phy_clock_t
enum	cgc_spi_async_clock_t
enum	cgc_sci_async_clock_t
enum	cgc_cpu_clock_div_t
enum	cgc_baseclock_div_t
enum	cgc_clock_t
enum	cgc_clock_change_t
enum	elc_peripheral_t
enum	error_event_t
enum	ether_event_t
enum	ether_phy_lsi_type_t
enum	ether_switch_event_t
enum	ioport_pin_pfc_t
enum	ioport_cfg_options_t
enum	poe3_state_t
enum	poe3_active_level_t
enum	poeg_state_t
enum	poeg_trigger_t
enum	transfer_event_t
enum	transfer_mode_t
enum	transfer_size_t
enum	transfer_addr_mode_t
enum	e_rsip_key_type
enum	e_rsip_aes_cipher_mode
enum	e_rsip_aes_aead_mode
enum	e_rsip_chacha_poly_mode
enum	e_rsip_aes_mac_mode
enum	e_rsip_hash_type
enum	e_rsip_mgf_type
enum	e_rsip_rsa_salt_length
enum	e_rsip_initial_vector_type
enum	e_rsip_otf_channel
enum	rsip_byte_size_wrapped_key_t
enum	rsip_byte_size_encrypted_key_t
enum	rsip_byte_size_wrapped_dkm_t
enum	rsip_byte_size_wrapped_iv_t
enum	rsip_tls12_prf_label_t
enum	rsip_auth_type_t

Functions
fsp_err_t	R_FSP_VersionGet (fsp_pack_version_t *const p_version)
fsp_err_t	R_ADC_Open (adc_ctrl_t *p_ctrl, adc_cfg_t const *const p_cfg)
fsp_err_t	R_ADC_ScanCfg (adc_ctrl_t *p_ctrl, void const *const p_channel_cfg)
fsp_err_t	R_ADC_CallbackSet (adc_ctrl_t *const p_ctrl, void(*p_callback)(adc_callback_args_t *), void *const p_context, adc_callback_args_t *const p_callback_memory)
fsp_err_t	R_ADC_ScanStart (adc_ctrl_t *p_ctrl)
fsp_err_t	R_ADC_ScanGroupStart (adc_ctrl_t *p_ctrl, adc_group_mask_t group_mask)
fsp_err_t	R_ADC_ScanStop (adc_ctrl_t *p_ctrl)
fsp_err_t	R_ADC_StatusGet (adc_ctrl_t *p_ctrl, adc_status_t *p_status)
fsp_err_t	R_ADC_Read (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint16_t *const p_data)
fsp_err_t	R_ADC_Read32 (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint32_t *const p_data)
fsp_err_t	R_ADC_SampleStateCountSet (adc_ctrl_t *p_ctrl, adc_sample_state_t *p_sample)
fsp_err_t	R_ADC_InfoGet (adc_ctrl_t *p_ctrl, adc_info_t *p_adc_info)
fsp_err_t	R_ADC_Close (adc_ctrl_t *p_ctrl)
fsp_err_t	R_ADC_Calibrate (adc_ctrl_t *const p_ctrl, void const *p_extend)
fsp_err_t	R_ADC_OffsetSet (adc_ctrl_t *const p_ctrl, adc_channel_t const reg_id, int32_t offset)
fsp_err_t	R_BSC_Open (external_bus_ctrl_t *p_ctrl, external_bus_cfg_t const *const p_cfg)
fsp_err_t	R_BSC_Close (external_bus_ctrl_t *p_ctrl)
fsp_err_t	R_BSC_CallbackSet (external_bus_ctrl_t *p_ctrl, void(*p_callback)(bsc_callback_args_t *), void *const p_context, bsc_callback_args_t *const p_callback_memory)
fsp_err_t	R_BSC_NOR_Open (nor_flash_ctrl_t *p_ctrl, nor_flash_cfg_t const *const p_cfg)
fsp_err_t	R_BSC_NOR_Write (nor_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint8_t *const p_dest, uint32_t byte_count)
fsp_err_t	R_BSC_NOR_Erase (nor_flash_ctrl_t *p_ctrl, uint8_t *const p_device_address, uint32_t byte_count)
fsp_err_t	R_BSC_NOR_StatusGet (nor_flash_ctrl_t *p_ctrl, uint8_t *const p_device_address, nor_flash_status_t *const p_status)
fsp_err_t	R_BSC_NOR_Close (nor_flash_ctrl_t *p_ctrl)
fsp_err_t	R_BSC_SDRAM_Open (sdram_ctrl_t *p_ctrl, sdram_cfg_t const *const p_cfg)
fsp_err_t	R_BSC_SDRAM_SelfRefreshEnter (sdram_ctrl_t *p_ctrl)
fsp_err_t	R_BSC_SDRAM_SelfRefreshExit (sdram_ctrl_t *p_ctrl)
fsp_err_t	R_BSC_SDRAM_PowerDownEnter (sdram_ctrl_t *p_ctrl)
fsp_err_t	R_BSC_SDRAM_PowerDownExit (sdram_ctrl_t *p_ctrl)
fsp_err_t	R_BSC_SDRAM_Close (sdram_ctrl_t *p_ctrl)
fsp_err_t	R_CANFD_Open (can_ctrl_t *const p_ctrl, can_cfg_t const *const p_cfg)
fsp_err_t	R_CANFD_Close (can_ctrl_t *const p_ctrl)
fsp_err_t	R_CANFD_Write (can_ctrl_t *const p_ctrl, uint32_t const buffer, can_frame_t *const p_frame)
fsp_err_t	R_CANFD_Read (can_ctrl_t *const p_ctrl, uint32_t const buffer, can_frame_t *const p_frame)
fsp_err_t	R_CANFD_ModeTransition (can_ctrl_t *const p_ctrl, can_operation_mode_t operation_mode, can_test_mode_t test_mode)
fsp_err_t	R_CANFD_InfoGet (can_ctrl_t *const p_ctrl, can_info_t *const p_info)
fsp_err_t	R_CANFD_CallbackSet (can_ctrl_t *const p_ctrl, void(*p_callback)(can_callback_args_t *), void *const p_context, can_callback_args_t *const p_callback_memory)
fsp_err_t	R_CGC_Open (cgc_ctrl_t *const p_ctrl, cgc_cfg_t const *const p_cfg)
fsp_err_t	R_CGC_ClocksCfg (cgc_ctrl_t *const p_ctrl, cgc_clocks_cfg_t const *const p_clock_cfg)
fsp_err_t	R_CGC_ClockStart (cgc_ctrl_t *const p_ctrl, cgc_clock_t clock_source, cgc_pll_cfg_t const *const p_pll_cfg)
fsp_err_t	R_CGC_ClockStop (cgc_ctrl_t *const p_ctrl, cgc_clock_t clock_source)
fsp_err_t	R_CGC_ClockCheck (cgc_ctrl_t *const p_ctrl, cgc_clock_t clock_source)
fsp_err_t	R_CGC_SystemClockSet (cgc_ctrl_t *const p_ctrl, cgc_clock_t clock_source, cgc_divider_cfg_t const *const p_divider_cfg)
fsp_err_t	R_CGC_SystemClockGet (cgc_ctrl_t *const p_ctrl, cgc_clock_t *const p_clock_source, cgc_divider_cfg_t *const p_divider_cfg)
fsp_err_t	R_CGC_OscStopDetectEnable (cgc_ctrl_t *const p_ctrl)
fsp_err_t	R_CGC_OscStopDetectDisable (cgc_ctrl_t *const p_ctrl)
fsp_err_t	R_CGC_OscStopStatusClear (cgc_ctrl_t *const p_ctrl)
fsp_err_t	R_CGC_CallbackSet (cgc_ctrl_t *const p_ctrl, void(*p_callback)(cgc_callback_args_t *), void *const p_context, cgc_callback_args_t *const p_callback_memory)
fsp_err_t	R_CGC_Close (cgc_ctrl_t *const p_ctrl)
fsp_err_t	R_CMT_Open (timer_ctrl_t *const p_ctrl, timer_cfg_t const *const p_cfg)
fsp_err_t	R_CMT_Stop (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_CMT_Start (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_CMT_Reset (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_CMT_Enable (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_CMT_Disable (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_CMT_PeriodSet (timer_ctrl_t *const p_ctrl, uint32_t const period_counts)
fsp_err_t	R_CMT_DutyCycleSet (timer_ctrl_t *const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin)
fsp_err_t	R_CMT_CompareMatchSet (timer_ctrl_t *const p_ctrl, uint32_t const compare_match_value, timer_compare_match_t const match_channel)
fsp_err_t	R_CMT_InfoGet (timer_ctrl_t *const p_ctrl, timer_info_t *const p_info)
fsp_err_t	R_CMT_StatusGet (timer_ctrl_t *const p_ctrl, timer_status_t *const p_status)
fsp_err_t	R_CMT_CounterSet (timer_ctrl_t *const p_ctrl, uint32_t counter)
fsp_err_t	R_CMT_CallbackSet (timer_ctrl_t *const p_ctrl, void(*p_callback)(timer_callback_args_t *), void *const p_context, timer_callback_args_t *const p_callback_memory)
fsp_err_t	R_CMT_Close (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_CMTW_Open (timer_ctrl_t *const p_ctrl, timer_cfg_t const *const p_cfg)
fsp_err_t	R_CMTW_Start (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_CMTW_Stop (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_CMTW_Reset (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_CMTW_Enable (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_CMTW_Disable (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_CMTW_PeriodSet (timer_ctrl_t *const p_ctrl, uint32_t const period_counts)
fsp_err_t	R_CMTW_DutyCycleSet (timer_ctrl_t *const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin)
fsp_err_t	R_CMTW_CompareMatchSet (timer_ctrl_t *const p_ctrl, uint32_t const compare_match_value, timer_compare_match_t const match_channel)
fsp_err_t	R_CMTW_InfoGet (timer_ctrl_t *const p_ctrl, timer_info_t *const p_info)
fsp_err_t	R_CMTW_StatusGet (timer_ctrl_t *const p_ctrl, timer_status_t *const p_status)
fsp_err_t	R_CMTW_OutputEnable (timer_ctrl_t *const p_ctrl, cmtw_io_pin_t pin)
fsp_err_t	R_CMTW_OutputDisable (timer_ctrl_t *const p_ctrl, cmtw_io_pin_t pin)
fsp_err_t	R_CMTW_CallbackSet (timer_ctrl_t *const p_ctrl, void(*p_callback)(timer_callback_args_t *), void *const p_context, timer_callback_args_t *const p_callback_memory)
fsp_err_t	R_CMTW_Close (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_CRC_Open (crc_ctrl_t *const p_ctrl, crc_cfg_t const *const p_cfg)
fsp_err_t	R_CRC_Close (crc_ctrl_t *const p_ctrl)
fsp_err_t	R_CRC_Calculate (crc_ctrl_t *const p_ctrl, crc_input_t *const p_crc_input, uint32_t *calculatedValue)
fsp_err_t	R_CRC_CalculatedValueGet (crc_ctrl_t *const p_ctrl, uint32_t *calculatedValue)
fsp_err_t	R_CRC_SnoopEnable (crc_ctrl_t *const p_ctrl, uint32_t crc_seed)
fsp_err_t	R_CRC_SnoopDisable (crc_ctrl_t *const p_ctrl)
fsp_err_t	R_DMAC_Open (transfer_ctrl_t *const p_ctrl, transfer_cfg_t const *const p_cfg)
fsp_err_t	R_DMAC_Reconfigure (transfer_ctrl_t *const p_ctrl, transfer_info_t *p_info)
fsp_err_t	R_DMAC_Reset (transfer_ctrl_t *const p_ctrl, void const *volatile p_src, void *volatile p_dest, uint16_t const num_transfers)
fsp_err_t	R_DMAC_SoftwareStart (transfer_ctrl_t *const p_ctrl, transfer_start_mode_t mode)
fsp_err_t	R_DMAC_SoftwareStop (transfer_ctrl_t *const p_ctrl)
fsp_err_t	R_DMAC_Enable (transfer_ctrl_t *const p_ctrl)
fsp_err_t	R_DMAC_Disable (transfer_ctrl_t *const p_ctrl)
fsp_err_t	R_DMAC_InfoGet (transfer_ctrl_t *const p_ctrl, transfer_properties_t *const p_info)
fsp_err_t	R_DMAC_Close (transfer_ctrl_t *const p_ctrl)
fsp_err_t	R_DMAC_Reload (transfer_ctrl_t *const p_ctrl, void const *p_src, void *p_dest, uint32_t const num_transfers)
fsp_err_t	R_DMAC_CallbackSet (transfer_ctrl_t *const p_ctrl, void(*p_callback)(transfer_callback_args_t *), void *const p_context, transfer_callback_args_t *const p_callback_memory)
fsp_err_t	R_DMAC_LinkDescriptorSet (transfer_ctrl_t *const p_ctrl, dmac_link_cfg_t *p_descriptor)
fsp_err_t	R_DSMIF_Open (adc_ctrl_t *p_ctrl, adc_cfg_t const *const p_cfg)
fsp_err_t	R_DSMIF_ScanStart (adc_ctrl_t *p_ctrl)
fsp_err_t	R_DSMIF_ScanStop (adc_ctrl_t *p_ctrl)
fsp_err_t	R_DSMIF_CfgSet (adc_ctrl_t *p_ctrl, adc_cfg_t const *const p_cfg)
fsp_err_t	R_DSMIF_StatusGet (adc_ctrl_t *p_ctrl, adc_status_t *p_status)
fsp_err_t	R_DSMIF_ErrorStatusGet (adc_ctrl_t *p_ctrl, dsmif_error_status_t *p_error_status)
fsp_err_t	R_DSMIF_Read (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint32_t *const p_data)
fsp_err_t	R_DSMIF_Close (adc_ctrl_t *p_ctrl)
fsp_err_t	R_DSMIF_CallbackSet (adc_ctrl_t *const p_ctrl, void(*p_callback)(adc_callback_args_t *), void *const p_context, adc_callback_args_t *const p_callback_memory)
fsp_err_t	R_ELC_Open (elc_ctrl_t *const p_ctrl, elc_cfg_t const *const p_cfg)
fsp_err_t	R_ELC_Close (elc_ctrl_t *const p_ctrl)
fsp_err_t	R_ELC_SoftwareEventGenerate (elc_ctrl_t *const p_ctrl, elc_software_event_t event_number)
fsp_err_t	R_ELC_LinkSet (elc_ctrl_t *const p_ctrl, elc_peripheral_t peripheral, elc_event_t signal)
fsp_err_t	R_ELC_LinkBreak (elc_ctrl_t *const p_ctrl, elc_peripheral_t peripheral)
fsp_err_t	R_ELC_Enable (elc_ctrl_t *const p_ctrl)
fsp_err_t	R_ELC_Disable (elc_ctrl_t *const p_ctrl)
fsp_err_t	R_ETHER_PHY_Open (ether_phy_ctrl_t *const p_ctrl, ether_phy_cfg_t const *const p_cfg)
fsp_err_t	R_ETHER_PHY_Close (ether_phy_ctrl_t *const p_ctrl)
fsp_err_t	R_ETHER_PHY_ChipInit (ether_phy_ctrl_t *const p_ctrl, ether_phy_cfg_t const *const p_cfg)
	Initialize Ethernet PHY device. Implements ether_phy_api_t::chipInit. More...
fsp_err_t	R_ETHER_PHY_Read (ether_phy_ctrl_t *const p_ctrl, uint32_t reg_addr, uint32_t *const p_data)
	Read data from register of PHY-LSI . Implements ether_phy_api_t::read. More...
fsp_err_t	R_ETHER_PHY_Write (ether_phy_ctrl_t *const p_ctrl, uint32_t reg_addr, uint32_t data)
	Write data to register of PHY-LSI . Implements ether_phy_api_t::write. More...
fsp_err_t	R_ETHER_PHY_StartAutoNegotiate (ether_phy_ctrl_t *const p_ctrl)
fsp_err_t	R_ETHER_PHY_LinkPartnerAbilityGet (ether_phy_ctrl_t *const p_ctrl, uint32_t *const p_line_speed_duplex, uint32_t *const p_local_pause, uint32_t *const p_partner_pause)
fsp_err_t	R_ETHER_PHY_LinkStatusGet (ether_phy_ctrl_t *const p_ctrl)
fsp_err_t	R_ETHER_SELECTOR_Open (ether_selector_ctrl_t *const p_ctrl, ether_selector_cfg_t const *const p_cfg)
fsp_err_t	R_ETHER_SELECTOR_Close (ether_selector_ctrl_t *const p_ctrl)
fsp_err_t	R_ETHER_SELECTOR_ConverterSet (ether_selector_ctrl_t *const p_ctrl, ether_selector_speed_t speed, ether_selector_duplex_t duplex)
fsp_err_t	R_ETHSW_Open (ether_switch_ctrl_t *const p_ctrl, ether_switch_cfg_t const *const p_cfg)
fsp_err_t	R_ETHSW_Close (ether_switch_ctrl_t *const p_ctrl)
fsp_err_t	R_ETHSW_SpeedCfg (ether_switch_ctrl_t *const p_ctrl, uint32_t const port, ethsw_link_speed_t const speed)
fsp_err_t	R_ETHSW_MacTableSet (ether_switch_ctrl_t *const p_ctrl, ethsw_mac_table_entry_addr_t *p_mac_entry_addr, ethsw_mac_table_entry_info_t *p_mac_entry_info)
fsp_err_t	R_ETHSW_MacTableGet (ether_switch_ctrl_t *const p_ctrl, ethsw_mac_table_entry_addr_t *p_mac_entry_addr, ethsw_mac_table_entry_info_t *p_mac_entry_info)
fsp_err_t	R_ETHSW_MacTableConfigSet (ether_switch_ctrl_t *const p_ctrl, ethsw_mac_table_config_t *p_mac_table_config)
fsp_err_t	R_ETHSW_MacTableClear (ether_switch_ctrl_t *const p_ctrl, ethsw_mac_table_clear_mode_t *p_mac_table_clear)
fsp_err_t	R_ETHSW_LearningSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool enable)
fsp_err_t	R_ETHSW_PortForwardAdd (ether_switch_ctrl_t *const p_ctrl, uint32_t port)
fsp_err_t	R_ETHSW_PortForwardDel (ether_switch_ctrl_t *const p_ctrl, uint32_t port)
fsp_err_t	R_ETHSW_FloodUnknownSet (ether_switch_ctrl_t *const p_ctrl, ethsw_flood_unknown_config_t *p_flood_config)
fsp_err_t	R_ETHSW_LinkStateGet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_link_status_t *p_state_link)
fsp_err_t	R_ETHSW_FrameSizeMaxSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, uint32_t frame_size_max)
fsp_err_t	R_ETHSW_DlrInitSet (ether_switch_ctrl_t *const p_ctrl, ethsw_dlr_init_t *p_dlr_init)
fsp_err_t	R_ETHSW_DlrUninitSet (ether_switch_ctrl_t *const p_ctrl)
fsp_err_t	R_ETHSW_DlrEnableSet (ether_switch_ctrl_t *const p_ctrl)
fsp_err_t	R_ETHSW_DlrDisableSet (ether_switch_ctrl_t *const p_ctrl)
fsp_err_t	R_ETHSW_DlrBeaconStateGet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_dlr_beacon_state_t *p_beacon_state)
fsp_err_t	R_ETHSW_DlrNodeStateGet (ether_switch_ctrl_t *const p_ctrl, ethsw_dlr_node_state_t *p_node_state)
fsp_err_t	R_ETHSW_DlrSvIpGet (ether_switch_ctrl_t *const p_ctrl, uint32_t *p_ip_addr)
fsp_err_t	R_ETHSW_DlrSvPriorityGet (ether_switch_ctrl_t *const p_ctrl, uint8_t *p_priority)
fsp_err_t	R_ETHSW_DlrVlanGet (ether_switch_ctrl_t *const p_ctrl, uint16_t *p_vlan_info)
fsp_err_t	R_ETHSW_DlrSvMacGet (ether_switch_ctrl_t *const p_ctrl, ethsw_mac_addr_t *p_addr_mac)
fsp_err_t	R_ETHSW_RxPatternMatcherSet (ether_switch_ctrl_t *const p_ctrl, ethsw_rx_pattern_matcher_t *p_rx_pattern_matcher)
fsp_err_t	R_ETHSW_RxPatternMatcherCallback (ether_switch_ctrl_t *const p_ctrl, void(*p_rx_pattern_callback_func)(ethsw_rx_pattern_event_t event, ethsw_rx_pattern_event_data_t *p_data))
fsp_err_t	R_ETHSW_PreemptQueueSet (ether_switch_ctrl_t *const p_ctrl, ethsw_preempt_queue_t *p_preempt_queue)
fsp_err_t	R_ETHSW_PreemptPortControlConfigSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_preempt_port_ctrl_config_t *p_preempt_port_ctrl)
fsp_err_t	R_ETHSW_PreemptPortControlEnableSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool frame_preempt_enable)
fsp_err_t	R_ETHSW_PreemptHoldReqForceSet (ether_switch_ctrl_t *const p_ctrl, ethsw_port_mask_t holdreq_request_port_mask)
fsp_err_t	R_ETHSW_PreemptHoldReqReleaseSet (ether_switch_ctrl_t *const p_ctrl, ethsw_port_mask_t holdreq_release_port_mask)
fsp_err_t	R_ETHSW_PreemptStatusGet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_preempt_status_t *p_preempt_status)
fsp_err_t	R_ETHSW_MmctlQgateSet (ether_switch_ctrl_t *const p_ctrl, ethsw_mmclt_qgate_t *p_mmctl_qgate)
fsp_err_t	R_ETHSW_MmctlPoolSizeSet (ether_switch_ctrl_t *const p_ctrl, ethsw_mmctl_pool_size_t *p_pool_size)
fsp_err_t	R_ETHSW_MmctlQueueAssignSet (ether_switch_ctrl_t *const p_ctrl, ethsw_mmctl_queue_assign_t *p_queue_assign)
fsp_err_t	R_ETHSW_MmctlYellowLengthSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_yellow_length_t *p_yellow_length)
fsp_err_t	R_ETHSW_QueueFlushEventSet (ether_switch_ctrl_t *const p_ctrl, ethsw_queue_flush_event_t *p_queue_flush_event)
fsp_err_t	R_ETHSW_MmctlQueueClosedNonemptyStatusGet (ether_switch_ctrl_t *const p_ctrl, ethsw_mmctl_qclosed_nonempty_t *p_qclosed_nonempty)
fsp_err_t	R_ETHSW_StatisticsSwitchGet (ether_switch_ctrl_t *const p_ctrl, bool clear, ethsw_statistics_switch_base_t *p_statistics_switch)
fsp_err_t	R_ETHSW_StatisticsMacGet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_statistics_mac_t *p_statistics_mac)
fsp_err_t	R_ETHSW_StatisticsMacClear (ether_switch_ctrl_t *const p_ctrl)
fsp_err_t	R_ETHSW_Statistics8023brGet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool clear, ethsw_statistics_8023br_t *p_statistics_8023br)
fsp_err_t	R_ETHSW_StatisticsDlrGet (ether_switch_ctrl_t *const p_ctrl, ethsw_statistics_dlr_t *p_statistics_dlr)
fsp_err_t	R_ETHSW_CqfEnableSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_cqf_enable_t *p_cqf_enable)
fsp_err_t	R_ETHSW_SnoopParserSet (ether_switch_ctrl_t *const p_ctrl, ethsw_snoop_parser_config_t *p_parser_cnf)
fsp_err_t	R_ETHSW_SnoopArithSet (ether_switch_ctrl_t *const p_ctrl, ethsw_snoop_arith_config_t *p_arith_cnf)
fsp_err_t	R_ETHSW_EeeSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_eee_t *p_cnf_eee)
fsp_err_t	R_ETHSW_StormTimeSet (ether_switch_ctrl_t *const p_ctrl, uint16_t storm_time)
fsp_err_t	R_ETHSW_BcastLimitSet (ether_switch_ctrl_t *const p_ctrl, uint16_t storm_frames)
fsp_err_t	R_ETHSW_McastLimitSet (ether_switch_ctrl_t *const p_ctrl, uint16_t storm_frames)
fsp_err_t	R_ETHSW_TxRateSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, float rate)
fsp_err_t	R_ETHSW_QosModeSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_qos_mode_t *p_qos_mode)
fsp_err_t	R_ETHSW_QosPrioValnSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_qos_prio_vlan_t *p_qos_prio_vlan)
fsp_err_t	R_ETHSW_QosPrioIpSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_qos_prio_ip_t *p_qos_prio_ip)
fsp_err_t	R_ETHSW_QosPrioTypeSet (ether_switch_ctrl_t *const p_ctrl, ethsw_qos_prio_type_t *p_qos_prio_ethtype)
fsp_err_t	R_ETHSW_MirrorSet (ether_switch_ctrl_t *const p_ctrl, ethsw_mirror_conf_t *p_mirror_conf)
fsp_err_t	R_ETHSW_CtEnableSet (ether_switch_ctrl_t *const p_ctrl, ethsw_port_mask_t port_mask)
fsp_err_t	R_ETHSW_CtDelaySet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, uint32_t ct_delay)
fsp_err_t	R_ETHSW_PulseGeneratorInit (ether_switch_ctrl_t *const p_ctrl, uint32_t time_num)
fsp_err_t	R_ETHSW_PulseGeneratorSet (ether_switch_ctrl_t *const p_ctrl, ethsw_ts_pulse_generator_t *p_pulse)
fsp_err_t	R_ETHSW_PortAuthSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool auth_state)
fsp_err_t	R_ETHSW_PortCtrlDirSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool dir_state)
fsp_err_t	R_ETHSW_PortEapolSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool eapol_state)
fsp_err_t	R_ETHSW_BpduSet (ether_switch_ctrl_t *const p_ctrl, bool bpdu_state)
fsp_err_t	R_ETHSW_VlanDefaultSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, uint16_t vlan_id)
fsp_err_t	R_ETHSW_VlanPortAdd (ether_switch_ctrl_t *const p_ctrl, uint32_t port, uint16_t vlan_id)
fsp_err_t	R_ETHSW_VlanPortRemove (ether_switch_ctrl_t *const p_ctrl, uint32_t port, uint16_t vlan_id)
fsp_err_t	R_ETHSW_VlanInModeSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_vlan_in_mode_t vlan_in_mode)
fsp_err_t	R_ETHSW_VlanOutModeSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_vlan_out_mode_t vlan_out_mode)
fsp_err_t	R_ETHSW_VlanVerifySet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool enable)
fsp_err_t	R_ETHSW_VlanDiscardUnknownSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool enable)
fsp_err_t	R_ETHSW_TdmaEnableSet (ether_switch_ctrl_t *const p_ctrl, ethsw_tdma_enable_t *p_tdma_enable)
fsp_err_t	R_ETHSW_TdmaScheduleSet (ether_switch_ctrl_t *const p_ctrl, ethsw_tdma_schedule_entry_t *p_tdma_schedule_entry, uint16_t tdma_schedule_entry_count)
fsp_err_t	R_ETHSW_TdmaGpioModeSet (ether_switch_ctrl_t *const p_ctrl, uint8_t gpio_num, ethsw_tdma_gpio_mode_t gpio_mode)
fsp_err_t	R_ETHSW_TdmaCounter0Set (ether_switch_ctrl_t *const p_ctrl, uint32_t tdma_counter0)
fsp_err_t	R_ETHSW_TdmaCounter0Get (ether_switch_ctrl_t *const p_ctrl, uint32_t *p_tdma_counter0)
fsp_err_t	R_ETHSW_TdmaCounter1Set (ether_switch_ctrl_t *const p_ctrl, ethsw_tdma_counter1_t *p_tdma_counter1)
fsp_err_t	R_ETHSW_TdmaCounter1Get (ether_switch_ctrl_t *const p_ctrl, ethsw_tdma_counter1_t *p_tdma_counter1)
fsp_err_t	R_ETHSW_TdmaHoldReqClear (ether_switch_ctrl_t *const p_ctrl)
fsp_err_t	R_ETHSW_TimeEnableSet (ether_switch_ctrl_t *const p_ctrl, ethsw_time_enable_t *p_time_enable)
fsp_err_t	R_ETHSW_TimeTransmitTimestampSet (ether_switch_ctrl_t *const p_ctrl, ethsw_time_transmit_t *p_time_transmit)
fsp_err_t	R_ETHSW_TimeValueSet (ether_switch_ctrl_t *const p_ctrl, ethsw_timestamp_t *p_timestamp)
fsp_err_t	R_ETHSW_TimeValueGet (ether_switch_ctrl_t *const p_ctrl, ethsw_timestamp_t *p_timestamp)
fsp_err_t	R_ETHSW_TimeValueGetAll (ether_switch_ctrl_t *const p_ctrl, ethsw_timestamp_t *p_timer0, ethsw_timestamp_t *p_timer1)
fsp_err_t	R_ETHSW_TimePeerDelaySet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_time_peerdelay_t *p_peerdelay)
fsp_err_t	R_ETHSW_TimeOffsetSet (ether_switch_ctrl_t *const p_ctrl, ethsw_time_offset_correction_t *p_offset)
fsp_err_t	R_ETHSW_TimeRateSet (ether_switch_ctrl_t *const p_ctrl, ethsw_time_rate_correction_t *p_rate)
fsp_err_t	R_ETHSW_TimeDomainSet (ether_switch_ctrl_t *const p_ctrl, ethsw_time_domain_t *p_domain)
fsp_err_t	R_GMAC_Open (ether_ctrl_t *const p_ctrl, ether_cfg_t const *const p_cfg)
fsp_err_t	R_GMAC_Close (ether_ctrl_t *const p_ctrl)
fsp_err_t	R_GMAC_Read (ether_ctrl_t *const p_ctrl, void *const p_buffer, uint32_t *const length_bytes)
fsp_err_t	R_GMAC_BufferRelease (ether_ctrl_t *const p_ctrl)
fsp_err_t	R_GMAC_RxBufferUpdate (ether_ctrl_t *const p_ctrl, void *const p_buffer)
fsp_err_t	R_GMAC_Write (ether_ctrl_t *const p_ctrl, void *const p_buffer, uint32_t const frame_length)
fsp_err_t	R_GMAC_LinkProcess (ether_ctrl_t *const p_ctrl)
fsp_err_t	R_GMAC_GetLinkStatus (ether_ctrl_t *const p_ctrl, uint8_t port, gmac_link_status_t *p_status)
fsp_err_t	R_GMAC_WakeOnLANEnable (ether_ctrl_t *const p_ctrl)
fsp_err_t	R_GMAC_TxStatusGet (ether_ctrl_t *const p_ctrl, void *const p_buffer_address)
fsp_err_t	R_GMAC_CallbackSet (ether_ctrl_t *const p_ctrl, void(*p_callback)(ether_callback_args_t *), void *const p_context, ether_callback_args_t *const p_callback_memory)
fsp_err_t	R_GMAC_B_Open (ether_ctrl_t *const p_ctrl, ether_cfg_t const *const p_cfg)
fsp_err_t	R_GMAC_B_Close (ether_ctrl_t *const p_ctrl)
fsp_err_t	R_GMAC_B_Read (ether_ctrl_t *const p_ctrl, void *const p_buffer, uint32_t *const length_bytes)
fsp_err_t	R_GMAC_B_BufferRelease (ether_ctrl_t *const p_ctrl)
fsp_err_t	R_GMAC_B_RxBufferUpdate (ether_ctrl_t *const p_ctrl, void *const p_buffer)
fsp_err_t	R_GMAC_B_Write (ether_ctrl_t *const p_ctrl, void *const p_buffer, uint32_t const frame_length)
fsp_err_t	R_GMAC_B_LinkProcess (ether_ctrl_t *const p_ctrl)
fsp_err_t	R_GMAC_B_GetLinkStatus (ether_ctrl_t *const p_ctrl, uint8_t port, gmac_b_link_status_t *p_status)
fsp_err_t	R_GMAC_B_WakeOnLANEnable (ether_ctrl_t *const p_ctrl)
fsp_err_t	R_GMAC_B_TxStatusGet (ether_ctrl_t *const p_ctrl, void *const p_buffer_address)
fsp_err_t	R_GMAC_B_CallbackSet (ether_ctrl_t *const p_ctrl, void(*p_callback)(ether_callback_args_t *), void *const p_context, ether_callback_args_t *const p_callback_memory)
fsp_err_t	R_GPT_Open (timer_ctrl_t *const p_ctrl, timer_cfg_t const *const p_cfg)
fsp_err_t	R_GPT_Stop (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_GPT_Start (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_GPT_Reset (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_GPT_Enable (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_GPT_Disable (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_GPT_PeriodSet (timer_ctrl_t *const p_ctrl, uint32_t const period_counts)
fsp_err_t	R_GPT_DutyCycleSet (timer_ctrl_t *const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin)
fsp_err_t	R_GPT_CompareMatchSet (timer_ctrl_t *const p_ctrl, uint32_t const compare_match_value, timer_compare_match_t const match_channel)
fsp_err_t	R_GPT_InfoGet (timer_ctrl_t *const p_ctrl, timer_info_t *const p_info)
fsp_err_t	R_GPT_StatusGet (timer_ctrl_t *const p_ctrl, timer_status_t *const p_status)
fsp_err_t	R_GPT_CounterSet (timer_ctrl_t *const p_ctrl, uint32_t counter)
fsp_err_t	R_GPT_OutputEnable (timer_ctrl_t *const p_ctrl, gpt_io_pin_t pin)
fsp_err_t	R_GPT_OutputDisable (timer_ctrl_t *const p_ctrl, gpt_io_pin_t pin)
fsp_err_t	R_GPT_AdcTriggerSet (timer_ctrl_t *const p_ctrl, gpt_adc_compare_match_t which_compare_match, uint32_t compare_match_value)
fsp_err_t	R_GPT_CallbackSet (timer_ctrl_t *const p_ctrl, void(*p_callback)(timer_callback_args_t *), void *const p_context, timer_callback_args_t *const p_callback_memory)
fsp_err_t	R_GPT_Close (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_GPT_THREE_PHASE_Open (three_phase_ctrl_t *const p_ctrl, three_phase_cfg_t const *const p_cfg)
fsp_err_t	R_GPT_THREE_PHASE_Stop (three_phase_ctrl_t *const p_ctrl)
fsp_err_t	R_GPT_THREE_PHASE_Start (three_phase_ctrl_t *const p_ctrl)
fsp_err_t	R_GPT_THREE_PHASE_Reset (three_phase_ctrl_t *const p_ctrl)
fsp_err_t	R_GPT_THREE_PHASE_DutyCycleSet (three_phase_ctrl_t *const p_ctrl, three_phase_duty_cycle_t *const p_duty_cycle)
fsp_err_t	R_GPT_THREE_PHASE_CallbackSet (three_phase_ctrl_t *const p_ctrl, void(*p_callback)(timer_callback_args_t *), void *const p_context, timer_callback_args_t *const p_callback_memory)
fsp_err_t	R_GPT_THREE_PHASE_Close (three_phase_ctrl_t *const p_ctrl)
fsp_err_t	R_ICU_ExternalIrqOpen (external_irq_ctrl_t *const p_ctrl, external_irq_cfg_t const *const p_cfg)
fsp_err_t	R_ICU_ExternalIrqEnable (external_irq_ctrl_t *const p_ctrl)
fsp_err_t	R_ICU_ExternalIrqDisable (external_irq_ctrl_t *const p_ctrl)
fsp_err_t	R_ICU_ExternalIrqCallbackSet (external_irq_ctrl_t *const p_ctrl, void(*p_callback)(external_irq_callback_args_t *), void *const p_context, external_irq_callback_args_t *const p_callback_memory)
fsp_err_t	R_ICU_ExternalIrqClose (external_irq_ctrl_t *const p_ctrl)
fsp_err_t	R_ICU_INTER_CPU_IRQ_Open (icu_inter_cpu_irq_ctrl_t *const p_ctrl, icu_inter_cpu_irq_cfg_t const *const p_cfg)
fsp_err_t	R_ICU_INTER_CPU_IRQ_Generate (icu_inter_cpu_irq_ctrl_t *const p_ctrl)
fsp_err_t	R_ICU_INTER_CPU_IRQ_CallbackSet (icu_inter_cpu_irq_ctrl_t *const p_ctrl, void(*p_callback)(icu_inter_cpu_irq_callback_args_t *), void *const p_context, icu_inter_cpu_irq_callback_args_t *const p_callback_memory)
fsp_err_t	R_ICU_INTER_CPU_IRQ_Close (icu_inter_cpu_irq_ctrl_t *const p_ctrl)
fsp_err_t	R_IIC_MASTER_Open (i2c_master_ctrl_t *const p_ctrl, i2c_master_cfg_t const *const p_cfg)
fsp_err_t	R_IIC_MASTER_Read (i2c_master_ctrl_t *const p_ctrl, uint8_t *const p_dest, uint32_t const bytes, bool const restart)
fsp_err_t	R_IIC_MASTER_Write (i2c_master_ctrl_t *const p_ctrl, uint8_t *const p_src, uint32_t const bytes, bool const restart)
fsp_err_t	R_IIC_MASTER_Abort (i2c_master_ctrl_t *const p_ctrl)
fsp_err_t	R_IIC_MASTER_SlaveAddressSet (i2c_master_ctrl_t *const p_ctrl, uint32_t const slave, i2c_master_addr_mode_t const addr_mode)
fsp_err_t	R_IIC_MASTER_Close (i2c_master_ctrl_t *const p_ctrl)
fsp_err_t	R_IIC_MASTER_CallbackSet (i2c_master_ctrl_t *const p_ctrl, void(*p_callback)(i2c_master_callback_args_t *), void *const p_context, i2c_master_callback_args_t *const p_callback_memory)
fsp_err_t	R_IIC_MASTER_StatusGet (i2c_master_ctrl_t *const p_ctrl, i2c_master_status_t *p_status)
fsp_err_t	R_IIC_SLAVE_Open (i2c_slave_ctrl_t *const p_ctrl, i2c_slave_cfg_t const *const p_cfg)
fsp_err_t	R_IIC_SLAVE_Read (i2c_slave_ctrl_t *const p_ctrl, uint8_t *const p_dest, uint32_t const bytes)
fsp_err_t	R_IIC_SLAVE_Write (i2c_slave_ctrl_t *const p_ctrl, uint8_t *const p_src, uint32_t const bytes)
fsp_err_t	R_IIC_SLAVE_Close (i2c_slave_ctrl_t *const p_ctrl)
fsp_err_t	R_IIC_SLAVE_CallbackSet (i2c_slave_ctrl_t *const p_ctrl, void(*p_callback)(i2c_slave_callback_args_t *), void *const p_context, i2c_slave_callback_args_t *const p_callback_memory)
fsp_err_t	R_IOPORT_Open (ioport_ctrl_t *const p_ctrl, const ioport_cfg_t *p_cfg)
fsp_err_t	R_IOPORT_Close (ioport_ctrl_t *const p_ctrl)
fsp_err_t	R_IOPORT_PinsCfg (ioport_ctrl_t *const p_ctrl, const ioport_cfg_t *p_cfg)
fsp_err_t	R_IOPORT_PinCfg (ioport_ctrl_t *const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg)
fsp_err_t	R_IOPORT_PinEventInputRead (ioport_ctrl_t *const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t *p_pin_event)
fsp_err_t	R_IOPORT_PinEventOutputWrite (ioport_ctrl_t *const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value)
fsp_err_t	R_IOPORT_PinRead (ioport_ctrl_t *const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t *p_pin_value)
fsp_err_t	R_IOPORT_PinWrite (ioport_ctrl_t *const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level)
fsp_err_t	R_IOPORT_PortDirectionSet (ioport_ctrl_t *const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, ioport_size_t mask)
fsp_err_t	R_IOPORT_PortEventInputRead (ioport_ctrl_t *const p_ctrl, bsp_io_port_t port, ioport_size_t *p_event_data)
fsp_err_t	R_IOPORT_PortEventOutputWrite (ioport_ctrl_t *const p_ctrl, bsp_io_port_t port, ioport_size_t event_data, ioport_size_t mask_value)
fsp_err_t	R_IOPORT_PortRead (ioport_ctrl_t *const p_ctrl, bsp_io_port_t port, ioport_size_t *p_port_value)
fsp_err_t	R_IOPORT_PortWrite (ioport_ctrl_t *const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask)
fsp_err_t	R_LCDC_Open (display_ctrl_t *const p_api_ctrl, display_cfg_t const *const p_cfg)
fsp_err_t	R_LCDC_Close (display_ctrl_t *const p_api_ctrl)
fsp_err_t	R_LCDC_Start (display_ctrl_t *const p_api_ctrl)
fsp_err_t	R_LCDC_Stop (display_ctrl_t *const p_api_ctrl)
fsp_err_t	R_LCDC_LayerChange (display_ctrl_t const *const p_api_ctrl, display_runtime_cfg_t const *const p_cfg, display_frame_layer_t layer)
fsp_err_t	R_LCDC_BufferChange (display_ctrl_t const *const p_api_ctrl, uint8_t *const framebuffer, display_frame_layer_t layer)
fsp_err_t	R_LCDC_ColorCorrection (display_ctrl_t const *const p_api_ctrl, display_correction_t const *const p_correction)
fsp_err_t	R_LCDC_ClutUpdate (display_ctrl_t const *const p_api_ctrl, display_clut_cfg_t const *const p_clut_cfg, display_frame_layer_t layer)
fsp_err_t	R_LCDC_ClutEdit (display_ctrl_t const *const p_api_ctrl, display_frame_layer_t layer, uint8_t index, uint32_t color)
fsp_err_t	R_LCDC_ColorKeySet (display_ctrl_t const *const p_api_ctrl, display_colorkeying_layer_t ck_cfg, display_frame_layer_t layer)
fsp_err_t	R_LCDC_StatusGet (display_ctrl_t const *const p_api_ctrl, display_status_t *const p_status)
fsp_err_t	R_MTU3_Open (timer_ctrl_t *const p_ctrl, timer_cfg_t const *const p_cfg)
fsp_err_t	R_MTU3_Stop (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_Start (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_Reset (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_PeriodSet (timer_ctrl_t *const p_ctrl, uint32_t const period_counts)
fsp_err_t	R_MTU3_DutyCycleSet (timer_ctrl_t *const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin)
fsp_err_t	R_MTU3_CompareMatchSet (timer_ctrl_t *const p_ctrl, uint32_t const compare_match_value, timer_compare_match_t const match_channel)
fsp_err_t	R_MTU3_InfoGet (timer_ctrl_t *const p_ctrl, timer_info_t *const p_info)
fsp_err_t	R_MTU3_StatusGet (timer_ctrl_t *const p_ctrl, timer_status_t *const p_status)
fsp_err_t	R_MTU3_CounterSet (timer_ctrl_t *const p_ctrl, uint32_t counter)
fsp_err_t	R_MTU3_OutputEnable (timer_ctrl_t *const p_ctrl, mtu3_output_pin_t pin_level)
fsp_err_t	R_MTU3_OutputDisable (timer_ctrl_t *const p_ctrl, mtu3_io_pin_t pin)
fsp_err_t	R_MTU3_Enable (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_Disable (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_AdcTriggerSet (timer_ctrl_t *const p_ctrl, mtu3_adc_compare_match_t which_compare_match, uint16_t compare_match_value)
fsp_err_t	R_MTU3_CallbackSet (timer_ctrl_t *const p_ctrl, void(*p_callback)(timer_callback_args_t *), void *const p_context, timer_callback_args_t *const p_callback_memory)
fsp_err_t	R_MTU3_Close (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_THREE_PHASE_Open (three_phase_ctrl_t *const p_ctrl, three_phase_cfg_t const *const p_cfg)
fsp_err_t	R_MTU3_THREE_PHASE_Stop (three_phase_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_THREE_PHASE_Start (three_phase_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_THREE_PHASE_Reset (three_phase_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_THREE_PHASE_DutyCycleSet (three_phase_ctrl_t *const p_ctrl, three_phase_duty_cycle_t *const p_duty_cycle)
fsp_err_t	R_MTU3_THREE_PHASE_CallbackSet (three_phase_ctrl_t *const p_ctrl, void(*p_callback)(timer_callback_args_t *), void *const p_context, timer_callback_args_t *const p_callback_memory)
fsp_err_t	R_MTU3_THREE_PHASE_Close (three_phase_ctrl_t *const p_ctrl)
fsp_err_t	R_PCIE_EP_Open (pci_ctrl_t *const p_ctrl, pci_cfg_t const *const p_cfg)
fsp_err_t	R_PCIE_EP_ConfigurationRegisterWrite (pci_ctrl_t *const p_ctrl, pci_configuration_write_type_t transaction_type, pci_configuration_register_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_EP_ConfigurationRegisterRead (pci_ctrl_t *const p_ctrl, pci_configuration_read_type_t transaction_type, pci_configuration_register_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_EP_SelfConfigurationRegisterGet (pci_ctrl_t *const p_ctrl, uint32_t register_number, uint32_t *p_data)
fsp_err_t	R_PCIE_EP_SelfConfigurationRegisterSet (pci_ctrl_t *const p_ctrl, uint32_t register_number, uint32_t data)
fsp_err_t	R_PCIE_EP_IORegisterWrite (pci_ctrl_t *const p_ctrl, pci_io_register_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_EP_IORegisterRead (pci_ctrl_t *const p_ctrl, pci_io_register_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_EP_MessageWrite (pci_ctrl_t *const p_ctrl, pci_message_transfer_t *const p_transfer, bool with_data)
fsp_err_t	R_PCIE_EP_MessageRead (pci_ctrl_t *const p_ctrl, pci_message_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_EP_IntxAssert (pci_ctrl_t *const p_ctrl)
fsp_err_t	R_PCIE_EP_IntxDeassert (pci_ctrl_t *const p_ctrl)
fsp_err_t	R_PCIE_EP_LinkStatusGet (pci_ctrl_t *const p_ctrl, pci_status_t *const p_status)
fsp_err_t	R_PCIE_EP_LinkWidthChange (pci_ctrl_t *const p_ctrl, uint32_t link_width, uint32_t option)
fsp_err_t	R_PCIE_EP_LinkSpeedChange (pci_ctrl_t *const p_ctrl, pci_link_speed_t link_speed, uint32_t option)
fsp_err_t	R_PCIE_EP_LinkEqualizationRequest (pci_ctrl_t *const p_ctrl)
fsp_err_t	R_PCIE_EP_CallbackSet (pci_ctrl_t *const p_ctrl, void(*p_callback)(pci_callback_args_t *), void *const p_context, pci_callback_args_t *const p_callback_memory)
fsp_err_t	R_PCIE_EP_Close (pci_ctrl_t *const p_ctrl)
fsp_err_t	R_PCIE_RC_Open (pci_ctrl_t *const p_ctrl, pci_cfg_t const *const p_cfg)
fsp_err_t	R_PCIE_RC_SelfConfigurationRegisterGet (pci_ctrl_t *const p_ctrl, uint32_t register_number, uint32_t *p_data)
fsp_err_t	R_PCIE_RC_SelfConfigurationRegisterSet (pci_ctrl_t *const p_ctrl, uint32_t register_number, uint32_t data)
fsp_err_t	R_PCIE_RC_MessageWrite (pci_ctrl_t *const p_ctrl, pci_message_transfer_t *const p_transfer, bool with_data)
fsp_err_t	R_PCIE_RC_MessageRead (pci_ctrl_t *const p_ctrl, pci_message_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_RC_ConfigurationRegisterWrite (pci_ctrl_t *const p_ctrl, pci_configuration_write_type_t transaction_type, pci_configuration_register_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_RC_ConfigurationRegisterRead (pci_ctrl_t *const p_ctrl, pci_configuration_read_type_t transaction_type, pci_configuration_register_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_RC_IORegisterWrite (pci_ctrl_t *const p_ctrl, pci_io_register_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_RC_IORegisterRead (pci_ctrl_t *const p_ctrl, pci_io_register_transfer_t *const p_transfer)
fsp_err_t	R_PCIE_RC_LinkStatusGet (pci_ctrl_t *const p_ctrl, pci_status_t *const p_status)
fsp_err_t	R_PCIE_RC_IntxAssert (pci_ctrl_t *const p_ctrl)
fsp_err_t	R_PCIE_RC_IntxDeassert (pci_ctrl_t *const p_ctrl)
fsp_err_t	R_PCIE_RC_LinkWidthChange (pci_ctrl_t *const p_ctrl, uint32_t link_width, uint32_t option)
fsp_err_t	R_PCIE_RC_LinkSpeedChange (pci_ctrl_t *const p_ctrl, pci_link_speed_t link_speed, uint32_t option)
fsp_err_t	R_PCIE_RC_LinkEqualizationRequest (pci_ctrl_t *const p_ctrl)
fsp_err_t	R_PCIE_RC_CallbackSet (pci_ctrl_t *const p_ctrl, void(*p_callback)(pci_callback_args_t *), void *const p_context, pci_callback_args_t *const p_callback_memory)
fsp_err_t	R_PCIE_RC_Close (pci_ctrl_t *const p_ctrl)
fsp_err_t	R_POE3_Open (poe3_ctrl_t *const p_ctrl, poe3_cfg_t const *const p_cfg)
fsp_err_t	R_POE3_OutputDisable (poe3_ctrl_t *const p_ctrl)
fsp_err_t	R_POE3_Reset (poe3_ctrl_t *const p_ctrl)
fsp_err_t	R_POE3_StatusGet (poe3_ctrl_t *const p_ctrl, poe3_status_t *const p_status)
fsp_err_t	R_POE3_Close (poe3_ctrl_t *const p_ctrl)
fsp_err_t	R_POE3_CallbackSet (poe3_ctrl_t *const p_ctrl, void(*p_callback)(poe3_callback_args_t *), void *const p_context, poe3_callback_args_t *const p_callback_memory)
fsp_err_t	R_POEG_Open (poeg_ctrl_t *const p_ctrl, poeg_cfg_t const *const p_cfg)
fsp_err_t	R_POEG_OutputDisable (poeg_ctrl_t *const p_ctrl)
fsp_err_t	R_POEG_Reset (poeg_ctrl_t *const p_ctrl)
fsp_err_t	R_POEG_StatusGet (poeg_ctrl_t *const p_ctrl, poeg_status_t *const p_status)
fsp_err_t	R_POEG_CallbackSet (poeg_ctrl_t *const p_ctrl, void(*p_callback)(poeg_callback_args_t *), void *const p_context, poeg_callback_args_t *const p_callback_memory)
fsp_err_t	R_POEG_Close (poeg_ctrl_t *const p_ctrl)
fsp_err_t	R_RTC_Open (rtc_ctrl_t *const p_ctrl, rtc_cfg_t const *const p_cfg)
fsp_err_t	R_RTC_Close (rtc_ctrl_t *const p_ctrl)
fsp_err_t	R_RTC_ClockSourceSet (rtc_ctrl_t *const p_ctrl)
fsp_err_t	R_RTC_CalendarTimeSet (rtc_ctrl_t *const p_ctrl, rtc_time_t *const p_time)
fsp_err_t	R_RTC_CalendarTimeGet (rtc_ctrl_t *const p_ctrl, rtc_time_t *const p_time)
fsp_err_t	R_RTC_CalendarAlarmSet (rtc_ctrl_t *const p_ctrl, rtc_alarm_time_t *const p_alarm)
fsp_err_t	R_RTC_CalendarAlarmGet (rtc_ctrl_t *const p_ctrl, rtc_alarm_time_t *const p_alarm)
fsp_err_t	R_RTC_PeriodicIrqRateSet (rtc_ctrl_t *const p_ctrl, rtc_periodic_irq_select_t const rate)
fsp_err_t	R_RTC_ErrorAdjustmentSet (rtc_ctrl_t *const p_ctrl, rtc_error_adjustment_cfg_t const *const err_adj_cfg)
fsp_err_t	R_RTC_InfoGet (rtc_ctrl_t *const p_ctrl, rtc_info_t *const p_rtc_info)
fsp_err_t	R_RTC_CallbackSet (rtc_ctrl_t *const p_ctrl, void(*p_callback)(rtc_callback_args_t *), void *const p_context, rtc_callback_args_t *const p_callback_memory)
fsp_err_t	R_RTC_TimeCaptureSet (rtc_ctrl_t *const p_ctrl, rtc_time_capture_t *const p_time_capture)
fsp_err_t	R_RTC_TimeCaptureGet (rtc_ctrl_t *const p_ctrl, rtc_time_capture_t *const p_time_capture)
fsp_err_t	R_SCI_I2C_Open (i2c_master_ctrl_t *const p_ctrl, i2c_master_cfg_t const *const p_cfg)
fsp_err_t	R_SCI_I2C_Close (i2c_master_ctrl_t *const p_ctrl)
fsp_err_t	R_SCI_I2C_Read (i2c_master_ctrl_t *const p_ctrl, uint8_t *const p_dest, uint32_t const bytes, bool const restart)
fsp_err_t	R_SCI_I2C_Write (i2c_master_ctrl_t *const p_ctrl, uint8_t *const p_src, uint32_t const bytes, bool const restart)
fsp_err_t	R_SCI_I2C_Abort (i2c_master_ctrl_t *const p_ctrl)
fsp_err_t	R_SCI_I2C_SlaveAddressSet (i2c_master_ctrl_t *const p_ctrl, uint32_t const slave, i2c_master_addr_mode_t const addr_mode)
fsp_err_t	R_SCI_I2C_CallbackSet (i2c_master_ctrl_t *const p_ctrl, void(*p_callback)(i2c_master_callback_args_t *), void *const p_context, i2c_master_callback_args_t *const p_callback_memory)
fsp_err_t	R_SCI_I2C_StatusGet (i2c_master_ctrl_t *const p_ctrl, i2c_master_status_t *p_status)
fsp_err_t	R_SCI_SMCI_Open (smci_ctrl_t *const p_ctrl, smci_cfg_t const *const p_cfg)
fsp_err_t	R_SCI_SMCI_Write (smci_ctrl_t *const p_ctrl, uint8_t const *const p_src, uint32_t const bytes)
fsp_err_t	R_SCI_SMCI_Read (smci_ctrl_t *const p_ctrl, uint8_t *const p_dest, uint32_t const bytes)
fsp_err_t	R_SCI_SMCI_TransferModeSet (smci_ctrl_t *const p_ctrl, smci_transfer_mode_t const *const p_transfer_mode_params)
fsp_err_t	R_SCI_SMCI_BaudCalculate (smci_speed_params_t const *const p_speed_params, uint32_t baud_rate_error_x_1000, sci_smci_clock_source_t clock_source, void *const p_baud_setting)
fsp_err_t	R_SCI_SMCI_BaudSet (smci_ctrl_t *const p_ctrl, void const *const p_baud_setting)
fsp_err_t	R_SCI_SMCI_StatusGet (smci_ctrl_t *const p_ctrl, smci_status_t *const p_status)
fsp_err_t	R_SCI_SMCI_ClockControl (smci_ctrl_t *const p_ctrl, bool clock_enable)
fsp_err_t	R_SCI_SMCI_CallbackSet (smci_ctrl_t *const p_ctrl, void(*p_callback)(smci_callback_args_t *), void *const p_context, smci_callback_args_t *const p_callback_memory)
fsp_err_t	R_SCI_SMCI_Close (smci_ctrl_t *const p_ctrl)
fsp_err_t	R_SCI_SPI_Open (spi_ctrl_t *p_ctrl, spi_cfg_t const *const p_cfg)
fsp_err_t	R_SCI_SPI_Read (spi_ctrl_t *const p_ctrl, void *p_dest, uint32_t const length, spi_bit_width_t const bit_width)
fsp_err_t	R_SCI_SPI_Write (spi_ctrl_t *const p_ctrl, void const *p_src, uint32_t const length, spi_bit_width_t const bit_width)
fsp_err_t	R_SCI_SPI_WriteRead (spi_ctrl_t *const p_ctrl, void const *p_src, void *p_dest, uint32_t const length, spi_bit_width_t const bit_width)
fsp_err_t	R_SCI_SPI_Close (spi_ctrl_t *const p_ctrl)
fsp_err_t	R_SCI_SPI_CalculateBitrate (uint32_t bitrate, sci_spi_clock_source_t clock_source, sci_spi_div_setting_t *sclk_div)
fsp_err_t	R_SCI_SPI_CallbackSet (spi_ctrl_t *const p_ctrl, void(*p_callback)(spi_callback_args_t *), void *const p_context, spi_callback_args_t *const p_callback_memory)
fsp_err_t	R_SCI_UART_Open (uart_ctrl_t *const p_ctrl, uart_cfg_t const *const p_cfg)
fsp_err_t	R_SCI_UART_Read (uart_ctrl_t *const p_ctrl, uint8_t *const p_dest, uint32_t const bytes)
fsp_err_t	R_SCI_UART_Write (uart_ctrl_t *const p_ctrl, uint8_t const *const p_src, uint32_t const bytes)
fsp_err_t	R_SCI_UART_BaudSet (uart_ctrl_t *const p_ctrl, void const *const p_baud_setting)
fsp_err_t	R_SCI_UART_InfoGet (uart_ctrl_t *const p_ctrl, uart_info_t *const p_info)
fsp_err_t	R_SCI_UART_Close (uart_ctrl_t *const p_ctrl)
fsp_err_t	R_SCI_UART_Abort (uart_ctrl_t *const p_ctrl, uart_dir_t communication_to_abort)
fsp_err_t	R_SCI_UART_BaudCalculate (sci_uart_baud_calculation_t const *const p_baud_target, sci_uart_clock_source_t clock_source, sci_baud_setting_t *const p_baud_setting)
fsp_err_t	R_SCI_UART_CallbackSet (uart_ctrl_t *const p_ctrl, void(*p_callback)(uart_callback_args_t *), void *const p_context, uart_callback_args_t *const p_callback_memory)
fsp_err_t	R_SCI_UART_ReadStop (uart_ctrl_t *const p_ctrl, uint32_t *remaining_bytes)
fsp_err_t	R_SCI_UART_ReceiveSuspend (uart_ctrl_t *const p_api_ctrl)
fsp_err_t	R_SCI_UART_ReceiveResume (uart_ctrl_t *const p_api_ctrl)
fsp_err_t	R_SDHI_Open (sdmmc_ctrl_t *const p_api_ctrl, sdmmc_cfg_t const *const p_cfg)
fsp_err_t	R_SDHI_MediaInit (sdmmc_ctrl_t *const p_api_ctrl, sdmmc_device_t *const p_device)
fsp_err_t	R_SDHI_Read (sdmmc_ctrl_t *const p_api_ctrl, uint8_t *const p_dest, uint32_t const start_sector, uint32_t const sector_count)
fsp_err_t	R_SDHI_Write (sdmmc_ctrl_t *const p_api_ctrl, uint8_t const *const p_source, uint32_t const start_sector, uint32_t const sector_count)
fsp_err_t	R_SDHI_ReadIo (sdmmc_ctrl_t *const p_api_ctrl, uint8_t *const p_data, uint32_t const function, uint32_t const address)
fsp_err_t	R_SDHI_WriteIo (sdmmc_ctrl_t *const p_api_ctrl, uint8_t *const p_data, uint32_t const function, uint32_t const address, sdmmc_io_write_mode_t const read_after_write)
fsp_err_t	R_SDHI_ReadIoExt (sdmmc_ctrl_t *const p_api_ctrl, uint8_t *const p_dest, uint32_t const function, uint32_t const address, uint32_t *const count, sdmmc_io_transfer_mode_t transfer_mode, sdmmc_io_address_mode_t address_mode)
fsp_err_t	R_SDHI_WriteIoExt (sdmmc_ctrl_t *const p_api_ctrl, uint8_t const *const p_source, uint32_t const function, uint32_t const address, uint32_t const count, sdmmc_io_transfer_mode_t transfer_mode, sdmmc_io_address_mode_t address_mode)
fsp_err_t	R_SDHI_IoIntEnable (sdmmc_ctrl_t *const p_api_ctrl, bool enable)
fsp_err_t	R_SDHI_StatusGet (sdmmc_ctrl_t *const p_api_ctrl, sdmmc_status_t *const p_status)
fsp_err_t	R_SDHI_Erase (sdmmc_ctrl_t *const p_api_ctrl, uint32_t const start_sector, uint32_t const sector_count)
fsp_err_t	R_SDHI_CallbackSet (sdmmc_ctrl_t *const p_api_ctrl, void(*p_callback)(sdmmc_callback_args_t *), void *const p_context, sdmmc_callback_args_t *const p_callback_memory)
fsp_err_t	R_SDHI_Close (sdmmc_ctrl_t *const p_api_ctrl)
fsp_err_t	R_SHARED_MEMORY_Open (shared_memory_ctrl_t *const p_ctrl, shared_memory_cfg_t const *const p_cfg)
fsp_err_t	R_SHARED_MEMORY_Read (shared_memory_ctrl_t *const p_ctrl, uint8_t *const p_dest, uint32_t const offset, uint32_t const bytes)
fsp_err_t	R_SHARED_MEMORY_Write (shared_memory_ctrl_t *const p_ctrl, uint8_t *const p_src, uint32_t const offset, uint32_t const bytes)
fsp_err_t	R_SHARED_MEMORY_StatusGet (shared_memory_ctrl_t *const p_ctrl, shared_memory_status_t *p_status)
fsp_err_t	R_SHARED_MEMORY_CallbackSet (shared_memory_ctrl_t *const p_ctrl, void(*p_callback)(shared_memory_callback_args_t *), void *const p_context, shared_memory_callback_args_t *const p_callback_memory)
fsp_err_t	R_SHARED_MEMORY_Close (shared_memory_ctrl_t *const p_ctrl)
fsp_err_t	R_SPI_Open (spi_ctrl_t *p_ctrl, spi_cfg_t const *const p_cfg)
fsp_err_t	R_SPI_Read (spi_ctrl_t *const p_ctrl, void *p_dest, uint32_t const length, spi_bit_width_t const bit_width)
fsp_err_t	R_SPI_Write (spi_ctrl_t *const p_ctrl, void const *p_src, uint32_t const length, spi_bit_width_t const bit_width)
fsp_err_t	R_SPI_WriteRead (spi_ctrl_t *const p_ctrl, void const *p_src, void *p_dest, uint32_t const length, spi_bit_width_t const bit_width)
fsp_err_t	R_SPI_Close (spi_ctrl_t *const p_ctrl)
fsp_err_t	R_SPI_CalculateBitrate (uint32_t bitrate, spi_clock_source_t clock_source, rspck_div_setting_t *spck_div)
fsp_err_t	R_SPI_CallbackSet (spi_ctrl_t *const p_ctrl, void(*p_callback)(spi_callback_args_t *), void *const p_context, spi_callback_args_t *const p_callback_memory)
fsp_err_t	R_TSU_Open (adc_ctrl_t *p_ctrl, adc_cfg_t const *const p_cfg)
fsp_err_t	R_TSU_ScanCfg (adc_ctrl_t *p_ctrl, void const *const p_extend)
fsp_err_t	R_TSU_ScanStart (adc_ctrl_t *p_ctrl)
fsp_err_t	R_TSU_ScanGroupStart (adc_ctrl_t *p_ctrl, adc_group_mask_t group_mask)
fsp_err_t	R_TSU_ScanStop (adc_ctrl_t *p_ctrl)
fsp_err_t	R_TSU_StatusGet (adc_ctrl_t *p_ctrl, adc_status_t *p_status)
fsp_err_t	R_TSU_Read (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint16_t *const p_data)
fsp_err_t	R_TSU_Read32 (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint32_t *const p_data)
fsp_err_t	R_TSU_Close (adc_ctrl_t *p_ctrl)
fsp_err_t	R_TSU_InfoGet (adc_ctrl_t *p_ctrl, adc_info_t *p_adc_info)
fsp_err_t	R_TSU_Calibrate (adc_ctrl_t *const p_ctrl, void const *p_extend)
fsp_err_t	R_TSU_OffsetSet (adc_ctrl_t *const p_ctrl, adc_channel_t const reg_id, int32_t offset)
fsp_err_t	R_TSU_CallbackSet (adc_ctrl_t *const p_ctrl, void(*p_callback)(adc_callback_args_t *), void *const p_context, adc_callback_args_t *const p_callback_memory)
fsp_err_t	R_TSU_B_Open (adc_ctrl_t *p_ctrl, adc_cfg_t const *const p_cfg)
fsp_err_t	R_TSU_B_ScanCfg (adc_ctrl_t *p_ctrl, void const *const p_channel_cfg)
fsp_err_t	R_TSU_B_ScanStart (adc_ctrl_t *p_ctrl)
fsp_err_t	R_TSU_B_ScanGroupStart (adc_ctrl_t *p_ctrl, adc_group_mask_t group_id)
fsp_err_t	R_TSU_B_ScanStop (adc_ctrl_t *p_ctrl)
fsp_err_t	R_TSU_B_StatusGet (adc_ctrl_t *p_ctrl, adc_status_t *p_status)
fsp_err_t	R_TSU_B_Read (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint16_t *const p_data)
fsp_err_t	R_TSU_B_Read32 (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint32_t *const p_data)
fsp_err_t	R_TSU_B_Close (adc_ctrl_t *p_ctrl)
fsp_err_t	R_TSU_B_InfoGet (adc_ctrl_t *p_ctrl, adc_info_t *p_adc_info)
fsp_err_t	R_TSU_B_Calibrate (adc_ctrl_t *const p_ctrl, void const *p_extend)
fsp_err_t	R_TSU_B_OffsetSet (adc_ctrl_t *const p_ctrl, adc_channel_t const reg_id, int32_t offset)
fsp_err_t	R_TSU_B_CallbackSet (adc_ctrl_t *const p_api_ctrl, void(*p_callback)(adc_callback_args_t *), void *const p_context, adc_callback_args_t *const p_callback_memory)
fsp_err_t	R_TSU_B_CalculateTemperature (adc_ctrl_t *p_ctrl, uint16_t temperature_code, float *const p_temperature)
fsp_err_t	R_USB_Open (usb_ctrl_t *const p_ctrl, usb_cfg_t const *const p_cfg)
	Applies power to the USB module specified in the argument (p_ctrl). More...
fsp_err_t	R_USB_Close (usb_ctrl_t *const p_ctrl)
	Terminates power to the USB module specified in argument (p_ctrl). USB0 module stops when USB_IP0 is specified to the member (module), USB1 module stops when USB_IP1 is specified to the member (module). More...
fsp_err_t	R_USB_Read (usb_ctrl_t *const p_ctrl, uint8_t *p_buf, uint32_t size, uint8_t destination)
	Bulk/interrupt data transfer and control data transfer. More...
fsp_err_t	R_USB_Write (usb_ctrl_t *const p_ctrl, uint8_t const *const p_buf, uint32_t size, uint8_t destination)
	Bulk/Interrupt data transfer and control data transfer. More...
fsp_err_t	R_USB_Stop (usb_ctrl_t *const p_ctrl, usb_transfer_t direction, uint8_t destination)
	Requests a data read/write transfer be terminated when a data read/write transfer is being performed. More...
fsp_err_t	R_USB_Suspend (usb_ctrl_t *const p_ctrl)
	Sends a SUSPEND signal from the USB module assigned to the member (module) of the usb_crtl_t structure. More...
fsp_err_t	R_USB_Resume (usb_ctrl_t *const p_ctrl)
	Sends a RESUME signal from the USB module assigned to the member (module) of the usb_ctrl_tstructure. More...
fsp_err_t	R_USB_VbusSet (usb_ctrl_t *const p_ctrl, uint16_t state)
	Specifies starting or stopping the VBUS supply. More...
fsp_err_t	R_USB_InfoGet (usb_ctrl_t *const p_ctrl, usb_info_t *p_info, uint8_t destination)
	Obtains completed USB-related events. More...
fsp_err_t	R_USB_PipeRead (usb_ctrl_t *const p_ctrl, uint8_t *p_buf, uint32_t size, uint8_t pipe_number)
	Requests a data read (bulk/interrupt transfer) via the pipe specified in the argument. More...
fsp_err_t	R_USB_PipeWrite (usb_ctrl_t *const p_ctrl, uint8_t *p_buf, uint32_t size, uint8_t pipe_number)
	Requests a data write (bulk/interrupt transfer). More...
fsp_err_t	R_USB_PipeStop (usb_ctrl_t *const p_ctrl, uint8_t pipe_number)
	Terminates a data read/write operation. More...
fsp_err_t	R_USB_UsedPipesGet (usb_ctrl_t *const p_ctrl, uint16_t *p_pipe, uint8_t destination)
	Gets the selected pipe number (number of the pipe that has completed initalization) via bit map information. More...
fsp_err_t	R_USB_PipeInfoGet (usb_ctrl_t *const p_ctrl, usb_pipe_t *p_info, uint8_t pipe_number)
	Gets the following pipe information regarding the pipe specified in the argument (p_ctrl) member (pipe): endpoint number, transfer type, transfer direction and maximum packet size. More...
fsp_err_t	R_USB_EventGet (usb_ctrl_t *const p_ctrl, usb_status_t *event)
	Obtains completed USB related events. (OS-less Only) More...
fsp_err_t	R_USB_Callback (usb_callback_t *p_callback)
	Register a callback function to be called upon completion of a USB related event. (RTOS only) More...
fsp_err_t	R_USB_PullUp (usb_ctrl_t *const p_ctrl, uint8_t state)
	This API enables or disables pull-up of D+/D- line. More...
fsp_err_t	R_USB_HostControlTransfer (usb_ctrl_t *const p_ctrl, usb_setup_t *p_setup, uint8_t *p_buf, uint8_t device_address)
	Performs settings and transmission processing when transmitting a setup packet. More...
fsp_err_t	R_USB_PeriControlDataGet (usb_ctrl_t *const p_ctrl, uint8_t *p_buf, uint32_t size)
	Receives data sent by control transfer. More...
fsp_err_t	R_USB_PeriControlDataSet (usb_ctrl_t *const p_ctrl, uint8_t *p_buf, uint32_t size)
	Performs transfer processing for control transfer. More...
fsp_err_t	R_USB_PeriControlStatusSet (usb_ctrl_t *const p_ctrl, usb_setup_status_t status)
	Set the response to the setup packet. More...
fsp_err_t	R_USB_RemoteWakeup (usb_ctrl_t *const p_ctrl)
	Sends a remote wake-up signal to the connected Host. More...
fsp_err_t	R_USB_DriverActivate (usb_ctrl_t *const p_api_ctrl)
	Activate USB Driver for USB Peripheral BareMetal. More...
fsp_err_t	R_USB_CallbackMemorySet (usb_ctrl_t *const p_api_ctrl, usb_callback_args_t *p_callback_memory)
	Set callback memory to USB Driver for USB Peripheral BareMetal. More...
fsp_err_t	R_USB_ModuleNumberGet (usb_ctrl_t *const p_ctrl, uint8_t *module_number)
	This API gets the module number. More...
fsp_err_t	R_USB_ClassTypeGet (usb_ctrl_t *const p_ctrl, usb_class_t *class_type)
	This API gets the class type. More...
fsp_err_t	R_USB_DeviceAddressGet (usb_ctrl_t *const p_ctrl, uint8_t *device_address)
	This API gets the device address. More...
fsp_err_t	R_USB_PipeNumberGet (usb_ctrl_t *const p_ctrl, uint8_t *pipe_number)
	This API gets the pipe number. More...
fsp_err_t	R_USB_DeviceStateGet (usb_ctrl_t *const p_ctrl, uint16_t *state)
	This API gets the state of the device. More...
fsp_err_t	R_USB_DataSizeGet (usb_ctrl_t *const p_ctrl, uint32_t *data_size)
	This API gets the data size. More...
fsp_err_t	R_USB_SetupGet (usb_ctrl_t *const p_ctrl, usb_setup_t *setup)
	This API gets the setup type. More...
fsp_err_t	R_USB_OtgCallbackSet (usb_ctrl_t *const p_api_ctrl, usb_otg_callback_t *p_callback)
	Set callback function to be called when the OTG role swap was completed on Azure RTOS. More...
fsp_err_t	R_USB_OtgSRP (usb_ctrl_t *const p_api_ctrl)
	Start the SRP processing for OTG on Azure RTOS. More...
fsp_err_t	R_USB_HHID_TypeGet (usb_ctrl_t *const p_ctrl, uint8_t *p_type, uint8_t device_address)
	Get HID protocol.(USB Mouse/USB Keyboard/Other Type.) More...
fsp_err_t	R_USB_HHID_MaxPacketSizeGet (usb_ctrl_t *const p_ctrl, uint16_t *p_size, uint8_t direction, uint8_t device_address)
	Obtains max packet size for the connected HID device. The max packet size is set to the area. Set the direction (USB_HID_IN/USB_HID_OUT). More...
fsp_err_t	R_USB_HMSC_StorageCommand (usb_ctrl_t *const p_ctrl, uint8_t *buf, uint8_t command, uint8_t destination)
	Processing for MassStorage(ATAPI) command. More...
fsp_err_t	R_USB_HMSC_DriveNumberGet (usb_ctrl_t *const p_ctrl, uint8_t *p_drive, uint8_t destination)
	Get number of Storage drive. More...
fsp_err_t	R_USB_HMSC_StorageReadSector (uint16_t drive_number, uint8_t *const buff, uint32_t sector_number, uint16_t sector_count)
	Read sector information. More...
fsp_err_t	R_USB_HMSC_StorageWriteSector (uint16_t drive_number, uint8_t const *const buff, uint32_t sector_number, uint16_t sector_count)
	Write sector information. More...
fsp_err_t	R_USB_HMSC_SemaphoreGet (void)
	Get a semaphore. (RTOS only) More...
fsp_err_t	R_USB_HMSC_SemaphoreRelease (void)
	Release a semaphore. (RTOS only) More...
fsp_err_t	R_WDT_Refresh (wdt_ctrl_t *const p_ctrl)
fsp_err_t	R_WDT_Open (wdt_ctrl_t *const p_ctrl, wdt_cfg_t const *const p_cfg)
fsp_err_t	R_WDT_StatusClear (wdt_ctrl_t *const p_ctrl, const wdt_status_t status)
fsp_err_t	R_WDT_StatusGet (wdt_ctrl_t *const p_ctrl, wdt_status_t *const p_status)
fsp_err_t	R_WDT_CounterGet (wdt_ctrl_t *const p_ctrl, uint32_t *const p_count)
fsp_err_t	R_WDT_TimeoutGet (wdt_ctrl_t *const p_ctrl, wdt_timeout_values_t *const p_timeout)
fsp_err_t	R_WDT_CallbackSet (wdt_ctrl_t *const p_ctrl, void(*p_callback)(wdt_callback_args_t *), void *const p_context, wdt_callback_args_t *const p_callback_memory)
fsp_err_t	R_XSPI_HYPER_Open (hyperbus_ctrl_t *p_ctrl, hyperbus_cfg_t const *const p_cfg)
fsp_err_t	R_XSPI_HYPER_Close (hyperbus_ctrl_t *p_ctrl)
fsp_err_t	R_XSPI_HYPER_BurstTypeSet (hyperbus_ctrl_t *p_ctrl, hyperbus_burst_type_t burst_type)
fsp_err_t	R_XSPI_HYPER_AccessSpaceSet (hyperbus_ctrl_t *p_ctrl, hyperbus_space_select_t access_space)
fsp_err_t	R_XSPI_HYPER_DirectTransfer (hyperbus_ctrl_t *const p_ctrl, hyperbus_direct_transfer_t *const p_transfer)
fsp_err_t	R_XSPI_HYPER_Write (hyperbus_ctrl_t *p_ctrl, uint8_t const *const p_src, uint8_t *const p_dest, uint32_t byte_count)
fsp_err_t	R_XSPI_HYPER_Erase (hyperbus_ctrl_t *p_ctrl, uint8_t *const p_device_address, uint32_t byte_count)
fsp_err_t	R_XSPI_HYPER_StatusGet (hyperbus_ctrl_t *p_ctrl, hyperbus_status_t *const p_status)
fsp_err_t	R_XSPI_HYPER_AutoCalibrate (hyperbus_ctrl_t *p_ctrl)
fsp_err_t	R_XSPI_OSPI_Open (spi_flash_ctrl_t *p_ctrl, spi_flash_cfg_t const *const p_cfg)
fsp_err_t	R_XSPI_OSPI_Close (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_XSPI_OSPI_DirectWrite (spi_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint32_t const bytes, bool const read_after_write)
fsp_err_t	R_XSPI_OSPI_DirectRead (spi_flash_ctrl_t *p_ctrl, uint8_t *const p_dest, uint32_t const bytes)
fsp_err_t	R_XSPI_OSPI_SpiProtocolSet (spi_flash_ctrl_t *p_ctrl, spi_flash_protocol_t spi_protocol)
fsp_err_t	R_XSPI_OSPI_XipEnter (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_XSPI_OSPI_XipExit (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_XSPI_OSPI_Write (spi_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint8_t *const p_dest, uint32_t byte_count)
fsp_err_t	R_XSPI_OSPI_Erase (spi_flash_ctrl_t *p_ctrl, uint8_t *const p_device_address, uint32_t byte_count)
fsp_err_t	R_XSPI_OSPI_StatusGet (spi_flash_ctrl_t *p_ctrl, spi_flash_status_t *const p_status)
fsp_err_t	R_XSPI_OSPI_BankSet (spi_flash_ctrl_t *p_ctrl, uint32_t bank)
fsp_err_t	R_XSPI_OSPI_DirectTransfer (spi_flash_ctrl_t *p_ctrl, spi_flash_direct_transfer_t *const p_transfer, spi_flash_direct_transfer_dir_t direction)
fsp_err_t	R_XSPI_OSPI_AutoCalibrate (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_XSPI_QSPI_Open (spi_flash_ctrl_t *p_ctrl, spi_flash_cfg_t const *const p_cfg)
fsp_err_t	R_XSPI_QSPI_Close (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_XSPI_QSPI_DirectWrite (spi_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint32_t const bytes, bool const read_after_write)
fsp_err_t	R_XSPI_QSPI_DirectRead (spi_flash_ctrl_t *p_ctrl, uint8_t *const p_dest, uint32_t const bytes)
fsp_err_t	R_XSPI_QSPI_SpiProtocolSet (spi_flash_ctrl_t *p_ctrl, spi_flash_protocol_t spi_protocol)
fsp_err_t	R_XSPI_QSPI_XipEnter (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_XSPI_QSPI_XipExit (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_XSPI_QSPI_Write (spi_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint8_t *const p_dest, uint32_t byte_count)
fsp_err_t	R_XSPI_QSPI_Erase (spi_flash_ctrl_t *p_ctrl, uint8_t *const p_device_address, uint32_t byte_count)
fsp_err_t	R_XSPI_QSPI_StatusGet (spi_flash_ctrl_t *p_ctrl, spi_flash_status_t *const p_status)
fsp_err_t	R_XSPI_QSPI_BankSet (spi_flash_ctrl_t *p_ctrl, uint32_t bank)
fsp_err_t	R_XSPI_QSPI_DirectTransfer (spi_flash_ctrl_t *p_ctrl, spi_flash_direct_transfer_t *const p_transfer, spi_flash_direct_transfer_dir_t direction)
fsp_err_t	R_XSPI_QSPI_AutoCalibrate (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	RM_BLOCK_MEDIA_SDMMC_Open (rm_block_media_ctrl_t *const p_ctrl, rm_block_media_cfg_t const *const p_cfg)
fsp_err_t	RM_BLOCK_MEDIA_SDMMC_MediaInit (rm_block_media_ctrl_t *const p_ctrl)
fsp_err_t	RM_BLOCK_MEDIA_SDMMC_Read (rm_block_media_ctrl_t *const p_ctrl, uint8_t *const p_dest_address, uint32_t const block_address, uint32_t const num_blocks)
fsp_err_t	RM_BLOCK_MEDIA_SDMMC_Write (rm_block_media_ctrl_t *const p_ctrl, uint8_t const *const p_src_address, uint32_t const block_address, uint32_t const num_blocks)
fsp_err_t	RM_BLOCK_MEDIA_SDMMC_Erase (rm_block_media_ctrl_t *const p_ctrl, uint32_t const block_address, uint32_t const num_blocks)
fsp_err_t	RM_BLOCK_MEDIA_SDMMC_CallbackSet (rm_block_media_ctrl_t *const p_ctrl, void(*p_callback)(rm_block_media_callback_args_t *), void *const p_context, rm_block_media_callback_args_t *const p_callback_memory)
fsp_err_t	RM_BLOCK_MEDIA_SDMMC_StatusGet (rm_block_media_ctrl_t *const p_api_ctrl, rm_block_media_status_t *const p_status)
fsp_err_t	RM_BLOCK_MEDIA_SDMMC_InfoGet (rm_block_media_ctrl_t *const p_ctrl, rm_block_media_info_t *const p_info)
fsp_err_t	RM_BLOCK_MEDIA_SDMMC_Close (rm_block_media_ctrl_t *const p_ctrl)
fsp_err_t	RM_BLOCK_MEDIA_USB_Open (rm_block_media_ctrl_t *const p_ctrl, rm_block_media_cfg_t const *const p_cfg)
fsp_err_t	RM_BLOCK_MEDIA_USB_MediaInit (rm_block_media_ctrl_t *const p_ctrl)
fsp_err_t	RM_BLOCK_MEDIA_USB_Read (rm_block_media_ctrl_t *const p_ctrl, uint8_t *const p_dest_address, uint32_t const block_address, uint32_t const num_blocks)
fsp_err_t	RM_BLOCK_MEDIA_USB_Write (rm_block_media_ctrl_t *const p_ctrl, uint8_t const *const p_src_address, uint32_t const block_address, uint32_t const num_blocks)
fsp_err_t	RM_BLOCK_MEDIA_USB_Erase (rm_block_media_ctrl_t *const p_ctrl, uint32_t const block_address, uint32_t const num_blocks)
fsp_err_t	RM_BLOCK_MEDIA_USB_CallbackSet (rm_block_media_ctrl_t *const p_ctrl, void(*p_callback)(rm_block_media_callback_args_t *), void *const p_context, rm_block_media_callback_args_t *const p_callback_memory)
fsp_err_t	RM_BLOCK_MEDIA_USB_StatusGet (rm_block_media_ctrl_t *const p_ctrl, rm_block_media_status_t *const p_status)
fsp_err_t	RM_BLOCK_MEDIA_USB_InfoGet (rm_block_media_ctrl_t *const p_ctrl, rm_block_media_info_t *const p_info)
fsp_err_t	RM_BLOCK_MEDIA_USB_Close (rm_block_media_ctrl_t *const p_ctrl)
fsp_err_t	RM_ETHERCAT_SSC_PORT_Open (ethercat_ssc_port_ctrl_t *const p_ctrl, ethercat_ssc_port_cfg_t const *const p_cfg)
	EtherCAT Slave Controller is initialized with this function. This function includes PHY initialization and ESC EEPROM loading. Afterwards, EtherCAT communication begins. Also EtherCAT interrupts are permitted if the interrupts are used. In order to receive the EtherCAT, EtherCAT Sync0, EtherCAT Sync1 interrupt event, it's necessary to register a callback function. Implements ethercat_ssc_port_api_t::open. More...
fsp_err_t	RM_ETHERCAT_SSC_PORT_Close (ethercat_ssc_port_ctrl_t *const p_ctrl)
fsp_err_t	RM_FREERTOS_PLUS_FAT_Open (rm_freertos_plus_fat_ctrl_t *const p_ctrl, rm_freertos_plus_fat_cfg_t const *const p_cfg)
fsp_err_t	RM_FREERTOS_PLUS_FAT_MediaInit (rm_freertos_plus_fat_ctrl_t *const p_ctrl, rm_freertos_plus_fat_device_t *const p_device)
fsp_err_t	RM_FREERTOS_PLUS_FAT_DiskInit (rm_freertos_plus_fat_ctrl_t *const p_ctrl, rm_freertos_plus_fat_disk_cfg_t const *const p_disk_cfg, FF_Disk_t *const p_disk)
fsp_err_t	RM_FREERTOS_PLUS_FAT_DiskDeinit (rm_freertos_plus_fat_ctrl_t *const p_ctrl, FF_Disk_t *const p_disk)
fsp_err_t	RM_FREERTOS_PLUS_FAT_InfoGet (rm_freertos_plus_fat_ctrl_t *const p_ctrl, FF_Disk_t *const p_disk, rm_freertos_plus_fat_info_t *const p_info)
fsp_err_t	RM_FREERTOS_PLUS_FAT_Close (rm_freertos_plus_fat_ctrl_t *const p_ctrl)
void	Default_Handler (void)
BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void	system_init (void)
BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void	bsp_register_initialization (void)
void	SystemInit (void)
void	R_BSP_WarmStart (bsp_warm_start_event_t event)
BSP_ATTRIBUTE_STACKLESS void	R_BSP_WarmStart_StackLess (void)
void	R_BSP_CacheEnableInst (void)
void	R_BSP_CacheEnableData (void)
void	R_BSP_CacheEnableMemoryProtect (void)
void	R_BSP_CacheDisableInst (void)
void	R_BSP_CacheDisableData (void)
void	R_BSP_CacheDisableMemoryProtect (void)
void	R_BSP_CacheCleanAll (void)
void	R_BSP_CacheInvalidateAll (void)
void	R_BSP_CacheCleanInvalidateAll (void)
void	R_BSP_CacheCleanRange (uintptr_t base_address, uintptr_t length)
void	R_BSP_CacheInvalidateRange (uintptr_t base_address, uintptr_t length)
void	R_BSP_CacheCleanInvalidateRange (uintptr_t base_address, uintptr_t length)
void	R_BSP_CacheL3PowerCtrl (void)
void	SystemCoreClockUpdate (void)
void	bsp_prv_clock_set (uint32_t sckcr, uint32_t sckcr2, uint32_t sckcr3, uint32_t sckcr4)
void	bsp_clock_init (void)
__WEAK void	R_BSP_FspAssert (void)
__STATIC_INLINE IRQn_Type	R_FSP_CurrentIrqGet (void)
__STATIC_INLINE uint32_t	R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
void	R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units)
void	R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect)
void	R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect)
__STATIC_INLINE void	R_BSP_PinSet (bsp_io_region_t region, bsp_io_port_pin_t pin)
__STATIC_INLINE void	R_BSP_PinClear (bsp_io_region_t region, bsp_io_port_pin_t pin)
__STATIC_INLINE void	R_BSP_PinToggle (bsp_io_region_t region, bsp_io_port_pin_t pin)
__STATIC_INLINE uint32_t	R_BSP_FastPinRead (bsp_io_region_t region, bsp_io_port_pin_t pin)
__STATIC_INLINE void	R_BSP_PortWrite (bsp_io_region_t region, bsp_io_port_t port, uint8_t set_value)
__STATIC_INLINE uint32_t	R_BSP_PortRead (bsp_io_region_t region, bsp_io_port_t port)
__STATIC_INLINE void	R_BSP_PinAccessEnable (void)
__STATIC_INLINE void	R_BSP_PinAccessDisable (void)
__STATIC_INLINE bsp_io_region_t	R_BSP_IoRegionGet (bsp_io_port_pin_t pin)
__STATIC_INLINE void	R_FSP_IsrContextSet (IRQn_Type const irq, void *p_context)
	Sets the ISR context associated with the requested IRQ. More...
__STATIC_INLINE void	R_BSP_IrqClearPending (IRQn_Type irq)
__STATIC_INLINE uint32_t	R_BSP_IrqPendingGet (IRQn_Type irq)
__STATIC_INLINE void	R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void *p_context)
__STATIC_INLINE void	R_BSP_IrqEnableNoClear (IRQn_Type const irq)
__STATIC_INLINE void	R_BSP_IrqEnable (IRQn_Type const irq)
__STATIC_INLINE void	R_BSP_IrqDisable (IRQn_Type const irq)
__STATIC_INLINE void	R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void *p_context)
__STATIC_INLINE void *	R_FSP_IsrContextGet (IRQn_Type const irq)
	Finds the ISR context associated with the requested IRQ. More...
__STATIC_INLINE void	R_BSP_IrqDetectTypeSet (IRQn_Type const irq, uint32_t detect_type)
__STATIC_INLINE void	R_BSP_IrqGroupSet (IRQn_Type const irq, uint32_t interrupt_group)
__STATIC_INLINE void	R_BSP_IrqMaskLevelSet (uint32_t mask_level)
__STATIC_INLINE uint32_t	R_BSP_IrqMaskLevelGet (void)
void	bsp_irq_cfg (void)
void	R_BSP_SystemReset (void)
void	R_BSP_CpuReset (bsp_reset_t cpu)
void	R_BSP_CpuResetAutoRelease (bsp_reset_t cpu)
void	R_BSP_CpuResetRelease (bsp_reset_t cpu)
void	R_BSP_ModuleResetEnable (bsp_module_reset_t module_to_enable)
void	R_BSP_ModuleResetDisable (bsp_module_reset_t module_to_disable)
BSP_TFU_INLINE float	__sinf (float angle)
BSP_TFU_INLINE float	__cosf (float angle)
BSP_TFU_INLINE void	__sincosf (float angle, float *sin, float *cos)
BSP_TFU_INLINE float	__atan2f (float y_cord, float x_cord)
BSP_TFU_INLINE float	__hypotf (float x_cord, float y_cord)
BSP_TFU_INLINE void	__atan2hypotf (float y_cord, float x_cord, float *atan2, float *hypot)
BSP_TFU_INLINE uint32_t	__sinfx (uint32_t angle)
BSP_TFU_INLINE uint32_t	__cosfx (uint32_t angle)
BSP_TFU_INLINE void	__sincosfx (uint32_t angle, uint32_t *sin, uint32_t *cos)
BSP_TFU_INLINE uint32_t	__atan2fx (uint32_t y_cord, uint32_t x_cord)
BSP_TFU_INLINE int32_t	__hypotfx (uint32_t x_cord, uint32_t y_cord)
BSP_TFU_INLINE void	__atan2hypotfx (uint32_t y_cord, uint32_t x_cord, uint32_t *atan2, int32_t *hypot)
BSP_ATTRIBUTE_STACKLESS void	r_bsp_software_delay_loop (__attribute__((unused)) uint32_t loop_cnt)
fsp_err_t	R_BSP_GroupIrqWrite (bsp_grp_irq_t irq, void(*p_callback)(bsp_grp_irq_t irq))
void	R_BSP_GICD_SetCtlr (bsp_gicd_ctlr_bit_t bit)
uint32_t	R_BSP_GICD_GetCtlr (void)
void	R_BSP_GICD_Enable (bsp_gicd_ctlr_bit_t bit)
void	R_BSP_GICD_Disable (bsp_gicd_ctlr_bit_t bit)
void	R_BSP_GICD_AffinityRouteEnable (bsp_gicd_ctlr_bit_t bit)
void	R_BSP_GICD_SpiEnable (IRQn_Type irq)
void	R_BSP_GICD_SpiDisable (IRQn_Type irq)
void	R_BSP_GICD_SetSpiPriority (IRQn_Type irq, uint32_t priority)
uint32_t	R_BSP_GICD_GetSpiPriority (IRQn_Type irq)
void	R_BSP_GICD_SetSpiRoute (IRQn_Type id, uint64_t route, bsp_gicd_irouter_route_t mode)
uint64_t	R_BSP_GICD_GetSpiRoute (IRQn_Type id)
void	R_BSP_GICD_SetSpiSense (IRQn_Type irq, bsp_gicd_icfgr_sense_t sense)
uint32_t	R_BSP_GICD_GetSpiSense (IRQn_Type irq)
void	R_BSP_GICD_SetSpiPending (IRQn_Type irq)
uint32_t	R_BSP_GICD_GetSpiPending (IRQn_Type irq)
void	R_BSP_GICD_SetSpiClearPending (IRQn_Type irq)
uint32_t	R_BSP_GICD_GetSpiClearPending (IRQn_Type irq)
void	R_BSP_GICD_SetSpiSecurity (IRQn_Type irq, bsp_gic_igroupr_secure_t group)
void	R_BSP_GICD_SetSpiSecurityLine (uint32_t line, bsp_gic_igroupr_secure_t group)
void	R_BSP_GICD_SetSpiSecurityAll (bsp_gic_igroupr_secure_t group)
void	R_BSP_GICD_SetSpiClass (IRQn_Type id, bsp_gicd_iclar_class_t class_group)
void	R_BSP_GICR_Enable (void)
void	R_BSP_GICR_SgiPpiEnable (IRQn_Type irq)
void	R_BSP_GICR_SgiPpiDisable (IRQn_Type irq)
void	R_BSP_GICR_SetSgiPpiPriority (IRQn_Type irq, uint32_t priority)
uint32_t	R_BSP_GICR_GetSgiPpiPriority (IRQn_Type irq)
void	R_BSP_GICR_SetSgiPpiSense (IRQn_Type irq, bsp_gicd_icfgr_sense_t sense)
uint32_t	R_BSP_GICR_GetSgiPpiSense (IRQn_Type irq)
void	R_BSP_GICR_SetSgiPpiPending (IRQn_Type irq)
uint32_t	R_BSP_GICR_GetSgiPpiPending (IRQn_Type irq)
void	R_BSP_GICR_SetSgiPpiClearPending (IRQn_Type irq)
uint32_t	R_BSP_GICR_GetSgiPpiClearPending (IRQn_Type irq)
void	R_BSP_GICR_SetSgiPpiSecurity (IRQn_Type irq, bsp_gic_igroupr_secure_t group)
void	R_BSP_GICR_SetSgiPpiSecurityLine (bsp_gic_igroupr_secure_t group)
void	R_BSP_GICR_SetClass (bsp_gicd_iclar_class_t class_group)
uint32_t	R_BSP_GICR_GetRoute (void)
void	R_BSP_GICC_SetMaskLevel (uint64_t mask_level)
uint64_t	R_BSP_GICC_GetMaskLevel (void)
void	R_BSP_GICC_SetEoiGrp0 (IRQn_Type irq)
void	R_BSP_GICC_SetEoiGrp1 (IRQn_Type irq)
uint32_t	R_BSP_GICC_Get_IntIdGrp0 (void)
uint32_t	R_BSP_GICC_Get_IntIdGrp1 (void)
fsp_err_t	R_BSP_MmuVatoPa (uint64_t vaddress, uint64_t *p_paddress)
fsp_err_t	R_BSP_MmuPatoVa (uint64_t paddress, uint64_t *p_vaddress, bsp_mmu_conversion_flag_t cache_flag)
fsp_err_t	R_BSP_MemoryMap (r_mmu_pgtbl_cfg_t *p_memory_map_cfg)
fsp_err_t	R_BSP_MemoryUnMap (void)
void	bsp_irq_core_cfg (void)
void	bsp_common_interrupt_handler (uint32_t id)
fsp_err_t	R_BSP_MpuRegionDynamicConfig (bsp_mpu_dynamic_cfg_t *p_dynamic_region_cfg)
fsp_err_t	R_BSP_MpuRegionRestoreConfig (void)
fsp_err_t	R_DOC_Open (doc_ctrl_t *const p_ctrl, doc_cfg_t const *const p_cfg)
fsp_err_t	R_DOC_Close (doc_ctrl_t *const p_ctrl)
fsp_err_t	R_DOC_Read (doc_ctrl_t *const p_ctrl, uint32_t *p_result)
fsp_err_t	R_DOC_Write (doc_ctrl_t *const p_ctrl, uint32_t data)
fsp_err_t	R_DOC_CallbackSet (doc_ctrl_t *const p_ctrl, void(*p_callback)(doc_callback_args_t *), void *const p_context, doc_callback_args_t *const p_callback_memory)
fsp_err_t	R_ICU_ERROR_Open (error_ctrl_t *const p_ctrl, error_cfg_t const *const p_cfg)
fsp_err_t	R_ICU_ERROR_Close (error_ctrl_t *const p_ctrl)
fsp_err_t	R_ICU_ERROR_StatusGet (error_ctrl_t *const p_ctrl, uint32_t source, uint32_t *const p_status)
fsp_err_t	R_ICU_ERROR_StatusClear (error_ctrl_t *const p_ctrl, uint32_t source, uint32_t const event)
fsp_err_t	R_ICU_ERROR_CallbackSet (error_ctrl_t *const p_ctrl, void(*p_callback)(error_callback_args_t *), void *const p_context, error_callback_args_t *const p_callback_memory)
fsp_err_t	R_RSIP_Open (rsip_ctrl_t *const p_ctrl, rsip_cfg_t const *const p_cfg)
fsp_err_t	R_RSIP_Close (rsip_ctrl_t *const p_ctrl)
fsp_err_t	R_RSIP_RandomNumberGenerate (rsip_ctrl_t *const p_ctrl, uint8_t *const p_random)
fsp_err_t	R_RSIP_KeyGenerate (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t *const p_wrapped_key)
fsp_err_t	R_RSIP_KeyPairGenerate (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t *const p_wrapped_public_key, rsip_wrapped_key_t *const p_wrapped_private_key)
fsp_err_t	R_RSIP_EncryptedKeyWrap (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_key_update_key, void const *const p_initial_vector, void const *const p_encrypted_key, rsip_wrapped_key_t *const p_wrapped_key)
fsp_err_t	R_RSIP_RFC3394_KeyWrap (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_kek, rsip_wrapped_key_t const *const p_wrapped_target_key, uint8_t *const p_rfc3394_wrapped_target_key)
fsp_err_t	R_RSIP_RFC3394_KeyUnwrap (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_kek, uint8_t const *const p_rfc3394_wrapped_target_key, rsip_wrapped_key_t *const p_wrapped_target_key)
fsp_err_t	R_RSIP_PublicKeyExport (rsip_wrapped_key_t const *const p_wrapped_public_key, uint8_t *const p_raw_public_key)
fsp_err_t	R_RSIP_AES_Cipher_Init (rsip_ctrl_t *const p_ctrl, rsip_aes_cipher_mode_t const mode, rsip_wrapped_key_t const *const p_wrapped_key, uint8_t const *const p_initial_vector)
fsp_err_t	R_RSIP_AES_Cipher_Update (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_input, uint8_t *const p_output, uint32_t const length)
fsp_err_t	R_RSIP_AES_Cipher_Finish (rsip_ctrl_t *const p_ctrl)
fsp_err_t	R_RSIP_AES_AEAD_Init (rsip_ctrl_t *const p_ctrl, rsip_aes_aead_mode_t mode, rsip_wrapped_key_t const *const p_wrapped_key, uint8_t const *const p_nonce, uint32_t const nonce_length)
fsp_err_t	R_RSIP_AES_AEAD_LengthsSet (rsip_ctrl_t *const p_ctrl, uint32_t const total_aad_length, uint32_t const total_text_length, uint32_t const tag_length)
fsp_err_t	R_RSIP_AES_AEAD_AADUpdate (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_aad, uint32_t const aad_length)
fsp_err_t	R_RSIP_AES_AEAD_Update (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_input, uint32_t const input_length, uint8_t *const p_output, uint32_t *const p_output_length)
fsp_err_t	R_RSIP_AES_AEAD_Finish (rsip_ctrl_t *const p_ctrl, uint8_t *const p_output, uint32_t *const p_output_length, uint8_t *const p_tag)
fsp_err_t	R_RSIP_AES_AEAD_Verify (rsip_ctrl_t *const p_ctrl, uint8_t *const p_output, uint32_t *const p_output_length, uint8_t const *const p_tag, uint32_t const tag_length)
fsp_err_t	R_RSIP_AES_MAC_Init (rsip_ctrl_t *const p_ctrl, rsip_aes_mac_mode_t const mode, rsip_wrapped_key_t const *const p_wrapped_key)
fsp_err_t	R_RSIP_AES_MAC_Update (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_message, uint32_t const message_length)
fsp_err_t	R_RSIP_AES_MAC_SignFinish (rsip_ctrl_t *const p_ctrl, uint8_t *const p_mac)
fsp_err_t	R_RSIP_AES_MAC_VerifyFinish (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_mac, uint32_t const mac_length)
fsp_err_t	R_RSIP_ChaCha20_Init (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_key, uint8_t const *const p_nonce, uint32_t const counter)
fsp_err_t	R_RSIP_ChaCha20_Update (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_input, uint32_t const input_length, uint8_t *const p_output, uint32_t *const p_output_length)
fsp_err_t	R_RSIP_ChaCha20_Finish (rsip_ctrl_t *const p_ctrl, uint8_t *const p_output, uint32_t *const p_output_length)
fsp_err_t	R_RSIP_ChaCha20_Poly1305_Init (rsip_ctrl_t *const p_ctrl, rsip_chacha_poly_mode_t const mode, rsip_wrapped_key_t const *const p_wrapped_key, uint8_t const *const p_nonce, uint32_t const nonce_length)
fsp_err_t	R_RSIP_ChaCha20_Poly1305_AADUpdate (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_aad, uint32_t const aad_length)
fsp_err_t	R_RSIP_ChaCha20_Poly1305_Update (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_input, uint32_t const input_length, uint8_t *const p_output, uint32_t *const p_output_length)
fsp_err_t	R_RSIP_ChaCha20_Poly1305_Finish (rsip_ctrl_t *const p_ctrl, uint8_t *const p_output, uint32_t *const p_output_length, uint8_t *const p_tag)
fsp_err_t	R_RSIP_ChaCha20_Poly1305_Verify (rsip_ctrl_t *const p_ctrl, uint8_t *const p_output, uint32_t *const p_output_length, uint8_t const *const p_tag, uint32_t const tag_length)
fsp_err_t	R_RSIP_ECDSA_Sign (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, uint8_t const *const p_hash, uint8_t *const p_signature)
fsp_err_t	R_RSIP_ECDSA_Verify (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, uint8_t const *const p_hash, uint8_t const *const p_signature)
fsp_err_t	R_RSIP_PKI_ECDSA_CertVerify (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, uint8_t const *const p_hash, uint8_t const *const p_signature)
fsp_err_t	R_RSIP_PureEdDSA_Sign (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, rsip_wrapped_key_t const *const p_wrapped_public_key, uint8_t const *const p_message, uint64_t const message_length, uint8_t *const p_signature)
fsp_err_t	R_RSIP_PureEdDSA_Verify (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, uint8_t const *const p_message, uint64_t const message_length, uint8_t const *const p_signature)
fsp_err_t	R_RSIP_ECDH_KeyAgree (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, rsip_wrapped_key_t const *const p_wrapped_public_key, rsip_wrapped_secret_t *const p_wrapped_secret)
fsp_err_t	R_RSIP_ECDH_PlainKeyAgree (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, uint8_t const *const p_plain_public_key, rsip_wrapped_secret_t *const p_wrapped_secret)
fsp_err_t	R_RSIP_KDF_SHA_Init (rsip_ctrl_t *const p_ctrl, rsip_hash_type_t const hash_type)
fsp_err_t	R_RSIP_KDF_SHA_ECDHSecretUpdate (rsip_ctrl_t *const p_ctrl, rsip_wrapped_secret_t const *const p_wrapped_secret)
fsp_err_t	R_RSIP_KDF_SHA_Update (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_message, uint32_t const message_length)
fsp_err_t	R_RSIP_KDF_SHA_Finish (rsip_ctrl_t *const p_ctrl, rsip_wrapped_dkm_t *const p_wrapped_dkm)
fsp_err_t	R_RSIP_KDF_SHA_Suspend (rsip_ctrl_t *const p_ctrl, rsip_kdf_sha_handle_t *const p_handle)
fsp_err_t	R_RSIP_KDF_SHA_Resume (rsip_ctrl_t *const p_ctrl, rsip_kdf_sha_handle_t const *const p_handle)
fsp_err_t	R_RSIP_KDF_HMAC_DKMKeyImport (rsip_ctrl_t *const p_ctrl, rsip_wrapped_dkm_t const *const p_wrapped_dkm, uint32_t const key_length, rsip_wrapped_key_t *const p_wrapped_key)
fsp_err_t	R_RSIP_KDF_HMAC_ECDHSecretKeyImport (rsip_ctrl_t *const p_ctrl, rsip_wrapped_secret_t const *const p_wrapped_secret, rsip_wrapped_key_t *const p_wrapped_key)
fsp_err_t	R_RSIP_KDF_HMAC_Init (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_key)
fsp_err_t	R_RSIP_KDF_HMAC_DKMUpdate (rsip_ctrl_t *const p_ctrl, rsip_wrapped_dkm_t const *const p_wrapped_dkm)
fsp_err_t	R_RSIP_KDF_HMAC_ECDHSecretUpdate (rsip_ctrl_t *const p_ctrl, rsip_wrapped_secret_t const *const p_wrapped_secret)
fsp_err_t	R_RSIP_KDF_HMAC_Update (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_message, uint32_t const message_length)
fsp_err_t	R_RSIP_KDF_HMAC_SignFinish (rsip_ctrl_t *const p_ctrl, rsip_wrapped_dkm_t *const p_wrapped_dkm)
fsp_err_t	R_RSIP_KDF_HMAC_Suspend (rsip_ctrl_t *const p_ctrl, rsip_kdf_hmac_handle_t *const p_handle)
fsp_err_t	R_RSIP_KDF_HMAC_Resume (rsip_ctrl_t *const p_ctrl, rsip_kdf_hmac_handle_t const *const p_handle)
fsp_err_t	R_RSIP_KDF_DKMConcatenate (rsip_wrapped_dkm_t *const p_wrapped_dkm1, rsip_wrapped_dkm_t const *const p_wrapped_dkm2, uint32_t const wrapped_dkm1_buffer_length)
fsp_err_t	R_RSIP_KDF_DerivedKeyImport (rsip_ctrl_t *const p_ctrl, rsip_wrapped_dkm_t const *const p_wrapped_dkm, uint32_t const position, rsip_wrapped_key_t *const p_wrapped_key)
fsp_err_t	R_RSIP_KDF_DerivedIVWrap (rsip_ctrl_t *const p_ctrl, rsip_wrapped_dkm_t const *const p_wrapped_dkm, rsip_initial_vector_type_t const initial_vector_type, uint32_t const position, uint8_t const *const p_tls_sequence_num, uint8_t *const p_wrapped_initial_vector)
fsp_err_t	R_RSIP_OTF_Init (rsip_ctrl_t *const p_ctrl, rsip_otf_channel_t const channel, rsip_wrapped_key_t *const p_wrapped_key, uint8_t const *const p_seed)
fsp_err_t	R_RSIP_PKI_VerifiedCertInfoExport (rsip_ctrl_t *const p_ctrl, rsip_verified_cert_info_t *const p_verified_cert_info)
fsp_err_t	R_RSIP_PKI_VerifiedCertInfoImport (rsip_ctrl_t *const p_ctrl, rsip_verified_cert_info_t const *const p_verified_cert_info)
fsp_err_t	R_RSIP_PKI_CertKeyImport (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_cert, uint32_t const cert_length, uint8_t const *const p_key_param1, uint32_t const key_param1_length, uint8_t const *const p_key_param2, uint32_t const key_param2_length, rsip_hash_type_t const hash_function, rsip_wrapped_key_t *const p_wrapped_public_key)
fsp_err_t	R_RSIP_RSA_Encrypt (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, uint8_t const *const p_plain, uint8_t *const p_cipher)
fsp_err_t	R_RSIP_RSA_Decrypt (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, uint8_t const *const p_cipher, uint8_t *const p_plain)
fsp_err_t	R_RSIP_RSAES_PKCS1_V1_5_Encrypt (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, uint8_t const *const p_plain, uint32_t const plain_length, uint8_t *const p_cipher)
fsp_err_t	R_RSIP_RSAES_PKCS1_V1_5_Decrypt (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, uint8_t const *const p_cipher, uint8_t *const p_plain, uint32_t *const p_plain_length, uint32_t const plain_buffer_length)
fsp_err_t	R_RSIP_RSAES_OAEP_Encrypt (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, rsip_hash_type_t const hash_function, rsip_mgf_type_t const mask_generation_function, uint8_t const *const p_label, uint32_t const label_length, uint8_t const *const p_plain, uint32_t const plain_length, uint8_t *const p_cipher)
fsp_err_t	R_RSIP_RSAES_OAEP_Decrypt (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, rsip_hash_type_t const hash_function, rsip_mgf_type_t const mask_generation_function, uint8_t const *const p_label, uint32_t const label_length, uint8_t const *const p_cipher, uint8_t *const p_plain, uint32_t *const p_plain_length, uint32_t const plain_buffer_length)
fsp_err_t	R_RSIP_RSASSA_PKCS1_V1_5_Sign (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, rsip_hash_type_t const hash_function, uint8_t const *const p_hash, uint8_t *const p_signature)
fsp_err_t	R_RSIP_RSASSA_PKCS1_V1_5_Verify (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, rsip_hash_type_t const hash_function, uint8_t const *const p_hash, uint8_t const *const p_signature)
fsp_err_t	R_RSIP_RSASSA_PSS_Sign (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, rsip_hash_type_t const hash_function, rsip_mgf_type_t const mask_generation_function, uint32_t const salt_length, uint8_t const *const p_hash, uint8_t *const p_signature)
fsp_err_t	R_RSIP_RSASSA_PSS_Verify (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, rsip_hash_type_t const hash_function, rsip_mgf_type_t const mask_generation_function, uint32_t const salt_length, uint8_t const *const p_hash, uint8_t const *const p_signature)
fsp_err_t	R_RSIP_PKI_RSASSA_PKCS1_V1_5_CertVerify (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, rsip_hash_type_t const hash_function, uint8_t const *const p_hash, uint8_t const *const p_signature)
fsp_err_t	R_RSIP_PKI_RSASSA_PSS_CertVerify (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, rsip_hash_type_t const hash_function, rsip_mgf_type_t const mask_generation_function, uint32_t const salt_length, uint8_t const *const p_hash, uint8_t const *const p_signature)
fsp_err_t	R_RSIP_SHA_Compute (rsip_ctrl_t *const p_ctrl, rsip_hash_type_t const hash_type, uint8_t const *const p_message, uint32_t const message_length, uint8_t *const p_digest)
fsp_err_t	R_RSIP_SHA_Init (rsip_ctrl_t *const p_ctrl, rsip_hash_type_t const hash_type)
fsp_err_t	R_RSIP_SHA_Update (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_message, uint32_t const message_length)
fsp_err_t	R_RSIP_SHA_Finish (rsip_ctrl_t *const p_ctrl, uint8_t *const p_digest)
fsp_err_t	R_RSIP_SHA_Suspend (rsip_ctrl_t *const p_ctrl, rsip_sha_handle_t *const p_handle)
fsp_err_t	R_RSIP_SHA_Resume (rsip_ctrl_t *const p_ctrl, rsip_sha_handle_t const *const p_handle)
fsp_err_t	R_RSIP_HMAC_Compute (rsip_ctrl_t *const p_ctrl, const rsip_wrapped_key_t *p_wrapped_key, uint8_t const *const p_message, uint32_t const message_length, uint8_t *const p_mac)
fsp_err_t	R_RSIP_HMAC_Verify (rsip_ctrl_t *const p_ctrl, const rsip_wrapped_key_t *p_wrapped_key, uint8_t const *const p_message, uint32_t const message_length, uint8_t const *const p_mac, uint32_t const mac_length)
fsp_err_t	R_RSIP_HMAC_Init (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_key)
fsp_err_t	R_RSIP_HMAC_Update (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_message, uint32_t const message_length)
fsp_err_t	R_RSIP_HMAC_SignFinish (rsip_ctrl_t *const p_ctrl, uint8_t *const p_mac)
fsp_err_t	R_RSIP_HMAC_VerifyFinish (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_mac, uint32_t const mac_length)
fsp_err_t	R_RSIP_HMAC_Suspend (rsip_ctrl_t *const p_ctrl, rsip_hmac_handle_t *const p_handle)
fsp_err_t	R_RSIP_HMAC_Resume (rsip_ctrl_t *const p_ctrl, rsip_hmac_handle_t const *const p_handle)
fsp_err_t	R_RSIP_InitialKeyWrap (rsip_ctrl_t *const p_ctrl, void const *const p_wrapped_user_factory_programming_key, void const *const p_initial_vector, void const *const p_encrypted_key, rsip_wrapped_key_t *const p_wrapped_key)
fsp_err_t	R_RSIP_SB_InitialCommonKeyWrap (rsip_ctrl_t *const p_ctrl, void const *const p_wrapped_user_factory_programming_key, void const *const p_initial_vector, void const *const p_encrypted_key, rsip_sb_common_key_t *const p_injected_key)
fsp_err_t	R_RSIP_AuthPasswordHashCompute (rsip_ctrl_t *const p_ctrl, void const *const p_wrapped_user_factory_programming_key, void const *const p_initial_vector, rsip_auth_type_t const authentication_type, void const *const p_encrypted_password, rsip_hashed_auth_password_t *const p_hashed_password)
fsp_err_t	R_RSIP_PKI_InitialRootCertWrap (rsip_ctrl_t *const p_ctrl, void const *const p_wrapped_user_factory_programming_key, void const *const p_initial_vector, void const *const p_encrypted_cert, uint32_t const cert_length, uint8_t *const p_cert, rsip_root_cert_mac_t *const p_cert_mac)
fsp_err_t	R_RSIP_PKI_RootCertKeyImport (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_cert, rsip_root_cert_mac_t const *const p_cert_mac, uint8_t const *const p_key_param1, uint32_t const key_param1_length, uint8_t const *const p_key_param2, uint32_t const key_param2_length, rsip_wrapped_key_t *const p_wrapped_public_key)
fsp_err_t	R_RSIP_KDF_TLS12PRFVerifyDataCompute (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_key, rsip_tls12_prf_label_t const label, uint8_t const *const p_hash, uint8_t *const p_verify_data)
fsp_err_t	R_RSIP_TLS12_RSAPremasterSecretGenerate (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t *const p_wrapped_premaster_secret)
fsp_err_t	R_RSIP_TLS12_RSAPremasterSecretEncrypt (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, rsip_wrapped_key_t const *const p_wrapped_premaster_secret, uint8_t *const p_encrypted_premaster_secret)
fsp_err_t	R_RSIP_TLS12_RSAPremasterSecretDecrypt (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, uint8_t const *const p_encrypted_premaster_secret, rsip_wrapped_key_t *const p_wrapped_premaster_secret)
fsp_err_t	R_RSIP_SB_ManifestVerify (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_key_cert, uint32_t const key_cert_max_length, uint8_t const *const p_code_cert, uint32_t const code_cert_max_length)
fsp_err_t	R_USB_HCDC_ControlDataRead (usb_ctrl_t *const p_api_ctrl, uint8_t *p_buf, uint32_t size, uint8_t device_address)
	Read Control Data.(CDC Interrupt IN data) More...
fsp_err_t	R_USB_HCDC_SpecificDeviceRegister (usb_ctrl_t *const p_api_ctrl, uint16_t vendor_id, uint16_t product_id)
	Register the specified vendor class device in the device table. More...
fsp_err_t	R_USB_HCDC_DeviceInfoGet (usb_ctrl_t *const p_api_ctrl, usb_hcdc_device_info_t *p_info, uint8_t device_address)
	Get the VID, PID and subclass code of the connected device. More...

Variables
uint32_t	SystemCoreClock
const uint32_t	BSP_GICD_ICFGR_INIT [BSP_NON_SELECTABLE_ICFGR_MAX]

Detailed Description

Default initialization function.

Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file.

Enumeration Type Documentation

adc_channel_t [1/2]

enum adc_channel_t

ADC channels

Enumerator
ADC_CHANNEL_0	ADC channel 0.
ADC_CHANNEL_1	ADC channel 1.
ADC_CHANNEL_2	ADC channel 2.
ADC_CHANNEL_3	ADC channel 3.
ADC_CHANNEL_4	ADC channel 4.
ADC_CHANNEL_5	ADC channel 5.
ADC_CHANNEL_6	ADC channel 6.
ADC_CHANNEL_7	ADC channel 7.
ADC_CHANNEL_8	ADC channel 8.
ADC_CHANNEL_9	ADC channel 9.
ADC_CHANNEL_10	ADC channel 10.
ADC_CHANNEL_11	ADC channel 11.
ADC_CHANNEL_12	ADC channel 12.
ADC_CHANNEL_13	ADC channel 13.
ADC_CHANNEL_14	ADC channel 14.
ADC_CHANNEL_15	ADC channel 15.
ADC_CHANNEL_16	ADC channel 16.
ADC_CHANNEL_17	ADC channel 17.
ADC_CHANNEL_18	ADC channel 18.
ADC_CHANNEL_19	ADC channel 19.
ADC_CHANNEL_20	ADC channel 20.
ADC_CHANNEL_21	ADC channel 21.
ADC_CHANNEL_22	ADC channel 22.
ADC_CHANNEL_23	ADC channel 23.
ADC_CHANNEL_24	ADC channel 24.
ADC_CHANNEL_25	ADC channel 25.
ADC_CHANNEL_26	ADC channel 26.
ADC_CHANNEL_27	ADC channel 27.
ADC_CHANNEL_28	ADC channel 28.
ADC_CHANNEL_DUPLEX_A	Data duplexing register A.
ADC_CHANNEL_DUPLEX_B	Data duplexing register B.
ADC_CHANNEL_DUPLEX	Data duplexing register.
ADC_CHANNEL_TEMPERATURE	Temperature sensor output.
ADC_CHANNEL_VOLT	Internal reference voltage.
ADC_CHANNEL_0	ADC channel 0.
ADC_CHANNEL_1	ADC channel 1.
ADC_CHANNEL_2	ADC channel 2.
ADC_CHANNEL_3	ADC channel 3.
ADC_CHANNEL_4	ADC channel 4.
ADC_CHANNEL_5	ADC channel 5.
ADC_CHANNEL_6	ADC channel 6.
ADC_CHANNEL_7	ADC channel 7.
ADC_CHANNEL_8	ADC channel 8.
ADC_CHANNEL_9	ADC channel 9.
ADC_CHANNEL_10	ADC channel 10.
ADC_CHANNEL_11	ADC channel 11.
ADC_CHANNEL_12	ADC channel 12.
ADC_CHANNEL_13	ADC channel 13.
ADC_CHANNEL_14	ADC channel 14.
ADC_CHANNEL_15	ADC channel 15.
ADC_CHANNEL_16	ADC channel 16.
ADC_CHANNEL_17	ADC channel 17.
ADC_CHANNEL_18	ADC channel 18.
ADC_CHANNEL_19	ADC channel 19.
ADC_CHANNEL_20	ADC channel 20.
ADC_CHANNEL_21	ADC channel 21.
ADC_CHANNEL_22	ADC channel 22.
ADC_CHANNEL_23	ADC channel 23.
ADC_CHANNEL_24	ADC channel 24.
ADC_CHANNEL_25	ADC channel 25.
ADC_CHANNEL_26	ADC channel 26.
ADC_CHANNEL_27	ADC channel 27.
ADC_CHANNEL_28	ADC channel 28.
ADC_CHANNEL_DUPLEX_A	Data duplexing register A.
ADC_CHANNEL_DUPLEX_B	Data duplexing register B.
ADC_CHANNEL_DUPLEX	Data duplexing register.
ADC_CHANNEL_TEMPERATURE	Temperature sensor output.
ADC_CHANNEL_VOLT	Internal reference voltage.
ADC_CHANNEL_0_DSMIF_CAPTURE_A	ADC channel 0 Capture Current Data Register A.
ADC_CHANNEL_0_DSMIF_CAPTURE_B	ADC channel 0 Capture Current Data Register B.
ADC_CHANNEL_1_DSMIF_CAPTURE_A	ADC channel 1 Capture Current Data Register A.
ADC_CHANNEL_1_DSMIF_CAPTURE_B	ADC channel 1 Capture Current Data Register B.
ADC_CHANNEL_2_DSMIF_CAPTURE_A	ADC channel 2 Capture Current Data Register A.
ADC_CHANNEL_2_DSMIF_CAPTURE_B	ADC channel 2 Capture Current Data Register B.
ADC_CHANNEL_0	ADC channel 0.
ADC_CHANNEL_1	ADC channel 1.
ADC_CHANNEL_2	ADC channel 2.
ADC_CHANNEL_3	ADC channel 3.
ADC_CHANNEL_4	ADC channel 4.
ADC_CHANNEL_5	ADC channel 5.
ADC_CHANNEL_6	ADC channel 6.
ADC_CHANNEL_7	ADC channel 7.
ADC_CHANNEL_8	ADC channel 8.
ADC_CHANNEL_9	ADC channel 9.
ADC_CHANNEL_10	ADC channel 10.
ADC_CHANNEL_11	ADC channel 11.
ADC_CHANNEL_12	ADC channel 12.
ADC_CHANNEL_13	ADC channel 13.
ADC_CHANNEL_14	ADC channel 14.
ADC_CHANNEL_15	ADC channel 15.
ADC_CHANNEL_16	ADC channel 16.
ADC_CHANNEL_17	ADC channel 17.
ADC_CHANNEL_18	ADC channel 18.
ADC_CHANNEL_19	ADC channel 19.
ADC_CHANNEL_20	ADC channel 20.
ADC_CHANNEL_21	ADC channel 21.
ADC_CHANNEL_22	ADC channel 22.
ADC_CHANNEL_23	ADC channel 23.
ADC_CHANNEL_24	ADC channel 24.
ADC_CHANNEL_25	ADC channel 25.
ADC_CHANNEL_26	ADC channel 26.
ADC_CHANNEL_27	ADC channel 27.
ADC_CHANNEL_DUPLEX_A	Data duplexing register A.
ADC_CHANNEL_DUPLEX_B	Data duplexing register B.
ADC_CHANNEL_DUPLEX	Data duplexing register.
ADC_CHANNEL_TEMPERATURE	Temperature sensor output.
ADC_CHANNEL_VOLT	Internal reference voltage.
ADC_CHANNEL_0_DSMIF_CAPTURE_A	ADC channel 0 Capture Current Data Register A.
ADC_CHANNEL_0_DSMIF_CAPTURE_B	ADC channel 0 Capture Current Data Register B.
ADC_CHANNEL_1_DSMIF_CAPTURE_A	ADC channel 1 Capture Current Data Register A.
ADC_CHANNEL_1_DSMIF_CAPTURE_B	ADC channel 1 Capture Current Data Register B.
ADC_CHANNEL_2_DSMIF_CAPTURE_A	ADC channel 2 Capture Current Data Register A.
ADC_CHANNEL_2_DSMIF_CAPTURE_B	ADC channel 2 Capture Current Data Register B.

cgc_fsel_xspi_clock_div_t [1/2]

enum cgc_fsel_xspi_clock_div_t

Divider values of clock provided to xSPI

Enumerator
CGC_FSEL_XSPI_CLOCK_DIV_6	XSPI_CLKn 133.3MHz (XSPI base clock divided by 3)
CGC_FSEL_XSPI_CLOCK_DIV_8	XSPI_CLKn 100.0MHz / 75.0MHz (XSPI base clock divided by 3 / divided by 4)
CGC_FSEL_XSPI_CLOCK_DIV_16	XSPI_CLKn 50.0MHz / 37.5MHz (XSPI base clock divided by 3 / divided by 4)
CGC_FSEL_XSPI_CLOCK_DIV_32	XSPI_CLKn 25.0MHz (XSPI base clock divided by 3)
CGC_FSEL_XSPI_CLOCK_DIV_64	XSPI_CLKn 12.5MHz (XSPI base clock divided by 3)
CGC_FSEL_XSPI_CLOCK_DIV_6	XSPI_CLKn 133.3MHz (XSPI base clock divided by 3)
CGC_FSEL_XSPI_CLOCK_DIV_8	XSPI_CLKn 100.0MHz / 75.0MHz (XSPI base clock divided by 3 / divided by 4)
CGC_FSEL_XSPI_CLOCK_DIV_16	XSPI_CLKn 50.0MHz / 37.5MHz (XSPI base clock divided by 3 / divided by 4)
CGC_FSEL_XSPI_CLOCK_DIV_32	XSPI_CLKn 25.0MHz (XSPI base clock divided by 3)
CGC_FSEL_XSPI_CLOCK_DIV_64	XSPI_CLKn 12.5MHz (XSPI base clock divided by 3)

cgc_divsel_xspi_clock_div_t [1/2]

enum cgc_divsel_xspi_clock_div_t

Divider values of base clock generated for xSPI

Enumerator
CGC_DIVSEL_XSPI_CLOCK_DIV_3	XSPI base clock divided by 3.
CGC_DIVSEL_XSPI_CLOCK_DIV_4	XSPI base clock divided by 4.
CGC_DIVSEL_XSPI_CLOCK_DIV_3	XSPI base clock divided by 3.
CGC_DIVSEL_XSPI_CLOCK_DIV_4	XSPI base clock divided by 4.

cgc_clock_out_clock_div_t [1/2]

enum cgc_clock_out_clock_div_t

Clock output divider values

Enumerator
CGC_CLOCK_OUT_CLOCK_DIV_2	CKIO 100.0MHz / 75.0MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_3	CKIO 66.7MHz / 50.0MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_4	CKIO 50.0MHz / 37.5MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_5	CKIO 40.0MHz / 30.0MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_6	CKIO 33.3MHz / 25.0MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_7	CKIO 28.6MHz / 21.4MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_8	CKIO 25.0MHz / 18.75MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_2	CKIO 100.0MHz / 75.0MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_3	CKIO 66.7MHz / 50.0MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_4	CKIO 50.0MHz / 37.5MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_5	CKIO 40.0MHz / 30.0MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_6	CKIO 33.3MHz / 25.0MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_7	CKIO 28.6MHz / 21.4MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_8	CKIO 25.0MHz / 18.75MHz (Base clock divided by 3 / divided by 4)

cgc_canfd_clock_div_t [1/2]

enum cgc_canfd_clock_div_t

CANFD clock divider values

Enumerator
CGC_CANFD_CLOCK_DIV_10	CANFD clock 80.0MHz.
CGC_CANFD_CLOCK_DIV_20	CANFD clock 40.0MHz.
CGC_CANFD_CLOCK_DIV_10	CANFD clock 80.0MHz.
CGC_CANFD_CLOCK_DIV_20	CANFD clock 40.0MHz.

cgc_phy_clock_t [1/2]

enum cgc_phy_clock_t

PHY clock source identifiers

Enumerator
CGC_PHY_CLOCK_PLL1	PLL1 divider clock.
CGC_PHY_CLOCK_MAIN_OSC	Main clock oscillator.
CGC_PHY_CLOCK_PLL1	PLL1 divider clock.
CGC_PHY_CLOCK_MAIN_OSC	Main clock oscillator.

cgc_spi_async_clock_t [1/2]

enum cgc_spi_async_clock_t

SPI asynchronous serial clock frequency

Enumerator
CGC_SPI_ASYNC_CLOCK_75MHZ	SPI asynchronous serial clock 75MHz.
CGC_SPI_ASYNC_CLOCK_80MHZ	SPI asynchronous serial clock 80MHz.
CGC_SPI_ASYNC_CLOCK_96MHZ	SPI asynchronous serial clock 96MHz.
CGC_SPI_ASYNC_CLOCK_100MHZ	SPI asynchronous serial clock 100MHz.
CGC_SPI_ASYNC_CLOCK_75MHZ	SPI asynchronous serial clock 75MHz.
CGC_SPI_ASYNC_CLOCK_96MHZ	SPI asynchronous serial clock 96MHz.

cgc_sci_async_clock_t [1/2]

enum cgc_sci_async_clock_t

SCI asynchronous serial clock frequency

Enumerator
CGC_SCI_ASYNC_CLOCK_75MHZ	SCI asynchronous serial clock 75MHz.
CGC_SCI_ASYNC_CLOCK_80MHZ	SCI asynchronous serial clock 80MHz.
CGC_SCI_ASYNC_CLOCK_96MHZ	SCI asynchronous serial clock 96MHz.
CGC_SCI_ASYNC_CLOCK_100MHZ	SCI asynchronous serial clock 100MHz.
CGC_SCI_ASYNC_CLOCK_75MHZ	SCI asynchronous serial clock 75MHz.
CGC_SCI_ASYNC_CLOCK_96MHZ	SCI asynchronous serial clock 96MHz.

cgc_lcdc_div_t

enum cgc_lcdc_div_t

LCDC clock divider values

Enumerator
CGC_LCDC_DIV_2	PLL3 output clock divided by 2.
CGC_LCDC_DIV_4	PLL3 output clock divided by 4.
CGC_LCDC_DIV_6	PLL3 output clock divided by 6.
CGC_LCDC_DIV_8	PLL3 output clock divided by 8.
CGC_LCDC_DIV_10	PLL3 output clock divided by 10.
CGC_LCDC_DIV_12	PLL3 output clock divided by 12.
CGC_LCDC_DIV_14	PLL3 output clock divided by 14.
CGC_LCDC_DIV_16	PLL3 output clock divided by 16.
CGC_LCDC_DIV_18	PLL3 output clock divided by 18.
CGC_LCDC_DIV_20	PLL3 output clock divided by 20.
CGC_LCDC_DIV_22	PLL3 output clock divided by 22.
CGC_LCDC_DIV_24	PLL3 output clock divided by 24.
CGC_LCDC_DIV_26	PLL3 output clock divided by 26.
CGC_LCDC_DIV_28	PLL3 output clock divided by 28.
CGC_LCDC_DIV_30	PLL3 output clock divided by 30.
CGC_LCDC_DIV_32	PLL3 output clock divided by 32s.

cgc_scie_async_clock_t

enum cgc_scie_async_clock_t

SCIE asynchronous serial clock frequency

Enumerator
CGC_SCIE_ASYNC_CLOCK_75MHZ	SCI asynchronous serial clock 75MHz.
CGC_SCIE_ASYNC_CLOCK_80MHZ	SCI asynchronous serial clock 80MHz.
CGC_SCIE_ASYNC_CLOCK_96MHZ	SCI asynchronous serial clock 96MHz.
CGC_SCIE_ASYNC_CLOCK_100MHZ	SCI asynchronous serial clock 100MHz.

cgc_encout_clock_t

enum cgc_encout_clock_t

ENCOUT clock frequency

Enumerator
CGC_ENCOUT_CLOCK_20MHZ	ENCOUT provided clock 20MHz.
CGC_ENCOUT_CLOCK_80MHZ	ENCOUT provided clock 80MHz.

cgc_cpu_clock_div_t [1/2]

enum cgc_cpu_clock_div_t

CPU clock divider values

Enumerator
CGC_CPU_CLOCK_DIV_2	CR52/DSU 500MHz, CA55 600MHz. CPU 200.0MHz / 150.0MHz (Base clock divided by 3 / divided by 4)
CGC_CPU_CLOCK_DIV_1	CR52/DSU 1000MHz, CA55 1200MHz. CPU 400.0MHz / 300.0MHz (Base clock divided by 3 / divided by 4)
CGC_CPU_CLOCK_DIV_2	CR52/DSU 500MHz, CA55 600MHz. CPU 200.0MHz / 150.0MHz (Base clock divided by 3 / divided by 4)
CGC_CPU_CLOCK_DIV_1	CR52/DSU 1000MHz, CA55 1200MHz. CPU 400.0MHz / 300.0MHz (Base clock divided by 3 / divided by 4)

cgc_clock_t [1/2]

enum cgc_clock_t

System clock source identifiers

Enumerator
CGC_CLOCK_HOCO	The high speed on chip oscillator.
CGC_CLOCK_MOCO	The middle speed on chip oscillator.
CGC_CLOCK_LOCO	The low speed on chip oscillator.
CGC_CLOCK_MAIN_OSC	The main oscillator.
CGC_CLOCK_SUBCLOCK	The subclock oscillator.
CGC_CLOCK_PLL	The PLL oscillator.
CGC_CLOCK_PLL2	The PLL2 oscillator.
CGC_CLOCK_LOCO	The low speed on chip oscillator.
CGC_CLOCK_PLL0	The PLL0 oscillator.
CGC_CLOCK_PLL1	The PLL1 oscillator.
CGC_CLOCK_PLL2	The PLL2 oscillator.
CGC_CLOCK_PLL3	The PLL3 oscillator.
CGC_CLOCK_PLL4	The PLL4 oscillator.
CGC_CLOCK_LOCO	The low speed on chip oscillator.
CGC_CLOCK_PLL0	The PLL0 oscillator.
CGC_CLOCK_PLL1	The PLL1 oscillator.

cgc_clock_change_t [1/2]

enum cgc_clock_change_t

Clock options

Enumerator
CGC_CLOCK_CHANGE_START	Start the clock.
CGC_CLOCK_CHANGE_STOP	Stop the clock.
CGC_CLOCK_CHANGE_NONE	No change to the clock.
CGC_CLOCK_CHANGE_START	Start the clock.
CGC_CLOCK_CHANGE_STOP	Stop the clock.
CGC_CLOCK_CHANGE_NONE	No change to the clock.
CGC_CLOCK_CHANGE_START	Start the clock.
CGC_CLOCK_CHANGE_STOP	Stop the clock.
CGC_CLOCK_CHANGE_NONE	No change to the clock.

display_in_format_t

enum display_in_format_t

Enumerator
DISPLAY_IN_FORMAT_32BITS_ARGB8888	ARGB8888, 32 bits.
DISPLAY_IN_FORMAT_32BITS_RGB888	RGB888, 32 bits.
DISPLAY_IN_FORMAT_16BITS_RGB565	RGB565, 16 bits.
DISPLAY_IN_FORMAT_16BITS_ARGB1555	ARGB1555, 16 bits.
DISPLAY_IN_FORMAT_16BITS_ARGB4444	ARGB4444, 16 bits.
DISPLAY_IN_FORMAT_CLUT8	CLUT8.
DISPLAY_IN_FORMAT_CLUT4	CLUT4.
DISPLAY_IN_FORMAT_CLUT1	CLUT1.
DISPLAY_IN_FORMAT_32BITS_ARGB8888	ARGB8888, 32 bits.
DISPLAY_IN_FORMAT_32BITS_RGB888	RGB888, 32 bits.
DISPLAY_IN_FORMAT_16BITS_RGB565	RGB565, 16 bits.
DISPLAY_IN_FORMAT_16BITS_ARGB1555	ARGB1555, 16 bits.
DISPLAY_IN_FORMAT_16BITS_ARGB4444	ARGB4444, 16 bits.
DISPLAY_IN_FORMAT_CLUT8	CLUT8.
DISPLAY_IN_FORMAT_CLUT4	CLUT4.
DISPLAY_IN_FORMAT_CLUT1	CLUT1.
DISPLAY_IN_FORMAT_32BITS_RGBA8888	RGBA8888, 32 bits.
DISPLAY_IN_FORMAT_24BITS_BGR888	BGR888, 24 bits.
DISPLAY_IN_FORMAT_24BITS_RGB888	RGB888, 24 bits.
DISPLAY_IN_FORMAT_32BITS_ABGR8888	ABGR8888, 32 bits.
DISPLAY_IN_FORMAT_24BITS_YCBCR444_INTERLEAVED	YCbCr444 interleaved, 24 bits.
DISPLAY_IN_FORMAT_16BITS_YCBCR422_INTERLEAVED_TYPE0_UYVY	YCbCr422 interleaved type0 UYVY, 16 bits.
DISPLAY_IN_FORMAT_16BITS_YCBCR422_INTERLEAVED_TYPE0_YUY2	YCbCr422 interleaved type0 YUY2, 16 bits.
DISPLAY_IN_FORMAT_16BITS_YCBCR422_INTERLEAVED_TYPE0_YVYU	YCbCr422 interleaved type0 YVYU, 16 bits.
DISPLAY_IN_FORMAT_16BITS_YCBCR422_INTERLEAVED_TYPE1	YCbCr420 interleaved type1, 16 bits.
DISPLAY_IN_FORMAT_16BITS_YCBCR420_INTERLEAVED	YCbCr420 interleaved, 12 bits.
DISPLAY_IN_FORMAT_16BITS_YCBCR420_PLANAR	YCbCr420 planar, 16bits.
DISPLAY_IN_FORMAT_CUSTOM	All other options start at this value.

elc_peripheral_t [1/2]

enum elc_peripheral_t

Possible peripherals to be linked to event signals (not all available on all MPUs)

error_event_t [1/2]

enum error_event_t

Error event source.

Enumerator
ERROR_EVENT_CPU0	Error event from CPU0. Error event from CR520.
ERROR_EVENT_CPU1	Error event from CPU1. Error event from CR521.
ERROR_EVENT_PERIPHERAL_0	Error event from Peripheral 0.
ERROR_EVENT_PERIPHERAL_1	Error event from Peripheral 1.
ERROR_EVENT_CPU0	Error event from CPU0. Error event from CR520.
ERROR_EVENT_CPU1	Error event from CPU1. Error event from CR521.
ERROR_EVENT_CA55	Error event from CA55.
ERROR_EVENT_PERIPHERAL_0	Error event from Peripheral 0.
ERROR_EVENT_PERIPHERAL_1	Error event from Peripheral 1.
ERROR_EVENT_PERIPHERAL_2	Error event from Peripheral 2.
ERROR_EVENT_DSMIF_0	Error event from DSMIF 0.
ERROR_EVENT_DSMIF_1	Error event from DSMIF 1.
ERROR_EVENT_DSMIF_2	Error event from DSMIF 2.
ERROR_EVENT_DSMIF_3	Error event from DSMIF 3.
ERROR_EVENT_DSMIF_4	Error event from DSMIF 4.
ERROR_EVENT_DSMIF_5	Error event from DSMIF 5.
ERROR_EVENT_DSMIF_7	Error event from DSMIF 7.
ERROR_EVENT_DSMIF_8	Error event from DSMIF 8.
ERROR_EVENT_DSMIF_10	Error event from DSMIF 10.
ERROR_EVENT_DSMIF_11	Error event from DSMIF 11.
ERROR_EVENT_ENCIF_0	Error event from ENCIF 0.
ERROR_EVENT_ENCIF_1	Error event from ENCIF 1.
ERROR_EVENT_ENCIF_2	Error event from ENCIF 2.
ERROR_EVENT_ENCIF_3	Error event from ENCIF 3.
ERROR_EVENT_ENCIF_4	Error event from ENCIF 4.
ERROR_EVENT_CPU0	Error event from CPU0. Error event from CR520.
ERROR_EVENT_PERIPHERAL_0	Error event from Peripheral 0.
ERROR_EVENT_PERIPHERAL_1	Error event from Peripheral 1.

ioport_pin_pfc_t [1/2]

enum ioport_pin_pfc_t

Superset of all peripheral functions.

Enumerator
IOPORT_PIN_P000_PFC_00_SEI	P00_0 / IRQ / SEI.
IOPORT_PIN_P000_PFC_04_D0	P00_0 / BSC / D0.
IOPORT_PIN_P000_PFC_06_MTIOC3B	P00_0 / MTU3 / MTIOC3B.
IOPORT_PIN_P000_PFC_09_GTIOC00_0A	P00_0 / GPT / GTIOC00_0A.
IOPORT_PIN_P000_PFC_0F_ETH3_TXER	P00_0 / ETHER_ETHn / ETH3_TXER.
IOPORT_PIN_P000_PFC_13_USB_VBUSEN	P00_0 / USB / USB_VBUSEN.
IOPORT_PIN_P000_PFC_24_DUEI00	P00_0 / ENDATn / DUEI00.
IOPORT_PIN_P000_PFC_25_HDSL00_LINK	P00_0 / HDSLn / HDSL00_LINK.
IOPORT_PIN_P001_PFC_00_IRQ0	P00_1 / IRQ / IRQ0.
IOPORT_PIN_P001_PFC_04_D1	P00_1 / BSC / D1.
IOPORT_PIN_P001_PFC_06_MTIOC3D	P00_1 / MTU3 / MTIOC3D.
IOPORT_PIN_P001_PFC_09_GTIOC00_0B	P00_1 / GPT / GTIOC00_0B.
IOPORT_PIN_P001_PFC_0F_ETH3_RXER	P00_1 / ETHER_ETHn / ETH3_RXER.
IOPORT_PIN_P001_PFC_13_USB_OVRCUR	P00_1 / USB / USB_OVRCUR.
IOPORT_PIN_P001_PFC_24_TST_OUT00	P00_1 / ENDATn / TST_OUT00.
IOPORT_PIN_P001_PFC_25_HDSL00_SMPL	P00_1 / HDSLn / HDSL00_SMPL.
IOPORT_PIN_P002_PFC_00_IRQ1	P00_2 / IRQ / IRQ1.
IOPORT_PIN_P002_PFC_04_D2	P00_2 / BSC / D2.
IOPORT_PIN_P002_PFC_06_MTIOC4A	P00_2 / MTU3 / MTIOC4A.
IOPORT_PIN_P002_PFC_09_GTIOC00_1A	P00_2 / GPT / GTIOC00_1A.
IOPORT_PIN_P002_PFC_0F_ETH3_CRS	P00_2 / ETHER_ETHn / ETH3_CRS.
IOPORT_PIN_P002_PFC_13_USB_EXICEN	P00_2 / USB / USB_EXICEN.
IOPORT_PIN_P002_PFC_1F_ADTRG0	P00_2 / ADCn / ADTRG0.
IOPORT_PIN_P002_PFC_24_SI00	P00_2 / ENDATn / SI00.
IOPORT_PIN_P002_PFC_25_HDSL00_CLK1	P00_2 / HDSLn / HDSL00_CLK1.
IOPORT_PIN_P003_PFC_00_IRQ2	P00_3 / IRQ / IRQ2.
IOPORT_PIN_P003_PFC_04_D3	P00_3 / BSC / D3.
IOPORT_PIN_P003_PFC_06_MTIOC4C	P00_3 / MTU3 / MTIOC4C.
IOPORT_PIN_P003_PFC_09_GTIOC00_1B	P00_3 / GPT / GTIOC00_1B.
IOPORT_PIN_P003_PFC_0F_ETH3_COL	P00_3 / ETHER_ETHn / ETH3_COL.
IOPORT_PIN_P003_PFC_1F_ADTRG1	P00_3 / ADCn / ADTRG1.
IOPORT_PIN_P003_PFC_24_DUEI01	P00_3 / ENDATn / DUEI01.
IOPORT_PIN_P003_PFC_25_HDSL00_SEL1	P00_3 / HDSLn / HDSL00_SEL1.
IOPORT_PIN_P004_PFC_00_IRQ3	P00_4 / IRQ / IRQ3.
IOPORT_PIN_P004_PFC_04_D4	P00_4 / BSC / D4.
IOPORT_PIN_P004_PFC_06_MTIOC4B	P00_4 / MTU3 / MTIOC4B.
IOPORT_PIN_P004_PFC_09_GTIOC00_2A	P00_4 / GPT / GTIOC00_2A.
IOPORT_PIN_P004_PFC_1F_ADTRG2	P00_4 / ADCn / ADTRG2.
IOPORT_PIN_P004_PFC_24_TST_OUT01	P00_4 / ENDATn / TST_OUT01.
IOPORT_PIN_P004_PFC_25_HDSL00_MISO1	P00_4 / HDSLn / HDSL00_MISO1.
IOPORT_PIN_P005_PFC_06_MTIOC4D	P00_5 / MTU3 / MTIOC4D.
IOPORT_PIN_P005_PFC_07_MTIOC8C	P00_5 / MTU3 / MTIOC8C.
IOPORT_PIN_P005_PFC_09_GTIOC00_2B	P00_5 / GPT / GTIOC00_2B.
IOPORT_PIN_P005_PFC_13_USB_VBUSEN	P00_5 / USB / USB_VBUSEN.
IOPORT_PIN_P005_PFC_24_SI01	P00_5 / ENDATn / SI01.
IOPORT_PIN_P005_PFC_25_HDSL00_MOSI1	P00_5 / HDSLn / HDSL00_MOSI1.
IOPORT_PIN_P006_PFC_00_IRQ4	P00_6 / IRQ / IRQ4.
IOPORT_PIN_P006_PFC_06_MTCLKA	P00_6 / MTU3 / MTCLKA.
IOPORT_PIN_P006_PFC_07_MTIOC8D	P00_6 / MTU3 / MTIOC8D.
IOPORT_PIN_P006_PFC_09_GTIOC00_3A	P00_6 / GPT / GTIOC00_3A.
IOPORT_PIN_P006_PFC_13_USB_OVRCUR	P00_6 / USB / USB_OVRCUR.
IOPORT_PIN_P006_PFC_15_SCKE00	P00_6 / SCIEn / SCKE00.
IOPORT_PIN_P006_PFC_16_SCKE04	P00_6 / SCIEn / SCKE04.
IOPORT_PIN_P006_PFC_17_IIC_SCL0	P00_6 / IICn / IIC_SCL0.
IOPORT_PIN_P006_PFC_22_ENCIFCK00	P00_6 / ENCIFn / ENCIFCK00.
IOPORT_PIN_P006_PFC_23_ENCIFCK04	P00_6 / ENCIFn / ENCIFCK04.
IOPORT_PIN_P006_PFC_25_HDSL00_CLK2	P00_6 / HDSLn / HDSL00_CLK2.
IOPORT_PIN_P007_PFC_00_IRQ5	P00_7 / IRQ / IRQ5.
IOPORT_PIN_P007_PFC_06_MTCLKB	P00_7 / MTU3 / MTCLKB.
IOPORT_PIN_P007_PFC_07_MTIOC1B	P00_7 / MTU3 / MTIOC1B.
IOPORT_PIN_P007_PFC_09_GTIOC00_3B	P00_7 / GPT / GTIOC00_3B.
IOPORT_PIN_P007_PFC_13_USB_EXICEN	P00_7 / USB / USB_EXICEN.
IOPORT_PIN_P007_PFC_15_DEE00	P00_7 / SCIEn / DEE00.
IOPORT_PIN_P007_PFC_16_DEE04	P00_7 / SCIEn / DEE04.
IOPORT_PIN_P007_PFC_17_IIC_SDA0	P00_7 / IICn / IIC_SDA0.
IOPORT_PIN_P007_PFC_22_ENCIFOE00	P00_7 / ENCIFn / ENCIFOE00.
IOPORT_PIN_P007_PFC_23_ENCIFOE04	P00_7 / ENCIFn / ENCIFOE04.
IOPORT_PIN_P007_PFC_25_HDSL00_SEL2	P00_7 / HDSLn / HDSL00_SEL2.
IOPORT_PIN_P010_PFC_00_IRQ6	P01_0 / IRQ / IRQ6.
IOPORT_PIN_P010_PFC_06_MTIOC3A	P01_0 / MTU3 / MTIOC3A.
IOPORT_PIN_P010_PFC_07_MTIOC1A	P01_0 / MTU3 / MTIOC1A.
IOPORT_PIN_P010_PFC_09_GTIOC00_4A	P01_0 / GPT / GTIOC00_4A.
IOPORT_PIN_P010_PFC_0A_GTIOC00_2B	P01_0 / GPT / GTIOC00_2B.
IOPORT_PIN_P010_PFC_15_TXDE00	P01_0 / SCIEn / TXDE00.
IOPORT_PIN_P010_PFC_16_TXDE04	P01_0 / SCIEn / TXDE04.
IOPORT_PIN_P010_PFC_17_IIC_SCL1	P01_0 / IICn / IIC_SCL1.
IOPORT_PIN_P010_PFC_1C_XSPI1_CKP	P01_0 / xSPIn / XSPI1_CKP.
IOPORT_PIN_P010_PFC_22_ENCIFDO00	P01_0 / ENCIFn / ENCIFDO00.
IOPORT_PIN_P010_PFC_23_ENCIFDO04	P01_0 / ENCIFn / ENCIFDO04.
IOPORT_PIN_P010_PFC_25_HDSL00_MISO2	P01_0 / HDSLn / HDSL00_MISO2.
IOPORT_PIN_P011_PFC_06_MTIOC3C	P01_1 / MTU3 / MTIOC3C.
IOPORT_PIN_P011_PFC_07_MTIOC8A	P01_1 / MTU3 / MTIOC8A.
IOPORT_PIN_P011_PFC_09_GTIOC00_4B	P01_1 / GPT / GTIOC00_4B.
IOPORT_PIN_P011_PFC_15_RXDE00	P01_1 / SCIEn / RXDE00.
IOPORT_PIN_P011_PFC_16_RXDE04	P01_1 / SCIEn / RXDE04.
IOPORT_PIN_P011_PFC_1C_XSPI1_CS0	P01_1 / xSPIn / XSPI1_CS0.
IOPORT_PIN_P011_PFC_1D_MCLK20	P01_1 / DSMIFn / MCLK20.
IOPORT_PIN_P011_PFC_22_ENCIFDI00	P01_1 / ENCIFn / ENCIFDI00.
IOPORT_PIN_P011_PFC_23_ENCIFDI04	P01_1 / ENCIFn / ENCIFDI04.
IOPORT_PIN_P011_PFC_25_HDSL00_MOSI2	P01_1 / HDSLn / HDSL00_MOSI2.
IOPORT_PIN_P012_PFC_06_MTIOC6B	P01_2 / MTU3 / MTIOC6B.
IOPORT_PIN_P012_PFC_07_MTIOC8B	P01_2 / MTU3 / MTIOC8B.
IOPORT_PIN_P012_PFC_09_GTIOC01_0A	P01_2 / GPT / GTIOC01_0A.
IOPORT_PIN_P012_PFC_0A_GTIOC04_0A	P01_2 / GPT / GTIOC04_0A.
IOPORT_PIN_P012_PFC_1C_XSPI1_CS1	P01_2 / xSPIn / XSPI1_CS1.
IOPORT_PIN_P012_PFC_24_DUEI02	P01_2 / ENDATn / DUEI02.
IOPORT_PIN_P012_PFC_25_HDSL01_LINK	P01_2 / HDSLn / HDSL01_LINK.
IOPORT_PIN_P013_PFC_06_MTIOC6D	P01_3 / MTU3 / MTIOC6D.
IOPORT_PIN_P013_PFC_07_MTIC5U	P01_3 / MTU3 / MTIC5U.
IOPORT_PIN_P013_PFC_09_GTIOC01_0B	P01_3 / GPT / GTIOC01_0B.
IOPORT_PIN_P013_PFC_0A_GTIOC04_0B	P01_3 / GPT / GTIOC04_0B.
IOPORT_PIN_P013_PFC_1C_XSPI1_DS	P01_3 / xSPIn / XSPI1_DS.
IOPORT_PIN_P013_PFC_24_TST_OUT02	P01_3 / ENDATn / TST_OUT02.
IOPORT_PIN_P013_PFC_25_HDSL01_SMPL	P01_3 / HDSLn / HDSL01_SMPL.
IOPORT_PIN_P014_PFC_06_MTIOC7A	P01_4 / MTU3 / MTIOC7A.
IOPORT_PIN_P014_PFC_07_MTIC5V	P01_4 / MTU3 / MTIC5V.
IOPORT_PIN_P014_PFC_09_GTIOC01_1A	P01_4 / GPT / GTIOC01_1A.
IOPORT_PIN_P014_PFC_0A_GTIOC04_1A	P01_4 / GPT / GTIOC04_1A.
IOPORT_PIN_P014_PFC_1C_XSPI1_IO0	P01_4 / xSPIn / XSPI1_IO0.
IOPORT_PIN_P014_PFC_24_SI02	P01_4 / ENDATn / SI02.
IOPORT_PIN_P014_PFC_25_HDSL01_CLK1	P01_4 / HDSLn / HDSL01_CLK1.
IOPORT_PIN_P015_PFC_06_MTIOC7C	P01_5 / MTU3 / MTIOC7C.
IOPORT_PIN_P015_PFC_07_MTIC5W	P01_5 / MTU3 / MTIC5W.
IOPORT_PIN_P015_PFC_09_GTIOC01_1B	P01_5 / GPT / GTIOC01_1B.
IOPORT_PIN_P015_PFC_0A_GTIOC04_1B	P01_5 / GPT / GTIOC04_1B.
IOPORT_PIN_P015_PFC_1C_XSPI1_IO1	P01_5 / xSPIn / XSPI1_IO1.
IOPORT_PIN_P015_PFC_24_DUEI03	P01_5 / ENDATn / DUEI03.
IOPORT_PIN_P015_PFC_25_HDSL01_SEL1	P01_5 / HDSLn / HDSL01_SEL1.
IOPORT_PIN_P016_PFC_06_MTIOC7B	P01_6 / MTU3 / MTIOC7B.
IOPORT_PIN_P016_PFC_07_MTIOC0A	P01_6 / MTU3 / MTIOC0A.
IOPORT_PIN_P016_PFC_09_GTIOC01_2A	P01_6 / GPT / GTIOC01_2A.
IOPORT_PIN_P016_PFC_0A_GTIOC04_2A	P01_6 / GPT / GTIOC04_2A.
IOPORT_PIN_P016_PFC_1C_XSPI1_IO2	P01_6 / xSPIn / XSPI1_IO2.
IOPORT_PIN_P016_PFC_24_TST_OUT03	P01_6 / ENDATn / TST_OUT03.
IOPORT_PIN_P016_PFC_25_HDSL01_MISO1	P01_6 / HDSLn / HDSL01_MISO1.
IOPORT_PIN_P017_PFC_06_MTIOC7D	P01_7 / MTU3 / MTIOC7D.
IOPORT_PIN_P017_PFC_07_MTIOC0B	P01_7 / MTU3 / MTIOC0B.
IOPORT_PIN_P017_PFC_09_GTIOC01_2B	P01_7 / GPT / GTIOC01_2B.
IOPORT_PIN_P017_PFC_0A_GTIOC04_2B	P01_7 / GPT / GTIOC04_2B.
IOPORT_PIN_P017_PFC_1C_XSPI1_IO3	P01_7 / xSPIn / XSPI1_IO3.
IOPORT_PIN_P017_PFC_24_SI03	P01_7 / ENDATn / SI03.
IOPORT_PIN_P017_PFC_25_HDSL01_MOSI1	P01_7 / HDSLn / HDSL01_MOSI1.
IOPORT_PIN_P020_PFC_00_IRQ7	P02_0 / IRQ / IRQ7.
IOPORT_PIN_P020_PFC_06_MTCLKC	P02_0 / MTU3 / MTCLKC.
IOPORT_PIN_P020_PFC_07_MTIOC0C	P02_0 / MTU3 / MTIOC0C.
IOPORT_PIN_P020_PFC_09_GTIOC01_3A	P02_0 / GPT / GTIOC01_3A.
IOPORT_PIN_P020_PFC_0F_ETH3_TXER	P02_0 / ETHER_ETHn / ETH3_TXER.
IOPORT_PIN_P020_PFC_15_SCKE01	P02_0 / SCIEn / SCKE01.
IOPORT_PIN_P020_PFC_17_IIC_SDA1	P02_0 / IICn / IIC_SDA1.
IOPORT_PIN_P020_PFC_1C_XSPI1_IO4	P02_0 / xSPIn / XSPI1_IO4.
IOPORT_PIN_P020_PFC_1D_MCLK21	P02_0 / DSMIFn / MCLK21.
IOPORT_PIN_P020_PFC_22_ENCIFCK01	P02_0 / ENCIFn / ENCIFCK01.
IOPORT_PIN_P020_PFC_25_HDSL01_CLK2	P02_0 / HDSLn / HDSL01_CLK2.
IOPORT_PIN_P021_PFC_00_IRQ8	P02_1 / IRQ / IRQ8.
IOPORT_PIN_P021_PFC_06_MTCLKD	P02_1 / MTU3 / MTCLKD.
IOPORT_PIN_P021_PFC_07_MTIOC0D	P02_1 / MTU3 / MTIOC0D.
IOPORT_PIN_P021_PFC_09_GTIOC01_3B	P02_1 / GPT / GTIOC01_3B.
IOPORT_PIN_P021_PFC_0F_ETH3_RXER	P02_1 / ETHER_ETHn / ETH3_RXER.
IOPORT_PIN_P021_PFC_15_DEE01	P02_1 / SCIEn / DEE01.
IOPORT_PIN_P021_PFC_17_IIC_SCL2	P02_1 / IICn / IIC_SCL2.
IOPORT_PIN_P021_PFC_1C_XSPI1_IO5	P02_1 / xSPIn / XSPI1_IO5.
IOPORT_PIN_P021_PFC_1D_MDAT21	P02_1 / DSMIFn / MDAT21.
IOPORT_PIN_P021_PFC_22_ENCIFOE01	P02_1 / ENCIFn / ENCIFOE01.
IOPORT_PIN_P021_PFC_25_HDSL01_SEL2	P02_1 / HDSLn / HDSL01_SEL2.
IOPORT_PIN_P022_PFC_00_IRQ9	P02_2 / IRQ / IRQ9.
IOPORT_PIN_P022_PFC_06_MTIOC6A	P02_2 / MTU3 / MTIOC6A.
IOPORT_PIN_P022_PFC_07_MTIOC1A	P02_2 / MTU3 / MTIOC1A.
IOPORT_PIN_P022_PFC_09_GTIOC01_4A	P02_2 / GPT / GTIOC01_4A.
IOPORT_PIN_P022_PFC_0F_ETH3_CRS	P02_2 / ETHER_ETHn / ETH3_CRS.
IOPORT_PIN_P022_PFC_13_USB_VBUSEN	P02_2 / USB / USB_VBUSEN.
IOPORT_PIN_P022_PFC_15_TXDE01	P02_2 / SCIEn / TXDE01.
IOPORT_PIN_P022_PFC_17_IIC_SDA2	P02_2 / IICn / IIC_SDA2.
IOPORT_PIN_P022_PFC_1C_XSPI1_IO6	P02_2 / xSPIn / XSPI1_IO6.
IOPORT_PIN_P022_PFC_1D_MCLK22	P02_2 / DSMIFn / MCLK22.
IOPORT_PIN_P022_PFC_22_ENCIFDO01	P02_2 / ENCIFn / ENCIFDO01.
IOPORT_PIN_P022_PFC_25_HDSL01_MISO2	P02_2 / HDSLn / HDSL01_MISO2.
IOPORT_PIN_P023_PFC_00_IRQ10	P02_3 / IRQ / IRQ10.
IOPORT_PIN_P023_PFC_06_MTIOC6C	P02_3 / MTU3 / MTIOC6C.
IOPORT_PIN_P023_PFC_07_MTIOC1B	P02_3 / MTU3 / MTIOC1B.
IOPORT_PIN_P023_PFC_09_GTIOC01_4B	P02_3 / GPT / GTIOC01_4B.
IOPORT_PIN_P023_PFC_0F_ETH3_COL	P02_3 / ETHER_ETHn / ETH3_COL.
IOPORT_PIN_P023_PFC_13_USB_OVRCUR	P02_3 / USB / USB_OVRCUR.
IOPORT_PIN_P023_PFC_15_RXDE01	P02_3 / SCIEn / RXDE01.
IOPORT_PIN_P023_PFC_17_IIC_SCL0	P02_3 / IICn / IIC_SCL0.
IOPORT_PIN_P023_PFC_18_IIC_SCL2	P02_3 / IICn / IIC_SCL2.
IOPORT_PIN_P023_PFC_1C_XSPI1_IO7	P02_3 / xSPIn / XSPI1_IO7.
IOPORT_PIN_P023_PFC_1D_MDAT22	P02_3 / DSMIFn / MDAT22.
IOPORT_PIN_P023_PFC_22_ENCIFDI01	P02_3 / ENCIFn / ENCIFDI01.
IOPORT_PIN_P023_PFC_25_HDSL01_MOSI2	P02_3 / HDSLn / HDSL01_MOSI2.
IOPORT_PIN_P024_PFC_00_IRQ11	P02_4 / IRQ / IRQ11.
IOPORT_PIN_P024_PFC_08_POE0	P02_4 / POE3 / POE0.
IOPORT_PIN_P024_PFC_13_USB_EXICEN	P02_4 / USB / USB_EXICEN.
IOPORT_PIN_P024_PFC_17_IIC_SDA0	P02_4 / IICn / IIC_SDA0.
IOPORT_PIN_P024_PFC_1D_MDAT20	P02_4 / DSMIFn / MDAT20.
IOPORT_PIN_P024_PFC_21_MBX_HINT	P02_4 / MBXSEM / MBX_HINT.
IOPORT_PIN_P024_PFC_25_HDSL02_LINK	P02_4 / HDSLn / HDSL02_LINK.
IOPORT_PIN_P025_PFC_04_D5	P02_5 / BSC / D5.
IOPORT_PIN_P025_PFC_06_MTIOC3B	P02_5 / MTU3 / MTIOC3B.
IOPORT_PIN_P025_PFC_07_MTIOC8A	P02_5 / MTU3 / MTIOC8A.
IOPORT_PIN_P025_PFC_09_GTIOC02_0A	P02_5 / GPT / GTIOC02_0A.
IOPORT_PIN_P025_PFC_0A_GTADSM06_0	P02_5 / GPT / GTADSM06_0.
IOPORT_PIN_P025_PFC_0D_CMTW0_TIC0	P02_5 / CMTW / CMTW0_TIC0.
IOPORT_PIN_P025_PFC_17_IIC_SCL0	P02_5 / IICn / IIC_SCL0.
IOPORT_PIN_P025_PFC_1D_MCLK00	P02_5 / DSMIFn / MCLK00.
IOPORT_PIN_P025_PFC_25_HDSL02_SMPL	P02_5 / HDSLn / HDSL02_SMPL.
IOPORT_PIN_P025_PFC_26_POUTA	P02_5 / ENCOUT / POUTA.
IOPORT_PIN_P025_PFC_29_SD0_PWEN	P02_5 / SDHI / SD0_PWEN.
IOPORT_PIN_P026_PFC_04_D6	P02_6 / BSC / D6.
IOPORT_PIN_P026_PFC_06_MTIOC3D	P02_6 / MTU3 / MTIOC3D.
IOPORT_PIN_P026_PFC_07_MTIOC8B	P02_6 / MTU3 / MTIOC8B.
IOPORT_PIN_P026_PFC_09_GTIOC02_0B	P02_6 / GPT / GTIOC02_0B.
IOPORT_PIN_P026_PFC_0A_GTADSM06_1	P02_6 / GPT / GTADSM06_1.
IOPORT_PIN_P026_PFC_0D_CMTW0_TOC0	P02_6 / CMTW / CMTW0_TOC0.
IOPORT_PIN_P026_PFC_1D_MDAT00	P02_6 / DSMIFn / MDAT00.
IOPORT_PIN_P026_PFC_25_HDSL02_CLK1	P02_6 / HDSLn / HDSL02_CLK1.
IOPORT_PIN_P026_PFC_26_POUTB	P02_6 / ENCOUT / POUTB.
IOPORT_PIN_P026_PFC_29_SD0_IOVS	P02_6 / SDHI / SD0_IOVS.
IOPORT_PIN_P027_PFC_04_D7	P02_7 / BSC / D7.
IOPORT_PIN_P027_PFC_06_MTIOC4A	P02_7 / MTU3 / MTIOC4A.
IOPORT_PIN_P027_PFC_07_MTIC5U	P02_7 / MTU3 / MTIC5U.
IOPORT_PIN_P027_PFC_09_GTIOC02_1A	P02_7 / GPT / GTIOC02_1A.
IOPORT_PIN_P027_PFC_0A_GTADSM07_0	P02_7 / GPT / GTADSM07_0.
IOPORT_PIN_P027_PFC_0D_CMTW0_TIC1	P02_7 / CMTW / CMTW0_TIC1.
IOPORT_PIN_P027_PFC_1D_MCLK01	P02_7 / DSMIFn / MCLK01.
IOPORT_PIN_P027_PFC_25_HDSL02_SEL1	P02_7 / HDSLn / HDSL02_SEL1.
IOPORT_PIN_P027_PFC_26_POUTZ	P02_7 / ENCOUT / POUTZ.
IOPORT_PIN_P030_PFC_04_D8	P03_0 / BSC / D8.
IOPORT_PIN_P030_PFC_06_MTIOC4C	P03_0 / MTU3 / MTIOC4C.
IOPORT_PIN_P030_PFC_07_MTIC5V	P03_0 / MTU3 / MTIC5V.
IOPORT_PIN_P030_PFC_09_GTIOC02_1B	P03_0 / GPT / GTIOC02_1B.
IOPORT_PIN_P030_PFC_0A_GTADSM07_1	P03_0 / GPT / GTADSM07_1.
IOPORT_PIN_P030_PFC_0D_CMTW0_TOC1	P03_0 / CMTW / CMTW0_TOC1.
IOPORT_PIN_P030_PFC_1D_MDAT01	P03_0 / DSMIFn / MDAT01.
IOPORT_PIN_P030_PFC_25_HDSL02_MISO1	P03_0 / HDSLn / HDSL02_MISO1.
IOPORT_PIN_P031_PFC_04_D9	P03_1 / BSC / D9.
IOPORT_PIN_P031_PFC_06_MTIOC4B	P03_1 / MTU3 / MTIOC4B.
IOPORT_PIN_P031_PFC_07_MTIOC1B	P03_1 / MTU3 / MTIOC1B.
IOPORT_PIN_P031_PFC_09_GTIOC02_2A	P03_1 / GPT / GTIOC02_2A.
IOPORT_PIN_P031_PFC_0A_GTADSM08_0	P03_1 / GPT / GTADSM08_0.
IOPORT_PIN_P031_PFC_0D_CMTW1_TIC0	P03_1 / CMTW / CMTW1_TIC0.
IOPORT_PIN_P031_PFC_15_TXDE02	P03_1 / SCIEn / TXDE02.
IOPORT_PIN_P031_PFC_22_ENCIFDO02	P03_1 / ENCIFn / ENCIFDO02.
IOPORT_PIN_P031_PFC_25_HDSL02_MOSI1	P03_1 / HDSLn / HDSL02_MOSI1.
IOPORT_PIN_P032_PFC_00_IRQ12	P03_2 / IRQ / IRQ12.
IOPORT_PIN_P032_PFC_04_D10	P03_2 / BSC / D10.
IOPORT_PIN_P032_PFC_06_MTIOC4D	P03_2 / MTU3 / MTIOC4D.
IOPORT_PIN_P032_PFC_07_MTIOC1A	P03_2 / MTU3 / MTIOC1A.
IOPORT_PIN_P032_PFC_09_GTIOC02_2B	P03_2 / GPT / GTIOC02_2B.
IOPORT_PIN_P032_PFC_0A_GTADSM08_1	P03_2 / GPT / GTADSM08_1.
IOPORT_PIN_P032_PFC_0D_CMTW1_TOC0	P03_2 / CMTW / CMTW1_TOC0.
IOPORT_PIN_P032_PFC_15_RXDE02	P03_2 / SCIEn / RXDE02.
IOPORT_PIN_P032_PFC_22_ENCIFDI02	P03_2 / ENCIFn / ENCIFDI02.
IOPORT_PIN_P032_PFC_25_HDSL02_CLK2	P03_2 / HDSLn / HDSL02_CLK2.
IOPORT_PIN_P033_PFC_00_IRQ13	P03_3 / IRQ / IRQ13.
IOPORT_PIN_P033_PFC_04_D11	P03_3 / BSC / D11.
IOPORT_PIN_P033_PFC_06_MTCLKA	P03_3 / MTU3 / MTCLKA.
IOPORT_PIN_P033_PFC_07_MTIOC8C	P03_3 / MTU3 / MTIOC8C.
IOPORT_PIN_P033_PFC_09_GTIOC02_3A	P03_3 / GPT / GTIOC02_3A.
IOPORT_PIN_P033_PFC_0A_GTADSM09_0	P03_3 / GPT / GTADSM09_0.
IOPORT_PIN_P033_PFC_0D_CMTW1_TIC1	P03_3 / CMTW / CMTW1_TIC1.
IOPORT_PIN_P033_PFC_15_SCKE02	P03_3 / SCIEn / SCKE02.
IOPORT_PIN_P033_PFC_17_IIC_SCL1	P03_3 / IICn / IIC_SCL1.
IOPORT_PIN_P033_PFC_22_ENCIFCK02	P03_3 / ENCIFn / ENCIFCK02.
IOPORT_PIN_P033_PFC_25_HDSL02_SEL2	P03_3 / HDSLn / HDSL02_SEL2.
IOPORT_PIN_P034_PFC_00_IRQ14	P03_4 / IRQ / IRQ14.
IOPORT_PIN_P034_PFC_04_D12	P03_4 / BSC / D12.
IOPORT_PIN_P034_PFC_06_MTCLKB	P03_4 / MTU3 / MTCLKB.
IOPORT_PIN_P034_PFC_07_MTIOC8D	P03_4 / MTU3 / MTIOC8D.
IOPORT_PIN_P034_PFC_09_GTIOC02_3B	P03_4 / GPT / GTIOC02_3B.
IOPORT_PIN_P034_PFC_0A_GTADSM09_1	P03_4 / GPT / GTADSM09_1.
IOPORT_PIN_P034_PFC_0D_CMTW1_TOC1	P03_4 / CMTW / CMTW1_TOC1.
IOPORT_PIN_P034_PFC_0E_RTCAT1HZ	P03_4 / RTC / RTCAT1HZ.
IOPORT_PIN_P034_PFC_15_DEE02	P03_4 / SCIEn / DEE02.
IOPORT_PIN_P034_PFC_17_IIC_SDA1	P03_4 / IICn / IIC_SDA1.
IOPORT_PIN_P034_PFC_22_ENCIFOE02	P03_4 / ENCIFn / ENCIFOE02.
IOPORT_PIN_P034_PFC_25_HDSL02_MISO2	P03_4 / HDSLn / HDSL02_MISO2.
IOPORT_PIN_P035_PFC_00_IRQ15	P03_5 / IRQ / IRQ15.
IOPORT_PIN_P035_PFC_06_MTIOC3A	P03_5 / MTU3 / MTIOC3A.
IOPORT_PIN_P035_PFC_07_MTIC5W	P03_5 / MTU3 / MTIC5W.
IOPORT_PIN_P035_PFC_09_GTIOC02_4A	P03_5 / GPT / GTIOC02_4A.
IOPORT_PIN_P035_PFC_15_TXDE02	P03_5 / SCIEn / TXDE02.
IOPORT_PIN_P035_PFC_17_IIC_SCL2	P03_5 / IICn / IIC_SCL2.
IOPORT_PIN_P035_PFC_22_ENCIFDO02	P03_5 / ENCIFn / ENCIFDO02.
IOPORT_PIN_P035_PFC_25_HDSL02_MOSI2	P03_5 / HDSLn / HDSL02_MOSI2.
IOPORT_PIN_P036_PFC_06_MTIOC3C	P03_6 / MTU3 / MTIOC3C.
IOPORT_PIN_P036_PFC_07_MTIOC1A	P03_6 / MTU3 / MTIOC1A.
IOPORT_PIN_P036_PFC_09_GTIOC02_4B	P03_6 / GPT / GTIOC02_4B.
IOPORT_PIN_P036_PFC_15_RXDE02	P03_6 / SCIEn / RXDE02.
IOPORT_PIN_P036_PFC_17_IIC_SDA2	P03_6 / IICn / IIC_SDA2.
IOPORT_PIN_P036_PFC_22_ENCIFDI02	P03_6 / ENCIFn / ENCIFDI02.
IOPORT_PIN_P036_PFC_25_HDSL03_LINK	P03_6 / HDSLn / HDSL03_LINK.
IOPORT_PIN_P037_PFC_06_MTIOC6B	P03_7 / MTU3 / MTIOC6B.
IOPORT_PIN_P037_PFC_07_MTIOC1B	P03_7 / MTU3 / MTIOC1B.
IOPORT_PIN_P037_PFC_09_GTIOC03_0A	P03_7 / GPT / GTIOC03_0A.
IOPORT_PIN_P037_PFC_0D_CMTW0_TIC0	P03_7 / CMTW / CMTW0_TIC0.
IOPORT_PIN_P037_PFC_24_DUEI04	P03_7 / ENDATn / DUEI04.
IOPORT_PIN_P037_PFC_25_HDSL03_SMPL	P03_7 / HDSLn / HDSL03_SMPL.
IOPORT_PIN_P040_PFC_06_MTIOC6D	P04_0 / MTU3 / MTIOC6D.
IOPORT_PIN_P040_PFC_09_GTIOC03_0B	P04_0 / GPT / GTIOC03_0B.
IOPORT_PIN_P040_PFC_0D_CMTW0_TOC0	P04_0 / CMTW / CMTW0_TOC0.
IOPORT_PIN_P040_PFC_24_TST_OUT04	P04_0 / ENDATn / TST_OUT04.
IOPORT_PIN_P040_PFC_25_HDSL03_CLK1	P04_0 / HDSLn / HDSL03_CLK1.
IOPORT_PIN_P041_PFC_06_MTIOC7A	P04_1 / MTU3 / MTIOC7A.
IOPORT_PIN_P041_PFC_09_GTIOC03_1A	P04_1 / GPT / GTIOC03_1A.
IOPORT_PIN_P041_PFC_0D_CMTW0_TIC1	P04_1 / CMTW / CMTW0_TIC1.
IOPORT_PIN_P041_PFC_24_SI04	P04_1 / ENDATn / SI04.
IOPORT_PIN_P041_PFC_25_HDSL03_SEL1	P04_1 / HDSLn / HDSL03_SEL1.
IOPORT_PIN_P042_PFC_06_MTIOC7C	P04_2 / MTU3 / MTIOC7C.
IOPORT_PIN_P042_PFC_09_GTIOC03_1B	P04_2 / GPT / GTIOC03_1B.
IOPORT_PIN_P042_PFC_0D_CMTW0_TOC1	P04_2 / CMTW / CMTW0_TOC1.
IOPORT_PIN_P042_PFC_24_DUEI05	P04_2 / ENDATn / DUEI05.
IOPORT_PIN_P042_PFC_25_HDSL03_MISO1	P04_2 / HDSLn / HDSL03_MISO1.
IOPORT_PIN_P043_PFC_06_MTIOC7B	P04_3 / MTU3 / MTIOC7B.
IOPORT_PIN_P043_PFC_09_GTIOC03_2A	P04_3 / GPT / GTIOC03_2A.
IOPORT_PIN_P043_PFC_0D_CMTW1_TIC0	P04_3 / CMTW / CMTW1_TIC0.
IOPORT_PIN_P043_PFC_24_TST_OUT05	P04_3 / ENDATn / TST_OUT05.
IOPORT_PIN_P043_PFC_25_HDSL03_MOSI1	P04_3 / HDSLn / HDSL03_MOSI1.
IOPORT_PIN_P044_PFC_06_MTIOC7D	P04_4 / MTU3 / MTIOC7D.
IOPORT_PIN_P044_PFC_09_GTIOC03_2B	P04_4 / GPT / GTIOC03_2B.
IOPORT_PIN_P044_PFC_0D_CMTW1_TOC0	P04_4 / CMTW / CMTW1_TOC0.
IOPORT_PIN_P044_PFC_1F_ADTRG0	P04_4 / ADCn / ADTRG0.
IOPORT_PIN_P044_PFC_24_SI05	P04_4 / ENDATn / SI05.
IOPORT_PIN_P044_PFC_25_HDSL03_CLK2	P04_4 / HDSLn / HDSL03_CLK2.
IOPORT_PIN_P045_PFC_00_SEI	P04_5 / IRQ / SEI.
IOPORT_PIN_P045_PFC_06_MTCLKC	P04_5 / MTU3 / MTCLKC.
IOPORT_PIN_P045_PFC_07_MTIOC0C	P04_5 / MTU3 / MTIOC0C.
IOPORT_PIN_P045_PFC_09_GTIOC03_3A	P04_5 / GPT / GTIOC03_3A.
IOPORT_PIN_P045_PFC_0D_CMTW1_TIC1	P04_5 / CMTW / CMTW1_TIC1.
IOPORT_PIN_P045_PFC_15_SCKE03	P04_5 / SCIEn / SCKE03.
IOPORT_PIN_P045_PFC_17_IIC_SCL0	P04_5 / IICn / IIC_SCL0.
IOPORT_PIN_P045_PFC_1F_ADTRG1	P04_5 / ADCn / ADTRG1.
IOPORT_PIN_P045_PFC_22_ENCIFCK03	P04_5 / ENCIFn / ENCIFCK03.
IOPORT_PIN_P045_PFC_25_HDSL03_SEL2	P04_5 / HDSLn / HDSL03_SEL2.
IOPORT_PIN_P046_PFC_00_IRQ0	P04_6 / IRQ / IRQ0.
IOPORT_PIN_P046_PFC_06_MTCLKD	P04_6 / MTU3 / MTCLKD.
IOPORT_PIN_P046_PFC_07_MTIOC0D	P04_6 / MTU3 / MTIOC0D.
IOPORT_PIN_P046_PFC_09_GTIOC03_3B	P04_6 / GPT / GTIOC03_3B.
IOPORT_PIN_P046_PFC_0D_CMTW1_TOC1	P04_6 / CMTW / CMTW1_TOC1.
IOPORT_PIN_P046_PFC_15_DEE03	P04_6 / SCIEn / DEE03.
IOPORT_PIN_P046_PFC_17_IIC_SDA0	P04_6 / IICn / IIC_SDA0.
IOPORT_PIN_P046_PFC_1F_ADTRG2	P04_6 / ADCn / ADTRG2.
IOPORT_PIN_P046_PFC_21_MBX_HINT	P04_6 / MBXSEM / MBX_HINT.
IOPORT_PIN_P046_PFC_22_ENCIFOE03	P04_6 / ENCIFn / ENCIFOE03.
IOPORT_PIN_P046_PFC_25_HDSL03_MISO2	P04_6 / HDSLn / HDSL03_MISO2.
IOPORT_PIN_P047_PFC_00_IRQ1	P04_7 / IRQ / IRQ1.
IOPORT_PIN_P047_PFC_06_MTIOC6A	P04_7 / MTU3 / MTIOC6A.
IOPORT_PIN_P047_PFC_07_MTIOC0A	P04_7 / MTU3 / MTIOC0A.
IOPORT_PIN_P047_PFC_09_GTIOC03_4A	P04_7 / GPT / GTIOC03_4A.
IOPORT_PIN_P047_PFC_15_TXDE03	P04_7 / SCIEn / TXDE03.
IOPORT_PIN_P047_PFC_17_IIC_SCL1	P04_7 / IICn / IIC_SCL1.
IOPORT_PIN_P047_PFC_22_ENCIFDO03	P04_7 / ENCIFn / ENCIFDO03.
IOPORT_PIN_P047_PFC_25_HDSL03_MOSI2	P04_7 / HDSLn / HDSL03_MOSI2.
IOPORT_PIN_P050_PFC_00_IRQ2	P05_0 / IRQ / IRQ2.
IOPORT_PIN_P050_PFC_06_MTIOC6C	P05_0 / MTU3 / MTIOC6C.
IOPORT_PIN_P050_PFC_07_MTIOC0B	P05_0 / MTU3 / MTIOC0B.
IOPORT_PIN_P050_PFC_09_GTIOC03_4B	P05_0 / GPT / GTIOC03_4B.
IOPORT_PIN_P050_PFC_15_RXDE03	P05_0 / SCIEn / RXDE03.
IOPORT_PIN_P050_PFC_17_IIC_SDA1	P05_0 / IICn / IIC_SDA1.
IOPORT_PIN_P050_PFC_22_ENCIFDI03	P05_0 / ENCIFn / ENCIFDI03.
IOPORT_PIN_P050_PFC_25_HDSL04_LINK	P05_0 / HDSLn / HDSL04_LINK.
IOPORT_PIN_P051_PFC_00_IRQ3	P05_1 / IRQ / IRQ3.
IOPORT_PIN_P051_PFC_1C_XSPI0_CKP	P05_1 / xSPIn / XSPI0_CKP.
IOPORT_PIN_P051_PFC_24_DUEI06	P05_1 / ENDATn / DUEI06.
IOPORT_PIN_P051_PFC_25_HDSL04_SMPL	P05_1 / HDSLn / HDSL04_SMPL.
IOPORT_PIN_P052_PFC_00_IRQ4	P05_2 / IRQ / IRQ4.
IOPORT_PIN_P052_PFC_17_IIC_SCL2	P05_2 / IICn / IIC_SCL2.
IOPORT_PIN_P052_PFC_1C_XSPI0_CKN	P05_2 / xSPIn / XSPI0_CKN.
IOPORT_PIN_P052_PFC_24_TST_OUT06	P05_2 / ENDATn / TST_OUT06.
IOPORT_PIN_P052_PFC_25_HDSL04_CLK1	P05_2 / HDSLn / HDSL04_CLK1.
IOPORT_PIN_P053_PFC_00_IRQ5	P05_3 / IRQ / IRQ5.
IOPORT_PIN_P053_PFC_1C_XSPI0_CS0	P05_3 / xSPIn / XSPI0_CS0.
IOPORT_PIN_P053_PFC_24_SI06	P05_3 / ENDATn / SI06.
IOPORT_PIN_P053_PFC_25_HDSL04_SEL1	P05_3 / HDSLn / HDSL04_SEL1.
IOPORT_PIN_P054_PFC_00_IRQ6	P05_4 / IRQ / IRQ6.
IOPORT_PIN_P054_PFC_17_IIC_SDA2	P05_4 / IICn / IIC_SDA2.
IOPORT_PIN_P054_PFC_1C_XSPI0_CS1	P05_4 / xSPIn / XSPI0_CS1.
IOPORT_PIN_P054_PFC_24_DUEI07	P05_4 / ENDATn / DUEI07.
IOPORT_PIN_P054_PFC_25_HDSL04_MISO1	P05_4 / HDSLn / HDSL04_MISO1.
IOPORT_PIN_P055_PFC_1C_XSPI0_DS	P05_5 / xSPIn / XSPI0_DS.
IOPORT_PIN_P055_PFC_24_TST_OUT07	P05_5 / ENDATn / TST_OUT07.
IOPORT_PIN_P055_PFC_25_HDSL04_MOSI1	P05_5 / HDSLn / HDSL04_MOSI1.
IOPORT_PIN_P056_PFC_1C_XSPI0_IO0	P05_6 / xSPIn / XSPI0_IO0.
IOPORT_PIN_P056_PFC_24_SI07	P05_6 / ENDATn / SI07.
IOPORT_PIN_P056_PFC_25_HDSL04_CLK2	P05_6 / HDSLn / HDSL04_CLK2.
IOPORT_PIN_P057_PFC_1C_XSPI0_IO1	P05_7 / xSPIn / XSPI0_IO1.
IOPORT_PIN_P057_PFC_24_DUEI08	P05_7 / ENDATn / DUEI08.
IOPORT_PIN_P057_PFC_25_HDSL04_SEL2	P05_7 / HDSLn / HDSL04_SEL2.
IOPORT_PIN_P060_PFC_1C_XSPI0_IO2	P06_0 / xSPIn / XSPI0_IO2.
IOPORT_PIN_P060_PFC_24_TST_OUT08	P06_0 / ENDATn / TST_OUT08.
IOPORT_PIN_P060_PFC_25_HDSL04_MISO2	P06_0 / HDSLn / HDSL04_MISO2.
IOPORT_PIN_P061_PFC_1C_XSPI0_IO3	P06_1 / xSPIn / XSPI0_IO3.
IOPORT_PIN_P061_PFC_24_SI08	P06_1 / ENDATn / SI08.
IOPORT_PIN_P061_PFC_25_HDSL04_MOSI2	P06_1 / HDSLn / HDSL04_MOSI2.
IOPORT_PIN_P062_PFC_00_IRQ8	P06_2 / IRQ / IRQ8.
IOPORT_PIN_P062_PFC_17_IIC_SCL0	P06_2 / IICn / IIC_SCL0.
IOPORT_PIN_P062_PFC_1C_XSPI0_IO4	P06_2 / xSPIn / XSPI0_IO4.
IOPORT_PIN_P062_PFC_24_DUEI09	P06_2 / ENDATn / DUEI09.
IOPORT_PIN_P062_PFC_25_HDSL05_LINK	P06_2 / HDSLn / HDSL05_LINK.
IOPORT_PIN_P063_PFC_00_IRQ9	P06_3 / IRQ / IRQ9.
IOPORT_PIN_P063_PFC_0C_GTETRGA	P06_3 / POEG / GTETRGA.
IOPORT_PIN_P063_PFC_17_IIC_SDA0	P06_3 / IICn / IIC_SDA0.
IOPORT_PIN_P063_PFC_1C_XSPI0_IO5	P06_3 / xSPIn / XSPI0_IO5.
IOPORT_PIN_P063_PFC_24_TST_OUT09	P06_3 / ENDATn / TST_OUT09.
IOPORT_PIN_P063_PFC_25_HDSL05_SMPL	P06_3 / HDSLn / HDSL05_SMPL.
IOPORT_PIN_P064_PFC_00_IRQ10	P06_4 / IRQ / IRQ10.
IOPORT_PIN_P064_PFC_0C_GTETRGB	P06_4 / POEG / GTETRGB.
IOPORT_PIN_P064_PFC_17_IIC_SCL1	P06_4 / IICn / IIC_SCL1.
IOPORT_PIN_P064_PFC_1C_XSPI0_IO6	P06_4 / xSPIn / XSPI0_IO6.
IOPORT_PIN_P064_PFC_24_SI09	P06_4 / ENDATn / SI09.
IOPORT_PIN_P064_PFC_25_HDSL05_CLK1	P06_4 / HDSLn / HDSL05_CLK1.
IOPORT_PIN_P065_PFC_00_IRQ11	P06_5 / IRQ / IRQ11.
IOPORT_PIN_P065_PFC_0C_GTETRGC	P06_5 / POEG / GTETRGC.
IOPORT_PIN_P065_PFC_17_IIC_SDA1	P06_5 / IICn / IIC_SDA1.
IOPORT_PIN_P065_PFC_1C_XSPI0_IO7	P06_5 / xSPIn / XSPI0_IO7.
IOPORT_PIN_P065_PFC_25_HDSL05_SEL1	P06_5 / HDSLn / HDSL05_SEL1.
IOPORT_PIN_P066_PFC_1C_XSPI0_RESET0	P06_6 / xSPIn / XSPI0_RESET0.
IOPORT_PIN_P067_PFC_00_IRQ12	P06_7 / IRQ / IRQ12.
IOPORT_PIN_P067_PFC_08_POE4	P06_7 / POE3 / POE4.
IOPORT_PIN_P067_PFC_0C_GTETRGD	P06_7 / POEG / GTETRGD.
IOPORT_PIN_P067_PFC_10_GMAC1_MDC	P06_7 / ETHER_GMACn / GMAC1_MDC.
IOPORT_PIN_P067_PFC_17_IIC_SCL2	P06_7 / IICn / IIC_SCL2.
IOPORT_PIN_P067_PFC_25_HDSL05_MISO1	P06_7 / HDSLn / HDSL05_MISO1.
IOPORT_PIN_P070_PFC_00_IRQ13	P07_0 / IRQ / IRQ13.
IOPORT_PIN_P070_PFC_10_GMAC1_MDIO	P07_0 / ETHER_GMACn / GMAC1_MDIO.
IOPORT_PIN_P070_PFC_17_IIC_SDA2	P07_0 / IICn / IIC_SDA2.
IOPORT_PIN_P070_PFC_1C_XSPI0_RESET1	P07_0 / xSPIn / XSPI0_RESET1.
IOPORT_PIN_P070_PFC_25_HDSL05_MOSI1	P07_0 / HDSLn / HDSL05_MOSI1.
IOPORT_PIN_P071_PFC_00_IRQ14	P07_1 / IRQ / IRQ14.
IOPORT_PIN_P071_PFC_08_POE8	P07_1 / POE3 / POE8.
IOPORT_PIN_P071_PFC_15_SCKE04	P07_1 / SCIEn / SCKE04.
IOPORT_PIN_P071_PFC_16_SCKE08	P07_1 / SCIEn / SCKE08.
IOPORT_PIN_P071_PFC_17_IIC_SCL0	P07_1 / IICn / IIC_SCL0.
IOPORT_PIN_P071_PFC_1C_XSPI0_RSTO0	P07_1 / xSPIn / XSPI0_RSTO0.
IOPORT_PIN_P071_PFC_1D_MCLK00	P07_1 / DSMIFn / MCLK00.
IOPORT_PIN_P071_PFC_22_ENCIFCK04	P07_1 / ENCIFn / ENCIFCK04.
IOPORT_PIN_P071_PFC_23_ENCIFCK12	P07_1 / ENCIFn / ENCIFCK12.
IOPORT_PIN_P071_PFC_25_HDSL05_CLK2	P07_1 / HDSLn / HDSL05_CLK2.
IOPORT_PIN_P072_PFC_00_IRQ15	P07_2 / IRQ / IRQ15.
IOPORT_PIN_P072_PFC_08_POE10	P07_2 / POE3 / POE10.
IOPORT_PIN_P072_PFC_15_DEE04	P07_2 / SCIEn / DEE04.
IOPORT_PIN_P072_PFC_16_DEE08	P07_2 / SCIEn / DEE08.
IOPORT_PIN_P072_PFC_17_IIC_SDA0	P07_2 / IICn / IIC_SDA0.
IOPORT_PIN_P072_PFC_1C_XSPI0_RSTO1	P07_2 / xSPIn / XSPI0_RSTO1.
IOPORT_PIN_P072_PFC_1D_MDAT00	P07_2 / DSMIFn / MDAT00.
IOPORT_PIN_P072_PFC_22_ENCIFOE04	P07_2 / ENCIFn / ENCIFOE04.
IOPORT_PIN_P072_PFC_23_ENCIFOE12	P07_2 / ENCIFn / ENCIFOE12.
IOPORT_PIN_P072_PFC_25_HDSL05_SEL2	P07_2 / HDSLn / HDSL05_SEL2.
IOPORT_PIN_P073_PFC_08_POE11	P07_3 / POE3 / POE11.
IOPORT_PIN_P073_PFC_15_TXDE04	P07_3 / SCIEn / TXDE04.
IOPORT_PIN_P073_PFC_16_TXDE08	P07_3 / SCIEn / TXDE08.
IOPORT_PIN_P073_PFC_17_IIC_SCL1	P07_3 / IICn / IIC_SCL1.
IOPORT_PIN_P073_PFC_1C_XSPI0_INT0	P07_3 / xSPIn / XSPI0_INT0.
IOPORT_PIN_P073_PFC_1D_MCLK01	P07_3 / DSMIFn / MCLK01.
IOPORT_PIN_P073_PFC_22_ENCIFDO04	P07_3 / ENCIFn / ENCIFDO04.
IOPORT_PIN_P073_PFC_23_ENCIFDO12	P07_3 / ENCIFn / ENCIFDO12.
IOPORT_PIN_P073_PFC_25_HDSL05_MISO2	P07_3 / HDSLn / HDSL05_MISO2.
IOPORT_PIN_P074_PFC_15_RXDE04	P07_4 / SCIEn / RXDE04.
IOPORT_PIN_P074_PFC_16_RXDE08	P07_4 / SCIEn / RXDE08.
IOPORT_PIN_P074_PFC_17_IIC_SDA1	P07_4 / IICn / IIC_SDA1.
IOPORT_PIN_P074_PFC_1C_XSPI0_INT1	P07_4 / xSPIn / XSPI0_INT1.
IOPORT_PIN_P074_PFC_1D_MDAT01	P07_4 / DSMIFn / MDAT01.
IOPORT_PIN_P074_PFC_22_ENCIFDI04	P07_4 / ENCIFn / ENCIFDI04.
IOPORT_PIN_P074_PFC_23_ENCIFDI12	P07_4 / ENCIFn / ENCIFDI12.
IOPORT_PIN_P074_PFC_25_HDSL05_MOSI2	P07_4 / HDSLn / HDSL05_MOSI2.
IOPORT_PIN_P075_PFC_15_SCKE05	P07_5 / SCIEn / SCKE05.
IOPORT_PIN_P075_PFC_17_IIC_SCL2	P07_5 / IICn / IIC_SCL2.
IOPORT_PIN_P075_PFC_1C_XSPI0_ECS0	P07_5 / xSPIn / XSPI0_ECS0.
IOPORT_PIN_P075_PFC_1D_MCLK02	P07_5 / DSMIFn / MCLK02.
IOPORT_PIN_P075_PFC_22_ENCIFCK05	P07_5 / ENCIFn / ENCIFCK05.
IOPORT_PIN_P075_PFC_25_HDSL06_LINK	P07_5 / HDSLn / HDSL06_LINK.
IOPORT_PIN_P076_PFC_15_DEE05	P07_6 / SCIEn / DEE05.
IOPORT_PIN_P076_PFC_17_IIC_SDA2	P07_6 / IICn / IIC_SDA2.
IOPORT_PIN_P076_PFC_1C_XSPI0_ECS1	P07_6 / xSPIn / XSPI0_ECS1.
IOPORT_PIN_P076_PFC_1D_MDAT02	P07_6 / DSMIFn / MDAT02.
IOPORT_PIN_P076_PFC_22_ENCIFOE05	P07_6 / ENCIFn / ENCIFOE05.
IOPORT_PIN_P076_PFC_25_HDSL06_SMPL	P07_6 / HDSLn / HDSL06_SMPL.
IOPORT_PIN_P077_PFC_15_TXDE05	P07_7 / SCIEn / TXDE05.
IOPORT_PIN_P077_PFC_17_IIC_SCL0	P07_7 / IICn / IIC_SCL0.
IOPORT_PIN_P077_PFC_1C_XSPI0_WP0	P07_7 / xSPIn / XSPI0_WP0.
IOPORT_PIN_P077_PFC_1D_MCLK10	P07_7 / DSMIFn / MCLK10.
IOPORT_PIN_P077_PFC_22_ENCIFDO05	P07_7 / ENCIFn / ENCIFDO05.
IOPORT_PIN_P077_PFC_25_HDSL06_CLK1	P07_7 / HDSLn / HDSL06_CLK1.
IOPORT_PIN_P080_PFC_0E_RTCAT1HZ	P08_0 / RTC / RTCAT1HZ.
IOPORT_PIN_P080_PFC_15_RXDE05	P08_0 / SCIEn / RXDE05.
IOPORT_PIN_P080_PFC_17_IIC_SDA0	P08_0 / IICn / IIC_SDA0.
IOPORT_PIN_P080_PFC_1C_XSPI0_WP1	P08_0 / xSPIn / XSPI0_WP1.
IOPORT_PIN_P080_PFC_1D_MDAT10	P08_0 / DSMIFn / MDAT10.
IOPORT_PIN_P080_PFC_21_MBX_HINT	P08_0 / MBXSEM / MBX_HINT.
IOPORT_PIN_P080_PFC_22_ENCIFDI05	P08_0 / ENCIFn / ENCIFDI05.
IOPORT_PIN_P080_PFC_25_HDSL06_SEL1	P08_0 / HDSLn / HDSL06_SEL1.
IOPORT_PIN_P081_PFC_01_TMS	P08_1 / JTAG/SWD / TMS.
IOPORT_PIN_P081_PFC_24_DUEI10	P08_1 / ENDATn / DUEI10.
IOPORT_PIN_P081_PFC_25_HDSL06_MISO1	P08_1 / HDSLn / HDSL06_MISO1.
IOPORT_PIN_P082_PFC_01_TDI	P08_2 / JTAG/SWD / TDI.
IOPORT_PIN_P082_PFC_24_TST_OUT10	P08_2 / ENDATn / TST_OUT10.
IOPORT_PIN_P082_PFC_25_HDSL06_MOSI1	P08_2 / HDSLn / HDSL06_MOSI1.
IOPORT_PIN_P083_PFC_01_TCK	P08_3 / JTAG/SWD / TCK.
IOPORT_PIN_P083_PFC_24_SI10	P08_3 / ENDATn / SI10.
IOPORT_PIN_P083_PFC_25_HDSL06_CLK2	P08_3 / HDSLn / HDSL06_CLK2.
IOPORT_PIN_P084_PFC_01_TDO	P08_4 / JTAG/SWD / TDO.
IOPORT_PIN_P084_PFC_25_HDSL06_SEL2	P08_4 / HDSLn / HDSL06_SEL2.
IOPORT_PIN_P085_PFC_00_IRQ8	P08_5 / IRQ / IRQ8.
IOPORT_PIN_P085_PFC_01_RSTOUT	P08_5 / JTAG/SWD / RSTOUT.
IOPORT_PIN_P085_PFC_0C_GTETRGSA	P08_5 / POEG / GTETRGSA.
IOPORT_PIN_P085_PFC_17_IIC_SCL1	P08_5 / IICn / IIC_SCL1.
IOPORT_PIN_P085_PFC_1D_MCLK02	P08_5 / DSMIFn / MCLK02.
IOPORT_PIN_P085_PFC_25_HDSL06_MISO2	P08_5 / HDSLn / HDSL06_MISO2.
IOPORT_PIN_P085_PFC_29_SD1_PWEN	P08_5 / SDHI / SD1_PWEN.
IOPORT_PIN_P086_PFC_00_SEI	P08_6 / IRQ / SEI.
IOPORT_PIN_P086_PFC_02_CKIO	P08_6 / BSC / CKIO.
IOPORT_PIN_P086_PFC_0B_GTIOC08_3A	P08_6 / GPT / GTIOC08_3A.
IOPORT_PIN_P086_PFC_0C_GTETRGSB	P08_6 / POEG / GTETRGSB.
IOPORT_PIN_P086_PFC_17_IIC_SDA1	P08_6 / IICn / IIC_SDA1.
IOPORT_PIN_P086_PFC_1D_MDAT02	P08_6 / DSMIFn / MDAT02.
IOPORT_PIN_P086_PFC_1E_MCLK11	P08_6 / DSMIFn / MCLK11.
IOPORT_PIN_P086_PFC_24_DUEI11	P08_6 / ENDATn / DUEI11.
IOPORT_PIN_P086_PFC_25_HDSL06_MOSI2	P08_6 / HDSLn / HDSL06_MOSI2.
IOPORT_PIN_P086_PFC_29_SD1_IOVS	P08_6 / SDHI / SD1_IOVS.
IOPORT_PIN_P087_PFC_00_IRQ0	P08_7 / IRQ / IRQ0.
IOPORT_PIN_P087_PFC_04_A0	P08_7 / BSC / A0.
IOPORT_PIN_P087_PFC_0B_GTIOC08_3B	P08_7 / GPT / GTIOC08_3B.
IOPORT_PIN_P087_PFC_17_IIC_SCL2	P08_7 / IICn / IIC_SCL2.
IOPORT_PIN_P087_PFC_18_IIC_SCL1	P08_7 / IICn / IIC_SCL1.
IOPORT_PIN_P087_PFC_1E_MDAT11	P08_7 / DSMIFn / MDAT11.
IOPORT_PIN_P087_PFC_24_TST_OUT11	P08_7 / ENDATn / TST_OUT11.
IOPORT_PIN_P087_PFC_25_HDSL07_LINK	P08_7 / HDSLn / HDSL07_LINK.
IOPORT_PIN_P090_PFC_17_IIC_SDA2	P09_0 / IICn / IIC_SDA2.
IOPORT_PIN_P090_PFC_1D_MCLK12	P09_0 / DSMIFn / MCLK12.
IOPORT_PIN_P090_PFC_24_SI11	P09_0 / ENDATn / SI11.
IOPORT_PIN_P090_PFC_25_HDSL07_SMPL	P09_0 / HDSLn / HDSL07_SMPL.
IOPORT_PIN_P091_PFC_1D_MDAT12	P09_1 / DSMIFn / MDAT12.
IOPORT_PIN_P091_PFC_24_DUEI12	P09_1 / ENDATn / DUEI12.
IOPORT_PIN_P091_PFC_25_HDSL07_CLK1	P09_1 / HDSLn / HDSL07_CLK1.
IOPORT_PIN_P092_PFC_1D_MCLK20	P09_2 / DSMIFn / MCLK20.
IOPORT_PIN_P092_PFC_24_TST_OUT12	P09_2 / ENDATn / TST_OUT12.
IOPORT_PIN_P092_PFC_25_HDSL07_SEL1	P09_2 / HDSLn / HDSL07_SEL1.
IOPORT_PIN_P093_PFC_1D_MDAT20	P09_3 / DSMIFn / MDAT20.
IOPORT_PIN_P093_PFC_24_SI12	P09_3 / ENDATn / SI12.
IOPORT_PIN_P093_PFC_25_HDSL07_MISO1	P09_3 / HDSLn / HDSL07_MISO1.
IOPORT_PIN_P094_PFC_04_D13	P09_4 / BSC / D13.
IOPORT_PIN_P094_PFC_06_MTIOC6B	P09_4 / MTU3 / MTIOC6B.
IOPORT_PIN_P094_PFC_09_GTIOC04_0A	P09_4 / GPT / GTIOC04_0A.
IOPORT_PIN_P094_PFC_0A_GTIOC10_0A	P09_4 / GPT / GTIOC10_0A.
IOPORT_PIN_P094_PFC_1D_MCLK70	P09_4 / DSMIFn / MCLK70.
IOPORT_PIN_P094_PFC_24_DUEI13	P09_4 / ENDATn / DUEI13.
IOPORT_PIN_P094_PFC_25_HDSL07_MOSI1	P09_4 / HDSLn / HDSL07_MOSI1.
IOPORT_PIN_P094_PFC_28_DISP_CLK	P09_4 / LCDC / DISP_CLK.
IOPORT_PIN_P095_PFC_04_D14	P09_5 / BSC / D14.
IOPORT_PIN_P095_PFC_06_MTIOC6D	P09_5 / MTU3 / MTIOC6D.
IOPORT_PIN_P095_PFC_09_GTIOC04_0B	P09_5 / GPT / GTIOC04_0B.
IOPORT_PIN_P095_PFC_0A_GTIOC10_0B	P09_5 / GPT / GTIOC10_0B.
IOPORT_PIN_P095_PFC_1D_MDAT70	P09_5 / DSMIFn / MDAT70.
IOPORT_PIN_P095_PFC_24_TST_OUT13	P09_5 / ENDATn / TST_OUT13.
IOPORT_PIN_P095_PFC_25_HDSL07_CLK2	P09_5 / HDSLn / HDSL07_CLK2.
IOPORT_PIN_P095_PFC_28_DISP_HSYNC	P09_5 / LCDC / DISP_HSYNC.
IOPORT_PIN_P096_PFC_04_D15	P09_6 / BSC / D15.
IOPORT_PIN_P096_PFC_06_MTIOC7A	P09_6 / MTU3 / MTIOC7A.
IOPORT_PIN_P096_PFC_09_GTIOC04_1A	P09_6 / GPT / GTIOC04_1A.
IOPORT_PIN_P096_PFC_0A_GTIOC10_1A	P09_6 / GPT / GTIOC10_1A.
IOPORT_PIN_P096_PFC_1D_MCLK71	P09_6 / DSMIFn / MCLK71.
IOPORT_PIN_P096_PFC_24_SI13	P09_6 / ENDATn / SI13.
IOPORT_PIN_P096_PFC_25_HDSL07_SEL2	P09_6 / HDSLn / HDSL07_SEL2.
IOPORT_PIN_P096_PFC_28_DISP_VSYNC	P09_6 / LCDC / DISP_VSYNC.
IOPORT_PIN_P097_PFC_04_WE0	P09_7 / BSC / WE0.
IOPORT_PIN_P097_PFC_06_MTIOC7C	P09_7 / MTU3 / MTIOC7C.
IOPORT_PIN_P097_PFC_09_GTIOC04_1B	P09_7 / GPT / GTIOC04_1B.
IOPORT_PIN_P097_PFC_0A_GTIOC10_1B	P09_7 / GPT / GTIOC10_1B.
IOPORT_PIN_P097_PFC_1D_MDAT71	P09_7 / DSMIFn / MDAT71.
IOPORT_PIN_P097_PFC_24_DUEI14	P09_7 / ENDATn / DUEI14.
IOPORT_PIN_P097_PFC_25_HDSL07_MISO2	P09_7 / HDSLn / HDSL07_MISO2.
IOPORT_PIN_P097_PFC_28_DISP_DE	P09_7 / LCDC / DISP_DE.
IOPORT_PIN_P100_PFC_00_IRQ4	P10_0 / IRQ / IRQ4.
IOPORT_PIN_P100_PFC_04_WE1	P10_0 / BSC / WE1.
IOPORT_PIN_P100_PFC_06_MTIOC7B	P10_0 / MTU3 / MTIOC7B.
IOPORT_PIN_P100_PFC_09_GTIOC04_2A	P10_0 / GPT / GTIOC04_2A.
IOPORT_PIN_P100_PFC_0A_GTIOC10_2A	P10_0 / GPT / GTIOC10_2A.
IOPORT_PIN_P100_PFC_1D_MCLK72	P10_0 / DSMIFn / MCLK72.
IOPORT_PIN_P100_PFC_24_TST_OUT14	P10_0 / ENDATn / TST_OUT14.
IOPORT_PIN_P100_PFC_25_HDSL07_MOSI2	P10_0 / HDSLn / HDSL07_MOSI2.
IOPORT_PIN_P100_PFC_28_DISP_DATAR0	P10_0 / LCDC / DISP_DATAR0.
IOPORT_PIN_P101_PFC_00_IRQ7	P10_1 / IRQ / IRQ7.
IOPORT_PIN_P101_PFC_04_WAIT	P10_1 / BSC / WAIT.
IOPORT_PIN_P101_PFC_06_MTIOC7D	P10_1 / MTU3 / MTIOC7D.
IOPORT_PIN_P101_PFC_09_GTIOC04_2B	P10_1 / GPT / GTIOC04_2B.
IOPORT_PIN_P101_PFC_0A_GTIOC10_2B	P10_1 / GPT / GTIOC10_2B.
IOPORT_PIN_P101_PFC_14_SCK0	P10_1 / SCIn / SCK0.
IOPORT_PIN_P101_PFC_1D_MDAT72	P10_1 / DSMIFn / MDAT72.
IOPORT_PIN_P101_PFC_24_SI14	P10_1 / ENDATn / SI14.
IOPORT_PIN_P101_PFC_25_HDSL08_LINK	P10_1 / HDSLn / HDSL08_LINK.
IOPORT_PIN_P101_PFC_28_DISP_DATAR1	P10_1 / LCDC / DISP_DATAR1.
IOPORT_PIN_P102_PFC_00_IRQ1	P10_2 / IRQ / IRQ1.
IOPORT_PIN_P102_PFC_04_CS0	P10_2 / BSC / CS0.
IOPORT_PIN_P102_PFC_06_MTCLKC	P10_2 / MTU3 / MTCLKC.
IOPORT_PIN_P102_PFC_07_MTIOC2A	P10_2 / MTU3 / MTIOC2A.
IOPORT_PIN_P102_PFC_09_GTIOC04_3A	P10_2 / GPT / GTIOC04_3A.
IOPORT_PIN_P102_PFC_0A_GTIOC10_3A	P10_2 / GPT / GTIOC10_3A.
IOPORT_PIN_P102_PFC_14_RXD0_SCL0_MISO0	P10_2 / SCIn / RXD0_SCL0_MISO0.
IOPORT_PIN_P102_PFC_15_SCKE04	P10_2 / SCIEn / SCKE04.
IOPORT_PIN_P102_PFC_1D_MCLK10	P10_2 / DSMIFn / MCLK10.
IOPORT_PIN_P102_PFC_1E_MCLK00	P10_2 / DSMIFn / MCLK00.
IOPORT_PIN_P102_PFC_22_ENCIFCK04	P10_2 / ENCIFn / ENCIFCK04.
IOPORT_PIN_P102_PFC_25_HDSL08_SMPL	P10_2 / HDSLn / HDSL08_SMPL.
IOPORT_PIN_P102_PFC_28_DISP_DATAR2	P10_2 / LCDC / DISP_DATAR2.
IOPORT_PIN_P103_PFC_00_IRQ2	P10_3 / IRQ / IRQ2.
IOPORT_PIN_P103_PFC_04_RD	P10_3 / BSC / RD.
IOPORT_PIN_P103_PFC_06_MTCLKD	P10_3 / MTU3 / MTCLKD.
IOPORT_PIN_P103_PFC_07_MTIOC2B	P10_3 / MTU3 / MTIOC2B.
IOPORT_PIN_P103_PFC_09_GTIOC04_3B	P10_3 / GPT / GTIOC04_3B.
IOPORT_PIN_P103_PFC_0A_GTIOC10_3B	P10_3 / GPT / GTIOC10_3B.
IOPORT_PIN_P103_PFC_14_TXD0_SDA0_MOSI0	P10_3 / SCIn / TXD0_SDA0_MOSI0.
IOPORT_PIN_P103_PFC_15_DEE04	P10_3 / SCIEn / DEE04.
IOPORT_PIN_P103_PFC_1D_MDAT10	P10_3 / DSMIFn / MDAT10.
IOPORT_PIN_P103_PFC_1E_MDAT00	P10_3 / DSMIFn / MDAT00.
IOPORT_PIN_P103_PFC_22_ENCIFOE04	P10_3 / ENCIFn / ENCIFOE04.
IOPORT_PIN_P103_PFC_25_HDSL08_CLK1	P10_3 / HDSLn / HDSL08_CLK1.
IOPORT_PIN_P103_PFC_28_DISP_DATAR3	P10_3 / LCDC / DISP_DATAR3.
IOPORT_PIN_P104_PFC_00_IRQ3	P10_4 / IRQ / IRQ3.
IOPORT_PIN_P104_PFC_04_A1	P10_4 / BSC / A1.
IOPORT_PIN_P104_PFC_06_MTIOC1A	P10_4 / MTU3 / MTIOC1A.
IOPORT_PIN_P104_PFC_09_GTIOC04_4A	P10_4 / GPT / GTIOC04_4A.
IOPORT_PIN_P104_PFC_14_SS0_CTS0_RTS0	P10_4 / SCIn / SS0_CTS0_RTS0.
IOPORT_PIN_P104_PFC_15_TXDE04	P10_4 / SCIEn / TXDE04.
IOPORT_PIN_P104_PFC_1D_MCLK11	P10_4 / DSMIFn / MCLK11.
IOPORT_PIN_P104_PFC_1E_MCLK01	P10_4 / DSMIFn / MCLK01.
IOPORT_PIN_P104_PFC_22_ENCIFDO04	P10_4 / ENCIFn / ENCIFDO04.
IOPORT_PIN_P104_PFC_25_HDSL08_SEL1	P10_4 / HDSLn / HDSL08_SEL1.
IOPORT_PIN_P104_PFC_28_DISP_DATAR4	P10_4 / LCDC / DISP_DATAR4.
IOPORT_PIN_P105_PFC_04_A2	P10_5 / BSC / A2.
IOPORT_PIN_P105_PFC_06_MTIOC1B	P10_5 / MTU3 / MTIOC1B.
IOPORT_PIN_P105_PFC_07_MTIOC0A	P10_5 / MTU3 / MTIOC0A.
IOPORT_PIN_P105_PFC_09_GTIOC04_4B	P10_5 / GPT / GTIOC04_4B.
IOPORT_PIN_P105_PFC_14_CTS0	P10_5 / SCIn / CTS0.
IOPORT_PIN_P105_PFC_15_RXDE04	P10_5 / SCIEn / RXDE04.
IOPORT_PIN_P105_PFC_1D_MDAT11	P10_5 / DSMIFn / MDAT11.
IOPORT_PIN_P105_PFC_1E_MDAT01	P10_5 / DSMIFn / MDAT01.
IOPORT_PIN_P105_PFC_22_ENCIFDI04	P10_5 / ENCIFn / ENCIFDI04.
IOPORT_PIN_P105_PFC_25_HDSL08_MISO1	P10_5 / HDSLn / HDSL08_MISO1.
IOPORT_PIN_P105_PFC_28_DISP_DATAR5	P10_5 / LCDC / DISP_DATAR5.
IOPORT_PIN_P106_PFC_00_IRQ0	P10_6 / IRQ / IRQ0.
IOPORT_PIN_P106_PFC_04_A3	P10_6 / BSC / A3.
IOPORT_PIN_P106_PFC_07_MTIOC0B	P10_6 / MTU3 / MTIOC0B.
IOPORT_PIN_P106_PFC_09_GTIOC05_0A	P10_6 / GPT / GTIOC05_0A.
IOPORT_PIN_P106_PFC_14_DE0	P10_6 / SCIn / DE0.
IOPORT_PIN_P106_PFC_1D_MCLK21	P10_6 / DSMIFn / MCLK21.
IOPORT_PIN_P106_PFC_25_HDSL08_MOSI1	P10_6 / HDSLn / HDSL08_MOSI1.
IOPORT_PIN_P106_PFC_26_POUTA	P10_6 / ENCOUT / POUTA.
IOPORT_PIN_P106_PFC_28_DISP_DATAR6	P10_6 / LCDC / DISP_DATAR6.
IOPORT_PIN_P107_PFC_00_IRQ9	P10_7 / IRQ / IRQ9.
IOPORT_PIN_P107_PFC_04_A4	P10_7 / BSC / A4.
IOPORT_PIN_P107_PFC_07_MTIC5U	P10_7 / MTU3 / MTIC5U.
IOPORT_PIN_P107_PFC_09_GTIOC05_0B	P10_7 / GPT / GTIOC05_0B.
IOPORT_PIN_P107_PFC_0B_GTIOC00_3A	P10_7 / GPT / GTIOC00_3A.
IOPORT_PIN_P107_PFC_14_SCK1	P10_7 / SCIn / SCK1.
IOPORT_PIN_P107_PFC_1D_MDAT21	P10_7 / DSMIFn / MDAT21.
IOPORT_PIN_P107_PFC_25_HDSL08_CLK2	P10_7 / HDSLn / HDSL08_CLK2.
IOPORT_PIN_P107_PFC_26_POUTB	P10_7 / ENCOUT / POUTB.
IOPORT_PIN_P107_PFC_28_DISP_DATAR7	P10_7 / LCDC / DISP_DATAR7.
IOPORT_PIN_P110_PFC_00_IRQ13	P11_0 / IRQ / IRQ13.
IOPORT_PIN_P110_PFC_04_A5	P11_0 / BSC / A5.
IOPORT_PIN_P110_PFC_0B_GTIOC00_3B	P11_0 / GPT / GTIOC00_3B.
IOPORT_PIN_P110_PFC_12_ESC_RESETOUT_N	P11_0 / ETHER_ESC / ESC_RESETOUT_N.
IOPORT_PIN_P110_PFC_14_RXD1_SCL1_MISO1	P11_0 / SCIn / RXD1_SCL1_MISO1.
IOPORT_PIN_P110_PFC_1D_MCLK22	P11_0 / DSMIFn / MCLK22.
IOPORT_PIN_P110_PFC_25_HDSL08_SEL2	P11_0 / HDSLn / HDSL08_SEL2.
IOPORT_PIN_P110_PFC_26_POUTZ	P11_0 / ENCOUT / POUTZ.
IOPORT_PIN_P110_PFC_28_DISP_DATAG0	P11_0 / LCDC / DISP_DATAG0.
IOPORT_PIN_P111_PFC_00_IRQ4	P11_1 / IRQ / IRQ4.
IOPORT_PIN_P111_PFC_12_ESC_LEDRUN	P11_1 / ETHER_ESC / ESC_LEDRUN.
IOPORT_PIN_P111_PFC_14_TXD1_SDA1_MOSI1	P11_1 / SCIn / TXD1_SDA1_MOSI1.
IOPORT_PIN_P111_PFC_1D_MDAT22	P11_1 / DSMIFn / MDAT22.
IOPORT_PIN_P111_PFC_24_DUEI15	P11_1 / ENDATn / DUEI15.
IOPORT_PIN_P111_PFC_25_HDSL08_MISO2	P11_1 / HDSLn / HDSL08_MISO2.
IOPORT_PIN_P112_PFC_00_IRQ5	P11_2 / IRQ / IRQ5.
IOPORT_PIN_P112_PFC_14_SS1_CTS1_RTS1	P11_2 / SCIn / SS1_CTS1_RTS1.
IOPORT_PIN_P112_PFC_1D_MCLK30	P11_2 / DSMIFn / MCLK30.
IOPORT_PIN_P112_PFC_24_TST_OUT15	P11_2 / ENDATn / TST_OUT15.
IOPORT_PIN_P112_PFC_25_HDSL08_MOSI2	P11_2 / HDSLn / HDSL08_MOSI2.
IOPORT_PIN_P113_PFC_00_IRQ6	P11_3 / IRQ / IRQ6.
IOPORT_PIN_P113_PFC_14_CTS1	P11_3 / SCIn / CTS1.
IOPORT_PIN_P113_PFC_1D_MDAT30	P11_3 / DSMIFn / MDAT30.
IOPORT_PIN_P113_PFC_24_SI15	P11_3 / ENDATn / SI15.
IOPORT_PIN_P113_PFC_25_HDSL09_LINK	P11_3 / HDSLn / HDSL09_LINK.
IOPORT_PIN_P114_PFC_00_IRQ7	P11_4 / IRQ / IRQ7.
IOPORT_PIN_P114_PFC_14_DE1	P11_4 / SCIn / DE1.
IOPORT_PIN_P114_PFC_1D_MCLK31	P11_4 / DSMIFn / MCLK31.
IOPORT_PIN_P114_PFC_25_HDSL09_SMPL	P11_4 / HDSLn / HDSL09_SMPL.
IOPORT_PIN_P115_PFC_1D_MDAT31	P11_5 / DSMIFn / MDAT31.
IOPORT_PIN_P115_PFC_24_DUEI00	P11_5 / ENDATn / DUEI00.
IOPORT_PIN_P115_PFC_25_HDSL09_CLK1	P11_5 / HDSLn / HDSL09_CLK1.
IOPORT_PIN_P116_PFC_09_GTIOC05_0A	P11_6 / GPT / GTIOC05_0A.
IOPORT_PIN_P116_PFC_24_TST_OUT00	P11_6 / ENDATn / TST_OUT00.
IOPORT_PIN_P116_PFC_25_HDSL09_SEL1	P11_6 / HDSLn / HDSL09_SEL1.
IOPORT_PIN_P117_PFC_09_GTIOC05_0B	P11_7 / GPT / GTIOC05_0B.
IOPORT_PIN_P117_PFC_24_SI00	P11_7 / ENDATn / SI00.
IOPORT_PIN_P117_PFC_25_HDSL09_MISO1	P11_7 / HDSLn / HDSL09_MISO1.
IOPORT_PIN_P120_PFC_04_D16	P12_0 / BSC / D16.
IOPORT_PIN_P120_PFC_07_MTIC5V	P12_0 / MTU3 / MTIC5V.
IOPORT_PIN_P120_PFC_09_GTIOC05_1A	P12_0 / GPT / GTIOC05_1A.
IOPORT_PIN_P120_PFC_0D_CMTW0_TIC0	P12_0 / CMTW / CMTW0_TIC0.
IOPORT_PIN_P120_PFC_19_CANRX1	P12_0 / CANFDn / CANRX1.
IOPORT_PIN_P120_PFC_24_DUEI01	P12_0 / ENDATn / DUEI01.
IOPORT_PIN_P120_PFC_25_HDSL09_MOSI1	P12_0 / HDSLn / HDSL09_MOSI1.
IOPORT_PIN_P120_PFC_29_SD0_CLK	P12_0 / SDHI / SD0_CLK.
IOPORT_PIN_P121_PFC_04_D17	P12_1 / BSC / D17.
IOPORT_PIN_P121_PFC_07_MTIC5W	P12_1 / MTU3 / MTIC5W.
IOPORT_PIN_P121_PFC_09_GTIOC05_1B	P12_1 / GPT / GTIOC05_1B.
IOPORT_PIN_P121_PFC_0D_CMTW0_TOC0	P12_1 / CMTW / CMTW0_TOC0.
IOPORT_PIN_P121_PFC_19_CANTX1	P12_1 / CANFDn / CANTX1.
IOPORT_PIN_P121_PFC_24_TST_OUT01	P12_1 / ENDATn / TST_OUT01.
IOPORT_PIN_P121_PFC_25_HDSL09_CLK2	P12_1 / HDSLn / HDSL09_CLK2.
IOPORT_PIN_P121_PFC_29_SD0_CMD	P12_1 / SDHI / SD0_CMD.
IOPORT_PIN_P122_PFC_04_D18	P12_2 / BSC / D18.
IOPORT_PIN_P122_PFC_09_GTIOC05_2A	P12_2 / GPT / GTIOC05_2A.
IOPORT_PIN_P122_PFC_0D_CMTW0_TIC1	P12_2 / CMTW / CMTW0_TIC1.
IOPORT_PIN_P122_PFC_19_CANRXDP1	P12_2 / CANFDn / CANRXDP1.
IOPORT_PIN_P122_PFC_24_SI01	P12_2 / ENDATn / SI01.
IOPORT_PIN_P122_PFC_25_HDSL09_SEL2	P12_2 / HDSLn / HDSL09_SEL2.
IOPORT_PIN_P122_PFC_29_SD0_DATA0	P12_2 / SDHI / SD0_DATA0.
IOPORT_PIN_P123_PFC_04_D19	P12_3 / BSC / D19.
IOPORT_PIN_P123_PFC_09_GTIOC05_2B	P12_3 / GPT / GTIOC05_2B.
IOPORT_PIN_P123_PFC_0D_CMTW0_TOC1	P12_3 / CMTW / CMTW0_TOC1.
IOPORT_PIN_P123_PFC_14_SCK2	P12_3 / SCIn / SCK2.
IOPORT_PIN_P123_PFC_19_CANTXDP1	P12_3 / CANFDn / CANTXDP1.
IOPORT_PIN_P123_PFC_25_HDSL09_MISO2	P12_3 / HDSLn / HDSL09_MISO2.
IOPORT_PIN_P123_PFC_29_SD0_DATA1	P12_3 / SDHI / SD0_DATA1.
IOPORT_PIN_P124_PFC_00_IRQ1	P12_4 / IRQ / IRQ1.
IOPORT_PIN_P124_PFC_04_D20	P12_4 / BSC / D20.
IOPORT_PIN_P124_PFC_09_GTIOC05_3A	P12_4 / GPT / GTIOC05_3A.
IOPORT_PIN_P124_PFC_0D_CMTW1_TIC0	P12_4 / CMTW / CMTW1_TIC0.
IOPORT_PIN_P124_PFC_14_RXD2_SCL2_MISO2	P12_4 / SCIn / RXD2_SCL2_MISO2.
IOPORT_PIN_P124_PFC_15_SCKE05	P12_4 / SCIEn / SCKE05.
IOPORT_PIN_P124_PFC_1D_MCLK02	P12_4 / DSMIFn / MCLK02.
IOPORT_PIN_P124_PFC_22_ENCIFCK05	P12_4 / ENCIFn / ENCIFCK05.
IOPORT_PIN_P124_PFC_25_HDSL09_MOSI2	P12_4 / HDSLn / HDSL09_MOSI2.
IOPORT_PIN_P124_PFC_29_SD0_DATA2	P12_4 / SDHI / SD0_DATA2.
IOPORT_PIN_P125_PFC_04_D21	P12_5 / BSC / D21.
IOPORT_PIN_P125_PFC_09_GTIOC05_3B	P12_5 / GPT / GTIOC05_3B.
IOPORT_PIN_P125_PFC_0B_GTIOC01_3A	P12_5 / GPT / GTIOC01_3A.
IOPORT_PIN_P125_PFC_0D_CMTW1_TOC0	P12_5 / CMTW / CMTW1_TOC0.
IOPORT_PIN_P125_PFC_14_TXD2_SDA2_MOSI2	P12_5 / SCIn / TXD2_SDA2_MOSI2.
IOPORT_PIN_P125_PFC_15_DEE05	P12_5 / SCIEn / DEE05.
IOPORT_PIN_P125_PFC_1D_MDAT02	P12_5 / DSMIFn / MDAT02.
IOPORT_PIN_P125_PFC_22_ENCIFOE05	P12_5 / ENCIFn / ENCIFOE05.
IOPORT_PIN_P125_PFC_25_HDSL10_LINK	P12_5 / HDSLn / HDSL10_LINK.
IOPORT_PIN_P125_PFC_29_SD0_DATA3	P12_5 / SDHI / SD0_DATA3.
IOPORT_PIN_P126_PFC_04_D22	P12_6 / BSC / D22.
IOPORT_PIN_P126_PFC_09_GTIOC05_4A	P12_6 / GPT / GTIOC05_4A.
IOPORT_PIN_P126_PFC_0B_GTIOC01_3B	P12_6 / GPT / GTIOC01_3B.
IOPORT_PIN_P126_PFC_0D_CMTW1_TIC1	P12_6 / CMTW / CMTW1_TIC1.
IOPORT_PIN_P126_PFC_14_SS2_CTS2_RTS2	P12_6 / SCIn / SS2_CTS2_RTS2.
IOPORT_PIN_P126_PFC_15_TXDE05	P12_6 / SCIEn / TXDE05.
IOPORT_PIN_P126_PFC_1D_MCLK10	P12_6 / DSMIFn / MCLK10.
IOPORT_PIN_P126_PFC_22_ENCIFDO05	P12_6 / ENCIFn / ENCIFDO05.
IOPORT_PIN_P126_PFC_25_HDSL10_SMPL	P12_6 / HDSLn / HDSL10_SMPL.
IOPORT_PIN_P126_PFC_29_SD0_DATA4	P12_6 / SDHI / SD0_DATA4.
IOPORT_PIN_P127_PFC_00_IRQ2	P12_7 / IRQ / IRQ2.
IOPORT_PIN_P127_PFC_04_D23	P12_7 / BSC / D23.
IOPORT_PIN_P127_PFC_09_GTIOC05_4B	P12_7 / GPT / GTIOC05_4B.
IOPORT_PIN_P127_PFC_0D_CMTW1_TOC1	P12_7 / CMTW / CMTW1_TOC1.
IOPORT_PIN_P127_PFC_14_CTS2	P12_7 / SCIn / CTS2.
IOPORT_PIN_P127_PFC_15_RXDE05	P12_7 / SCIEn / RXDE05.
IOPORT_PIN_P127_PFC_1D_MDAT10	P12_7 / DSMIFn / MDAT10.
IOPORT_PIN_P127_PFC_22_ENCIFDI05	P12_7 / ENCIFn / ENCIFDI05.
IOPORT_PIN_P127_PFC_25_HDSL10_CLK1	P12_7 / HDSLn / HDSL10_CLK1.
IOPORT_PIN_P127_PFC_29_SD0_DATA5	P12_7 / SDHI / SD0_DATA5.
IOPORT_PIN_P130_PFC_04_D24	P13_0 / BSC / D24.
IOPORT_PIN_P130_PFC_0B_GTIOC02_3A	P13_0 / GPT / GTIOC02_3A.
IOPORT_PIN_P130_PFC_14_DE2	P13_0 / SCIn / DE2.
IOPORT_PIN_P130_PFC_15_SCKE08	P13_0 / SCIEn / SCKE08.
IOPORT_PIN_P130_PFC_16_SCKE03	P13_0 / SCIEn / SCKE03.
IOPORT_PIN_P130_PFC_1A_SPI_RSPCK3	P13_0 / SPIn / SPI_RSPCK3.
IOPORT_PIN_P130_PFC_1D_MCLK00	P13_0 / DSMIFn / MCLK00.
IOPORT_PIN_P130_PFC_22_ENCIFCK12	P13_0 / ENCIFn / ENCIFCK12.
IOPORT_PIN_P130_PFC_23_ENCIFCK03	P13_0 / ENCIFn / ENCIFCK03.
IOPORT_PIN_P130_PFC_25_HDSL10_SEL1	P13_0 / HDSLn / HDSL10_SEL1.
IOPORT_PIN_P130_PFC_29_SD0_DATA6	P13_0 / SDHI / SD0_DATA6.
IOPORT_PIN_P131_PFC_04_D25	P13_1 / BSC / D25.
IOPORT_PIN_P131_PFC_0B_GTIOC02_3B	P13_1 / GPT / GTIOC02_3B.
IOPORT_PIN_P131_PFC_15_DEE08	P13_1 / SCIEn / DEE08.
IOPORT_PIN_P131_PFC_16_DEE03	P13_1 / SCIEn / DEE03.
IOPORT_PIN_P131_PFC_1A_SPI_MOSI3	P13_1 / SPIn / SPI_MOSI3.
IOPORT_PIN_P131_PFC_1D_MDAT00	P13_1 / DSMIFn / MDAT00.
IOPORT_PIN_P131_PFC_22_ENCIFOE12	P13_1 / ENCIFn / ENCIFOE12.
IOPORT_PIN_P131_PFC_23_ENCIFOE03	P13_1 / ENCIFn / ENCIFOE03.
IOPORT_PIN_P131_PFC_25_HDSL10_MISO1	P13_1 / HDSLn / HDSL10_MISO1.
IOPORT_PIN_P131_PFC_29_SD0_DATA7	P13_1 / SDHI / SD0_DATA7.
IOPORT_PIN_P132_PFC_00_IRQ3	P13_2 / IRQ / IRQ3.
IOPORT_PIN_P132_PFC_04_D26	P13_2 / BSC / D26.
IOPORT_PIN_P132_PFC_15_TXDE08	P13_2 / SCIEn / TXDE08.
IOPORT_PIN_P132_PFC_16_TXDE03	P13_2 / SCIEn / TXDE03.
IOPORT_PIN_P132_PFC_1A_SPI_MISO3	P13_2 / SPIn / SPI_MISO3.
IOPORT_PIN_P132_PFC_1D_MCLK01	P13_2 / DSMIFn / MCLK01.
IOPORT_PIN_P132_PFC_22_ENCIFDO12	P13_2 / ENCIFn / ENCIFDO12.
IOPORT_PIN_P132_PFC_23_ENCIFDO03	P13_2 / ENCIFn / ENCIFDO03.
IOPORT_PIN_P132_PFC_25_HDSL10_MOSI1	P13_2 / HDSLn / HDSL10_MOSI1.
IOPORT_PIN_P132_PFC_29_SD0_RST	P13_2 / SDHI / SD0_RST.
IOPORT_PIN_P133_PFC_04_D27	P13_3 / BSC / D27.
IOPORT_PIN_P133_PFC_0B_GTIOC03_3A	P13_3 / GPT / GTIOC03_3A.
IOPORT_PIN_P133_PFC_14_SCK3	P13_3 / SCIn / SCK3.
IOPORT_PIN_P133_PFC_15_RXDE08	P13_3 / SCIEn / RXDE08.
IOPORT_PIN_P133_PFC_16_RXDE03	P13_3 / SCIEn / RXDE03.
IOPORT_PIN_P133_PFC_1A_SPI_SSL30	P13_3 / SPIn / SPI_SSL30.
IOPORT_PIN_P133_PFC_1D_MDAT01	P13_3 / DSMIFn / MDAT01.
IOPORT_PIN_P133_PFC_22_ENCIFDI12	P13_3 / ENCIFn / ENCIFDI12.
IOPORT_PIN_P133_PFC_23_ENCIFDI03	P13_3 / ENCIFn / ENCIFDI03.
IOPORT_PIN_P133_PFC_25_HDSL10_CLK2	P13_3 / HDSLn / HDSL10_CLK2.
IOPORT_PIN_P134_PFC_04_D28	P13_4 / BSC / D28.
IOPORT_PIN_P134_PFC_0B_GTIOC03_3B	P13_4 / GPT / GTIOC03_3B.
IOPORT_PIN_P134_PFC_14_RXD3_SCL3_MISO3	P13_4 / SCIn / RXD3_SCL3_MISO3.
IOPORT_PIN_P134_PFC_15_SCKE09	P13_4 / SCIEn / SCKE09.
IOPORT_PIN_P134_PFC_1A_SPI_SSL31	P13_4 / SPIn / SPI_SSL31.
IOPORT_PIN_P134_PFC_1D_MCLK40	P13_4 / DSMIFn / MCLK40.
IOPORT_PIN_P134_PFC_22_ENCIFCK13	P13_4 / ENCIFn / ENCIFCK13.
IOPORT_PIN_P134_PFC_25_HDSL10_SEL2	P13_4 / HDSLn / HDSL10_SEL2.
IOPORT_PIN_P135_PFC_00_IRQ4	P13_5 / IRQ / IRQ4.
IOPORT_PIN_P135_PFC_04_D29	P13_5 / BSC / D29.
IOPORT_PIN_P135_PFC_09_GTIOC06_3A	P13_5 / GPT / GTIOC06_3A.
IOPORT_PIN_P135_PFC_14_TXD3_SDA3_MOSI3	P13_5 / SCIn / TXD3_SDA3_MOSI3.
IOPORT_PIN_P135_PFC_15_DEE09	P13_5 / SCIEn / DEE09.
IOPORT_PIN_P135_PFC_1A_SPI_SSL32	P13_5 / SPIn / SPI_SSL32.
IOPORT_PIN_P135_PFC_1D_MDAT40	P13_5 / DSMIFn / MDAT40.
IOPORT_PIN_P135_PFC_22_ENCIFOE13	P13_5 / ENCIFn / ENCIFOE13.
IOPORT_PIN_P135_PFC_25_HDSL10_MISO2	P13_5 / HDSLn / HDSL10_MISO2.
IOPORT_PIN_P136_PFC_04_D30	P13_6 / BSC / D30.
IOPORT_PIN_P136_PFC_09_GTIOC06_3B	P13_6 / GPT / GTIOC06_3B.
IOPORT_PIN_P136_PFC_0B_GTIOC04_3A	P13_6 / GPT / GTIOC04_3A.
IOPORT_PIN_P136_PFC_14_SS3_CTS3_RTS3	P13_6 / SCIn / SS3_CTS3_RTS3.
IOPORT_PIN_P136_PFC_15_TXDE09	P13_6 / SCIEn / TXDE09.
IOPORT_PIN_P136_PFC_1A_SPI_SSL23	P13_6 / SPIn / SPI_SSL23.
IOPORT_PIN_P136_PFC_1D_MCLK41	P13_6 / DSMIFn / MCLK41.
IOPORT_PIN_P136_PFC_22_ENCIFDO13	P13_6 / ENCIFn / ENCIFDO13.
IOPORT_PIN_P136_PFC_25_HDSL10_MOSI2	P13_6 / HDSLn / HDSL10_MOSI2.
IOPORT_PIN_P137_PFC_00_IRQ14	P13_7 / IRQ / IRQ14.
IOPORT_PIN_P137_PFC_04_D31	P13_7 / BSC / D31.
IOPORT_PIN_P137_PFC_09_GTIOC06_4A	P13_7 / GPT / GTIOC06_4A.
IOPORT_PIN_P137_PFC_0B_GTIOC04_3B	P13_7 / GPT / GTIOC04_3B.
IOPORT_PIN_P137_PFC_14_CTS3	P13_7 / SCIn / CTS3.
IOPORT_PIN_P137_PFC_15_RXDE09	P13_7 / SCIEn / RXDE09.
IOPORT_PIN_P137_PFC_1D_MDAT41	P13_7 / DSMIFn / MDAT41.
IOPORT_PIN_P137_PFC_22_ENCIFDI13	P13_7 / ENCIFn / ENCIFDI13.
IOPORT_PIN_P137_PFC_25_HDSL11_LINK	P13_7 / HDSLn / HDSL11_LINK.
IOPORT_PIN_P140_PFC_00_IRQ5	P14_0 / IRQ / IRQ5.
IOPORT_PIN_P140_PFC_04_A0	P14_0 / BSC / A0.
IOPORT_PIN_P140_PFC_09_GTIOC06_4B	P14_0 / GPT / GTIOC06_4B.
IOPORT_PIN_P140_PFC_11_ETHSW_PTPOUT2	P14_0 / ETHER_ETHSW / ETHSW_PTPOUT2.
IOPORT_PIN_P140_PFC_12_ESC_SYNC0	P14_0 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P140_PFC_14_DE3	P14_0 / SCIn / DE3.
IOPORT_PIN_P140_PFC_1D_MCLK42	P14_0 / DSMIFn / MCLK42.
IOPORT_PIN_P140_PFC_25_HDSL11_SMPL	P14_0 / HDSLn / HDSL11_SMPL.
IOPORT_PIN_P141_PFC_04_RD_WR	P14_1 / BSC / RD_WR.
IOPORT_PIN_P141_PFC_09_GTIOC06_0A	P14_1 / GPT / GTIOC06_0A.
IOPORT_PIN_P141_PFC_0A_GTIOC09_0A	P14_1 / GPT / GTIOC09_0A.
IOPORT_PIN_P141_PFC_0B_GTIOC05_3A	P14_1 / GPT / GTIOC05_3A.
IOPORT_PIN_P141_PFC_0E_RTCAT1HZ	P14_1 / RTC / RTCAT1HZ.
IOPORT_PIN_P141_PFC_14_SCK4	P14_1 / SCIn / SCK4.
IOPORT_PIN_P141_PFC_1D_MDAT42	P14_1 / DSMIFn / MDAT42.
IOPORT_PIN_P141_PFC_24_DUEI02	P14_1 / ENDATn / DUEI02.
IOPORT_PIN_P141_PFC_25_HDSL11_CLK1	P14_1 / HDSLn / HDSL11_CLK1.
IOPORT_PIN_P141_PFC_28_DISP_DATAG1	P14_1 / LCDC / DISP_DATAG1.
IOPORT_PIN_P141_PFC_29_SD0_CD	P14_1 / SDHI / SD0_CD.
IOPORT_PIN_P142_PFC_04_BS	P14_2 / BSC / BS.
IOPORT_PIN_P142_PFC_09_GTIOC06_0B	P14_2 / GPT / GTIOC06_0B.
IOPORT_PIN_P142_PFC_0A_GTIOC09_0B	P14_2 / GPT / GTIOC09_0B.
IOPORT_PIN_P142_PFC_0B_GTIOC05_3B	P14_2 / GPT / GTIOC05_3B.
IOPORT_PIN_P142_PFC_14_RXD4_SCL4_MISO4	P14_2 / SCIn / RXD4_SCL4_MISO4.
IOPORT_PIN_P142_PFC_15_SCKE00	P14_2 / SCIEn / SCKE00.
IOPORT_PIN_P142_PFC_22_ENCIFCK00	P14_2 / ENCIFn / ENCIFCK00.
IOPORT_PIN_P142_PFC_25_HDSL11_SEL1	P14_2 / HDSLn / HDSL11_SEL1.
IOPORT_PIN_P142_PFC_28_DISP_DATAG2	P14_2 / LCDC / DISP_DATAG2.
IOPORT_PIN_P142_PFC_29_SD0_WP	P14_2 / SDHI / SD0_WP.
IOPORT_PIN_P143_PFC_00_IRQ6	P14_3 / IRQ / IRQ6.
IOPORT_PIN_P143_PFC_05_DREQ	P14_3 / DMAC / DREQ.
IOPORT_PIN_P143_PFC_08_POE0	P14_3 / POE3 / POE0.
IOPORT_PIN_P143_PFC_09_GTIOC06_1A	P14_3 / GPT / GTIOC06_1A.
IOPORT_PIN_P143_PFC_0A_GTIOC09_1A	P14_3 / GPT / GTIOC09_1A.
IOPORT_PIN_P143_PFC_12_ESC_LINKACT2	P14_3 / ETHER_ESC / ESC_LINKACT2.
IOPORT_PIN_P143_PFC_14_TXD4_SDA4_MOSI4	P14_3 / SCIn / TXD4_SDA4_MOSI4.
IOPORT_PIN_P143_PFC_15_DEE00	P14_3 / SCIEn / DEE00.
IOPORT_PIN_P143_PFC_22_ENCIFOE00	P14_3 / ENCIFn / ENCIFOE00.
IOPORT_PIN_P143_PFC_25_HDSL11_MISO1	P14_3 / HDSLn / HDSL11_MISO1.
IOPORT_PIN_P143_PFC_28_DISP_DATAG3	P14_3 / LCDC / DISP_DATAG3.
IOPORT_PIN_P143_PFC_29_SD1_CD	P14_3 / SDHI / SD1_CD.
IOPORT_PIN_P144_PFC_05_DACK	P14_4 / DMAC / DACK.
IOPORT_PIN_P144_PFC_08_POE4	P14_4 / POE3 / POE4.
IOPORT_PIN_P144_PFC_09_GTIOC06_1B	P14_4 / GPT / GTIOC06_1B.
IOPORT_PIN_P144_PFC_0A_GTIOC09_1B	P14_4 / GPT / GTIOC09_1B.
IOPORT_PIN_P144_PFC_0B_GTIOC06_3A	P14_4 / GPT / GTIOC06_3A.
IOPORT_PIN_P144_PFC_0D_CMTW0_TIC0	P14_4 / CMTW / CMTW0_TIC0.
IOPORT_PIN_P144_PFC_12_ESC_IRQ	P14_4 / ETHER_ESC / ESC_IRQ.
IOPORT_PIN_P144_PFC_14_SS4_CTS4_RTS4	P14_4 / SCIn / SS4_CTS4_RTS4.
IOPORT_PIN_P144_PFC_15_TXDE00	P14_4 / SCIEn / TXDE00.
IOPORT_PIN_P144_PFC_21_MBX_HINT	P14_4 / MBXSEM / MBX_HINT.
IOPORT_PIN_P144_PFC_22_ENCIFDO00	P14_4 / ENCIFn / ENCIFDO00.
IOPORT_PIN_P144_PFC_25_HDSL11_MOSI1	P14_4 / HDSLn / HDSL11_MOSI1.
IOPORT_PIN_P144_PFC_28_DISP_DATAG4	P14_4 / LCDC / DISP_DATAG4.
IOPORT_PIN_P144_PFC_29_SD1_WP	P14_4 / SDHI / SD1_WP.
IOPORT_PIN_P145_PFC_05_TEND	P14_5 / DMAC / TEND.
IOPORT_PIN_P145_PFC_08_POE8	P14_5 / POE3 / POE8.
IOPORT_PIN_P145_PFC_09_GTIOC06_2A	P14_5 / GPT / GTIOC06_2A.
IOPORT_PIN_P145_PFC_0A_GTIOC09_2A	P14_5 / GPT / GTIOC09_2A.
IOPORT_PIN_P145_PFC_0B_GTIOC06_3B	P14_5 / GPT / GTIOC06_3B.
IOPORT_PIN_P145_PFC_0D_CMTW0_TOC0	P14_5 / CMTW / CMTW0_TOC0.
IOPORT_PIN_P145_PFC_12_ESC_RESETOUT_N	P14_5 / ETHER_ESC / ESC_RESETOUT_N.
IOPORT_PIN_P145_PFC_14_CTS4	P14_5 / SCIn / CTS4.
IOPORT_PIN_P145_PFC_15_RXDE00	P14_5 / SCIEn / RXDE00.
IOPORT_PIN_P145_PFC_22_ENCIFDI00	P14_5 / ENCIFn / ENCIFDI00.
IOPORT_PIN_P145_PFC_25_HDSL11_CLK2	P14_5 / HDSLn / HDSL11_CLK2.
IOPORT_PIN_P145_PFC_28_DISP_DATAG5	P14_5 / LCDC / DISP_DATAG5.
IOPORT_PIN_P146_PFC_00_IRQ8	P14_6 / IRQ / IRQ8.
IOPORT_PIN_P146_PFC_08_POE10	P14_6 / POE3 / POE10.
IOPORT_PIN_P146_PFC_09_GTIOC06_2B	P14_6 / GPT / GTIOC06_2B.
IOPORT_PIN_P146_PFC_0A_GTIOC09_2B	P14_6 / GPT / GTIOC09_2B.
IOPORT_PIN_P146_PFC_0D_CMTW0_TIC1	P14_6 / CMTW / CMTW0_TIC1.
IOPORT_PIN_P146_PFC_12_ESC_I2CCLK	P14_6 / ETHER_ESC / ESC_I2CCLK.
IOPORT_PIN_P146_PFC_14_DE4	P14_6 / SCIn / DE4.
IOPORT_PIN_P146_PFC_17_IIC_SCL0	P14_6 / IICn / IIC_SCL0.
IOPORT_PIN_P146_PFC_24_TST_OUT02	P14_6 / ENDATn / TST_OUT02.
IOPORT_PIN_P146_PFC_25_HDSL11_SEL2	P14_6 / HDSLn / HDSL11_SEL2.
IOPORT_PIN_P146_PFC_28_DISP_DATAG6	P14_6 / LCDC / DISP_DATAG6.
IOPORT_PIN_P146_PFC_29_SD0_PWEN	P14_6 / SDHI / SD0_PWEN.
IOPORT_PIN_P147_PFC_00_IRQ9	P14_7 / IRQ / IRQ9.
IOPORT_PIN_P147_PFC_08_POE11	P14_7 / POE3 / POE11.
IOPORT_PIN_P147_PFC_0A_GTIOC09_3A	P14_7 / GPT / GTIOC09_3A.
IOPORT_PIN_P147_PFC_0D_CMTW0_TOC1	P14_7 / CMTW / CMTW0_TOC1.
IOPORT_PIN_P147_PFC_12_ESC_I2CDATA	P14_7 / ETHER_ESC / ESC_I2CDATA.
IOPORT_PIN_P147_PFC_17_IIC_SDA0	P14_7 / IICn / IIC_SDA0.
IOPORT_PIN_P147_PFC_1D_MCLK32	P14_7 / DSMIFn / MCLK32.
IOPORT_PIN_P147_PFC_24_SI02	P14_7 / ENDATn / SI02.
IOPORT_PIN_P147_PFC_25_HDSL11_MISO2	P14_7 / HDSLn / HDSL11_MISO2.
IOPORT_PIN_P147_PFC_29_SD0_IOVS	P14_7 / SDHI / SD0_IOVS.
IOPORT_PIN_P150_PFC_0A_GTIOC09_3B	P15_0 / GPT / GTIOC09_3B.
IOPORT_PIN_P150_PFC_15_SCKE06	P15_0 / SCIEn / SCKE06.
IOPORT_PIN_P150_PFC_1D_MDAT32	P15_0 / DSMIFn / MDAT32.
IOPORT_PIN_P150_PFC_22_ENCIFCK06	P15_0 / ENCIFn / ENCIFCK06.
IOPORT_PIN_P150_PFC_25_HDSL11_MOSI2	P15_0 / HDSLn / HDSL11_MOSI2.
IOPORT_PIN_P151_PFC_0A_GTIOC09_4A	P15_1 / GPT / GTIOC09_4A.
IOPORT_PIN_P151_PFC_15_DEE06	P15_1 / SCIEn / DEE06.
IOPORT_PIN_P151_PFC_1D_MCLK40	P15_1 / DSMIFn / MCLK40.
IOPORT_PIN_P151_PFC_22_ENCIFOE06	P15_1 / ENCIFn / ENCIFOE06.
IOPORT_PIN_P151_PFC_25_HDSL12_LINK	P15_1 / HDSLn / HDSL12_LINK.
IOPORT_PIN_P152_PFC_0A_GTIOC09_4B	P15_2 / GPT / GTIOC09_4B.
IOPORT_PIN_P152_PFC_15_TXDE06	P15_2 / SCIEn / TXDE06.
IOPORT_PIN_P152_PFC_1D_MDAT40	P15_2 / DSMIFn / MDAT40.
IOPORT_PIN_P152_PFC_22_ENCIFDO06	P15_2 / ENCIFn / ENCIFDO06.
IOPORT_PIN_P152_PFC_25_HDSL12_SMPL	P15_2 / HDSLn / HDSL12_SMPL.
IOPORT_PIN_P153_PFC_0A_GTIOC09_5A	P15_3 / GPT / GTIOC09_5A.
IOPORT_PIN_P153_PFC_15_RXDE06	P15_3 / SCIEn / RXDE06.
IOPORT_PIN_P153_PFC_1D_MCLK41	P15_3 / DSMIFn / MCLK41.
IOPORT_PIN_P153_PFC_22_ENCIFDI06	P15_3 / ENCIFn / ENCIFDI06.
IOPORT_PIN_P153_PFC_25_HDSL12_CLK1	P15_3 / HDSLn / HDSL12_CLK1.
IOPORT_PIN_P154_PFC_0A_GTIOC09_5B	P15_4 / GPT / GTIOC09_5B.
IOPORT_PIN_P154_PFC_15_SCKE07	P15_4 / SCIEn / SCKE07.
IOPORT_PIN_P154_PFC_1D_MDAT41	P15_4 / DSMIFn / MDAT41.
IOPORT_PIN_P154_PFC_22_ENCIFCK07	P15_4 / ENCIFn / ENCIFCK07.
IOPORT_PIN_P154_PFC_25_HDSL12_SEL1	P15_4 / HDSLn / HDSL12_SEL1.
IOPORT_PIN_P155_PFC_00_IRQ0	P15_5 / IRQ / IRQ0.
IOPORT_PIN_P155_PFC_0A_GTIOC09_6A	P15_5 / GPT / GTIOC09_6A.
IOPORT_PIN_P155_PFC_15_DEE07	P15_5 / SCIEn / DEE07.
IOPORT_PIN_P155_PFC_1D_MCLK42	P15_5 / DSMIFn / MCLK42.
IOPORT_PIN_P155_PFC_22_ENCIFOE07	P15_5 / ENCIFn / ENCIFOE07.
IOPORT_PIN_P155_PFC_25_HDSL12_MISO1	P15_5 / HDSLn / HDSL12_MISO1.
IOPORT_PIN_P156_PFC_00_IRQ1	P15_6 / IRQ / IRQ1.
IOPORT_PIN_P156_PFC_0A_GTIOC09_6B	P15_6 / GPT / GTIOC09_6B.
IOPORT_PIN_P156_PFC_15_TXDE07	P15_6 / SCIEn / TXDE07.
IOPORT_PIN_P156_PFC_1D_MDAT42	P15_6 / DSMIFn / MDAT42.
IOPORT_PIN_P156_PFC_22_ENCIFDO07	P15_6 / ENCIFn / ENCIFDO07.
IOPORT_PIN_P156_PFC_25_HDSL12_MOSI1	P15_6 / HDSLn / HDSL12_MOSI1.
IOPORT_PIN_P157_PFC_14_SS5_CTS5_RTS5	P15_7 / SCIn / SS5_CTS5_RTS5.
IOPORT_PIN_P157_PFC_15_RXDE07	P15_7 / SCIEn / RXDE07.
IOPORT_PIN_P157_PFC_1D_MCLK50	P15_7 / DSMIFn / MCLK50.
IOPORT_PIN_P157_PFC_22_ENCIFDI07	P15_7 / ENCIFn / ENCIFDI07.
IOPORT_PIN_P157_PFC_25_HDSL12_CLK2	P15_7 / HDSLn / HDSL12_CLK2.
IOPORT_PIN_P160_PFC_00_IRQ2	P16_0 / IRQ / IRQ2.
IOPORT_PIN_P160_PFC_14_CTS5	P16_0 / SCIn / CTS5.
IOPORT_PIN_P160_PFC_15_TXDE07	P16_0 / SCIEn / TXDE07.
IOPORT_PIN_P160_PFC_1D_MDAT50	P16_0 / DSMIFn / MDAT50.
IOPORT_PIN_P160_PFC_24_DUEI03	P16_0 / ENDATn / DUEI03.
IOPORT_PIN_P160_PFC_25_HDSL12_SEL2	P16_0 / HDSLn / HDSL12_SEL2.
IOPORT_PIN_P161_PFC_14_DE5	P16_1 / SCIn / DE5.
IOPORT_PIN_P161_PFC_1D_MCLK51	P16_1 / DSMIFn / MCLK51.
IOPORT_PIN_P161_PFC_24_TST_OUT03	P16_1 / ENDATn / TST_OUT03.
IOPORT_PIN_P161_PFC_25_HDSL12_MISO2	P16_1 / HDSLn / HDSL12_MISO2.
IOPORT_PIN_P162_PFC_14_SCK5	P16_2 / SCIn / SCK5.
IOPORT_PIN_P162_PFC_1D_MDAT51	P16_2 / DSMIFn / MDAT51.
IOPORT_PIN_P162_PFC_24_SI03	P16_2 / ENDATn / SI03.
IOPORT_PIN_P162_PFC_25_HDSL12_MOSI2	P16_2 / HDSLn / HDSL12_MOSI2.
IOPORT_PIN_P163_PFC_00_IRQ10	P16_3 / IRQ / IRQ10.
IOPORT_PIN_P163_PFC_0C_GTETRGSA	P16_3 / POEG / GTETRGSA.
IOPORT_PIN_P163_PFC_12_ESC_LINKACT0	P16_3 / ETHER_ESC / ESC_LINKACT0.
IOPORT_PIN_P163_PFC_14_RXD5_SCL5_MISO5	P16_3 / SCIn / RXD5_SCL5_MISO5.
IOPORT_PIN_P163_PFC_24_DUEI04	P16_3 / ENDATn / DUEI04.
IOPORT_PIN_P163_PFC_25_HDSL13_LINK	P16_3 / HDSLn / HDSL13_LINK.
IOPORT_PIN_P164_PFC_00_IRQ11	P16_4 / IRQ / IRQ11.
IOPORT_PIN_P164_PFC_0C_GTETRGSB	P16_4 / POEG / GTETRGSB.
IOPORT_PIN_P164_PFC_12_ESC_LINKACT1	P16_4 / ETHER_ESC / ESC_LINKACT1.
IOPORT_PIN_P164_PFC_14_TXD5_SDA5_MOSI5	P16_4 / SCIn / TXD5_SDA5_MOSI5.
IOPORT_PIN_P164_PFC_24_TST_OUT04	P16_4 / ENDATn / TST_OUT04.
IOPORT_PIN_P164_PFC_25_HDSL13_SMPL	P16_4 / HDSLn / HDSL13_SMPL.
IOPORT_PIN_P165_PFC_09_GTIOC03_0A	P16_5 / GPT / GTIOC03_0A.
IOPORT_PIN_P165_PFC_24_SI04	P16_5 / ENDATn / SI04.
IOPORT_PIN_P165_PFC_25_HDSL13_CLK1	P16_5 / HDSLn / HDSL13_CLK1.
IOPORT_PIN_P165_PFC_29_SD1_CLK	P16_5 / SDHI / SD1_CLK.
IOPORT_PIN_P166_PFC_09_GTIOC03_0B	P16_6 / GPT / GTIOC03_0B.
IOPORT_PIN_P166_PFC_24_DUEI05	P16_6 / ENDATn / DUEI05.
IOPORT_PIN_P166_PFC_25_HDSL13_SEL1	P16_6 / HDSLn / HDSL13_SEL1.
IOPORT_PIN_P166_PFC_29_SD1_CMD	P16_6 / SDHI / SD1_CMD.
IOPORT_PIN_P167_PFC_09_GTIOC03_1A	P16_7 / GPT / GTIOC03_1A.
IOPORT_PIN_P167_PFC_24_TST_OUT05	P16_7 / ENDATn / TST_OUT05.
IOPORT_PIN_P167_PFC_25_HDSL13_MISO1	P16_7 / HDSLn / HDSL13_MISO1.
IOPORT_PIN_P167_PFC_29_SD1_DATA0	P16_7 / SDHI / SD1_DATA0.
IOPORT_PIN_P170_PFC_00_IRQ12	P17_0 / IRQ / IRQ12.
IOPORT_PIN_P170_PFC_09_GTIOC03_1B	P17_0 / GPT / GTIOC03_1B.
IOPORT_PIN_P170_PFC_24_SI05	P17_0 / ENDATn / SI05.
IOPORT_PIN_P170_PFC_25_HDSL13_MOSI1	P17_0 / HDSLn / HDSL13_MOSI1.
IOPORT_PIN_P170_PFC_29_SD1_DATA1	P17_0 / SDHI / SD1_DATA1.
IOPORT_PIN_P171_PFC_00_IRQ13	P17_1 / IRQ / IRQ13.
IOPORT_PIN_P171_PFC_09_GTIOC03_2A	P17_1 / GPT / GTIOC03_2A.
IOPORT_PIN_P171_PFC_24_DUEI06	P17_1 / ENDATn / DUEI06.
IOPORT_PIN_P171_PFC_25_HDSL13_CLK2	P17_1 / HDSLn / HDSL13_CLK2.
IOPORT_PIN_P171_PFC_29_SD1_DATA2	P17_1 / SDHI / SD1_DATA2.
IOPORT_PIN_P172_PFC_00_IRQ14	P17_2 / IRQ / IRQ14.
IOPORT_PIN_P172_PFC_09_GTIOC03_2B	P17_2 / GPT / GTIOC03_2B.
IOPORT_PIN_P172_PFC_24_TST_OUT06	P17_2 / ENDATn / TST_OUT06.
IOPORT_PIN_P172_PFC_25_HDSL13_SEL2	P17_2 / HDSLn / HDSL13_SEL2.
IOPORT_PIN_P172_PFC_29_SD1_DATA3	P17_2 / SDHI / SD1_DATA3.
IOPORT_PIN_P173_PFC_00_IRQ15	P17_3 / IRQ / IRQ15.
IOPORT_PIN_P173_PFC_0C_GTETRGA	P17_3 / POEG / GTETRGA.
IOPORT_PIN_P173_PFC_24_SI06	P17_3 / ENDATn / SI06.
IOPORT_PIN_P173_PFC_25_HDSL13_MISO2	P17_3 / HDSLn / HDSL13_MISO2.
IOPORT_PIN_P174_PFC_04_A6	P17_4 / BSC / A6.
IOPORT_PIN_P174_PFC_05_DREQ	P17_4 / DMAC / DREQ.
IOPORT_PIN_P174_PFC_0A_GTADSM00_0	P17_4 / GPT / GTADSM00_0.
IOPORT_PIN_P174_PFC_0C_GTETRGB	P17_4 / POEG / GTETRGB.
IOPORT_PIN_P174_PFC_0D_CMTW1_TIC0	P17_4 / CMTW / CMTW1_TIC0.
IOPORT_PIN_P174_PFC_14_DE0	P17_4 / SCIn / DE0.
IOPORT_PIN_P174_PFC_19_CANRX0	P17_4 / CANFDn / CANRX0.
IOPORT_PIN_P174_PFC_24_DUEI07	P17_4 / ENDATn / DUEI07.
IOPORT_PIN_P174_PFC_25_HDSL13_MOSI2	P17_4 / HDSLn / HDSL13_MOSI2.
IOPORT_PIN_P174_PFC_29_SD1_CD	P17_4 / SDHI / SD1_CD.
IOPORT_PIN_P175_PFC_04_A7	P17_5 / BSC / A7.
IOPORT_PIN_P175_PFC_05_DACK	P17_5 / DMAC / DACK.
IOPORT_PIN_P175_PFC_0A_GTADSM00_1	P17_5 / GPT / GTADSM00_1.
IOPORT_PIN_P175_PFC_0C_GTETRGC	P17_5 / POEG / GTETRGC.
IOPORT_PIN_P175_PFC_0D_CMTW1_TOC0	P17_5 / CMTW / CMTW1_TOC0.
IOPORT_PIN_P175_PFC_14_SCK0	P17_5 / SCIn / SCK0.
IOPORT_PIN_P175_PFC_19_CANTX0	P17_5 / CANFDn / CANTX0.
IOPORT_PIN_P175_PFC_24_TST_OUT07	P17_5 / ENDATn / TST_OUT07.
IOPORT_PIN_P175_PFC_25_HDSL14_LINK	P17_5 / HDSLn / HDSL14_LINK.
IOPORT_PIN_P175_PFC_29_SD1_WP	P17_5 / SDHI / SD1_WP.
IOPORT_PIN_P176_PFC_04_WE2	P17_6 / BSC / WE2.
IOPORT_PIN_P176_PFC_0A_GTADSM01_0	P17_6 / GPT / GTADSM01_0.
IOPORT_PIN_P176_PFC_0C_GTETRGD	P17_6 / POEG / GTETRGD.
IOPORT_PIN_P176_PFC_0D_CMTW1_TIC1	P17_6 / CMTW / CMTW1_TIC1.
IOPORT_PIN_P176_PFC_11_ETHSW_PTPOUT0	P17_6 / ETHER_ETHSW / ETHSW_PTPOUT0.
IOPORT_PIN_P176_PFC_12_ESC_SYNC0	P17_6 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P176_PFC_14_RXD0_SCL0_MISO0	P17_6 / SCIn / RXD0_SCL0_MISO0.
IOPORT_PIN_P176_PFC_24_SI07	P17_6 / ENDATn / SI07.
IOPORT_PIN_P176_PFC_25_HDSL14_SMPL	P17_6 / HDSLn / HDSL14_SMPL.
IOPORT_PIN_P176_PFC_28_DISP_DATAG7	P17_6 / LCDC / DISP_DATAG7.
IOPORT_PIN_P176_PFC_29_SD1_PWEN	P17_6 / SDHI / SD1_PWEN.
IOPORT_PIN_P177_PFC_04_WE3_AH	P17_7 / BSC / WE3_AH.
IOPORT_PIN_P177_PFC_0A_GTADSM01_1	P17_7 / GPT / GTADSM01_1.
IOPORT_PIN_P177_PFC_0D_CMTW1_TOC1	P17_7 / CMTW / CMTW1_TOC1.
IOPORT_PIN_P177_PFC_11_ETHSW_PTPOUT1	P17_7 / ETHER_ETHSW / ETHSW_PTPOUT1.
IOPORT_PIN_P177_PFC_12_ESC_SYNC1	P17_7 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P177_PFC_14_TXD0_SDA0_MOSI0	P17_7 / SCIn / TXD0_SDA0_MOSI0.
IOPORT_PIN_P177_PFC_24_DUEI08	P17_7 / ENDATn / DUEI08.
IOPORT_PIN_P177_PFC_25_HDSL14_CLK1	P17_7 / HDSLn / HDSL14_CLK1.
IOPORT_PIN_P177_PFC_28_DISP_DATAB0	P17_7 / LCDC / DISP_DATAB0.
IOPORT_PIN_P177_PFC_29_SD1_IOVS	P17_7 / SDHI / SD1_IOVS.
IOPORT_PIN_P180_PFC_00_IRQ7	P18_0 / IRQ / IRQ7.
IOPORT_PIN_P180_PFC_04_A8	P18_0 / BSC / A8.
IOPORT_PIN_P180_PFC_05_TEND	P18_0 / DMAC / TEND.
IOPORT_PIN_P180_PFC_0A_GTADSM02_0	P18_0 / GPT / GTADSM02_0.
IOPORT_PIN_P180_PFC_12_ESC_LEDRUN	P18_0 / ETHER_ESC / ESC_LEDRUN.
IOPORT_PIN_P180_PFC_14_SS0_CTS0_RTS0	P18_0 / SCIn / SS0_CTS0_RTS0.
IOPORT_PIN_P180_PFC_19_CANRXDP0	P18_0 / CANFDn / CANRXDP0.
IOPORT_PIN_P180_PFC_24_TST_OUT08	P18_0 / ENDATn / TST_OUT08.
IOPORT_PIN_P180_PFC_25_HDSL14_SEL1	P18_0 / HDSLn / HDSL14_SEL1.
IOPORT_PIN_P180_PFC_28_DISP_DATAB1	P18_0 / LCDC / DISP_DATAB1.
IOPORT_PIN_P180_PFC_29_SD1_PWEN	P18_0 / SDHI / SD1_PWEN.
IOPORT_PIN_P181_PFC_00_IRQ15	P18_1 / IRQ / IRQ15.
IOPORT_PIN_P181_PFC_04_A9	P18_1 / BSC / A9.
IOPORT_PIN_P181_PFC_0A_GTADSM02_1	P18_1 / GPT / GTADSM02_1.
IOPORT_PIN_P181_PFC_0B_GTIOC07_3A	P18_1 / GPT / GTIOC07_3A.
IOPORT_PIN_P181_PFC_12_ESC_LEDERR	P18_1 / ETHER_ESC / ESC_LEDERR.
IOPORT_PIN_P181_PFC_14_CTS0	P18_1 / SCIn / CTS0.
IOPORT_PIN_P181_PFC_19_CANTXDP0	P18_1 / CANFDn / CANTXDP0.
IOPORT_PIN_P181_PFC_24_SI08	P18_1 / ENDATn / SI08.
IOPORT_PIN_P181_PFC_25_HDSL14_MISO1	P18_1 / HDSLn / HDSL14_MISO1.
IOPORT_PIN_P181_PFC_28_DISP_DATAB2	P18_1 / LCDC / DISP_DATAB2.
IOPORT_PIN_P181_PFC_29_SD1_IOVS	P18_1 / SDHI / SD1_IOVS.
IOPORT_PIN_P182_PFC_00_SEI	P18_2 / IRQ / SEI.
IOPORT_PIN_P182_PFC_04_A10	P18_2 / BSC / A10.
IOPORT_PIN_P182_PFC_0A_GTADSM03_0	P18_2 / GPT / GTADSM03_0.
IOPORT_PIN_P182_PFC_0B_GTIOC07_3B	P18_2 / GPT / GTIOC07_3B.
IOPORT_PIN_P182_PFC_0F_ETH1_CRS	P18_2 / ETHER_ETHn / ETH1_CRS.
IOPORT_PIN_P182_PFC_10_GMAC1_MDC	P18_2 / ETHER_GMACn / GMAC1_MDC.
IOPORT_PIN_P182_PFC_14_SCK1	P18_2 / SCIn / SCK1.
IOPORT_PIN_P182_PFC_19_CANRX0	P18_2 / CANFDn / CANRX0.
IOPORT_PIN_P182_PFC_1D_MCLK10	P18_2 / DSMIFn / MCLK10.
IOPORT_PIN_P182_PFC_25_HDSL14_MOSI1	P18_2 / HDSLn / HDSL14_MOSI1.
IOPORT_PIN_P182_PFC_28_DISP_DATAB3	P18_2 / LCDC / DISP_DATAB3.
IOPORT_PIN_P182_PFC_29_SD1_PWEN	P18_2 / SDHI / SD1_PWEN.
IOPORT_PIN_P183_PFC_00_IRQ0	P18_3 / IRQ / IRQ0.
IOPORT_PIN_P183_PFC_04_A11	P18_3 / BSC / A11.
IOPORT_PIN_P183_PFC_0A_GTADSM03_1	P18_3 / GPT / GTADSM03_1.
IOPORT_PIN_P183_PFC_0E_RTCAT1HZ	P18_3 / RTC / RTCAT1HZ.
IOPORT_PIN_P183_PFC_0F_ETH1_COL	P18_3 / ETHER_ETHn / ETH1_COL.
IOPORT_PIN_P183_PFC_10_GMAC1_MDIO	P18_3 / ETHER_GMACn / GMAC1_MDIO.
IOPORT_PIN_P183_PFC_14_RXD1_SCL1_MISO1	P18_3 / SCIn / RXD1_SCL1_MISO1.
IOPORT_PIN_P183_PFC_19_CANTX0	P18_3 / CANFDn / CANTX0.
IOPORT_PIN_P183_PFC_1D_MDAT10	P18_3 / DSMIFn / MDAT10.
IOPORT_PIN_P183_PFC_25_HDSL14_CLK2	P18_3 / HDSLn / HDSL14_CLK2.
IOPORT_PIN_P183_PFC_28_DISP_DATAB4	P18_3 / LCDC / DISP_DATAB4.
IOPORT_PIN_P183_PFC_29_SD1_IOVS	P18_3 / SDHI / SD1_IOVS.
IOPORT_PIN_P184_PFC_00_IRQ1	P18_4 / IRQ / IRQ1.
IOPORT_PIN_P184_PFC_04_A12	P18_4 / BSC / A12.
IOPORT_PIN_P184_PFC_09_GTIOC07_3A	P18_4 / GPT / GTIOC07_3A.
IOPORT_PIN_P184_PFC_0A_GTADSM04_0	P18_4 / GPT / GTADSM04_0.
IOPORT_PIN_P184_PFC_12_ESC_LEDSTER	P18_4 / ETHER_ESC / ESC_LEDSTER.
IOPORT_PIN_P184_PFC_14_TXD1_SDA1_MOSI1	P18_4 / SCIn / TXD1_SDA1_MOSI1.
IOPORT_PIN_P184_PFC_15_SCKE09	P18_4 / SCIEn / SCKE09.
IOPORT_PIN_P184_PFC_16_SCKE10	P18_4 / SCIEn / SCKE10.
IOPORT_PIN_P184_PFC_19_CANRX1	P18_4 / CANFDn / CANRX1.
IOPORT_PIN_P184_PFC_1D_MCLK11	P18_4 / DSMIFn / MCLK11.
IOPORT_PIN_P184_PFC_22_ENCIFCK13	P18_4 / ENCIFn / ENCIFCK13.
IOPORT_PIN_P184_PFC_23_ENCIFCK14	P18_4 / ENCIFn / ENCIFCK14.
IOPORT_PIN_P184_PFC_25_HDSL14_SEL2	P18_4 / HDSLn / HDSL14_SEL2.
IOPORT_PIN_P184_PFC_28_DISP_DATAB5	P18_4 / LCDC / DISP_DATAB5.
IOPORT_PIN_P185_PFC_00_IRQ2	P18_5 / IRQ / IRQ2.
IOPORT_PIN_P185_PFC_04_A13	P18_5 / BSC / A13.
IOPORT_PIN_P185_PFC_09_GTIOC07_3B	P18_5 / GPT / GTIOC07_3B.
IOPORT_PIN_P185_PFC_0A_GTADSM04_1	P18_5 / GPT / GTADSM04_1.
IOPORT_PIN_P185_PFC_14_SS1_CTS1_RTS1	P18_5 / SCIn / SS1_CTS1_RTS1.
IOPORT_PIN_P185_PFC_15_DEE09	P18_5 / SCIEn / DEE09.
IOPORT_PIN_P185_PFC_16_DEE10	P18_5 / SCIEn / DEE10.
IOPORT_PIN_P185_PFC_19_CANTX1	P18_5 / CANFDn / CANTX1.
IOPORT_PIN_P185_PFC_1D_MDAT11	P18_5 / DSMIFn / MDAT11.
IOPORT_PIN_P185_PFC_22_ENCIFOE13	P18_5 / ENCIFn / ENCIFOE13.
IOPORT_PIN_P185_PFC_23_ENCIFOE14	P18_5 / ENCIFn / ENCIFOE14.
IOPORT_PIN_P185_PFC_25_HDSL14_MISO2	P18_5 / HDSLn / HDSL14_MISO2.
IOPORT_PIN_P185_PFC_28_DISP_DATAB6	P18_5 / LCDC / DISP_DATAB6.
IOPORT_PIN_P186_PFC_00_IRQ3	P18_6 / IRQ / IRQ3.
IOPORT_PIN_P186_PFC_04_A14	P18_6 / BSC / A14.
IOPORT_PIN_P186_PFC_09_GTIOC07_4A	P18_6 / GPT / GTIOC07_4A.
IOPORT_PIN_P186_PFC_0A_GTADSM05_0	P18_6 / GPT / GTADSM05_0.
IOPORT_PIN_P186_PFC_14_CTS1	P18_6 / SCIn / CTS1.
IOPORT_PIN_P186_PFC_15_TXDE09	P18_6 / SCIEn / TXDE09.
IOPORT_PIN_P186_PFC_16_TXDE10	P18_6 / SCIEn / TXDE10.
IOPORT_PIN_P186_PFC_19_CANRXDP1	P18_6 / CANFDn / CANRXDP1.
IOPORT_PIN_P186_PFC_1D_MCLK12	P18_6 / DSMIFn / MCLK12.
IOPORT_PIN_P186_PFC_22_ENCIFDO13	P18_6 / ENCIFn / ENCIFDO13.
IOPORT_PIN_P186_PFC_23_ENCIFDO14	P18_6 / ENCIFn / ENCIFDO14.
IOPORT_PIN_P186_PFC_25_HDSL14_MOSI2	P18_6 / HDSLn / HDSL14_MOSI2.
IOPORT_PIN_P186_PFC_28_DISP_DATAB7	P18_6 / LCDC / DISP_DATAB7.
IOPORT_PIN_P187_PFC_00_IRQ4	P18_7 / IRQ / IRQ4.
IOPORT_PIN_P187_PFC_04_A15	P18_7 / BSC / A15.
IOPORT_PIN_P187_PFC_09_GTIOC07_4B	P18_7 / GPT / GTIOC07_4B.
IOPORT_PIN_P187_PFC_0A_GTADSM05_1	P18_7 / GPT / GTADSM05_1.
IOPORT_PIN_P187_PFC_11_ETHSW_PTPOUT3	P18_7 / ETHER_ETHSW / ETHSW_PTPOUT3.
IOPORT_PIN_P187_PFC_12_ESC_SYNC1	P18_7 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P187_PFC_14_DE1	P18_7 / SCIn / DE1.
IOPORT_PIN_P187_PFC_15_RXDE09	P18_7 / SCIEn / RXDE09.
IOPORT_PIN_P187_PFC_16_RXDE10	P18_7 / SCIEn / RXDE10.
IOPORT_PIN_P187_PFC_19_CANTXDP1	P18_7 / CANFDn / CANTXDP1.
IOPORT_PIN_P187_PFC_1D_MDAT12	P18_7 / DSMIFn / MDAT12.
IOPORT_PIN_P187_PFC_22_ENCIFDI13	P18_7 / ENCIFn / ENCIFDI13.
IOPORT_PIN_P187_PFC_23_ENCIFDI14	P18_7 / ENCIFn / ENCIFDI14.
IOPORT_PIN_P187_PFC_25_HDSL15_LINK	P18_7 / HDSLn / HDSL15_LINK.
IOPORT_PIN_P190_PFC_09_GTIOC07_0A	P19_0 / GPT / GTIOC07_0A.
IOPORT_PIN_P190_PFC_24_DUEI09	P19_0 / ENDATn / DUEI09.
IOPORT_PIN_P190_PFC_25_HDSL15_SMPL	P19_0 / HDSLn / HDSL15_SMPL.
IOPORT_PIN_P191_PFC_09_GTIOC07_0B	P19_1 / GPT / GTIOC07_0B.
IOPORT_PIN_P191_PFC_24_TST_OUT09	P19_1 / ENDATn / TST_OUT09.
IOPORT_PIN_P191_PFC_25_HDSL15_CLK1	P19_1 / HDSLn / HDSL15_CLK1.
IOPORT_PIN_P192_PFC_09_GTIOC07_1A	P19_2 / GPT / GTIOC07_1A.
IOPORT_PIN_P192_PFC_24_SI09	P19_2 / ENDATn / SI09.
IOPORT_PIN_P192_PFC_25_HDSL15_SEL1	P19_2 / HDSLn / HDSL15_SEL1.
IOPORT_PIN_P193_PFC_09_GTIOC07_1B	P19_3 / GPT / GTIOC07_1B.
IOPORT_PIN_P193_PFC_24_DUEI10	P19_3 / ENDATn / DUEI10.
IOPORT_PIN_P193_PFC_25_HDSL15_MISO1	P19_3 / HDSLn / HDSL15_MISO1.
IOPORT_PIN_P194_PFC_09_GTIOC07_2A	P19_4 / GPT / GTIOC07_2A.
IOPORT_PIN_P194_PFC_24_TST_OUT10	P19_4 / ENDATn / TST_OUT10.
IOPORT_PIN_P194_PFC_25_HDSL15_MOSI1	P19_4 / HDSLn / HDSL15_MOSI1.
IOPORT_PIN_P195_PFC_09_GTIOC07_2B	P19_5 / GPT / GTIOC07_2B.
IOPORT_PIN_P195_PFC_24_SI10	P19_5 / ENDATn / SI10.
IOPORT_PIN_P195_PFC_25_HDSL15_CLK2	P19_5 / HDSLn / HDSL15_CLK2.
IOPORT_PIN_P196_PFC_1D_MCLK52	P19_6 / DSMIFn / MCLK52.
IOPORT_PIN_P196_PFC_25_HDSL15_SEL2	P19_6 / HDSLn / HDSL15_SEL2.
IOPORT_PIN_P197_PFC_1D_MDAT52	P19_7 / DSMIFn / MDAT52.
IOPORT_PIN_P197_PFC_25_HDSL15_MISO2	P19_7 / HDSLn / HDSL15_MISO2.
IOPORT_PIN_P200_PFC_0F_ETH0_TXCLK	P20_0 / ETHER_ETHn / ETH0_TXCLK.
IOPORT_PIN_P200_PFC_25_HDSL15_MOSI2	P20_0 / HDSLn / HDSL15_MOSI2.
IOPORT_PIN_P201_PFC_0F_ETH0_TXD0	P20_1 / ETHER_ETHn / ETH0_TXD0.
IOPORT_PIN_P202_PFC_0F_ETH0_TXD1	P20_2 / ETHER_ETHn / ETH0_TXD1.
IOPORT_PIN_P203_PFC_0F_ETH0_TXD2	P20_3 / ETHER_ETHn / ETH0_TXD2.
IOPORT_PIN_P203_PFC_19_CANRX0	P20_3 / CANFDn / CANRX0.
IOPORT_PIN_P204_PFC_0F_ETH0_TXD3	P20_4 / ETHER_ETHn / ETH0_TXD3.
IOPORT_PIN_P204_PFC_19_CANTX0	P20_4 / CANFDn / CANTX0.
IOPORT_PIN_P205_PFC_0F_ETH0_TXEN	P20_5 / ETHER_ETHn / ETH0_TXEN.
IOPORT_PIN_P205_PFC_24_DUEI11	P20_5 / ENDATn / DUEI11.
IOPORT_PIN_P205_PFC_25_HDSL00_LINK	P20_5 / HDSLn / HDSL00_LINK.
IOPORT_PIN_P206_PFC_0F_ETH0_RXCLK	P20_6 / ETHER_ETHn / ETH0_RXCLK.
IOPORT_PIN_P206_PFC_24_TST_OUT11	P20_6 / ENDATn / TST_OUT11.
IOPORT_PIN_P206_PFC_25_HDSL00_SMPL	P20_6 / HDSLn / HDSL00_SMPL.
IOPORT_PIN_P207_PFC_0F_ETH0_RXD0	P20_7 / ETHER_ETHn / ETH0_RXD0.
IOPORT_PIN_P207_PFC_24_SI11	P20_7 / ENDATn / SI11.
IOPORT_PIN_P207_PFC_25_HDSL00_CLK1	P20_7 / HDSLn / HDSL00_CLK1.
IOPORT_PIN_P210_PFC_0F_ETH0_RXD1	P21_0 / ETHER_ETHn / ETH0_RXD1.
IOPORT_PIN_P210_PFC_24_DUEI12	P21_0 / ENDATn / DUEI12.
IOPORT_PIN_P210_PFC_25_HDSL00_SEL1	P21_0 / HDSLn / HDSL00_SEL1.
IOPORT_PIN_P211_PFC_0F_ETH0_RXD2	P21_1 / ETHER_ETHn / ETH0_RXD2.
IOPORT_PIN_P211_PFC_19_CANRXDP0	P21_1 / CANFDn / CANRXDP0.
IOPORT_PIN_P211_PFC_24_TST_OUT12	P21_1 / ENDATn / TST_OUT12.
IOPORT_PIN_P211_PFC_25_HDSL00_MISO1	P21_1 / HDSLn / HDSL00_MISO1.
IOPORT_PIN_P212_PFC_0F_ETH0_RXD3	P21_2 / ETHER_ETHn / ETH0_RXD3.
IOPORT_PIN_P212_PFC_19_CANTXDP0	P21_2 / CANFDn / CANTXDP0.
IOPORT_PIN_P212_PFC_24_SI12	P21_2 / ENDATn / SI12.
IOPORT_PIN_P212_PFC_25_HDSL00_MOSI1	P21_2 / HDSLn / HDSL00_MOSI1.
IOPORT_PIN_P213_PFC_0F_ETH0_RXDV	P21_3 / ETHER_ETHn / ETH0_RXDV.
IOPORT_PIN_P213_PFC_24_DUEI13	P21_3 / ENDATn / DUEI13.
IOPORT_PIN_P213_PFC_25_HDSL00_CLK2	P21_3 / HDSLn / HDSL00_CLK2.
IOPORT_PIN_P214_PFC_10_GMAC0_MDC	P21_4 / ETHER_GMACn / GMAC0_MDC.
IOPORT_PIN_P214_PFC_11_ETHSW_MDC	P21_4 / ETHER_ETHSW / ETHSW_MDC.
IOPORT_PIN_P214_PFC_12_ESC_MDC	P21_4 / ETHER_ESC / ESC_MDC.
IOPORT_PIN_P214_PFC_19_CANRX1	P21_4 / CANFDn / CANRX1.
IOPORT_PIN_P214_PFC_24_TST_OUT13	P21_4 / ENDATn / TST_OUT13.
IOPORT_PIN_P214_PFC_25_HDSL00_SEL2	P21_4 / HDSLn / HDSL00_SEL2.
IOPORT_PIN_P215_PFC_10_GMAC0_MDIO	P21_5 / ETHER_GMACn / GMAC0_MDIO.
IOPORT_PIN_P215_PFC_11_ETHSW_MDIO	P21_5 / ETHER_ETHSW / ETHSW_MDIO.
IOPORT_PIN_P215_PFC_12_ESC_MDIO	P21_5 / ETHER_ESC / ESC_MDIO.
IOPORT_PIN_P215_PFC_19_CANTX1	P21_5 / CANFDn / CANTX1.
IOPORT_PIN_P215_PFC_24_SI13	P21_5 / ENDATn / SI13.
IOPORT_PIN_P215_PFC_25_HDSL00_MISO2	P21_5 / HDSLn / HDSL00_MISO2.
IOPORT_PIN_P216_PFC_11_ETHSW_PHYLINK0	P21_6 / ETHER_ETHSW / ETHSW_PHYLINK0.
IOPORT_PIN_P216_PFC_12_ESC_PHYLINK0	P21_6 / ETHER_ESC / ESC_PHYLINK0.
IOPORT_PIN_P216_PFC_19_CANRXDP1	P21_6 / CANFDn / CANRXDP1.
IOPORT_PIN_P216_PFC_25_HDSL00_MOSI2	P21_6 / HDSLn / HDSL00_MOSI2.
IOPORT_PIN_P217_PFC_02_ETH0_REFCLK	P21_7 / ETHER_ETHn / ETH0_REFCLK.
IOPORT_PIN_P217_PFC_03_RMII0_REFCLK	P21_7 / ETHER_ETHn / RMII0_REFCLK.
IOPORT_PIN_P217_PFC_19_CANTXDP1	P21_7 / CANFDn / CANTXDP1.
IOPORT_PIN_P217_PFC_25_HDSL01_LINK	P21_7 / HDSLn / HDSL01_LINK.
IOPORT_PIN_P220_PFC_00_IRQ11	P22_0 / IRQ / IRQ11.
IOPORT_PIN_P220_PFC_25_HDSL01_SMPL	P22_0 / HDSLn / HDSL01_SMPL.
IOPORT_PIN_P221_PFC_0C_GTETRGA	P22_1 / POEG / GTETRGA.
IOPORT_PIN_P221_PFC_0F_ETH0_TXER	P22_1 / ETHER_ETHn / ETH0_TXER.
IOPORT_PIN_P221_PFC_14_TXD5_SDA5_MOSI5	P22_1 / SCIn / TXD5_SDA5_MOSI5.
IOPORT_PIN_P221_PFC_19_CANTX0	P22_1 / CANFDn / CANTX0.
IOPORT_PIN_P221_PFC_25_HDSL01_CLK1	P22_1 / HDSLn / HDSL01_CLK1.
IOPORT_PIN_P222_PFC_04_A23	P22_2 / BSC / A23.
IOPORT_PIN_P222_PFC_0C_GTETRGB	P22_2 / POEG / GTETRGB.
IOPORT_PIN_P222_PFC_0F_ETH0_RXER	P22_2 / ETHER_ETHn / ETH0_RXER.
IOPORT_PIN_P222_PFC_14_RXD5_SCL5_MISO5	P22_2 / SCIn / RXD5_SCL5_MISO5.
IOPORT_PIN_P222_PFC_19_CANRX0	P22_2 / CANFDn / CANRX0.
IOPORT_PIN_P222_PFC_25_HDSL01_SEL1	P22_2 / HDSLn / HDSL01_SEL1.
IOPORT_PIN_P223_PFC_00_IRQ5	P22_3 / IRQ / IRQ5.
IOPORT_PIN_P223_PFC_04_A22	P22_3 / BSC / A22.
IOPORT_PIN_P223_PFC_0C_GTETRGC	P22_3 / POEG / GTETRGC.
IOPORT_PIN_P223_PFC_0F_ETH0_CRS	P22_3 / ETHER_ETHn / ETH0_CRS.
IOPORT_PIN_P223_PFC_14_SCK5	P22_3 / SCIn / SCK5.
IOPORT_PIN_P223_PFC_19_CANRXDP0	P22_3 / CANFDn / CANRXDP0.
IOPORT_PIN_P223_PFC_24_DUEI14	P22_3 / ENDATn / DUEI14.
IOPORT_PIN_P223_PFC_25_HDSL01_MISO1	P22_3 / HDSLn / HDSL01_MISO1.
IOPORT_PIN_P224_PFC_00_IRQ6	P22_4 / IRQ / IRQ6.
IOPORT_PIN_P224_PFC_04_A21	P22_4 / BSC / A21.
IOPORT_PIN_P224_PFC_0C_GTETRGD	P22_4 / POEG / GTETRGD.
IOPORT_PIN_P224_PFC_0F_ETH0_COL	P22_4 / ETHER_ETHn / ETH0_COL.
IOPORT_PIN_P224_PFC_14_SS5_CTS5_RTS5	P22_4 / SCIn / SS5_CTS5_RTS5.
IOPORT_PIN_P224_PFC_19_CANTXDP0	P22_4 / CANFDn / CANTXDP0.
IOPORT_PIN_P224_PFC_24_TST_OUT14	P22_4 / ENDATn / TST_OUT14.
IOPORT_PIN_P224_PFC_25_HDSL01_MOSI1	P22_4 / HDSLn / HDSL01_MOSI1.
IOPORT_PIN_P225_PFC_00_IRQ7	P22_5 / IRQ / IRQ7.
IOPORT_PIN_P225_PFC_04_A20	P22_5 / BSC / A20.
IOPORT_PIN_P225_PFC_0C_GTETRGSA	P22_5 / POEG / GTETRGSA.
IOPORT_PIN_P225_PFC_10_GMAC0_PTPTRG0	P22_5 / ETHER_GMACn / GMAC0_PTPTRG0.
IOPORT_PIN_P225_PFC_12_ESC_LATCH0	P22_5 / ETHER_ESC / ESC_LATCH0.
IOPORT_PIN_P225_PFC_14_CTS5	P22_5 / SCIn / CTS5.
IOPORT_PIN_P225_PFC_19_CANRX1	P22_5 / CANFDn / CANRX1.
IOPORT_PIN_P225_PFC_24_SI14	P22_5 / ENDATn / SI14.
IOPORT_PIN_P225_PFC_25_HDSL01_CLK2	P22_5 / HDSLn / HDSL01_CLK2.
IOPORT_PIN_P225_PFC_29_SD0_CD	P22_5 / SDHI / SD0_CD.
IOPORT_PIN_P226_PFC_00_IRQ8	P22_6 / IRQ / IRQ8.
IOPORT_PIN_P226_PFC_04_A19	P22_6 / BSC / A19.
IOPORT_PIN_P226_PFC_0C_GTETRGSB	P22_6 / POEG / GTETRGSB.
IOPORT_PIN_P226_PFC_10_GMAC0_PTPTRG1	P22_6 / ETHER_GMACn / GMAC0_PTPTRG1.
IOPORT_PIN_P226_PFC_12_ESC_LATCH1	P22_6 / ETHER_ESC / ESC_LATCH1.
IOPORT_PIN_P226_PFC_14_DE5	P22_6 / SCIn / DE5.
IOPORT_PIN_P226_PFC_19_CANTX1	P22_6 / CANFDn / CANTX1.
IOPORT_PIN_P226_PFC_24_DUEI15	P22_6 / ENDATn / DUEI15.
IOPORT_PIN_P226_PFC_25_HDSL01_SEL2	P22_6 / HDSLn / HDSL01_SEL2.
IOPORT_PIN_P226_PFC_29_SD0_WP	P22_6 / SDHI / SD0_WP.
IOPORT_PIN_P227_PFC_00_IRQ9	P22_7 / IRQ / IRQ9.
IOPORT_PIN_P227_PFC_04_A18	P22_7 / BSC / A18.
IOPORT_PIN_P227_PFC_09_GTIOC06_0A	P22_7 / GPT / GTIOC06_0A.
IOPORT_PIN_P227_PFC_0F_ETH1_CRS	P22_7 / ETHER_ETHn / ETH1_CRS.
IOPORT_PIN_P227_PFC_11_ETHSW_TDMAOUT2	P22_7 / ETHER_ETHSW / ETHSW_TDMAOUT2.
IOPORT_PIN_P227_PFC_12_ESC_LINKACT0	P22_7 / ETHER_ESC / ESC_LINKACT0.
IOPORT_PIN_P227_PFC_19_CANRXDP1	P22_7 / CANFDn / CANRXDP1.
IOPORT_PIN_P227_PFC_24_TST_OUT15	P22_7 / ENDATn / TST_OUT15.
IOPORT_PIN_P227_PFC_25_HDSL01_MISO2	P22_7 / HDSLn / HDSL01_MISO2.
IOPORT_PIN_P230_PFC_00_IRQ10	P23_0 / IRQ / IRQ10.
IOPORT_PIN_P230_PFC_04_A17	P23_0 / BSC / A17.
IOPORT_PIN_P230_PFC_09_GTIOC06_0B	P23_0 / GPT / GTIOC06_0B.
IOPORT_PIN_P230_PFC_0F_ETH1_COL	P23_0 / ETHER_ETHn / ETH1_COL.
IOPORT_PIN_P230_PFC_11_ETHSW_TDMAOUT3	P23_0 / ETHER_ETHSW / ETHSW_TDMAOUT3.
IOPORT_PIN_P230_PFC_12_ESC_LINKACT1	P23_0 / ETHER_ESC / ESC_LINKACT1.
IOPORT_PIN_P230_PFC_19_CANTXDP1	P23_0 / CANFDn / CANTXDP1.
IOPORT_PIN_P230_PFC_24_SI15	P23_0 / ENDATn / SI15.
IOPORT_PIN_P230_PFC_25_HDSL01_MOSI2	P23_0 / HDSLn / HDSL01_MOSI2.
IOPORT_PIN_P231_PFC_09_GTIOC06_1A	P23_1 / GPT / GTIOC06_1A.
IOPORT_PIN_P231_PFC_12_ESC_IRQ	P23_1 / ETHER_ESC / ESC_IRQ.
IOPORT_PIN_P231_PFC_24_DUEI00	P23_1 / ENDATn / DUEI00.
IOPORT_PIN_P231_PFC_25_HDSL02_LINK	P23_1 / HDSLn / HDSL02_LINK.
IOPORT_PIN_P232_PFC_09_GTIOC06_1B	P23_2 / GPT / GTIOC06_1B.
IOPORT_PIN_P232_PFC_12_ESC_RESETOUT_N	P23_2 / ETHER_ESC / ESC_RESETOUT_N.
IOPORT_PIN_P232_PFC_24_TST_OUT00	P23_2 / ENDATn / TST_OUT00.
IOPORT_PIN_P232_PFC_25_HDSL02_SMPL	P23_2 / HDSLn / HDSL02_SMPL.
IOPORT_PIN_P233_PFC_09_GTIOC06_2A	P23_3 / GPT / GTIOC06_2A.
IOPORT_PIN_P233_PFC_12_ESC_I2CCLK	P23_3 / ETHER_ESC / ESC_I2CCLK.
IOPORT_PIN_P233_PFC_17_IIC_SCL0	P23_3 / IICn / IIC_SCL0.
IOPORT_PIN_P233_PFC_24_SI00	P23_3 / ENDATn / SI00.
IOPORT_PIN_P233_PFC_25_HDSL02_CLK1	P23_3 / HDSLn / HDSL02_CLK1.
IOPORT_PIN_P234_PFC_09_GTIOC06_2B	P23_4 / GPT / GTIOC06_2B.
IOPORT_PIN_P234_PFC_12_ESC_I2CDATA	P23_4 / ETHER_ESC / ESC_I2CDATA.
IOPORT_PIN_P234_PFC_17_IIC_SDA0	P23_4 / IICn / IIC_SDA0.
IOPORT_PIN_P234_PFC_24_DUEI01	P23_4 / ENDATn / DUEI01.
IOPORT_PIN_P234_PFC_25_HDSL02_SEL1	P23_4 / HDSLn / HDSL02_SEL1.
IOPORT_PIN_P235_PFC_12_ESC_LINKACT2	P23_5 / ETHER_ESC / ESC_LINKACT2.
IOPORT_PIN_P235_PFC_1D_MCLK60	P23_5 / DSMIFn / MCLK60.
IOPORT_PIN_P235_PFC_24_TST_OUT01	P23_5 / ENDATn / TST_OUT01.
IOPORT_PIN_P235_PFC_25_HDSL02_MISO1	P23_5 / HDSLn / HDSL02_MISO1.
IOPORT_PIN_P236_PFC_11_ETHSW_LPI0	P23_6 / ETHER_ETHSW / ETHSW_LPI0.
IOPORT_PIN_P236_PFC_1D_MDAT60	P23_6 / DSMIFn / MDAT60.
IOPORT_PIN_P236_PFC_24_SI01	P23_6 / ENDATn / SI01.
IOPORT_PIN_P236_PFC_25_HDSL02_MOSI1	P23_6 / HDSLn / HDSL02_MOSI1.
IOPORT_PIN_P237_PFC_11_ETHSW_LPI1	P23_7 / ETHER_ETHSW / ETHSW_LPI1.
IOPORT_PIN_P237_PFC_1D_MCLK61	P23_7 / DSMIFn / MCLK61.
IOPORT_PIN_P237_PFC_24_DUEI02	P23_7 / ENDATn / DUEI02.
IOPORT_PIN_P237_PFC_25_HDSL02_CLK2	P23_7 / HDSLn / HDSL02_CLK2.
IOPORT_PIN_P240_PFC_00_IRQ11	P24_0 / IRQ / IRQ11.
IOPORT_PIN_P240_PFC_11_ETHSW_LPI2	P24_0 / ETHER_ETHSW / ETHSW_LPI2.
IOPORT_PIN_P240_PFC_1D_MDAT61	P24_0 / DSMIFn / MDAT61.
IOPORT_PIN_P240_PFC_24_TST_OUT02	P24_0 / ENDATn / TST_OUT02.
IOPORT_PIN_P240_PFC_25_HDSL02_SEL2	P24_0 / HDSLn / HDSL02_SEL2.
IOPORT_PIN_P241_PFC_00_IRQ12	P24_1 / IRQ / IRQ12.
IOPORT_PIN_P241_PFC_1D_MCLK62	P24_1 / DSMIFn / MCLK62.
IOPORT_PIN_P241_PFC_24_SI02	P24_1 / ENDATn / SI02.
IOPORT_PIN_P241_PFC_25_HDSL02_MISO2	P24_1 / HDSLn / HDSL02_MISO2.
IOPORT_PIN_P242_PFC_00_IRQ13	P24_2 / IRQ / IRQ13.
IOPORT_PIN_P242_PFC_1D_MDAT62	P24_2 / DSMIFn / MDAT62.
IOPORT_PIN_P242_PFC_25_HDSL02_MOSI2	P24_2 / HDSLn / HDSL02_MOSI2.
IOPORT_PIN_P243_PFC_00_IRQ14	P24_3 / IRQ / IRQ14.
IOPORT_PIN_P243_PFC_12_ESC_I2CCLK	P24_3 / ETHER_ESC / ESC_I2CCLK.
IOPORT_PIN_P243_PFC_17_IIC_SCL1	P24_3 / IICn / IIC_SCL1.
IOPORT_PIN_P243_PFC_19_CANRX0	P24_3 / CANFDn / CANRX0.
IOPORT_PIN_P243_PFC_1D_MCLK70	P24_3 / DSMIFn / MCLK70.
IOPORT_PIN_P243_PFC_25_HDSL03_LINK	P24_3 / HDSLn / HDSL03_LINK.
IOPORT_PIN_P244_PFC_00_IRQ15	P24_4 / IRQ / IRQ15.
IOPORT_PIN_P244_PFC_12_ESC_I2CDATA	P24_4 / ETHER_ESC / ESC_I2CDATA.
IOPORT_PIN_P244_PFC_17_IIC_SDA1	P24_4 / IICn / IIC_SDA1.
IOPORT_PIN_P244_PFC_19_CANTX0	P24_4 / CANFDn / CANTX0.
IOPORT_PIN_P244_PFC_1D_MDAT70	P24_4 / DSMIFn / MDAT70.
IOPORT_PIN_P244_PFC_25_HDSL03_SMPL	P24_4 / HDSLn / HDSL03_SMPL.
IOPORT_PIN_P245_PFC_0F_ETH1_TXCLK	P24_5 / ETHER_ETHn / ETH1_TXCLK.
IOPORT_PIN_P245_PFC_25_HDSL03_CLK1	P24_5 / HDSLn / HDSL03_CLK1.
IOPORT_PIN_P246_PFC_0F_ETH1_TXD0	P24_6 / ETHER_ETHn / ETH1_TXD0.
IOPORT_PIN_P247_PFC_0F_ETH1_TXD1	P24_7 / ETHER_ETHn / ETH1_TXD1.
IOPORT_PIN_P250_PFC_0F_ETH1_TXD2	P25_0 / ETHER_ETHn / ETH1_TXD2.
IOPORT_PIN_P250_PFC_19_CANRXDP0	P25_0 / CANFDn / CANRXDP0.
IOPORT_PIN_P251_PFC_0F_ETH1_TXD3	P25_1 / ETHER_ETHn / ETH1_TXD3.
IOPORT_PIN_P251_PFC_19_CANTXDP0	P25_1 / CANFDn / CANTXDP0.
IOPORT_PIN_P252_PFC_0F_ETH1_TXEN	P25_2 / ETHER_ETHn / ETH1_TXEN.
IOPORT_PIN_P253_PFC_0F_ETH1_RXCLK	P25_3 / ETHER_ETHn / ETH1_RXCLK.
IOPORT_PIN_P253_PFC_24_DUEI03	P25_3 / ENDATn / DUEI03.
IOPORT_PIN_P253_PFC_25_HDSL03_SEL1	P25_3 / HDSLn / HDSL03_SEL1.
IOPORT_PIN_P254_PFC_0F_ETH1_RXD0	P25_4 / ETHER_ETHn / ETH1_RXD0.
IOPORT_PIN_P254_PFC_24_TST_OUT03	P25_4 / ENDATn / TST_OUT03.
IOPORT_PIN_P254_PFC_25_HDSL03_MISO1	P25_4 / HDSLn / HDSL03_MISO1.
IOPORT_PIN_P255_PFC_0F_ETH1_RXD1	P25_5 / ETHER_ETHn / ETH1_RXD1.
IOPORT_PIN_P255_PFC_24_SI03	P25_5 / ENDATn / SI03.
IOPORT_PIN_P255_PFC_25_HDSL03_MOSI1	P25_5 / HDSLn / HDSL03_MOSI1.
IOPORT_PIN_P256_PFC_0F_ETH1_RXD2	P25_6 / ETHER_ETHn / ETH1_RXD2.
IOPORT_PIN_P256_PFC_19_CANRX1	P25_6 / CANFDn / CANRX1.
IOPORT_PIN_P256_PFC_24_DUEI04	P25_6 / ENDATn / DUEI04.
IOPORT_PIN_P256_PFC_25_HDSL03_CLK2	P25_6 / HDSLn / HDSL03_CLK2.
IOPORT_PIN_P257_PFC_0F_ETH1_RXD3	P25_7 / ETHER_ETHn / ETH1_RXD3.
IOPORT_PIN_P257_PFC_19_CANTX1	P25_7 / CANFDn / CANTX1.
IOPORT_PIN_P257_PFC_24_TST_OUT04	P25_7 / ENDATn / TST_OUT04.
IOPORT_PIN_P257_PFC_25_HDSL03_SEL2	P25_7 / HDSLn / HDSL03_SEL2.
IOPORT_PIN_P260_PFC_0F_ETH1_RXDV	P26_0 / ETHER_ETHn / ETH1_RXDV.
IOPORT_PIN_P260_PFC_24_SI04	P26_0 / ENDATn / SI04.
IOPORT_PIN_P260_PFC_25_HDSL03_MISO2	P26_0 / HDSLn / HDSL03_MISO2.
IOPORT_PIN_P261_PFC_10_GMAC1_MDC	P26_1 / ETHER_GMACn / GMAC1_MDC.
IOPORT_PIN_P261_PFC_11_ETHSW_MDC	P26_1 / ETHER_ETHSW / ETHSW_MDC.
IOPORT_PIN_P261_PFC_12_ESC_MDC	P26_1 / ETHER_ESC / ESC_MDC.
IOPORT_PIN_P261_PFC_19_CANRXDP1	P26_1 / CANFDn / CANRXDP1.
IOPORT_PIN_P261_PFC_25_HDSL03_MOSI2	P26_1 / HDSLn / HDSL03_MOSI2.
IOPORT_PIN_P262_PFC_10_GMAC1_MDIO	P26_2 / ETHER_GMACn / GMAC1_MDIO.
IOPORT_PIN_P262_PFC_11_ETHSW_MDIO	P26_2 / ETHER_ETHSW / ETHSW_MDIO.
IOPORT_PIN_P262_PFC_12_ESC_MDIO	P26_2 / ETHER_ESC / ESC_MDIO.
IOPORT_PIN_P262_PFC_19_CANTXDP1	P26_2 / CANFDn / CANTXDP1.
IOPORT_PIN_P262_PFC_25_HDSL04_LINK	P26_2 / HDSLn / HDSL04_LINK.
IOPORT_PIN_P263_PFC_11_ETHSW_PHYLINK1	P26_3 / ETHER_ETHSW / ETHSW_PHYLINK1.
IOPORT_PIN_P263_PFC_12_ESC_PHYLINK1	P26_3 / ETHER_ESC / ESC_PHYLINK1.
IOPORT_PIN_P263_PFC_25_HDSL04_SMPL	P26_3 / HDSLn / HDSL04_SMPL.
IOPORT_PIN_P264_PFC_02_ETH1_REFCLK	P26_4 / ETHER_ETHn / ETH1_REFCLK.
IOPORT_PIN_P264_PFC_03_RMII1_REFCLK	P26_4 / ETHER_ETHn / RMII1_REFCLK.
IOPORT_PIN_P265_PFC_00_IRQ12	P26_5 / IRQ / IRQ12.
IOPORT_PIN_P265_PFC_15_SCKE01	P26_5 / SCIEn / SCKE01.
IOPORT_PIN_P265_PFC_19_CANTX0	P26_5 / CANFDn / CANTX0.
IOPORT_PIN_P265_PFC_22_ENCIFCK01	P26_5 / ENCIFn / ENCIFCK01.
IOPORT_PIN_P265_PFC_25_HDSL04_CLK1	P26_5 / HDSLn / HDSL04_CLK1.
IOPORT_PIN_P266_PFC_00_SEI	P26_6 / IRQ / SEI.
IOPORT_PIN_P266_PFC_04_CS2	P26_6 / BSC / CS2.
IOPORT_PIN_P266_PFC_0F_ETH1_TXER	P26_6 / ETHER_ETHn / ETH1_TXER.
IOPORT_PIN_P266_PFC_12_ESC_RESETOUT_N	P26_6 / ETHER_ESC / ESC_RESETOUT_N.
IOPORT_PIN_P266_PFC_15_DEE01	P26_6 / SCIEn / DEE01.
IOPORT_PIN_P266_PFC_19_CANRX0	P26_6 / CANFDn / CANRX0.
IOPORT_PIN_P266_PFC_22_ENCIFOE01	P26_6 / ENCIFn / ENCIFOE01.
IOPORT_PIN_P266_PFC_25_HDSL04_SEL1	P26_6 / HDSLn / HDSL04_SEL1.
IOPORT_PIN_P267_PFC_00_IRQ0	P26_7 / IRQ / IRQ0.
IOPORT_PIN_P267_PFC_04_CS3	P26_7 / BSC / CS3.
IOPORT_PIN_P267_PFC_0F_ETH1_RXER	P26_7 / ETHER_ETHn / ETH1_RXER.
IOPORT_PIN_P267_PFC_12_ESC_LEDSTER	P26_7 / ETHER_ESC / ESC_LEDSTER.
IOPORT_PIN_P267_PFC_15_TXDE01	P26_7 / SCIEn / TXDE01.
IOPORT_PIN_P267_PFC_19_CANRXDP0	P26_7 / CANFDn / CANRXDP0.
IOPORT_PIN_P267_PFC_1A_SPI_SSL01	P26_7 / SPIn / SPI_SSL01.
IOPORT_PIN_P267_PFC_22_ENCIFDO01	P26_7 / ENCIFn / ENCIFDO01.
IOPORT_PIN_P267_PFC_25_HDSL04_MISO1	P26_7 / HDSLn / HDSL04_MISO1.
IOPORT_PIN_P270_PFC_00_IRQ1	P27_0 / IRQ / IRQ1.
IOPORT_PIN_P270_PFC_04_CS5	P27_0 / BSC / CS5.
IOPORT_PIN_P270_PFC_0F_ETH1_CRS	P27_0 / ETHER_ETHn / ETH1_CRS.
IOPORT_PIN_P270_PFC_15_RXDE01	P27_0 / SCIEn / RXDE01.
IOPORT_PIN_P270_PFC_19_CANTXDP0	P27_0 / CANFDn / CANTXDP0.
IOPORT_PIN_P270_PFC_1A_SPI_SSL02	P27_0 / SPIn / SPI_SSL02.
IOPORT_PIN_P270_PFC_20_HSPI_INT	P27_0 / SHOSTIF / HSPI_INT.
IOPORT_PIN_P270_PFC_22_ENCIFDI01	P27_0 / ENCIFn / ENCIFDI01.
IOPORT_PIN_P270_PFC_25_HDSL04_MOSI1	P27_0 / HDSLn / HDSL04_MOSI1.
IOPORT_PIN_P271_PFC_00_IRQ2	P27_1 / IRQ / IRQ2.
IOPORT_PIN_P271_PFC_0A_GTIOC02_0A	P27_1 / GPT / GTIOC02_0A.
IOPORT_PIN_P271_PFC_0F_ETH1_COL	P27_1 / ETHER_ETHn / ETH1_COL.
IOPORT_PIN_P271_PFC_19_CANRX1	P27_1 / CANFDn / CANRX1.
IOPORT_PIN_P271_PFC_1A_SPI_SSL03	P27_1 / SPIn / SPI_SSL03.
IOPORT_PIN_P271_PFC_20_HSPI_CS	P27_1 / SHOSTIF / HSPI_CS.
IOPORT_PIN_P271_PFC_25_HDSL04_CLK2	P27_1 / HDSLn / HDSL04_CLK2.
IOPORT_PIN_P272_PFC_00_IRQ3	P27_2 / IRQ / IRQ3.
IOPORT_PIN_P272_PFC_0A_GTIOC02_0B	P27_2 / GPT / GTIOC02_0B.
IOPORT_PIN_P272_PFC_10_GMAC1_PTPTRG0	P27_2 / ETHER_GMACn / GMAC1_PTPTRG0.
IOPORT_PIN_P272_PFC_12_ESC_LEDERR	P27_2 / ETHER_ESC / ESC_LEDERR.
IOPORT_PIN_P272_PFC_19_CANTX1	P27_2 / CANFDn / CANTX1.
IOPORT_PIN_P272_PFC_1A_SPI_RSPCK0	P27_2 / SPIn / SPI_RSPCK0.
IOPORT_PIN_P272_PFC_20_HSPI_IO0	P27_2 / SHOSTIF / HSPI_IO0.
IOPORT_PIN_P272_PFC_25_HDSL04_SEL2	P27_2 / HDSLn / HDSL04_SEL2.
IOPORT_PIN_P273_PFC_06_MTIOC2A	P27_3 / MTU3 / MTIOC2A.
IOPORT_PIN_P273_PFC_09_GTIOC08_3A	P27_3 / GPT / GTIOC08_3A.
IOPORT_PIN_P273_PFC_0A_GTIOC02_1A	P27_3 / GPT / GTIOC02_1A.
IOPORT_PIN_P273_PFC_10_GMAC1_PTPTRG1	P27_3 / ETHER_GMACn / GMAC1_PTPTRG1.
IOPORT_PIN_P273_PFC_14_SCK0	P27_3 / SCIn / SCK0.
IOPORT_PIN_P273_PFC_15_SCKE10	P27_3 / SCIEn / SCKE10.
IOPORT_PIN_P273_PFC_19_CANRXDP1	P27_3 / CANFDn / CANRXDP1.
IOPORT_PIN_P273_PFC_1A_SPI_MOSI0	P27_3 / SPIn / SPI_MOSI0.
IOPORT_PIN_P273_PFC_20_HSPI_IO1	P27_3 / SHOSTIF / HSPI_IO1.
IOPORT_PIN_P273_PFC_22_ENCIFCK14	P27_3 / ENCIFn / ENCIFCK14.
IOPORT_PIN_P273_PFC_25_HDSL04_MISO2	P27_3 / HDSLn / HDSL04_MISO2.
IOPORT_PIN_P274_PFC_06_MTIOC2B	P27_4 / MTU3 / MTIOC2B.
IOPORT_PIN_P274_PFC_09_GTIOC08_3B	P27_4 / GPT / GTIOC08_3B.
IOPORT_PIN_P274_PFC_0A_GTIOC02_1B	P27_4 / GPT / GTIOC02_1B.
IOPORT_PIN_P274_PFC_14_RXD0_SCL0_MISO0	P27_4 / SCIn / RXD0_SCL0_MISO0.
IOPORT_PIN_P274_PFC_15_DEE10	P27_4 / SCIEn / DEE10.
IOPORT_PIN_P274_PFC_19_CANTXDP1	P27_4 / CANFDn / CANTXDP1.
IOPORT_PIN_P274_PFC_1A_SPI_MISO0	P27_4 / SPIn / SPI_MISO0.
IOPORT_PIN_P274_PFC_20_HSPI_IO2	P27_4 / SHOSTIF / HSPI_IO2.
IOPORT_PIN_P274_PFC_22_ENCIFOE14	P27_4 / ENCIFn / ENCIFOE14.
IOPORT_PIN_P274_PFC_25_HDSL04_MOSI2	P27_4 / HDSLn / HDSL04_MOSI2.
IOPORT_PIN_P275_PFC_06_MTIOC1A	P27_5 / MTU3 / MTIOC1A.
IOPORT_PIN_P275_PFC_09_GTIOC08_4A	P27_5 / GPT / GTIOC08_4A.
IOPORT_PIN_P275_PFC_0A_GTIOC02_2A	P27_5 / GPT / GTIOC02_2A.
IOPORT_PIN_P275_PFC_14_TXD0_SDA0_MOSI0	P27_5 / SCIn / TXD0_SDA0_MOSI0.
IOPORT_PIN_P275_PFC_15_TXDE10	P27_5 / SCIEn / TXDE10.
IOPORT_PIN_P275_PFC_1A_SPI_SSL00	P27_5 / SPIn / SPI_SSL00.
IOPORT_PIN_P275_PFC_20_HSPI_IO3	P27_5 / SHOSTIF / HSPI_IO3.
IOPORT_PIN_P275_PFC_22_ENCIFDO14	P27_5 / ENCIFn / ENCIFDO14.
IOPORT_PIN_P275_PFC_25_HDSL05_LINK	P27_5 / HDSLn / HDSL05_LINK.
IOPORT_PIN_P276_PFC_06_MTIOC1B	P27_6 / MTU3 / MTIOC1B.
IOPORT_PIN_P276_PFC_09_GTIOC08_4B	P27_6 / GPT / GTIOC08_4B.
IOPORT_PIN_P276_PFC_0A_GTIOC02_2B	P27_6 / GPT / GTIOC02_2B.
IOPORT_PIN_P276_PFC_15_RXDE10	P27_6 / SCIEn / RXDE10.
IOPORT_PIN_P276_PFC_20_HSPI_CK	P27_6 / SHOSTIF / HSPI_CK.
IOPORT_PIN_P276_PFC_22_ENCIFDI14	P27_6 / ENCIFn / ENCIFDI14.
IOPORT_PIN_P276_PFC_25_HDSL05_SMPL	P27_6 / HDSLn / HDSL05_SMPL.
IOPORT_PIN_P277_PFC_00_IRQ4	P27_7 / IRQ / IRQ4.
IOPORT_PIN_P277_PFC_09_GTIOC08_0A	P27_7 / GPT / GTIOC08_0A.
IOPORT_PIN_P277_PFC_11_ETHSW_TDMAOUT0	P27_7 / ETHER_ETHSW / ETHSW_TDMAOUT0.
IOPORT_PIN_P277_PFC_1A_SPI_RSPCK1	P27_7 / SPIn / SPI_RSPCK1.
IOPORT_PIN_P277_PFC_24_DUEI05	P27_7 / ENDATn / DUEI05.
IOPORT_PIN_P277_PFC_25_HDSL05_CLK1	P27_7 / HDSLn / HDSL05_CLK1.
IOPORT_PIN_P280_PFC_00_IRQ5	P28_0 / IRQ / IRQ5.
IOPORT_PIN_P280_PFC_09_GTIOC08_0B	P28_0 / GPT / GTIOC08_0B.
IOPORT_PIN_P280_PFC_11_ETHSW_TDMAOUT1	P28_0 / ETHER_ETHSW / ETHSW_TDMAOUT1.
IOPORT_PIN_P280_PFC_1A_SPI_MOSI1	P28_0 / SPIn / SPI_MOSI1.
IOPORT_PIN_P280_PFC_24_TST_OUT05	P28_0 / ENDATn / TST_OUT05.
IOPORT_PIN_P280_PFC_25_HDSL05_SEL1	P28_0 / HDSLn / HDSL05_SEL1.
IOPORT_PIN_P281_PFC_00_IRQ6	P28_1 / IRQ / IRQ6.
IOPORT_PIN_P281_PFC_09_GTIOC08_1A	P28_1 / GPT / GTIOC08_1A.
IOPORT_PIN_P281_PFC_11_ETHSW_TDMAOUT2	P28_1 / ETHER_ETHSW / ETHSW_TDMAOUT2.
IOPORT_PIN_P281_PFC_1A_SPI_MISO1	P28_1 / SPIn / SPI_MISO1.
IOPORT_PIN_P281_PFC_24_SI05	P28_1 / ENDATn / SI05.
IOPORT_PIN_P281_PFC_25_HDSL05_MISO1	P28_1 / HDSLn / HDSL05_MISO1.
IOPORT_PIN_P282_PFC_00_IRQ7	P28_2 / IRQ / IRQ7.
IOPORT_PIN_P282_PFC_09_GTIOC08_1B	P28_2 / GPT / GTIOC08_1B.
IOPORT_PIN_P282_PFC_11_ETHSW_TDMAOUT3	P28_2 / ETHER_ETHSW / ETHSW_TDMAOUT3.
IOPORT_PIN_P282_PFC_1A_SPI_SSL10	P28_2 / SPIn / SPI_SSL10.
IOPORT_PIN_P282_PFC_24_DUEI06	P28_2 / ENDATn / DUEI06.
IOPORT_PIN_P282_PFC_25_HDSL05_MOSI1	P28_2 / HDSLn / HDSL05_MOSI1.
IOPORT_PIN_P283_PFC_09_GTIOC08_2A	P28_3 / GPT / GTIOC08_2A.
IOPORT_PIN_P283_PFC_1A_SPI_SSL11	P28_3 / SPIn / SPI_SSL11.
IOPORT_PIN_P283_PFC_24_TST_OUT06	P28_3 / ENDATn / TST_OUT06.
IOPORT_PIN_P283_PFC_25_HDSL05_CLK2	P28_3 / HDSLn / HDSL05_CLK2.
IOPORT_PIN_P284_PFC_09_GTIOC08_2B	P28_4 / GPT / GTIOC08_2B.
IOPORT_PIN_P284_PFC_1A_SPI_SSL12	P28_4 / SPIn / SPI_SSL12.
IOPORT_PIN_P284_PFC_24_SI06	P28_4 / ENDATn / SI06.
IOPORT_PIN_P284_PFC_25_HDSL05_SEL2	P28_4 / HDSLn / HDSL05_SEL2.
IOPORT_PIN_P285_PFC_15_SCKE08	P28_5 / SCIEn / SCKE08.
IOPORT_PIN_P285_PFC_16_SCKE00	P28_5 / SCIEn / SCKE00.
IOPORT_PIN_P285_PFC_19_CANRX0	P28_5 / CANFDn / CANRX0.
IOPORT_PIN_P285_PFC_1A_SPI_SSL13	P28_5 / SPIn / SPI_SSL13.
IOPORT_PIN_P285_PFC_1D_MCLK71	P28_5 / DSMIFn / MCLK71.
IOPORT_PIN_P285_PFC_22_ENCIFCK08	P28_5 / ENCIFn / ENCIFCK08.
IOPORT_PIN_P285_PFC_23_ENCIFCK00	P28_5 / ENCIFn / ENCIFCK00.
IOPORT_PIN_P285_PFC_25_HDSL05_MISO2	P28_5 / HDSLn / HDSL05_MISO2.
IOPORT_PIN_P286_PFC_15_DEE08	P28_6 / SCIEn / DEE08.
IOPORT_PIN_P286_PFC_16_DEE00	P28_6 / SCIEn / DEE00.
IOPORT_PIN_P286_PFC_19_CANTX0	P28_6 / CANFDn / CANTX0.
IOPORT_PIN_P286_PFC_1D_MDAT71	P28_6 / DSMIFn / MDAT71.
IOPORT_PIN_P286_PFC_22_ENCIFOE08	P28_6 / ENCIFn / ENCIFOE08.
IOPORT_PIN_P286_PFC_23_ENCIFOE00	P28_6 / ENCIFn / ENCIFOE00.
IOPORT_PIN_P286_PFC_25_HDSL05_MOSI2	P28_6 / HDSLn / HDSL05_MOSI2.
IOPORT_PIN_P287_PFC_15_TXDE08	P28_7 / SCIEn / TXDE08.
IOPORT_PIN_P287_PFC_16_TXDE00	P28_7 / SCIEn / TXDE00.
IOPORT_PIN_P287_PFC_19_CANRXDP0	P28_7 / CANFDn / CANRXDP0.
IOPORT_PIN_P287_PFC_1D_MCLK72	P28_7 / DSMIFn / MCLK72.
IOPORT_PIN_P287_PFC_22_ENCIFDO08	P28_7 / ENCIFn / ENCIFDO08.
IOPORT_PIN_P287_PFC_23_ENCIFDO00	P28_7 / ENCIFn / ENCIFDO00.
IOPORT_PIN_P287_PFC_25_HDSL06_LINK	P28_7 / HDSLn / HDSL06_LINK.
IOPORT_PIN_P290_PFC_15_RXDE08	P29_0 / SCIEn / RXDE08.
IOPORT_PIN_P290_PFC_16_RXDE00	P29_0 / SCIEn / RXDE00.
IOPORT_PIN_P290_PFC_19_CANTXDP0	P29_0 / CANFDn / CANTXDP0.
IOPORT_PIN_P290_PFC_1D_MDAT72	P29_0 / DSMIFn / MDAT72.
IOPORT_PIN_P290_PFC_22_ENCIFDI08	P29_0 / ENCIFn / ENCIFDI08.
IOPORT_PIN_P290_PFC_23_ENCIFDI00	P29_0 / ENCIFn / ENCIFDI00.
IOPORT_PIN_P290_PFC_25_HDSL06_SMPL	P29_0 / HDSLn / HDSL06_SMPL.
IOPORT_PIN_P291_PFC_09_GTIOC09_0A	P29_1 / GPT / GTIOC09_0A.
IOPORT_PIN_P291_PFC_0F_ETH2_TXCLK	P29_1 / ETHER_ETHn / ETH2_TXCLK.
IOPORT_PIN_P291_PFC_15_SCKE09	P29_1 / SCIEn / SCKE09.
IOPORT_PIN_P291_PFC_22_ENCIFCK09	P29_1 / ENCIFn / ENCIFCK09.
IOPORT_PIN_P291_PFC_25_HDSL06_CLK1	P29_1 / HDSLn / HDSL06_CLK1.
IOPORT_PIN_P292_PFC_09_GTIOC09_0B	P29_2 / GPT / GTIOC09_0B.
IOPORT_PIN_P292_PFC_0F_ETH2_TXD0	P29_2 / ETHER_ETHn / ETH2_TXD0.
IOPORT_PIN_P292_PFC_15_DEE09	P29_2 / SCIEn / DEE09.
IOPORT_PIN_P292_PFC_22_ENCIFOE09	P29_2 / ENCIFn / ENCIFOE09.
IOPORT_PIN_P292_PFC_25_HDSL06_SEL1	P29_2 / HDSLn / HDSL06_SEL1.
IOPORT_PIN_P293_PFC_09_GTIOC09_1A	P29_3 / GPT / GTIOC09_1A.
IOPORT_PIN_P293_PFC_0F_ETH2_TXD1	P29_3 / ETHER_ETHn / ETH2_TXD1.
IOPORT_PIN_P293_PFC_15_TXDE09	P29_3 / SCIEn / TXDE09.
IOPORT_PIN_P293_PFC_22_ENCIFDO09	P29_3 / ENCIFn / ENCIFDO09.
IOPORT_PIN_P293_PFC_25_HDSL06_MISO1	P29_3 / HDSLn / HDSL06_MISO1.
IOPORT_PIN_P294_PFC_00_IRQ8	P29_4 / IRQ / IRQ8.
IOPORT_PIN_P294_PFC_09_GTIOC09_1B	P29_4 / GPT / GTIOC09_1B.
IOPORT_PIN_P294_PFC_0F_ETH2_TXD2	P29_4 / ETHER_ETHn / ETH2_TXD2.
IOPORT_PIN_P294_PFC_15_RXDE09	P29_4 / SCIEn / RXDE09.
IOPORT_PIN_P294_PFC_1A_SPI_SSL20	P29_4 / SPIn / SPI_SSL20.
IOPORT_PIN_P294_PFC_22_ENCIFDI09	P29_4 / ENCIFn / ENCIFDI09.
IOPORT_PIN_P294_PFC_25_HDSL06_MOSI1	P29_4 / HDSLn / HDSL06_MOSI1.
IOPORT_PIN_P295_PFC_00_IRQ9	P29_5 / IRQ / IRQ9.
IOPORT_PIN_P295_PFC_09_GTIOC09_2A	P29_5 / GPT / GTIOC09_2A.
IOPORT_PIN_P295_PFC_0F_ETH2_TXD3	P29_5 / ETHER_ETHn / ETH2_TXD3.
IOPORT_PIN_P295_PFC_15_SCKE10	P29_5 / SCIEn / SCKE10.
IOPORT_PIN_P295_PFC_1A_SPI_SSL21	P29_5 / SPIn / SPI_SSL21.
IOPORT_PIN_P295_PFC_22_ENCIFCK10	P29_5 / ENCIFn / ENCIFCK10.
IOPORT_PIN_P295_PFC_25_HDSL06_CLK2	P29_5 / HDSLn / HDSL06_CLK2.
IOPORT_PIN_P296_PFC_09_GTIOC09_2B	P29_6 / GPT / GTIOC09_2B.
IOPORT_PIN_P296_PFC_0F_ETH2_TXEN	P29_6 / ETHER_ETHn / ETH2_TXEN.
IOPORT_PIN_P296_PFC_15_DEE10	P29_6 / SCIEn / DEE10.
IOPORT_PIN_P296_PFC_1A_SPI_SSL22	P29_6 / SPIn / SPI_SSL22.
IOPORT_PIN_P296_PFC_22_ENCIFOE10	P29_6 / ENCIFn / ENCIFOE10.
IOPORT_PIN_P296_PFC_25_HDSL06_SEL2	P29_6 / HDSLn / HDSL06_SEL2.
IOPORT_PIN_P297_PFC_09_GTIOC09_3A	P29_7 / GPT / GTIOC09_3A.
IOPORT_PIN_P297_PFC_0F_ETH2_RXCLK	P29_7 / ETHER_ETHn / ETH2_RXCLK.
IOPORT_PIN_P297_PFC_15_TXDE10	P29_7 / SCIEn / TXDE10.
IOPORT_PIN_P297_PFC_1A_SPI_SSL23	P29_7 / SPIn / SPI_SSL23.
IOPORT_PIN_P297_PFC_22_ENCIFDO10	P29_7 / ENCIFn / ENCIFDO10.
IOPORT_PIN_P297_PFC_25_HDSL06_MISO2	P29_7 / HDSLn / HDSL06_MISO2.
IOPORT_PIN_P300_PFC_09_GTIOC09_3B	P30_0 / GPT / GTIOC09_3B.
IOPORT_PIN_P300_PFC_0F_ETH2_RXD0	P30_0 / ETHER_ETHn / ETH2_RXD0.
IOPORT_PIN_P300_PFC_15_RXDE10	P30_0 / SCIEn / RXDE10.
IOPORT_PIN_P300_PFC_22_ENCIFDI10	P30_0 / ENCIFn / ENCIFDI10.
IOPORT_PIN_P300_PFC_25_HDSL06_MOSI2	P30_0 / HDSLn / HDSL06_MOSI2.
IOPORT_PIN_P301_PFC_09_GTIOC09_4A	P30_1 / GPT / GTIOC09_4A.
IOPORT_PIN_P301_PFC_0F_ETH2_RXD1	P30_1 / ETHER_ETHn / ETH2_RXD1.
IOPORT_PIN_P301_PFC_15_SCKE11	P30_1 / SCIEn / SCKE11.
IOPORT_PIN_P301_PFC_22_ENCIFCK11	P30_1 / ENCIFn / ENCIFCK11.
IOPORT_PIN_P301_PFC_25_HDSL07_LINK	P30_1 / HDSLn / HDSL07_LINK.
IOPORT_PIN_P302_PFC_00_IRQ10	P30_2 / IRQ / IRQ10.
IOPORT_PIN_P302_PFC_09_GTIOC09_4B	P30_2 / GPT / GTIOC09_4B.
IOPORT_PIN_P302_PFC_0F_ETH2_RXD2	P30_2 / ETHER_ETHn / ETH2_RXD2.
IOPORT_PIN_P302_PFC_15_DEE11	P30_2 / SCIEn / DEE11.
IOPORT_PIN_P302_PFC_1A_SPI_MOSI2	P30_2 / SPIn / SPI_MOSI2.
IOPORT_PIN_P302_PFC_22_ENCIFOE11	P30_2 / ENCIFn / ENCIFOE11.
IOPORT_PIN_P302_PFC_25_HDSL07_SMPL	P30_2 / HDSLn / HDSL07_SMPL.
IOPORT_PIN_P303_PFC_00_IRQ11	P30_3 / IRQ / IRQ11.
IOPORT_PIN_P303_PFC_09_GTIOC09_5A	P30_3 / GPT / GTIOC09_5A.
IOPORT_PIN_P303_PFC_0F_ETH2_RXD3	P30_3 / ETHER_ETHn / ETH2_RXD3.
IOPORT_PIN_P303_PFC_15_TXDE11	P30_3 / SCIEn / TXDE11.
IOPORT_PIN_P303_PFC_1A_SPI_MISO2	P30_3 / SPIn / SPI_MISO2.
IOPORT_PIN_P303_PFC_22_ENCIFDO11	P30_3 / ENCIFn / ENCIFDO11.
IOPORT_PIN_P303_PFC_25_HDSL07_CLK1	P30_3 / HDSLn / HDSL07_CLK1.
IOPORT_PIN_P304_PFC_09_GTIOC09_5B	P30_4 / GPT / GTIOC09_5B.
IOPORT_PIN_P304_PFC_0F_ETH2_RXDV	P30_4 / ETHER_ETHn / ETH2_RXDV.
IOPORT_PIN_P304_PFC_15_RXDE11	P30_4 / SCIEn / RXDE11.
IOPORT_PIN_P304_PFC_22_ENCIFDI11	P30_4 / ENCIFn / ENCIFDI11.
IOPORT_PIN_P304_PFC_25_HDSL07_SEL1	P30_4 / HDSLn / HDSL07_SEL1.
IOPORT_PIN_P305_PFC_09_GTIOC09_6A	P30_5 / GPT / GTIOC09_6A.
IOPORT_PIN_P305_PFC_10_GMAC2_MDC	P30_5 / ETHER_GMACn / GMAC2_MDC.
IOPORT_PIN_P305_PFC_11_ETHSW_MDC	P30_5 / ETHER_ETHSW / ETHSW_MDC.
IOPORT_PIN_P305_PFC_12_ESC_MDC	P30_5 / ETHER_ESC / ESC_MDC.
IOPORT_PIN_P305_PFC_1A_SPI_RSPCK3	P30_5 / SPIn / SPI_RSPCK3.
IOPORT_PIN_P305_PFC_24_DUEI07	P30_5 / ENDATn / DUEI07.
IOPORT_PIN_P305_PFC_25_HDSL07_MISO1	P30_5 / HDSLn / HDSL07_MISO1.
IOPORT_PIN_P306_PFC_09_GTIOC09_6B	P30_6 / GPT / GTIOC09_6B.
IOPORT_PIN_P306_PFC_10_GMAC2_MDIO	P30_6 / ETHER_GMACn / GMAC2_MDIO.
IOPORT_PIN_P306_PFC_11_ETHSW_MDIO	P30_6 / ETHER_ETHSW / ETHSW_MDIO.
IOPORT_PIN_P306_PFC_12_ESC_MDIO	P30_6 / ETHER_ESC / ESC_MDIO.
IOPORT_PIN_P306_PFC_1A_SPI_MOSI3	P30_6 / SPIn / SPI_MOSI3.
IOPORT_PIN_P306_PFC_24_TST_OUT07	P30_6 / ENDATn / TST_OUT07.
IOPORT_PIN_P306_PFC_25_HDSL07_MOSI1	P30_6 / HDSLn / HDSL07_MOSI1.
IOPORT_PIN_P307_PFC_00_IRQ14	P30_7 / IRQ / IRQ14.
IOPORT_PIN_P307_PFC_11_ETHSW_PHYLINK2	P30_7 / ETHER_ETHSW / ETHSW_PHYLINK2.
IOPORT_PIN_P307_PFC_12_ESC_PHYLINK2	P30_7 / ETHER_ESC / ESC_PHYLINK2.
IOPORT_PIN_P307_PFC_1A_SPI_MISO3	P30_7 / SPIn / SPI_MISO3.
IOPORT_PIN_P307_PFC_1E_MCLK30	P30_7 / DSMIFn / MCLK30.
IOPORT_PIN_P307_PFC_24_SI07	P30_7 / ENDATn / SI07.
IOPORT_PIN_P307_PFC_25_HDSL07_CLK2	P30_7 / HDSLn / HDSL07_CLK2.
IOPORT_PIN_P307_PFC_29_SD1_IOVS	P30_7 / SDHI / SD1_IOVS.
IOPORT_PIN_P310_PFC_02_ETH2_REFCLK	P31_0 / ETHER_ETHn / ETH2_REFCLK.
IOPORT_PIN_P310_PFC_03_RMII2_REFCLK	P31_0 / ETHER_ETHn / RMII2_REFCLK.
IOPORT_PIN_P310_PFC_0C_GTETRGSA	P31_0 / POEG / GTETRGSA.
IOPORT_PIN_P310_PFC_1A_SPI_SSL30	P31_0 / SPIn / SPI_SSL30.
IOPORT_PIN_P310_PFC_25_HDSL07_SEL2	P31_0 / HDSLn / HDSL07_SEL2.
IOPORT_PIN_P311_PFC_00_IRQ13	P31_1 / IRQ / IRQ13.
IOPORT_PIN_P311_PFC_0C_GTETRGSB	P31_1 / POEG / GTETRGSB.
IOPORT_PIN_P311_PFC_0F_ETH2_RXER	P31_1 / ETHER_ETHn / ETH2_RXER.
IOPORT_PIN_P311_PFC_1A_SPI_SSL31	P31_1 / SPIn / SPI_SSL31.
IOPORT_PIN_P311_PFC_25_HDSL07_MISO2	P31_1 / HDSLn / HDSL07_MISO2.
IOPORT_PIN_P312_PFC_08_POE0	P31_2 / POE3 / POE0.
IOPORT_PIN_P312_PFC_0F_ETH2_TXER	P31_2 / ETHER_ETHn / ETH2_TXER.
IOPORT_PIN_P312_PFC_15_SCKE09	P31_2 / SCIEn / SCKE09.
IOPORT_PIN_P312_PFC_1A_SPI_SSL32	P31_2 / SPIn / SPI_SSL32.
IOPORT_PIN_P312_PFC_1D_MCLK80	P31_2 / DSMIFn / MCLK80.
IOPORT_PIN_P312_PFC_1E_MDAT30	P31_2 / DSMIFn / MDAT30.
IOPORT_PIN_P312_PFC_20_HSPI_IO4	P31_2 / SHOSTIF / HSPI_IO4.
IOPORT_PIN_P312_PFC_22_ENCIFCK09	P31_2 / ENCIFn / ENCIFCK09.
IOPORT_PIN_P312_PFC_25_HDSL07_MOSI2	P31_2 / HDSLn / HDSL07_MOSI2.
IOPORT_PIN_P312_PFC_26_POUTA	P31_2 / ENCOUT / POUTA.
IOPORT_PIN_P313_PFC_08_POE4	P31_3 / POE3 / POE4.
IOPORT_PIN_P313_PFC_0F_ETH2_RXER	P31_3 / ETHER_ETHn / ETH2_RXER.
IOPORT_PIN_P313_PFC_11_ETHSW_TDMAOUT1	P31_3 / ETHER_ETHSW / ETHSW_TDMAOUT1.
IOPORT_PIN_P313_PFC_12_ESC_LEDERR	P31_3 / ETHER_ESC / ESC_LEDERR.
IOPORT_PIN_P313_PFC_15_DEE09	P31_3 / SCIEn / DEE09.
IOPORT_PIN_P313_PFC_1A_SPI_SSL33	P31_3 / SPIn / SPI_SSL33.
IOPORT_PIN_P313_PFC_1D_MDAT80	P31_3 / DSMIFn / MDAT80.
IOPORT_PIN_P313_PFC_1E_MCLK31	P31_3 / DSMIFn / MCLK31.
IOPORT_PIN_P313_PFC_20_HSPI_IO5	P31_3 / SHOSTIF / HSPI_IO5.
IOPORT_PIN_P313_PFC_22_ENCIFOE09	P31_3 / ENCIFn / ENCIFOE09.
IOPORT_PIN_P313_PFC_25_HDSL08_LINK	P31_3 / HDSLn / HDSL08_LINK.
IOPORT_PIN_P314_PFC_05_DREQ	P31_4 / DMAC / DREQ.
IOPORT_PIN_P314_PFC_08_POE8	P31_4 / POE3 / POE8.
IOPORT_PIN_P314_PFC_0F_ETH2_CRS	P31_4 / ETHER_ETHn / ETH2_CRS.
IOPORT_PIN_P314_PFC_11_ETHSW_PTPOUT2	P31_4 / ETHER_ETHSW / ETHSW_PTPOUT2.
IOPORT_PIN_P314_PFC_12_ESC_SYNC0	P31_4 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P314_PFC_15_TXDE09	P31_4 / SCIEn / TXDE09.
IOPORT_PIN_P314_PFC_1A_SPI_RSPCK0	P31_4 / SPIn / SPI_RSPCK0.
IOPORT_PIN_P314_PFC_1B_SPI_SSL30	P31_4 / SPIn / SPI_SSL30.
IOPORT_PIN_P314_PFC_1D_MCLK81	P31_4 / DSMIFn / MCLK81.
IOPORT_PIN_P314_PFC_1E_MDAT31	P31_4 / DSMIFn / MDAT31.
IOPORT_PIN_P314_PFC_20_HSPI_IO6	P31_4 / SHOSTIF / HSPI_IO6.
IOPORT_PIN_P314_PFC_22_ENCIFDO09	P31_4 / ENCIFn / ENCIFDO09.
IOPORT_PIN_P314_PFC_25_HDSL08_SMPL	P31_4 / HDSLn / HDSL08_SMPL.
IOPORT_PIN_P314_PFC_26_POUTB	P31_4 / ENCOUT / POUTB.
IOPORT_PIN_P315_PFC_05_DACK	P31_5 / DMAC / DACK.
IOPORT_PIN_P315_PFC_08_POE10	P31_5 / POE3 / POE10.
IOPORT_PIN_P315_PFC_0F_ETH2_COL	P31_5 / ETHER_ETHn / ETH2_COL.
IOPORT_PIN_P315_PFC_11_ETHSW_PTPOUT3	P31_5 / ETHER_ETHSW / ETHSW_PTPOUT3.
IOPORT_PIN_P315_PFC_12_ESC_SYNC1	P31_5 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P315_PFC_15_RXDE09	P31_5 / SCIEn / RXDE09.
IOPORT_PIN_P315_PFC_1A_SPI_MOSI0	P31_5 / SPIn / SPI_MOSI0.
IOPORT_PIN_P315_PFC_1B_SPI_SSL31	P31_5 / SPIn / SPI_SSL31.
IOPORT_PIN_P315_PFC_1D_MDAT81	P31_5 / DSMIFn / MDAT81.
IOPORT_PIN_P315_PFC_1E_MCLK32	P31_5 / DSMIFn / MCLK32.
IOPORT_PIN_P315_PFC_20_HSPI_IO7	P31_5 / SHOSTIF / HSPI_IO7.
IOPORT_PIN_P315_PFC_22_ENCIFDI09	P31_5 / ENCIFn / ENCIFDI09.
IOPORT_PIN_P315_PFC_25_HDSL08_CLK1	P31_5 / HDSLn / HDSL08_CLK1.
IOPORT_PIN_P315_PFC_26_POUTZ	P31_5 / ENCOUT / POUTZ.
IOPORT_PIN_P316_PFC_04_A16	P31_6 / BSC / A16.
IOPORT_PIN_P316_PFC_05_TEND	P31_6 / DMAC / TEND.
IOPORT_PIN_P316_PFC_08_POE11	P31_6 / POE3 / POE11.
IOPORT_PIN_P316_PFC_10_GMAC2_PTPTRG0	P31_6 / ETHER_GMACn / GMAC2_PTPTRG0.
IOPORT_PIN_P316_PFC_11_ETHSW_TDMAOUT0	P31_6 / ETHER_ETHSW / ETHSW_TDMAOUT0.
IOPORT_PIN_P316_PFC_12_ESC_LEDRUN	P31_6 / ETHER_ESC / ESC_LEDRUN.
IOPORT_PIN_P316_PFC_15_SCKE11	P31_6 / SCIEn / SCKE11.
IOPORT_PIN_P316_PFC_16_SCKE01	P31_6 / SCIEn / SCKE01.
IOPORT_PIN_P316_PFC_1A_SPI_MISO0	P31_6 / SPIn / SPI_MISO0.
IOPORT_PIN_P316_PFC_1E_MDAT32	P31_6 / DSMIFn / MDAT32.
IOPORT_PIN_P316_PFC_22_ENCIFCK15	P31_6 / ENCIFn / ENCIFCK15.
IOPORT_PIN_P316_PFC_23_ENCIFCK01	P31_6 / ENCIFn / ENCIFCK01.
IOPORT_PIN_P316_PFC_25_HDSL08_SEL1	P31_6 / HDSLn / HDSL08_SEL1.
IOPORT_PIN_P317_PFC_10_GMAC2_PTPTRG1	P31_7 / ETHER_GMACn / GMAC2_PTPTRG1.
IOPORT_PIN_P317_PFC_15_DEE11	P31_7 / SCIEn / DEE11.
IOPORT_PIN_P317_PFC_16_DEE01	P31_7 / SCIEn / DEE01.
IOPORT_PIN_P317_PFC_1A_SPI_SSL00	P31_7 / SPIn / SPI_SSL00.
IOPORT_PIN_P317_PFC_22_ENCIFOE15	P31_7 / ENCIFn / ENCIFOE15.
IOPORT_PIN_P317_PFC_23_ENCIFOE01	P31_7 / ENCIFn / ENCIFOE01.
IOPORT_PIN_P317_PFC_25_HDSL08_MISO1	P31_7 / HDSLn / HDSL08_MISO1.
IOPORT_PIN_P320_PFC_15_TXDE11	P32_0 / SCIEn / TXDE11.
IOPORT_PIN_P320_PFC_16_TXDE01	P32_0 / SCIEn / TXDE01.
IOPORT_PIN_P320_PFC_1A_SPI_SSL01	P32_0 / SPIn / SPI_SSL01.
IOPORT_PIN_P320_PFC_22_ENCIFDO15	P32_0 / ENCIFn / ENCIFDO15.
IOPORT_PIN_P320_PFC_23_ENCIFDO01	P32_0 / ENCIFn / ENCIFDO01.
IOPORT_PIN_P320_PFC_25_HDSL08_MOSI1	P32_0 / HDSLn / HDSL08_MOSI1.
IOPORT_PIN_P321_PFC_15_RXDE11	P32_1 / SCIEn / RXDE11.
IOPORT_PIN_P321_PFC_16_RXDE01	P32_1 / SCIEn / RXDE01.
IOPORT_PIN_P321_PFC_1A_SPI_SSL02	P32_1 / SPIn / SPI_SSL02.
IOPORT_PIN_P321_PFC_22_ENCIFDI15	P32_1 / ENCIFn / ENCIFDI15.
IOPORT_PIN_P321_PFC_23_ENCIFDI01	P32_1 / ENCIFn / ENCIFDI01.
IOPORT_PIN_P321_PFC_25_HDSL08_CLK2	P32_1 / HDSLn / HDSL08_CLK2.
IOPORT_PIN_P322_PFC_09_GTIOC10_0A	P32_2 / GPT / GTIOC10_0A.
IOPORT_PIN_P322_PFC_0A_GTIOC01_0A	P32_2 / GPT / GTIOC01_0A.
IOPORT_PIN_P322_PFC_15_SCKE10	P32_2 / SCIEn / SCKE10.
IOPORT_PIN_P322_PFC_1A_SPI_SSL03	P32_2 / SPIn / SPI_SSL03.
IOPORT_PIN_P322_PFC_22_ENCIFCK10	P32_2 / ENCIFn / ENCIFCK10.
IOPORT_PIN_P322_PFC_25_HDSL08_SEL2	P32_2 / HDSLn / HDSL08_SEL2.
IOPORT_PIN_P323_PFC_09_GTIOC10_0B	P32_3 / GPT / GTIOC10_0B.
IOPORT_PIN_P323_PFC_0A_GTIOC01_0B	P32_3 / GPT / GTIOC01_0B.
IOPORT_PIN_P323_PFC_15_DEE10	P32_3 / SCIEn / DEE10.
IOPORT_PIN_P323_PFC_1A_SPI_RSPCK1	P32_3 / SPIn / SPI_RSPCK1.
IOPORT_PIN_P323_PFC_22_ENCIFOE10	P32_3 / ENCIFn / ENCIFOE10.
IOPORT_PIN_P323_PFC_25_HDSL08_MISO2	P32_3 / HDSLn / HDSL08_MISO2.
IOPORT_PIN_P324_PFC_09_GTIOC10_1A	P32_4 / GPT / GTIOC10_1A.
IOPORT_PIN_P324_PFC_0A_GTIOC01_1A	P32_4 / GPT / GTIOC01_1A.
IOPORT_PIN_P324_PFC_15_TXDE10	P32_4 / SCIEn / TXDE10.
IOPORT_PIN_P324_PFC_1A_SPI_MOSI1	P32_4 / SPIn / SPI_MOSI1.
IOPORT_PIN_P324_PFC_22_ENCIFDO10	P32_4 / ENCIFn / ENCIFDO10.
IOPORT_PIN_P324_PFC_25_HDSL08_MOSI2	P32_4 / HDSLn / HDSL08_MOSI2.
IOPORT_PIN_P325_PFC_09_GTIOC10_1B	P32_5 / GPT / GTIOC10_1B.
IOPORT_PIN_P325_PFC_0A_GTIOC01_1B	P32_5 / GPT / GTIOC01_1B.
IOPORT_PIN_P325_PFC_15_RXDE10	P32_5 / SCIEn / RXDE10.
IOPORT_PIN_P325_PFC_1A_SPI_MISO1	P32_5 / SPIn / SPI_MISO1.
IOPORT_PIN_P325_PFC_22_ENCIFDI10	P32_5 / ENCIFn / ENCIFDI10.
IOPORT_PIN_P325_PFC_25_HDSL09_LINK	P32_5 / HDSLn / HDSL09_LINK.
IOPORT_PIN_P326_PFC_09_GTIOC10_2A	P32_6 / GPT / GTIOC10_2A.
IOPORT_PIN_P326_PFC_0A_GTIOC01_2A	P32_6 / GPT / GTIOC01_2A.
IOPORT_PIN_P326_PFC_15_SCKE11	P32_6 / SCIEn / SCKE11.
IOPORT_PIN_P326_PFC_1A_SPI_SSL10	P32_6 / SPIn / SPI_SSL10.
IOPORT_PIN_P326_PFC_22_ENCIFCK11	P32_6 / ENCIFn / ENCIFCK11.
IOPORT_PIN_P326_PFC_25_HDSL09_SMPL	P32_6 / HDSLn / HDSL09_SMPL.
IOPORT_PIN_P327_PFC_09_GTIOC10_2B	P32_7 / GPT / GTIOC10_2B.
IOPORT_PIN_P327_PFC_0A_GTIOC01_2B	P32_7 / GPT / GTIOC01_2B.
IOPORT_PIN_P327_PFC_15_DEE11	P32_7 / SCIEn / DEE11.
IOPORT_PIN_P327_PFC_1A_SPI_SSL11	P32_7 / SPIn / SPI_SSL11.
IOPORT_PIN_P327_PFC_22_ENCIFOE11	P32_7 / ENCIFn / ENCIFOE11.
IOPORT_PIN_P327_PFC_25_HDSL09_CLK1	P32_7 / HDSLn / HDSL09_CLK1.
IOPORT_PIN_P330_PFC_09_GTIOC10_3A	P33_0 / GPT / GTIOC10_3A.
IOPORT_PIN_P330_PFC_15_TXDE11	P33_0 / SCIEn / TXDE11.
IOPORT_PIN_P330_PFC_1A_SPI_SSL12	P33_0 / SPIn / SPI_SSL12.
IOPORT_PIN_P330_PFC_1D_MCLK82	P33_0 / DSMIFn / MCLK82.
IOPORT_PIN_P330_PFC_22_ENCIFDO11	P33_0 / ENCIFn / ENCIFDO11.
IOPORT_PIN_P330_PFC_25_HDSL09_SEL1	P33_0 / HDSLn / HDSL09_SEL1.
IOPORT_PIN_P331_PFC_09_GTIOC10_3B	P33_1 / GPT / GTIOC10_3B.
IOPORT_PIN_P331_PFC_15_RXDE11	P33_1 / SCIEn / RXDE11.
IOPORT_PIN_P331_PFC_1A_SPI_SSL13	P33_1 / SPIn / SPI_SSL13.
IOPORT_PIN_P331_PFC_1D_MDAT82	P33_1 / DSMIFn / MDAT82.
IOPORT_PIN_P331_PFC_22_ENCIFDI11	P33_1 / ENCIFn / ENCIFDI11.
IOPORT_PIN_P331_PFC_25_HDSL09_MISO1	P33_1 / HDSLn / HDSL09_MISO1.
IOPORT_PIN_P332_PFC_04_A16	P33_2 / BSC / A16.
IOPORT_PIN_P332_PFC_09_GTADSM00_0	P33_2 / GPT / GTADSM00_0.
IOPORT_PIN_P332_PFC_0F_ETH3_TXCLK	P33_2 / ETHER_ETHn / ETH3_TXCLK.
IOPORT_PIN_P332_PFC_14_SCK1	P33_2 / SCIn / SCK1.
IOPORT_PIN_P332_PFC_15_SCKE01	P33_2 / SCIEn / SCKE01.
IOPORT_PIN_P332_PFC_1A_SPI_RSPCK1	P33_2 / SPIn / SPI_RSPCK1.
IOPORT_PIN_P332_PFC_1B_SPI_SSL30	P33_2 / SPIn / SPI_SSL30.
IOPORT_PIN_P332_PFC_1D_MCLK50	P33_2 / DSMIFn / MCLK50.
IOPORT_PIN_P332_PFC_22_ENCIFCK01	P33_2 / ENCIFn / ENCIFCK01.
IOPORT_PIN_P332_PFC_25_HDSL09_MOSI1	P33_2 / HDSLn / HDSL09_MOSI1.
IOPORT_PIN_P333_PFC_00_IRQ12	P33_3 / IRQ / IRQ12.
IOPORT_PIN_P333_PFC_04_A17	P33_3 / BSC / A17.
IOPORT_PIN_P333_PFC_09_GTADSM00_1	P33_3 / GPT / GTADSM00_1.
IOPORT_PIN_P333_PFC_0F_ETH3_TXD0	P33_3 / ETHER_ETHn / ETH3_TXD0.
IOPORT_PIN_P333_PFC_14_RXD1_SCL1_MISO1	P33_3 / SCIn / RXD1_SCL1_MISO1.
IOPORT_PIN_P333_PFC_15_DEE01	P33_3 / SCIEn / DEE01.
IOPORT_PIN_P333_PFC_1A_SPI_MOSI1	P33_3 / SPIn / SPI_MOSI1.
IOPORT_PIN_P333_PFC_1B_SPI_RSPCK0	P33_3 / SPIn / SPI_RSPCK0.
IOPORT_PIN_P333_PFC_1D_MDAT50	P33_3 / DSMIFn / MDAT50.
IOPORT_PIN_P333_PFC_22_ENCIFOE01	P33_3 / ENCIFn / ENCIFOE01.
IOPORT_PIN_P333_PFC_25_HDSL09_CLK2	P33_3 / HDSLn / HDSL09_CLK2.
IOPORT_PIN_P333_PFC_27_PCIE_RSTOUT0B	P33_3 / PCIE / PCIE_RSTOUT0B.
IOPORT_PIN_P334_PFC_00_IRQ13	P33_4 / IRQ / IRQ13.
IOPORT_PIN_P334_PFC_04_A18	P33_4 / BSC / A18.
IOPORT_PIN_P334_PFC_09_GTADSM01_0	P33_4 / GPT / GTADSM01_0.
IOPORT_PIN_P334_PFC_0F_ETH3_TXD1	P33_4 / ETHER_ETHn / ETH3_TXD1.
IOPORT_PIN_P334_PFC_14_TXD1_SDA1_MOSI1	P33_4 / SCIn / TXD1_SDA1_MOSI1.
IOPORT_PIN_P334_PFC_15_TXDE01	P33_4 / SCIEn / TXDE01.
IOPORT_PIN_P334_PFC_1A_SPI_MISO1	P33_4 / SPIn / SPI_MISO1.
IOPORT_PIN_P334_PFC_1B_SPI_MOSI0	P33_4 / SPIn / SPI_MOSI0.
IOPORT_PIN_P334_PFC_1D_MCLK51	P33_4 / DSMIFn / MCLK51.
IOPORT_PIN_P334_PFC_22_ENCIFDO01	P33_4 / ENCIFn / ENCIFDO01.
IOPORT_PIN_P334_PFC_25_HDSL09_SEL2	P33_4 / HDSLn / HDSL09_SEL2.
IOPORT_PIN_P334_PFC_27_PCIE_RSTOUT1B	P33_4 / PCIE / PCIE_RSTOUT1B.
IOPORT_PIN_P335_PFC_00_IRQ14	P33_5 / IRQ / IRQ14.
IOPORT_PIN_P335_PFC_04_A19	P33_5 / BSC / A19.
IOPORT_PIN_P335_PFC_09_GTADSM01_1	P33_5 / GPT / GTADSM01_1.
IOPORT_PIN_P335_PFC_0F_ETH3_TXD2	P33_5 / ETHER_ETHn / ETH3_TXD2.
IOPORT_PIN_P335_PFC_14_RXD2_SCL2_MISO2	P33_5 / SCIn / RXD2_SCL2_MISO2.
IOPORT_PIN_P335_PFC_15_RXDE01	P33_5 / SCIEn / RXDE01.
IOPORT_PIN_P335_PFC_1A_SPI_SSL10	P33_5 / SPIn / SPI_SSL10.
IOPORT_PIN_P335_PFC_1B_SPI_MISO0	P33_5 / SPIn / SPI_MISO0.
IOPORT_PIN_P335_PFC_1D_MDAT51	P33_5 / DSMIFn / MDAT51.
IOPORT_PIN_P335_PFC_22_ENCIFDI01	P33_5 / ENCIFn / ENCIFDI01.
IOPORT_PIN_P335_PFC_25_HDSL09_MISO2	P33_5 / HDSLn / HDSL09_MISO2.
IOPORT_PIN_P336_PFC_00_IRQ15	P33_6 / IRQ / IRQ15.
IOPORT_PIN_P336_PFC_04_A20	P33_6 / BSC / A20.
IOPORT_PIN_P336_PFC_09_GTADSM02_0	P33_6 / GPT / GTADSM02_0.
IOPORT_PIN_P336_PFC_0F_ETH3_TXD3	P33_6 / ETHER_ETHn / ETH3_TXD3.
IOPORT_PIN_P336_PFC_14_TXD2_SDA2_MOSI2	P33_6 / SCIn / TXD2_SDA2_MOSI2.
IOPORT_PIN_P336_PFC_15_SCKE06	P33_6 / SCIEn / SCKE06.
IOPORT_PIN_P336_PFC_1A_SPI_SSL11	P33_6 / SPIn / SPI_SSL11.
IOPORT_PIN_P336_PFC_1B_SPI_SSL00	P33_6 / SPIn / SPI_SSL00.
IOPORT_PIN_P336_PFC_1D_MCLK52	P33_6 / DSMIFn / MCLK52.
IOPORT_PIN_P336_PFC_22_ENCIFCK06	P33_6 / ENCIFn / ENCIFCK06.
IOPORT_PIN_P336_PFC_25_HDSL09_MOSI2	P33_6 / HDSLn / HDSL09_MOSI2.
IOPORT_PIN_P337_PFC_04_A21	P33_7 / BSC / A21.
IOPORT_PIN_P337_PFC_09_GTADSM02_1	P33_7 / GPT / GTADSM02_1.
IOPORT_PIN_P337_PFC_0F_ETH3_TXEN	P33_7 / ETHER_ETHn / ETH3_TXEN.
IOPORT_PIN_P337_PFC_15_DEE06	P33_7 / SCIEn / DEE06.
IOPORT_PIN_P337_PFC_1A_SPI_RSPCK2	P33_7 / SPIn / SPI_RSPCK2.
IOPORT_PIN_P337_PFC_1D_MDAT52	P33_7 / DSMIFn / MDAT52.
IOPORT_PIN_P337_PFC_22_ENCIFOE06	P33_7 / ENCIFn / ENCIFOE06.
IOPORT_PIN_P337_PFC_25_HDSL10_LINK	P33_7 / HDSLn / HDSL10_LINK.
IOPORT_PIN_P340_PFC_04_A22	P34_0 / BSC / A22.
IOPORT_PIN_P340_PFC_09_GTADSM03_0	P34_0 / GPT / GTADSM03_0.
IOPORT_PIN_P340_PFC_0A_GTIOC03_0A	P34_0 / GPT / GTIOC03_0A.
IOPORT_PIN_P340_PFC_0F_ETH3_RXCLK	P34_0 / ETHER_ETHn / ETH3_RXCLK.
IOPORT_PIN_P340_PFC_15_TXDE06	P34_0 / SCIEn / TXDE06.
IOPORT_PIN_P340_PFC_1A_SPI_MOSI2	P34_0 / SPIn / SPI_MOSI2.
IOPORT_PIN_P340_PFC_22_ENCIFDO06	P34_0 / ENCIFn / ENCIFDO06.
IOPORT_PIN_P340_PFC_25_HDSL10_SMPL	P34_0 / HDSLn / HDSL10_SMPL.
IOPORT_PIN_P341_PFC_04_A23	P34_1 / BSC / A23.
IOPORT_PIN_P341_PFC_09_GTADSM03_1	P34_1 / GPT / GTADSM03_1.
IOPORT_PIN_P341_PFC_0A_GTIOC03_0B	P34_1 / GPT / GTIOC03_0B.
IOPORT_PIN_P341_PFC_0F_ETH3_RXD0	P34_1 / ETHER_ETHn / ETH3_RXD0.
IOPORT_PIN_P341_PFC_15_RXDE06	P34_1 / SCIEn / RXDE06.
IOPORT_PIN_P341_PFC_1A_SPI_MISO2	P34_1 / SPIn / SPI_MISO2.
IOPORT_PIN_P341_PFC_22_ENCIFDI06	P34_1 / ENCIFn / ENCIFDI06.
IOPORT_PIN_P341_PFC_25_HDSL10_CLK1	P34_1 / HDSLn / HDSL10_CLK1.
IOPORT_PIN_P342_PFC_04_A24	P34_2 / BSC / A24.
IOPORT_PIN_P342_PFC_09_GTADSM04_0	P34_2 / GPT / GTADSM04_0.
IOPORT_PIN_P342_PFC_0A_GTIOC03_1A	P34_2 / GPT / GTIOC03_1A.
IOPORT_PIN_P342_PFC_0F_ETH3_RXD1	P34_2 / ETHER_ETHn / ETH3_RXD1.
IOPORT_PIN_P342_PFC_15_SCKE07	P34_2 / SCIEn / SCKE07.
IOPORT_PIN_P342_PFC_1A_SPI_SSL20	P34_2 / SPIn / SPI_SSL20.
IOPORT_PIN_P342_PFC_22_ENCIFCK07	P34_2 / ENCIFn / ENCIFCK07.
IOPORT_PIN_P342_PFC_25_HDSL10_SEL1	P34_2 / HDSLn / HDSL10_SEL1.
IOPORT_PIN_P343_PFC_04_A25	P34_3 / BSC / A25.
IOPORT_PIN_P343_PFC_09_GTADSM04_1	P34_3 / GPT / GTADSM04_1.
IOPORT_PIN_P343_PFC_0A_GTIOC03_1B	P34_3 / GPT / GTIOC03_1B.
IOPORT_PIN_P343_PFC_0F_ETH3_RXD2	P34_3 / ETHER_ETHn / ETH3_RXD2.
IOPORT_PIN_P343_PFC_15_DEE07	P34_3 / SCIEn / DEE07.
IOPORT_PIN_P343_PFC_1A_SPI_SSL21	P34_3 / SPIn / SPI_SSL21.
IOPORT_PIN_P343_PFC_22_ENCIFOE07	P34_3 / ENCIFn / ENCIFOE07.
IOPORT_PIN_P343_PFC_25_HDSL10_MISO1	P34_3 / HDSLn / HDSL10_MISO1.
IOPORT_PIN_P343_PFC_29_SD1_PWEN	P34_3 / SDHI / SD1_PWEN.
IOPORT_PIN_P344_PFC_04_CS2	P34_4 / BSC / CS2.
IOPORT_PIN_P344_PFC_09_GTADSM05_0	P34_4 / GPT / GTADSM05_0.
IOPORT_PIN_P344_PFC_0A_GTIOC03_2A	P34_4 / GPT / GTIOC03_2A.
IOPORT_PIN_P344_PFC_0F_ETH3_RXD3	P34_4 / ETHER_ETHn / ETH3_RXD3.
IOPORT_PIN_P344_PFC_14_RXD3_SCL3_MISO3	P34_4 / SCIn / RXD3_SCL3_MISO3.
IOPORT_PIN_P344_PFC_15_TXDE07	P34_4 / SCIEn / TXDE07.
IOPORT_PIN_P344_PFC_1A_SPI_SSL22	P34_4 / SPIn / SPI_SSL22.
IOPORT_PIN_P344_PFC_1F_ADTRG0	P34_4 / ADCn / ADTRG0.
IOPORT_PIN_P344_PFC_22_ENCIFDO07	P34_4 / ENCIFn / ENCIFDO07.
IOPORT_PIN_P344_PFC_25_HDSL10_MOSI1	P34_4 / HDSLn / HDSL10_MOSI1.
IOPORT_PIN_P344_PFC_29_SD1_IOVS	P34_4 / SDHI / SD1_IOVS.
IOPORT_PIN_P345_PFC_04_CS3	P34_5 / BSC / CS3.
IOPORT_PIN_P345_PFC_09_GTADSM05_1	P34_5 / GPT / GTADSM05_1.
IOPORT_PIN_P345_PFC_0A_GTIOC03_2B	P34_5 / GPT / GTIOC03_2B.
IOPORT_PIN_P345_PFC_0F_ETH3_RXDV	P34_5 / ETHER_ETHn / ETH3_RXDV.
IOPORT_PIN_P345_PFC_12_ESC_I2CCLK	P34_5 / ETHER_ESC / ESC_I2CCLK.
IOPORT_PIN_P345_PFC_14_TXD3_SDA3_MOSI3	P34_5 / SCIn / TXD3_SDA3_MOSI3.
IOPORT_PIN_P345_PFC_15_RXDE07	P34_5 / SCIEn / RXDE07.
IOPORT_PIN_P345_PFC_17_IIC_SCL1	P34_5 / IICn / IIC_SCL1.
IOPORT_PIN_P345_PFC_1A_SPI_SSL23	P34_5 / SPIn / SPI_SSL23.
IOPORT_PIN_P345_PFC_1F_ADTRG1	P34_5 / ADCn / ADTRG1.
IOPORT_PIN_P345_PFC_22_ENCIFDI07	P34_5 / ENCIFn / ENCIFDI07.
IOPORT_PIN_P345_PFC_25_HDSL10_CLK2	P34_5 / HDSLn / HDSL10_CLK2.
IOPORT_PIN_P346_PFC_02_ETH3_REFCLK	P34_6 / ETHER_ETHn / ETH3_REFCLK.
IOPORT_PIN_P346_PFC_03_RMII3_REFCLK	P34_6 / ETHER_ETHn / RMII3_REFCLK.
IOPORT_PIN_P346_PFC_04_CS5	P34_6 / BSC / CS5.
IOPORT_PIN_P346_PFC_0F_ETH1_RXER	P34_6 / ETHER_ETHn / ETH1_RXER.
IOPORT_PIN_P346_PFC_12_ESC_I2CDATA	P34_6 / ETHER_ESC / ESC_I2CDATA.
IOPORT_PIN_P346_PFC_17_IIC_SDA1	P34_6 / IICn / IIC_SDA1.
IOPORT_PIN_P346_PFC_1A_SPI_RSPCK3	P34_6 / SPIn / SPI_RSPCK3.
IOPORT_PIN_P346_PFC_1F_ADTRG2	P34_6 / ADCn / ADTRG2.
IOPORT_PIN_P346_PFC_24_DUEI08	P34_6 / ENDATn / DUEI08.
IOPORT_PIN_P346_PFC_25_HDSL10_SEL2	P34_6 / HDSLn / HDSL10_SEL2.
IOPORT_PIN_P347_PFC_00_IRQ14	P34_7 / IRQ / IRQ14.
IOPORT_PIN_P347_PFC_05_DREQ	P34_7 / DMAC / DREQ.
IOPORT_PIN_P347_PFC_09_GTADSM06_0	P34_7 / GPT / GTADSM06_0.
IOPORT_PIN_P347_PFC_0F_ETH3_TXER	P34_7 / ETHER_ETHn / ETH3_TXER.
IOPORT_PIN_P347_PFC_12_ESC_RESETOUT_N	P34_7 / ETHER_ESC / ESC_RESETOUT_N.
IOPORT_PIN_P347_PFC_1A_SPI_MOSI3	P34_7 / SPIn / SPI_MOSI3.
IOPORT_PIN_P347_PFC_24_TST_OUT08	P34_7 / ENDATn / TST_OUT08.
IOPORT_PIN_P347_PFC_25_HDSL10_MISO2	P34_7 / HDSLn / HDSL10_MISO2.
IOPORT_PIN_P350_PFC_05_DACK	P35_0 / DMAC / DACK.
IOPORT_PIN_P350_PFC_09_GTADSM06_1	P35_0 / GPT / GTADSM06_1.
IOPORT_PIN_P350_PFC_0F_ETH3_RXER	P35_0 / ETHER_ETHn / ETH3_RXER.
IOPORT_PIN_P350_PFC_1A_SPI_MISO3	P35_0 / SPIn / SPI_MISO3.
IOPORT_PIN_P350_PFC_24_SI08	P35_0 / ENDATn / SI08.
IOPORT_PIN_P350_PFC_25_HDSL10_MOSI2	P35_0 / HDSLn / HDSL10_MOSI2.
IOPORT_PIN_P351_PFC_05_TEND	P35_1 / DMAC / TEND.
IOPORT_PIN_P351_PFC_09_GTADSM07_0	P35_1 / GPT / GTADSM07_0.
IOPORT_PIN_P351_PFC_0F_ETH3_CRS	P35_1 / ETHER_ETHn / ETH3_CRS.
IOPORT_PIN_P351_PFC_1A_SPI_SSL30	P35_1 / SPIn / SPI_SSL30.
IOPORT_PIN_P351_PFC_1B_SPI_MISO1	P35_1 / SPIn / SPI_MISO1.
IOPORT_PIN_P351_PFC_1D_MCLK90	P35_1 / DSMIFn / MCLK90.
IOPORT_PIN_P351_PFC_24_DUEI09	P35_1 / ENDATn / DUEI09.
IOPORT_PIN_P351_PFC_25_HDSL11_LINK	P35_1 / HDSLn / HDSL11_LINK.
IOPORT_PIN_P352_PFC_09_GTADSM07_1	P35_2 / GPT / GTADSM07_1.
IOPORT_PIN_P352_PFC_0F_ETH3_COL	P35_2 / ETHER_ETHn / ETH3_COL.
IOPORT_PIN_P352_PFC_1A_SPI_SSL31	P35_2 / SPIn / SPI_SSL31.
IOPORT_PIN_P352_PFC_1B_SPI_SSL10	P35_2 / SPIn / SPI_SSL10.
IOPORT_PIN_P352_PFC_1D_MDAT90	P35_2 / DSMIFn / MDAT90.
IOPORT_PIN_P352_PFC_1F_ADTRG2	P35_2 / ADCn / ADTRG2.
IOPORT_PIN_P352_PFC_24_TST_OUT09	P35_2 / ENDATn / TST_OUT09.
IOPORT_PIN_P352_PFC_25_HDSL11_SMPL	P35_2 / HDSLn / HDSL11_SMPL.
IOPORT_PIN_P353_PFC_09_GTADSM08_0	P35_3 / GPT / GTADSM08_0.
IOPORT_PIN_P353_PFC_1A_SPI_SSL32	P35_3 / SPIn / SPI_SSL32.
IOPORT_PIN_P353_PFC_1B_SPI_MOSI1	P35_3 / SPIn / SPI_MOSI1.
IOPORT_PIN_P353_PFC_1D_MCLK91	P35_3 / DSMIFn / MCLK91.
IOPORT_PIN_P353_PFC_1F_ADTRG0	P35_3 / ADCn / ADTRG0.
IOPORT_PIN_P353_PFC_24_SI09	P35_3 / ENDATn / SI09.
IOPORT_PIN_P353_PFC_25_HDSL11_CLK1	P35_3 / HDSLn / HDSL11_CLK1.
IOPORT_PIN_P354_PFC_09_GTADSM08_1	P35_4 / GPT / GTADSM08_1.
IOPORT_PIN_P354_PFC_1A_SPI_SSL33	P35_4 / SPIn / SPI_SSL33.
IOPORT_PIN_P354_PFC_1B_SPI_SSL11	P35_4 / SPIn / SPI_SSL11.
IOPORT_PIN_P354_PFC_1D_MDAT91	P35_4 / DSMIFn / MDAT91.
IOPORT_PIN_P354_PFC_1F_ADTRG1	P35_4 / ADCn / ADTRG1.
IOPORT_PIN_P354_PFC_24_DUEI10	P35_4 / ENDATn / DUEI10.
IOPORT_PIN_P354_PFC_25_HDSL11_SEL1	P35_4 / HDSLn / HDSL11_SEL1.
IOPORT_PIN_P355_PFC_09_GTADSM09_0	P35_5 / GPT / GTADSM09_0.
IOPORT_PIN_P355_PFC_14_RXD4_SCL4_MISO4	P35_5 / SCIn / RXD4_SCL4_MISO4.
IOPORT_PIN_P355_PFC_1B_SPI_RSPCK1	P35_5 / SPIn / SPI_RSPCK1.
IOPORT_PIN_P355_PFC_1D_MCLK92	P35_5 / DSMIFn / MCLK92.
IOPORT_PIN_P355_PFC_24_TST_OUT10	P35_5 / ENDATn / TST_OUT10.
IOPORT_PIN_P355_PFC_25_HDSL11_MISO1	P35_5 / HDSLn / HDSL11_MISO1.
IOPORT_PIN_P356_PFC_09_GTADSM09_1	P35_6 / GPT / GTADSM09_1.
IOPORT_PIN_P356_PFC_14_TXD4_SDA4_MOSI4	P35_6 / SCIn / TXD4_SDA4_MOSI4.
IOPORT_PIN_P356_PFC_1B_SPI_SSL12	P35_6 / SPIn / SPI_SSL12.
IOPORT_PIN_P356_PFC_1D_MDAT92	P35_6 / DSMIFn / MDAT92.
IOPORT_PIN_P356_PFC_24_SI10	P35_6 / ENDATn / SI10.
IOPORT_PIN_P356_PFC_25_HDSL11_MOSI1	P35_6 / HDSLn / HDSL11_MOSI1.
IOPORT_PERIPHERAL_END	Marks end of enum - used by parameter checking
IOPORT_PIN_P000_PFC_00_ETH2_RXD3	P00_0 / ETHER_ETHn / ETH2_RXD3.
IOPORT_PIN_P000_PFC_02_D15	P00_0 / BSC / D15.
IOPORT_PIN_P000_PFC_03_SCK2	P00_0 / SCIn / SCK2.
IOPORT_PIN_P000_PFC_04_DE2	P00_0 / SCIn / DE2.
IOPORT_PIN_P000_PFC_05_HD15	P00_0 / PHOSTIF / HD15.
IOPORT_PIN_P001_PFC_00_IRQ0	P00_1 / IRQ / IRQ0.
IOPORT_PIN_P001_PFC_01_ETH2_RXDV	P00_1 / ETHER_ETHn / ETH2_RXDV.
IOPORT_PIN_P001_PFC_03_A13	P00_1 / BSC / A13.
IOPORT_PIN_P001_PFC_04_MTIC5U	P00_1 / MTU3n / MTIC5U.
IOPORT_PIN_P001_PFC_05_RXD2_SCL2_MISO2	P00_1 / SCIn / RXD2_SCL2_MISO2.
IOPORT_PIN_P002_PFC_00_ETH2_TXEN	P00_2 / ETHER_ETHn / ETH2_TXEN.
IOPORT_PIN_P002_PFC_02_RD	P00_2 / BSC / RD.
IOPORT_PIN_P002_PFC_03_MTIC5V	P00_2 / MTU3n / MTIC5V.
IOPORT_PIN_P002_PFC_04_TXD2_SDA2_MOSI2	P00_2 / SCIn / TXD2_SDA2_MOSI2.
IOPORT_PIN_P002_PFC_05_USB_OVRCUR	P00_2 / USB_HS / USB_OVRCUR.
IOPORT_PIN_P003_PFC_00_IRQ1	P00_3 / IRQ / IRQ1.
IOPORT_PIN_P003_PFC_01_ETH2_REFCLK	P00_3 / ETHER_ETHn / ETH2_REFCLK.
IOPORT_PIN_P003_PFC_02_RMII2_REFCLK	P00_3 / ETHER_ETHn / RMII2_REFCLK.
IOPORT_PIN_P003_PFC_04_RD_WR	P00_3 / BSC / RD_WR.
IOPORT_PIN_P003_PFC_05_MTIC5W	P00_3 / MTU3n / MTIC5W.
IOPORT_PIN_P003_PFC_06_SS2_CTS2_RTS2	P00_3 / SCIn / SS2_CTS2_RTS2.
IOPORT_PIN_P004_PFC_00_IRQ13	P00_4 / IRQ / IRQ13.
IOPORT_PIN_P004_PFC_01_ETH2_RXER	P00_4 / ETHER_ETHn / ETH2_RXER.
IOPORT_PIN_P004_PFC_03_WAIT	P00_4 / BSC / WAIT.
IOPORT_PIN_P004_PFC_04_MTIOC3A	P00_4 / MTU3n / MTIOC3A.
IOPORT_PIN_P004_PFC_05_GTIOC0A	P00_4 / GPTn / GTIOC0A.
IOPORT_PIN_P004_PFC_06_MCLK0	P00_4 / DSMIFn / MCLK0.
IOPORT_PIN_P004_PFC_07_HWAIT	P00_4 / PHOSTIF / HWAIT.
IOPORT_PIN_P005_PFC_00_ETHSW_PHYLINK2	P00_5 / ETHER_ETHSW / ETHSW_PHYLINK2.
IOPORT_PIN_P005_PFC_02_CS0	P00_5 / BSC / CS0.
IOPORT_PIN_P005_PFC_03_ESC_PHYLINK2	P00_5 / ETHER_ESC / ESC_PHYLINK2.
IOPORT_PIN_P005_PFC_04_MTIOC3C	P00_5 / MTU3n / MTIOC3C.
IOPORT_PIN_P005_PFC_05_GTIOC0B	P00_5 / GPTn / GTIOC0B.
IOPORT_PIN_P005_PFC_06_MDAT0	P00_5 / DSMIFn / MDAT0.
IOPORT_PIN_P005_PFC_07_ETHSW_PHYLINK0	P00_5 / ETHER_ETHSW / ETHSW_PHYLINK0.
IOPORT_PIN_P005_PFC_08_ESC_PHYLINK0	P00_5 / ETHER_ESC / ESC_PHYLINK0.
IOPORT_PIN_P006_PFC_00_ETH2_TXCLK	P00_6 / ETHER_ETHn / ETH2_TXCLK.
IOPORT_PIN_P006_PFC_01_CS5	P00_6 / BSC / CS5.
IOPORT_PIN_P006_PFC_02_MTIOC3B	P00_6 / MTU3n / MTIOC3B.
IOPORT_PIN_P006_PFC_03_GTIOC1A	P00_6 / GPTn / GTIOC1A.
IOPORT_PIN_P007_PFC_00_IRQ13	P00_7 / IRQ / IRQ13.
IOPORT_PIN_P007_PFC_01_RAS	P00_7 / BSC / RAS.
IOPORT_PIN_P007_PFC_02_MTIOC4A	P00_7 / MTU3n / MTIOC4A.
IOPORT_PIN_P007_PFC_03_GTIOC2A	P00_7 / GPTn / GTIOC2A.
IOPORT_PIN_P010_PFC_00_GMAC_MDIO	P01_0 / ETHER_GMAC / GMAC_MDIO.
IOPORT_PIN_P010_PFC_01_ETHSW_MDIO	P01_0 / ETHER_ETHSW / ETHSW_MDIO.
IOPORT_PIN_P010_PFC_02_CAS	P01_0 / BSC / CAS.
IOPORT_PIN_P010_PFC_03_ESC_MDIO	P01_0 / ETHER_ESC / ESC_MDIO.
IOPORT_PIN_P010_PFC_04_MTIOC4C	P01_0 / MTU3n / MTIOC4C.
IOPORT_PIN_P010_PFC_05_GTIOC3A	P01_0 / GPTn / GTIOC3A.
IOPORT_PIN_P010_PFC_06_CTS2	P01_0 / SCIn / CTS2.
IOPORT_PIN_P010_PFC_07_MCLK1	P01_0 / DSMIFn / MCLK1.
IOPORT_PIN_P011_PFC_00_GMAC_MDC	P01_1 / ETHER_GMAC / GMAC_MDC.
IOPORT_PIN_P011_PFC_01_ETHSW_MDC	P01_1 / ETHER_ETHSW / ETHSW_MDC.
IOPORT_PIN_P011_PFC_02_CKE	P01_1 / BSC / CKE.
IOPORT_PIN_P011_PFC_03_ESC_MDC	P01_1 / ETHER_ESC / ESC_MDC.
IOPORT_PIN_P011_PFC_04_MTIOC3D	P01_1 / MTU3n / MTIOC3D.
IOPORT_PIN_P011_PFC_05_GTIOC1B	P01_1 / GPTn / GTIOC1B.
IOPORT_PIN_P011_PFC_06_DE2	P01_1 / SCIn / DE2.
IOPORT_PIN_P011_PFC_07_MDAT1	P01_1 / DSMIFn / MDAT1.
IOPORT_PIN_P012_PFC_00_IRQ2	P01_2 / IRQ / IRQ2.
IOPORT_PIN_P012_PFC_01_ETH2_TXD3	P01_2 / ETHER_ETHn / ETH2_TXD3.
IOPORT_PIN_P012_PFC_02_CS2	P01_2 / BSC / CS2.
IOPORT_PIN_P012_PFC_03_MTIOC4B	P01_2 / MTU3n / MTIOC4B.
IOPORT_PIN_P012_PFC_04_GTIOC2B	P01_2 / GPTn / GTIOC2B.
IOPORT_PIN_P013_PFC_00_ETH2_TXD2	P01_3 / ETHER_ETHn / ETH2_TXD2.
IOPORT_PIN_P013_PFC_01_AH	P01_3 / BSC / AH.
IOPORT_PIN_P013_PFC_02_MTIOC4D	P01_3 / MTU3n / MTIOC4D.
IOPORT_PIN_P013_PFC_03_GTIOC3B	P01_3 / GPTn / GTIOC3B.
IOPORT_PIN_P014_PFC_00_IRQ3	P01_4 / IRQ / IRQ3.
IOPORT_PIN_P014_PFC_01_ETH2_TXD1	P01_4 / ETHER_ETHn / ETH2_TXD1.
IOPORT_PIN_P014_PFC_02_WE1_DQMLU	P01_4 / BSC / WE1_DQMLU.
IOPORT_PIN_P014_PFC_03_POE0	P01_4 / MTU_POE3 / POE0.
IOPORT_PIN_P015_PFC_00_ETH2_TXD0	P01_5 / ETHER_ETHn / ETH2_TXD0.
IOPORT_PIN_P015_PFC_01_WE0_DQMLL	P01_5 / BSC / WE0_DQMLL.
IOPORT_PIN_P016_PFC_00_GMAC_PTPTRG1	P01_6 / ETHER_GMAC / GMAC_PTPTRG1.
IOPORT_PIN_P016_PFC_01_TRACEDATA0	P01_6 / TRACE / TRACEDATA0.
IOPORT_PIN_P016_PFC_02_A20	P01_6 / BSC / A20.
IOPORT_PIN_P016_PFC_03_ESC_LATCH1	P01_6 / ETHER_ESC / ESC_LATCH1.
IOPORT_PIN_P016_PFC_04_ESC_LATCH0	P01_6 / ETHER_ESC / ESC_LATCH0.
IOPORT_PIN_P016_PFC_05_MTIOC1A	P01_6 / MTU3n / MTIOC1A.
IOPORT_PIN_P016_PFC_06_GTIOC9A	P01_6 / GPTn / GTIOC9A.
IOPORT_PIN_P016_PFC_07_CTS1	P01_6 / SCIn / CTS1.
IOPORT_PIN_P016_PFC_08_CANTXDP1	P01_6 / CANFDn / CANTXDP1.
IOPORT_PIN_P016_PFC_0A_HA20	P01_6 / PHOSTIF / HA20.
IOPORT_PIN_P017_PFC_00_ETHSW_LPI1	P01_7 / ETHER_ETHSW / ETHSW_LPI1.
IOPORT_PIN_P017_PFC_01_TRACEDATA1	P01_7 / TRACE / TRACEDATA1.
IOPORT_PIN_P017_PFC_02_A19	P01_7 / BSC / A19.
IOPORT_PIN_P017_PFC_03_MTIOC1B	P01_7 / MTU3n / MTIOC1B.
IOPORT_PIN_P017_PFC_04_GTIOC9B	P01_7 / GPTn / GTIOC9B.
IOPORT_PIN_P017_PFC_05_ADTRG0	P01_7 / ADCn / ADTRG0.
IOPORT_PIN_P017_PFC_06_SCK1	P01_7 / SCIn / SCK1.
IOPORT_PIN_P017_PFC_07_SPI_RSPCK3	P01_7 / SPIn / SPI_RSPCK3.
IOPORT_PIN_P017_PFC_08_CANRX0	P01_7 / CANFDn / CANRX0.
IOPORT_PIN_P017_PFC_0A_HA19	P01_7 / PHOSTIF / HA19.
IOPORT_PIN_P020_PFC_00_IRQ4	P02_0 / IRQ / IRQ4.
IOPORT_PIN_P020_PFC_01_ETHSW_LPI2	P02_0 / ETHER_ETHSW / ETHSW_LPI2.
IOPORT_PIN_P020_PFC_02_TRACEDATA2	P02_0 / TRACE / TRACEDATA2.
IOPORT_PIN_P020_PFC_03_A18	P02_0 / BSC / A18.
IOPORT_PIN_P020_PFC_04_GTADSML0	P02_0 / GPT / GTADSML0.
IOPORT_PIN_P020_PFC_05_RXD1_SCL1_MISO1	P02_0 / SCIn / RXD1_SCL1_MISO1.
IOPORT_PIN_P020_PFC_06_SPI_MISO3	P02_0 / SPIn / SPI_MISO3.
IOPORT_PIN_P020_PFC_07_CANTX1	P02_0 / CANFDn / CANTX1.
IOPORT_PIN_P020_PFC_08_USB_OTGID	P02_0 / USB_HS / USB_OTGID.
IOPORT_PIN_P020_PFC_0A_HA18	P02_0 / PHOSTIF / HA18.
IOPORT_PIN_P021_PFC_00_ETHSW_PTPOUT1	P02_1 / ETHER_ETHSW / ETHSW_PTPOUT1.
IOPORT_PIN_P021_PFC_01_A17	P02_1 / BSC / A17.
IOPORT_PIN_P021_PFC_02_ESC_SYNC1	P02_1 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P021_PFC_03_ESC_SYNC0	P02_1 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P021_PFC_04_DE1	P02_1 / SCIn / DE1.
IOPORT_PIN_P021_PFC_05_HA17	P02_1 / PHOSTIF / HA17.
IOPORT_PIN_P022_PFC_00_IRQ14	P02_2 / IRQ / IRQ14.
IOPORT_PIN_P022_PFC_01_ETHSW_TDMAOUT0	P02_2 / ETHER_ETHSW / ETHSW_TDMAOUT0.
IOPORT_PIN_P022_PFC_02_A16	P02_2 / BSC / A16.
IOPORT_PIN_P022_PFC_03_MTIOC2A	P02_2 / MTU3n / MTIOC2A.
IOPORT_PIN_P022_PFC_04_GTIOC10A	P02_2 / GPTn / GTIOC10A.
IOPORT_PIN_P022_PFC_05_POE10	P02_2 / MTU_POE3 / POE10.
IOPORT_PIN_P022_PFC_06_TXD1_SDA1_MOSI1	P02_2 / SCIn / TXD1_SDA1_MOSI1.
IOPORT_PIN_P022_PFC_07_SPI_MOSI3	P02_2 / SPIn / SPI_MOSI3.
IOPORT_PIN_P022_PFC_08_CANTX0	P02_2 / CANFDn / CANTX0.
IOPORT_PIN_P022_PFC_0A_RTCAT1HZ	P02_2 / RTC / RTCAT1HZ.
IOPORT_PIN_P022_PFC_0B_HA16	P02_2 / PHOSTIF / HA16.
IOPORT_PIN_P023_PFC_00_IRQ15	P02_3 / IRQ / IRQ15.
IOPORT_PIN_P023_PFC_01_ETHSW_TDMAOUT1	P02_3 / ETHER_ETHSW / ETHSW_TDMAOUT1.
IOPORT_PIN_P023_PFC_02_A15	P02_3 / BSC / A15.
IOPORT_PIN_P023_PFC_03_AH	P02_3 / BSC / AH.
IOPORT_PIN_P023_PFC_04_MTIOC2B	P02_3 / MTU3n / MTIOC2B.
IOPORT_PIN_P023_PFC_05_GTIOC10B	P02_3 / GPTn / GTIOC10B.
IOPORT_PIN_P023_PFC_06_POE11	P02_3 / MTU_POE3 / POE11.
IOPORT_PIN_P023_PFC_07_SS1_CTS1_RTS1	P02_3 / SCIn / SS1_CTS1_RTS1.
IOPORT_PIN_P023_PFC_08_SPI_SSL30	P02_3 / SPIn / SPI_SSL30.
IOPORT_PIN_P023_PFC_09_CANRX1	P02_3 / CANFDn / CANRX1.
IOPORT_PIN_P023_PFC_0B_HA15	P02_3 / PHOSTIF / HA15.
IOPORT_PIN_P024_PFC_00_TDO	P02_4 / JTAG/SWD / TDO.
IOPORT_PIN_P024_PFC_01_WE0_DQMLL	P02_4 / BSC / WE0_DQMLL.
IOPORT_PIN_P024_PFC_02_DE1	P02_4 / SCIn / DE1.
IOPORT_PIN_P024_PFC_03_SPI_SSL33	P02_4 / SPIn / SPI_SSL33.
IOPORT_PIN_P025_PFC_00_ETHSW_TDMAOUT3	P02_5 / ETHER_ETHSW / ETHSW_TDMAOUT3.
IOPORT_PIN_P025_PFC_01_TDI	P02_5 / JTAG/SWD / TDI.
IOPORT_PIN_P025_PFC_02_WE1_DQMLU	P02_5 / BSC / WE1_DQMLU.
IOPORT_PIN_P025_PFC_03_SCK5	P02_5 / SCIn / SCK5.
IOPORT_PIN_P025_PFC_04_SPI_SSL31	P02_5 / SPIn / SPI_SSL31.
IOPORT_PIN_P026_PFC_00_TMS_SWDIO	P02_6 / JTAG/SWD / TMS_SWDIO.
IOPORT_PIN_P026_PFC_01_RXD5_SCL5_MISO5	P02_6 / SCIn / RXD5_SCL5_MISO5.
IOPORT_PIN_P027_PFC_00_TCK_SWCLK	P02_7 / JTAG/SWD / TCK_SWCLK.
IOPORT_PIN_P027_PFC_01_TXD5_SDA5_MOSI5	P02_7 / SCIn / TXD5_SDA5_MOSI5.
IOPORT_PIN_P030_PFC_00_IRQ14	P03_0 / IRQ / IRQ14.
IOPORT_PIN_P030_PFC_01_TRACEDATA3	P03_0 / TRACE / TRACEDATA3.
IOPORT_PIN_P030_PFC_02_A14	P03_0 / BSC / A14.
IOPORT_PIN_P030_PFC_03_CS5	P03_0 / BSC / CS5.
IOPORT_PIN_P030_PFC_04_GTADSML1	P03_0 / GPT / GTADSML1.
IOPORT_PIN_P030_PFC_05_SCK2	P03_0 / SCIn / SCK2.
IOPORT_PIN_P030_PFC_06_SPI_SSL32	P03_0 / SPIn / SPI_SSL32.
IOPORT_PIN_P030_PFC_07_CANTXDP1	P03_0 / CANFDn / CANTXDP1.
IOPORT_PIN_P030_PFC_09_HA14	P03_0 / PHOSTIF / HA14.
IOPORT_PIN_P035_PFC_00_IRQ5	P03_5 / IRQ / IRQ5.
IOPORT_PIN_P035_PFC_01_ETH2_CRS	P03_5 / ETHER_ETHn / ETH2_CRS.
IOPORT_PIN_P035_PFC_02_A12	P03_5 / BSC / A12.
IOPORT_PIN_P035_PFC_03_MTIOC3A	P03_5 / MTU3n / MTIOC3A.
IOPORT_PIN_P035_PFC_04_GTIOC4A	P03_5 / GPTn / GTIOC4A.
IOPORT_PIN_P035_PFC_05_RXD2_SCL2_MISO2	P03_5 / SCIn / RXD2_SCL2_MISO2.
IOPORT_PIN_P035_PFC_06_MCLK2	P03_5 / DSMIFn / MCLK2.
IOPORT_PIN_P035_PFC_07_HA12	P03_5 / PHOSTIF / HA12.
IOPORT_PIN_P036_PFC_00_IRQ8	P03_6 / IRQ / IRQ8.
IOPORT_PIN_P036_PFC_01_ETH2_COL	P03_6 / ETHER_ETHn / ETH2_COL.
IOPORT_PIN_P036_PFC_02_TRACEDATA4	P03_6 / TRACE / TRACEDATA4.
IOPORT_PIN_P036_PFC_03_A11	P03_6 / BSC / A11.
IOPORT_PIN_P036_PFC_04_MTIOC3B	P03_6 / MTU3n / MTIOC3B.
IOPORT_PIN_P036_PFC_05_GTIOC4B	P03_6 / GPTn / GTIOC4B.
IOPORT_PIN_P036_PFC_06_TXD2_SDA2_MOSI2	P03_6 / SCIn / TXD2_SDA2_MOSI2.
IOPORT_PIN_P036_PFC_07_SPI_SSL13	P03_6 / SPIn / SPI_SSL13.
IOPORT_PIN_P036_PFC_08_MDAT2	P03_6 / DSMIFn / MDAT2.
IOPORT_PIN_P036_PFC_09_HA11	P03_6 / PHOSTIF / HA11.
IOPORT_PIN_P037_PFC_00_IRQ9	P03_7 / IRQ / IRQ9.
IOPORT_PIN_P037_PFC_01_ETH2_TXER	P03_7 / ETHER_ETHn / ETH2_TXER.
IOPORT_PIN_P037_PFC_02_TRACEDATA5	P03_7 / TRACE / TRACEDATA5.
IOPORT_PIN_P037_PFC_03_A10	P03_7 / BSC / A10.
IOPORT_PIN_P037_PFC_04_MTIOC3C	P03_7 / MTU3n / MTIOC3C.
IOPORT_PIN_P037_PFC_05_GTIOC5A	P03_7 / GPTn / GTIOC5A.
IOPORT_PIN_P037_PFC_06_SCK3	P03_7 / SCIn / SCK3.
IOPORT_PIN_P037_PFC_07_HA10	P03_7 / PHOSTIF / HA10.
IOPORT_PIN_P040_PFC_00_TRACEDATA6	P04_0 / TRACE / TRACEDATA6.
IOPORT_PIN_P040_PFC_01_A9	P04_0 / BSC / A9.
IOPORT_PIN_P040_PFC_02_MTIOC3D	P04_0 / MTU3n / MTIOC3D.
IOPORT_PIN_P040_PFC_03_GTIOC5B	P04_0 / GPTn / GTIOC5B.
IOPORT_PIN_P040_PFC_04_RXD3_SCL3_MISO3	P04_0 / SCIn / RXD3_SCL3_MISO3.
IOPORT_PIN_P040_PFC_05_HA9	P04_0 / PHOSTIF / HA9.
IOPORT_PIN_P041_PFC_00_CKIO	P04_1 / BSC / CKIO.
IOPORT_PIN_P041_PFC_01_TXD3_SDA3_MOSI3	P04_1 / SCIn / TXD3_SDA3_MOSI3.
IOPORT_PIN_P041_PFC_02_SPI_MOSI0	P04_1 / SPIn / SPI_MOSI0.
IOPORT_PIN_P041_PFC_03_IIC_SDA2	P04_1 / IICn / IIC_SDA2.
IOPORT_PIN_P041_PFC_04_HCKIO	P04_1 / PHOSTIF / HCKIO.
IOPORT_PIN_P044_PFC_00_IRQ10	P04_4 / IRQ / IRQ10.
IOPORT_PIN_P044_PFC_01_TRACEDATA7	P04_4 / TRACE / TRACEDATA7.
IOPORT_PIN_P044_PFC_02_A8	P04_4 / BSC / A8.
IOPORT_PIN_P044_PFC_03_GTADSMP0	P04_4 / GPT / GTADSMP0.
IOPORT_PIN_P044_PFC_04_POE10	P04_4 / MTU_POE3 / POE10.
IOPORT_PIN_P044_PFC_05_CTS3	P04_4 / SCIn / CTS3.
IOPORT_PIN_P044_PFC_06_SPI_RSPCK1	P04_4 / SPIn / SPI_RSPCK1.
IOPORT_PIN_P044_PFC_08_HA8	P04_4 / PHOSTIF / HA8.
IOPORT_PIN_P045_PFC_00_A7	P04_5 / BSC / A7.
IOPORT_PIN_P045_PFC_01_DE3	P04_5 / SCIn / DE3.
IOPORT_PIN_P045_PFC_02_ETHSW_PTPOUT0	P04_5 / ETHER_ETHSW / ETHSW_PTPOUT0.
IOPORT_PIN_P045_PFC_03_ESC_SYNC0	P04_5 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P045_PFC_04_ESC_SYNC1	P04_5 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P045_PFC_05_HA7	P04_5 / PHOSTIF / HA7.
IOPORT_PIN_P046_PFC_00_ETH1_TXER	P04_6 / ETHER_ETHn / ETH1_TXER.
IOPORT_PIN_P046_PFC_01_A6	P04_6 / BSC / A6.
IOPORT_PIN_P046_PFC_02_DACK	P04_6 / DMAC / DACK.
IOPORT_PIN_P046_PFC_03_RTCAT1HZ	P04_6 / RTC / RTCAT1HZ.
IOPORT_PIN_P046_PFC_04_HA6	P04_6 / PHOSTIF / HA6.
IOPORT_PIN_P047_PFC_00_ETH0_TXER	P04_7 / ETHER_ETHn / ETH0_TXER.
IOPORT_PIN_P047_PFC_01_A5	P04_7 / BSC / A5.
IOPORT_PIN_P047_PFC_02_SPI_SSL21	P04_7 / SPIn / SPI_SSL21.
IOPORT_PIN_P047_PFC_03_ETH2_TXER	P04_7 / ETHER_ETHn / ETH2_TXER.
IOPORT_PIN_P047_PFC_04_HA5	P04_7 / PHOSTIF / HA5.
IOPORT_PIN_P050_PFC_00_IRQ12	P05_0 / IRQ / IRQ12.
IOPORT_PIN_P050_PFC_01_ETH1_CRS	P05_0 / ETHER_ETHn / ETH1_CRS.
IOPORT_PIN_P050_PFC_02_A4	P05_0 / BSC / A4.
IOPORT_PIN_P050_PFC_03_MTIOC4A	P05_0 / MTU3n / MTIOC4A.
IOPORT_PIN_P050_PFC_04_GTIOC6A	P05_0 / GPTn / GTIOC6A.
IOPORT_PIN_P050_PFC_05_CMTW0_TOC0	P05_0 / CMTWn / CMTW0_TOC0.
IOPORT_PIN_P050_PFC_06_SS5_CTS5_RTS5	P05_0 / SCIn / SS5_CTS5_RTS5.
IOPORT_PIN_P050_PFC_07_CANTXDP0	P05_0 / CANFDn / CANTXDP0.
IOPORT_PIN_P050_PFC_08_USB_VBUSEN	P05_0 / USB_HS / USB_VBUSEN.
IOPORT_PIN_P050_PFC_09_MCLK3	P05_0 / DSMIFn / MCLK3.
IOPORT_PIN_P050_PFC_0B_HA4	P05_0 / PHOSTIF / HA4.
IOPORT_PIN_P051_PFC_00_IRQ13	P05_1 / IRQ / IRQ13.
IOPORT_PIN_P051_PFC_01_ETH1_COL	P05_1 / ETHER_ETHn / ETH1_COL.
IOPORT_PIN_P051_PFC_02_A3	P05_1 / BSC / A3.
IOPORT_PIN_P051_PFC_03_MTIOC4B	P05_1 / MTU3n / MTIOC4B.
IOPORT_PIN_P051_PFC_04_GTIOC6B	P05_1 / GPTn / GTIOC6B.
IOPORT_PIN_P051_PFC_05_CMTW0_TIC1	P05_1 / CMTWn / CMTW0_TIC1.
IOPORT_PIN_P051_PFC_06_CTS5	P05_1 / SCIn / CTS5.
IOPORT_PIN_P051_PFC_07_CANRXDP0	P05_1 / CANFDn / CANRXDP0.
IOPORT_PIN_P051_PFC_08_USB_EXICEN	P05_1 / USB_HS / USB_EXICEN.
IOPORT_PIN_P051_PFC_09_MDAT3	P05_1 / DSMIFn / MDAT3.
IOPORT_PIN_P051_PFC_0B_HA3	P05_1 / PHOSTIF / HA3.
IOPORT_PIN_P052_PFC_00_IRQ14	P05_2 / IRQ / IRQ14.
IOPORT_PIN_P052_PFC_01_ETH0_CRS	P05_2 / ETHER_ETHn / ETH0_CRS.
IOPORT_PIN_P052_PFC_02_A2	P05_2 / BSC / A2.
IOPORT_PIN_P052_PFC_03_MTIOC4C	P05_2 / MTU3n / MTIOC4C.
IOPORT_PIN_P052_PFC_04_GTETRGSA	P05_2 / GPT_POEG / GTETRGSA.
IOPORT_PIN_P052_PFC_05_GTIOC7A	P05_2 / GPTn / GTIOC7A.
IOPORT_PIN_P052_PFC_06_CMTW0_TOC0	P05_2 / CMTWn / CMTW0_TOC0.
IOPORT_PIN_P052_PFC_07_DE5	P05_2 / SCIn / DE5.
IOPORT_PIN_P052_PFC_08_IIC_SCL1	P05_2 / IICn / IIC_SCL1.
IOPORT_PIN_P052_PFC_09_CANRX0	P05_2 / CANFDn / CANRX0.
IOPORT_PIN_P052_PFC_0A_DREQ	P05_2 / DMAC / DREQ.
IOPORT_PIN_P052_PFC_0B_USB_VBUSEN	P05_2 / USB_HS / USB_VBUSEN.
IOPORT_PIN_P052_PFC_0D_HA2	P05_2 / PHOSTIF / HA2.
IOPORT_PIN_P053_PFC_00_IRQ15	P05_3 / IRQ / IRQ15.
IOPORT_PIN_P053_PFC_01_ETH0_COL	P05_3 / ETHER_ETHn / ETH0_COL.
IOPORT_PIN_P053_PFC_02_A1	P05_3 / BSC / A1.
IOPORT_PIN_P053_PFC_03_MTIOC4D	P05_3 / MTU3n / MTIOC4D.
IOPORT_PIN_P053_PFC_04_GTETRGSB	P05_3 / GPT_POEG / GTETRGSB.
IOPORT_PIN_P053_PFC_05_GTIOC7B	P05_3 / GPTn / GTIOC7B.
IOPORT_PIN_P053_PFC_06_POE11	P05_3 / MTU_POE3 / POE11.
IOPORT_PIN_P053_PFC_07_CMTW0_TIC0	P05_3 / CMTWn / CMTW0_TIC0.
IOPORT_PIN_P053_PFC_08_SCK4	P05_3 / SCIn / SCK4.
IOPORT_PIN_P053_PFC_09_IIC_SDA1	P05_3 / IICn / IIC_SDA1.
IOPORT_PIN_P053_PFC_0A_CANTX0	P05_3 / CANFDn / CANTX0.
IOPORT_PIN_P053_PFC_0B_USB_EXICEN	P05_3 / USB_HS / USB_EXICEN.
IOPORT_PIN_P053_PFC_0D_HA1	P05_3 / PHOSTIF / HA1.
IOPORT_PIN_P054_PFC_00_IRQ12	P05_4 / IRQ / IRQ12.
IOPORT_PIN_P054_PFC_01_ETHSW_LPI0	P05_4 / ETHER_ETHSW / ETHSW_LPI0.
IOPORT_PIN_P054_PFC_02_A0	P05_4 / BSC / A0.
IOPORT_PIN_P054_PFC_03_GTIOC14A	P05_4 / GPTn / GTIOC14A.
IOPORT_PIN_P054_PFC_04_RXD4_SCL4_MISO4	P05_4 / SCIn / RXD4_SCL4_MISO4.
IOPORT_PIN_P054_PFC_05_SPI_SSL00	P05_4 / SPIn / SPI_SSL00.
IOPORT_PIN_P054_PFC_06_CANTXDP0	P05_4 / CANFDn / CANTXDP0.
IOPORT_PIN_P054_PFC_07_DACK	P05_4 / DMAC / DACK.
IOPORT_PIN_P054_PFC_08_USB_OVRCUR	P05_4 / USB_HS / USB_OVRCUR.
IOPORT_PIN_P054_PFC_0A_HA0	P05_4 / PHOSTIF / HA0.
IOPORT_PIN_P055_PFC_00_ETHSW_PHYLINK1	P05_5 / ETHER_ETHSW / ETHSW_PHYLINK1.
IOPORT_PIN_P055_PFC_02_ESC_PHYLINK1	P05_5 / ETHER_ESC / ESC_PHYLINK1.
IOPORT_PIN_P055_PFC_03_GTIOC14B	P05_5 / GPTn / GTIOC14B.
IOPORT_PIN_P055_PFC_04_CMTW0_TOC1	P05_5 / CMTWn / CMTW0_TOC1.
IOPORT_PIN_P055_PFC_05_SPI_RSPCK2	P05_5 / SPIn / SPI_RSPCK2.
IOPORT_PIN_P056_PFC_00_IRQ12	P05_6 / IRQ / IRQ12.
IOPORT_PIN_P056_PFC_01_ETH1_RXER	P05_6 / ETHER_ETHn / ETH1_RXER.
IOPORT_PIN_P056_PFC_03_GTIOC15A	P05_6 / GPTn / GTIOC15A.
IOPORT_PIN_P056_PFC_04_CMTW1_TIC0	P05_6 / CMTWn / CMTW1_TIC0.
IOPORT_PIN_P056_PFC_05_SPI_SSL22	P05_6 / SPIn / SPI_SSL22.
IOPORT_PIN_P057_PFC_00_ETH1_TXD2	P05_7 / ETHER_ETHn / ETH1_TXD2.
IOPORT_PIN_P057_PFC_02_GTIOC15B	P05_7 / GPTn / GTIOC15B.
IOPORT_PIN_P057_PFC_03_CMTW1_TOC1	P05_7 / CMTWn / CMTW1_TOC1.
IOPORT_PIN_P057_PFC_04_TXD4_SDA4_MOSI4	P05_7 / SCIn / TXD4_SDA4_MOSI4.
IOPORT_PIN_P057_PFC_05_SPI_SSL23	P05_7 / SPIn / SPI_SSL23.
IOPORT_PIN_P060_PFC_00_ETH1_TXD3	P06_0 / ETHER_ETHn / ETH1_TXD3.
IOPORT_PIN_P060_PFC_02_GTIOC16A	P06_0 / GPTn / GTIOC16A.
IOPORT_PIN_P060_PFC_03_CMTW1_TOC0	P06_0 / CMTWn / CMTW1_TOC0.
IOPORT_PIN_P060_PFC_04_SS4_CTS4_RTS4	P06_0 / SCIn / SS4_CTS4_RTS4.
IOPORT_PIN_P060_PFC_05_SPI_SSL23	P06_0 / SPIn / SPI_SSL23.
IOPORT_PIN_P060_PFC_06_CANRX1	P06_0 / CANFDn / CANRX1.
IOPORT_PIN_P061_PFC_00_ETH1_REFCLK	P06_1 / ETHER_ETHn / ETH1_REFCLK.
IOPORT_PIN_P061_PFC_01_RMII1_REFCLK	P06_1 / ETHER_ETHn / RMII1_REFCLK.
IOPORT_PIN_P061_PFC_03_GTIOC16B	P06_1 / GPTn / GTIOC16B.
IOPORT_PIN_P061_PFC_04_CTS4	P06_1 / SCIn / CTS4.
IOPORT_PIN_P061_PFC_05_SPI_SSL22	P06_1 / SPIn / SPI_SSL22.
IOPORT_PIN_P061_PFC_06_CANTX1	P06_1 / CANFDn / CANTX1.
IOPORT_PIN_P062_PFC_00_ETH1_TXD1	P06_2 / ETHER_ETHn / ETH1_TXD1.
IOPORT_PIN_P062_PFC_02_GTIOC17A	P06_2 / GPTn / GTIOC17A.
IOPORT_PIN_P062_PFC_03_CANRXDP1	P06_2 / CANFDn / CANRXDP1.
IOPORT_PIN_P063_PFC_00_ETH1_TXD0	P06_3 / ETHER_ETHn / ETH1_TXD0.
IOPORT_PIN_P063_PFC_02_GTIOC17B	P06_3 / GPTn / GTIOC17B.
IOPORT_PIN_P063_PFC_03_CMTW1_TIC1	P06_3 / CMTWn / CMTW1_TIC1.
IOPORT_PIN_P063_PFC_04_DE4	P06_3 / SCIn / DE4.
IOPORT_PIN_P063_PFC_05_SPI_MISO1	P06_3 / SPIn / SPI_MISO1.
IOPORT_PIN_P063_PFC_06_CANTXDP1	P06_3 / CANFDn / CANTXDP1.
IOPORT_PIN_P064_PFC_00_ETH1_TXCLK	P06_4 / ETHER_ETHn / ETH1_TXCLK.
IOPORT_PIN_P064_PFC_02_GTIOC11A	P06_4 / GPTn / GTIOC11A.
IOPORT_PIN_P064_PFC_03_SPI_MOSI1	P06_4 / SPIn / SPI_MOSI1.
IOPORT_PIN_P065_PFC_00_ETH1_TXEN	P06_5 / ETHER_ETHn / ETH1_TXEN.
IOPORT_PIN_P065_PFC_02_GTIOC11B	P06_5 / GPTn / GTIOC11B.
IOPORT_PIN_P066_PFC_00_ETH1_RXD0	P06_6 / ETHER_ETHn / ETH1_RXD0.
IOPORT_PIN_P066_PFC_02_GTIOC12A	P06_6 / GPTn / GTIOC12A.
IOPORT_PIN_P066_PFC_03_SPI_SSL10	P06_6 / SPIn / SPI_SSL10.
IOPORT_PIN_P067_PFC_00_ETH1_RXD1	P06_7 / ETHER_ETHn / ETH1_RXD1.
IOPORT_PIN_P067_PFC_02_GTIOC12B	P06_7 / GPTn / GTIOC12B.
IOPORT_PIN_P067_PFC_03_SPI_SSL11	P06_7 / SPIn / SPI_SSL11.
IOPORT_PIN_P070_PFC_00_ETH1_RXD2	P07_0 / ETHER_ETHn / ETH1_RXD2.
IOPORT_PIN_P070_PFC_02_GTIOC13A	P07_0 / GPTn / GTIOC13A.
IOPORT_PIN_P071_PFC_00_ETH1_RXD3	P07_1 / ETHER_ETHn / ETH1_RXD3.
IOPORT_PIN_P071_PFC_02_GTIOC13B	P07_1 / GPTn / GTIOC13B.
IOPORT_PIN_P072_PFC_00_ETH1_RXDV	P07_2 / ETHER_ETHn / ETH1_RXDV.
IOPORT_PIN_P073_PFC_00_ETH1_RXCLK	P07_3 / ETHER_ETHn / ETH1_RXCLK.
IOPORT_PIN_P074_PFC_00_IRQ1	P07_4 / IRQ / IRQ1.
IOPORT_PIN_P074_PFC_01_ADTRG0	P07_4 / ADCn / ADTRG0.
IOPORT_PIN_P074_PFC_02_USB_VBUSIN	P07_4 / USB_HS / USB_VBUSIN.
IOPORT_PIN_P084_PFC_00_ETH0_RXD3	P08_4 / ETHER_ETHn / ETH0_RXD3.
IOPORT_PIN_P084_PFC_02_MTIOC6A	P08_4 / MTU3n / MTIOC6A.
IOPORT_PIN_P085_PFC_00_ETH0_RXDV	P08_5 / ETHER_ETHn / ETH0_RXDV.
IOPORT_PIN_P085_PFC_01_MTIOC6B	P08_5 / MTU3n / MTIOC6B.
IOPORT_PIN_P086_PFC_00_ETH0_RXCLK	P08_6 / ETHER_ETHn / ETH0_RXCLK.
IOPORT_PIN_P086_PFC_01_MTIOC6C	P08_6 / MTU3n / MTIOC6C.
IOPORT_PIN_P087_PFC_00_GMAC_MDC	P08_7 / ETHER_GMAC / GMAC_MDC.
IOPORT_PIN_P087_PFC_01_ETHSW_MDC	P08_7 / ETHER_ETHSW / ETHSW_MDC.
IOPORT_PIN_P087_PFC_03_ESC_MDC	P08_7 / ETHER_ESC / ESC_MDC.
IOPORT_PIN_P087_PFC_04_MTIOC6D	P08_7 / MTU3n / MTIOC6D.
IOPORT_PIN_P090_PFC_00_GMAC_MDIO	P09_0 / ETHER_GMAC / GMAC_MDIO.
IOPORT_PIN_P090_PFC_01_ETHSW_MDIO	P09_0 / ETHER_ETHSW / ETHSW_MDIO.
IOPORT_PIN_P090_PFC_03_ESC_MDIO	P09_0 / ETHER_ESC / ESC_MDIO.
IOPORT_PIN_P090_PFC_04_MTIOC7A	P09_0 / MTU3n / MTIOC7A.
IOPORT_PIN_P091_PFC_00_ETH0_REFCLK	P09_1 / ETHER_ETHn / ETH0_REFCLK.
IOPORT_PIN_P091_PFC_01_RMII0_REFCLK	P09_1 / ETHER_ETHn / RMII0_REFCLK.
IOPORT_PIN_P091_PFC_02_MTIOC7B	P09_1 / MTU3n / MTIOC7B.
IOPORT_PIN_P092_PFC_00_IRQ0	P09_2 / IRQ / IRQ0.
IOPORT_PIN_P092_PFC_01_ETH0_RXER	P09_2 / ETHER_ETHn / ETH0_RXER.
IOPORT_PIN_P092_PFC_03_MTIOC7C	P09_2 / MTU3n / MTIOC7C.
IOPORT_PIN_P093_PFC_00_ETH0_TXD3	P09_3 / ETHER_ETHn / ETH0_TXD3.
IOPORT_PIN_P093_PFC_01_MTIOC7D	P09_3 / MTU3n / MTIOC7D.
IOPORT_PIN_P094_PFC_00_ETH0_TXD2	P09_4 / ETHER_ETHn / ETH0_TXD2.
IOPORT_PIN_P095_PFC_00_ETH0_TXD1	P09_5 / ETHER_ETHn / ETH0_TXD1.
IOPORT_PIN_P096_PFC_00_ETH0_TXD0	P09_6 / ETHER_ETHn / ETH0_TXD0.
IOPORT_PIN_P097_PFC_00_ETH0_TXCLK	P09_7 / ETHER_ETHn / ETH0_TXCLK.
IOPORT_PIN_P100_PFC_00_ETH0_TXEN	P10_0 / ETHER_ETHn / ETH0_TXEN.
IOPORT_PIN_P101_PFC_00_ETH0_RXD0	P10_1 / ETHER_ETHn / ETH0_RXD0.
IOPORT_PIN_P102_PFC_00_ETH0_RXD1	P10_2 / ETHER_ETHn / ETH0_RXD1.
IOPORT_PIN_P103_PFC_00_ETH0_RXD2	P10_3 / ETHER_ETHn / ETH0_RXD2.
IOPORT_PIN_P103_PFC_01_RTCAT1HZ	P10_3 / RTC / RTCAT1HZ.
IOPORT_PIN_P104_PFC_00_IRQ11	P10_4 / IRQ / IRQ11.
IOPORT_PIN_P104_PFC_01_ETHSW_PHYLINK0	P10_4 / ETHER_ETHSW / ETHSW_PHYLINK0.
IOPORT_PIN_P104_PFC_03_ESC_PHYLINK0	P10_4 / ETHER_ESC / ESC_PHYLINK0.
IOPORT_PIN_P124_PFC_01_ETH1_CRS	P12_4 / ETHER_ETHn / ETH1_CRS.
IOPORT_PIN_P124_PFC_02_TRACEDATA0	P12_4 / TRACE / TRACEDATA0.
IOPORT_PIN_P124_PFC_03_D15	P12_4 / BSC / D15.
IOPORT_PIN_P124_PFC_04_MTIOC8B	P12_4 / MTU3n / MTIOC8B.
IOPORT_PIN_P124_PFC_05_GTIOC8B	P12_4 / GPTn / GTIOC8B.
IOPORT_PIN_P124_PFC_06_SPI_SSL01	P12_4 / SPIn / SPI_SSL01.
IOPORT_PIN_P124_PFC_08_MBX_HINT	P12_4 / MBXSEM / MBX_HINT.
IOPORT_PIN_P132_PFC_00_IRQ5	P13_2 / IRQ / IRQ5.
IOPORT_PIN_P132_PFC_02_ETHSW_PTPOUT2	P13_2 / ETHER_ETHSW / ETHSW_PTPOUT2.
IOPORT_PIN_P132_PFC_03_TRACEDATA6	P13_2 / TRACE / TRACEDATA6.
IOPORT_PIN_P132_PFC_04_D9	P13_2 / BSC / D9.
IOPORT_PIN_P132_PFC_05_ESC_I2CCLK	P13_2 / ETHER_ESC / ESC_I2CCLK.
IOPORT_PIN_P132_PFC_06_MTIOC0A	P13_2 / MTU3n / MTIOC0A.
IOPORT_PIN_P132_PFC_07_GTIOC10A	P13_2 / GPTn / GTIOC10A.
IOPORT_PIN_P132_PFC_08_POE8	P13_2 / MTU_POE3 / POE8.
IOPORT_PIN_P132_PFC_09_SS1_CTS1_RTS1	P13_2 / SCIn / SS1_CTS1_RTS1.
IOPORT_PIN_P132_PFC_0A_SPI_MISO0	P13_2 / SPIn / SPI_MISO0.
IOPORT_PIN_P132_PFC_0B_IIC_SCL0	P13_2 / IICn / IIC_SCL0.
IOPORT_PIN_P132_PFC_0C_MCLK4	P13_2 / DSMIFn / MCLK4.
IOPORT_PIN_P132_PFC_0E_A13	P13_2 / BSC / A13.
IOPORT_PIN_P133_PFC_01_ETHSW_PTPOUT3	P13_3 / ETHER_ETHSW / ETHSW_PTPOUT3.
IOPORT_PIN_P133_PFC_02_TRACEDATA7	P13_3 / TRACE / TRACEDATA7.
IOPORT_PIN_P133_PFC_03_D8	P13_3 / BSC / D8.
IOPORT_PIN_P133_PFC_04_ESC_I2CDATA	P13_3 / ETHER_ESC / ESC_I2CDATA.
IOPORT_PIN_P133_PFC_05_MTIOC0C	P13_3 / MTU3n / MTIOC0C.
IOPORT_PIN_P133_PFC_06_MTIOC0B	P13_3 / MTU3n / MTIOC0B.
IOPORT_PIN_P133_PFC_07_GTIOC10B	P13_3 / GPTn / GTIOC10B.
IOPORT_PIN_P133_PFC_08_CMTW1_TOC0	P13_3 / CMTWn / CMTW1_TOC0.
IOPORT_PIN_P133_PFC_09_CTS1	P13_3 / SCIn / CTS1.
IOPORT_PIN_P133_PFC_0A_SPI_RSPCK0	P13_3 / SPIn / SPI_RSPCK0.
IOPORT_PIN_P133_PFC_0B_IIC_SDA0	P13_3 / IICn / IIC_SDA0.
IOPORT_PIN_P133_PFC_0C_MDAT4	P13_3 / DSMIFn / MDAT4.
IOPORT_PIN_P133_PFC_0E_RD	P13_3 / BSC / RD.
IOPORT_PIN_P134_PFC_01_ESC_RESETOUT	P13_4 / ETHER_ESC / ESC_RESETOUT.
IOPORT_PIN_P134_PFC_02_MTIOC0D	P13_4 / MTU3n / MTIOC0D.
IOPORT_PIN_P134_PFC_03_GTIOC8B	P13_4 / GPTn / GTIOC8B.
IOPORT_PIN_P134_PFC_05_A0	P13_4 / BSC / A0.
IOPORT_PIN_P135_PFC_00_XSPI0_WP1	P13_5 / XSPIn / XSPI0_WP1.
IOPORT_PIN_P135_PFC_01_GMAC_PTPTRG0	P13_5 / ETHER_GMAC / GMAC_PTPTRG0.
IOPORT_PIN_P135_PFC_02_ESC_LATCH0	P13_5 / ETHER_ESC / ESC_LATCH0.
IOPORT_PIN_P135_PFC_03_ESC_LATCH1	P13_5 / ETHER_ESC / ESC_LATCH1.
IOPORT_PIN_P135_PFC_04_MTCLKA	P13_5 / MTU3 / MTCLKA.
IOPORT_PIN_P135_PFC_05_SPI_RSPCK1	P13_5 / SPIn / SPI_RSPCK1.
IOPORT_PIN_P135_PFC_06_IIC_SCL2	P13_5 / IICn / IIC_SCL2.
IOPORT_PIN_P136_PFC_00_XSPI0_WP0	P13_6 / XSPIn / XSPI0_WP0.
IOPORT_PIN_P136_PFC_01_ETHSW_PTPOUT0	P13_6 / ETHER_ETHSW / ETHSW_PTPOUT0.
IOPORT_PIN_P136_PFC_02_ESC_SYNC0	P13_6 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P136_PFC_03_ESC_SYNC1	P13_6 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P136_PFC_04_MTCLKB	P13_6 / MTU3 / MTCLKB.
IOPORT_PIN_P137_PFC_00_XSPI0_ECS1	P13_7 / XSPIn / XSPI0_ECS1.
IOPORT_PIN_P137_PFC_01_GMAC_PTPTRG1	P13_7 / ETHER_GMAC / GMAC_PTPTRG1.
IOPORT_PIN_P137_PFC_02_ESC_LATCH1	P13_7 / ETHER_ESC / ESC_LATCH1.
IOPORT_PIN_P137_PFC_03_ESC_LATCH0	P13_7 / ETHER_ESC / ESC_LATCH0.
IOPORT_PIN_P137_PFC_04_MTCLKC	P13_7 / MTU3 / MTCLKC.
IOPORT_PIN_P137_PFC_05_MBX_HINT	P13_7 / MBXSEM / MBX_HINT.
IOPORT_PIN_P140_PFC_00_XSPI0_INT0	P14_0 / XSPIn / XSPI0_INT0.
IOPORT_PIN_P140_PFC_01_ETHSW_PTPOUT1	P14_0 / ETHER_ETHSW / ETHSW_PTPOUT1.
IOPORT_PIN_P140_PFC_02_ESC_SYNC1	P14_0 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P140_PFC_03_ESC_SYNC0	P14_0 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P140_PFC_04_MTCLKD	P14_0 / MTU3 / MTCLKD.
IOPORT_PIN_P141_PFC_00_XSPI0_INT1	P14_1 / XSPIn / XSPI0_INT1.
IOPORT_PIN_P141_PFC_01_ETH1_COL	P14_1 / ETHER_ETHn / ETH1_COL.
IOPORT_PIN_P141_PFC_03_MTIOC8A	P14_1 / MTU3n / MTIOC8A.
IOPORT_PIN_P141_PFC_04_GTIOC8A	P14_1 / GPTn / GTIOC8A.
IOPORT_PIN_P141_PFC_06_GMAC_PTPTRG1	P14_1 / ETHER_GMAC / GMAC_PTPTRG1.
IOPORT_PIN_P141_PFC_07_ESC_LATCH0	P14_1 / ETHER_ESC / ESC_LATCH0.
IOPORT_PIN_P141_PFC_08_ESC_LATCH1	P14_1 / ETHER_ESC / ESC_LATCH1.
IOPORT_PIN_P141_PFC_09_HSPI_IO0	P14_1 / SHOSTIF / HSPI_IO0.
IOPORT_PIN_P142_PFC_00_IRQ6	P14_2 / IRQ / IRQ6.
IOPORT_PIN_P142_PFC_01_XSPI0_ECS0	P14_2 / XSPIn / XSPI0_ECS0.
IOPORT_PIN_P142_PFC_02_ETH0_CRS	P14_2 / ETHER_ETHn / ETH0_CRS.
IOPORT_PIN_P142_PFC_04_MTIOC8B	P14_2 / MTU3n / MTIOC8B.
IOPORT_PIN_P142_PFC_05_GTIOC8B	P14_2 / GPTn / GTIOC8B.
IOPORT_PIN_P142_PFC_07_ETH2_CRS	P14_2 / ETHER_ETHn / ETH2_CRS.
IOPORT_PIN_P142_PFC_08_HSPI_CK	P14_2 / SHOSTIF / HSPI_CK.
IOPORT_PIN_P143_PFC_00_XSPI0_RSTO1	P14_3 / XSPIn / XSPI0_RSTO1.
IOPORT_PIN_P143_PFC_01_ETH0_COL	P14_3 / ETHER_ETHn / ETH0_COL.
IOPORT_PIN_P143_PFC_04_MTIOC0A	P14_3 / MTU3n / MTIOC0A.
IOPORT_PIN_P143_PFC_06_ETH2_COL	P14_3 / ETHER_ETHn / ETH2_COL.
IOPORT_PIN_P143_PFC_07_HSPI_IO1	P14_3 / SHOSTIF / HSPI_IO1.
IOPORT_PIN_P144_PFC_00_XSPI0_DS	P14_4 / XSPIn / XSPI0_DS.
IOPORT_PIN_P144_PFC_01_BS	P14_4 / BSC / BS.
IOPORT_PIN_P144_PFC_02_ESC_IRQ	P14_4 / ETHER_ESC / ESC_IRQ.
IOPORT_PIN_P144_PFC_03_MTIOC0B	P14_4 / MTU3n / MTIOC0B.
IOPORT_PIN_P144_PFC_04_HBS	P14_4 / PHOSTIF / HBS.
IOPORT_PIN_P145_PFC_00_XSPI0_CKN	P14_5 / XSPIn / XSPI0_CKN.
IOPORT_PIN_P145_PFC_01_CS3	P14_5 / BSC / CS3.
IOPORT_PIN_P145_PFC_02_POE8	P14_5 / MTU_POE3 / POE8.
IOPORT_PIN_P145_PFC_03_HSPI_INT	P14_5 / SHOSTIF / HSPI_INT.
IOPORT_PIN_P146_PFC_00_XSPI0_CKP	P14_6 / XSPIn / XSPI0_CKP.
IOPORT_PIN_P146_PFC_01_A21	P14_6 / BSC / A21.
IOPORT_PIN_P147_PFC_00_XSPI0_IO0	P14_7 / XSPIn / XSPI0_IO0.
IOPORT_PIN_P147_PFC_01_A22	P14_7 / BSC / A22.
IOPORT_PIN_P147_PFC_02_SCK5	P14_7 / SCIn / SCK5.
IOPORT_PIN_P147_PFC_03_SPI_MISO1	P14_7 / SPIn / SPI_MISO1.
IOPORT_PIN_P147_PFC_04_BS	P14_7 / BSC / BS.
IOPORT_PIN_P150_PFC_00_XSPI0_IO1	P15_0 / XSPIn / XSPI0_IO1.
IOPORT_PIN_P150_PFC_01_A23	P15_0 / BSC / A23.
IOPORT_PIN_P150_PFC_02_RXD5_SCL5_MISO5	P15_0 / SCIn / RXD5_SCL5_MISO5.
IOPORT_PIN_P150_PFC_03_SPI_MOSI1	P15_0 / SPIn / SPI_MOSI1.
IOPORT_PIN_P150_PFC_04_CKE	P15_0 / BSC / CKE.
IOPORT_PIN_P151_PFC_00_XSPI0_IO2	P15_1 / XSPIn / XSPI0_IO2.
IOPORT_PIN_P151_PFC_01_A24	P15_1 / BSC / A24.
IOPORT_PIN_P151_PFC_02_MTIOC0C	P15_1 / MTU3n / MTIOC0C.
IOPORT_PIN_P151_PFC_03_TXD5_SDA5_MOSI5	P15_1 / SCIn / TXD5_SDA5_MOSI5.
IOPORT_PIN_P151_PFC_04_SPI_SSL10	P15_1 / SPIn / SPI_SSL10.
IOPORT_PIN_P151_PFC_05_CAS	P15_1 / BSC / CAS.
IOPORT_PIN_P152_PFC_00_XSPI0_IO3	P15_2 / XSPIn / XSPI0_IO3.
IOPORT_PIN_P152_PFC_01_A25	P15_2 / BSC / A25.
IOPORT_PIN_P152_PFC_02_MTIOC0D	P15_2 / MTU3n / MTIOC0D.
IOPORT_PIN_P152_PFC_03_SS5_CTS5_RTS5	P15_2 / SCIn / SS5_CTS5_RTS5.
IOPORT_PIN_P152_PFC_04_SPI_SSL11	P15_2 / SPIn / SPI_SSL11.
IOPORT_PIN_P152_PFC_05_RAS	P15_2 / BSC / RAS.
IOPORT_PIN_P153_PFC_00_XSPI0_IO4	P15_3 / XSPIn / XSPI0_IO4.
IOPORT_PIN_P153_PFC_01_MTIOC8C	P15_3 / MTU3n / MTIOC8C.
IOPORT_PIN_P153_PFC_02_MCLK1	P15_3 / DSMIFn / MCLK1.
IOPORT_PIN_P153_PFC_03_D11	P15_3 / BSC / D11.
IOPORT_PIN_P154_PFC_00_XSPI0_IO5	P15_4 / XSPIn / XSPI0_IO5.
IOPORT_PIN_P154_PFC_01_MTIOC8D	P15_4 / MTU3n / MTIOC8D.
IOPORT_PIN_P154_PFC_02_MDAT1	P15_4 / DSMIFn / MDAT1.
IOPORT_PIN_P154_PFC_03_D12	P15_4 / BSC / D12.
IOPORT_PIN_P155_PFC_00_XSPI0_IO6	P15_5 / XSPIn / XSPI0_IO6.
IOPORT_PIN_P155_PFC_01_MCLK2	P15_5 / DSMIFn / MCLK2.
IOPORT_PIN_P155_PFC_02_D13	P15_5 / BSC / D13.
IOPORT_PIN_P156_PFC_00_XSPI0_IO7	P15_6 / XSPIn / XSPI0_IO7.
IOPORT_PIN_P156_PFC_01_SPI_SSL12	P15_6 / SPIn / SPI_SSL12.
IOPORT_PIN_P156_PFC_02_MDAT2	P15_6 / DSMIFn / MDAT2.
IOPORT_PIN_P156_PFC_03_D14	P15_6 / BSC / D14.
IOPORT_PIN_P157_PFC_00_XSPI0_CS0	P15_7 / XSPIn / XSPI0_CS0.
IOPORT_PIN_P157_PFC_01_CTS5	P15_7 / SCIn / CTS5.
IOPORT_PIN_P157_PFC_02_SPI_SSL13	P15_7 / SPIn / SPI_SSL13.
IOPORT_PIN_P157_PFC_03_TEND	P15_7 / DMAC / TEND.
IOPORT_PIN_P160_PFC_00_XSPI0_CS1	P16_0 / XSPIn / XSPI0_CS1.
IOPORT_PIN_P160_PFC_01_ETH0_TXER	P16_0 / ETHER_ETHn / ETH0_TXER.
IOPORT_PIN_P160_PFC_02_TXD0_SDA0_MOSI0	P16_0 / SCIn / TXD0_SDA0_MOSI0.
IOPORT_PIN_P160_PFC_03_SPI_MOSI3	P16_0 / SPIn / SPI_MOSI3.
IOPORT_PIN_P160_PFC_04_MCLK3	P16_0 / DSMIFn / MCLK3.
IOPORT_PIN_P160_PFC_06_ETH2_REFCLK	P16_0 / ETHER_ETHn / ETH2_REFCLK.
IOPORT_PIN_P160_PFC_07_HSPI_CS	P16_0 / SHOSTIF / HSPI_CS.
IOPORT_PIN_P161_PFC_00_XSPI0_RESET0	P16_1 / XSPIn / XSPI0_RESET0.
IOPORT_PIN_P161_PFC_01_CMTW0_TOC1	P16_1 / CMTWn / CMTW0_TOC1.
IOPORT_PIN_P161_PFC_02_ADTRG0	P16_1 / ADCn / ADTRG0.
IOPORT_PIN_P161_PFC_03_RXD0_SCL0_MISO0	P16_1 / SCIn / RXD0_SCL0_MISO0.
IOPORT_PIN_P161_PFC_04_SPI_MISO3	P16_1 / SPIn / SPI_MISO3.
IOPORT_PIN_P161_PFC_05_MDAT3	P16_1 / DSMIFn / MDAT3.
IOPORT_PIN_P161_PFC_07_CS2	P16_1 / BSC / CS2.
IOPORT_PIN_P161_PFC_08_HCS1	P16_1 / PHOSTIF / HCS1.
IOPORT_PIN_P162_PFC_00_NMI	P16_2 / IRQ / NMI.
IOPORT_PIN_P162_PFC_01_XSPI0_RESET1	P16_2 / XSPIn / XSPI0_RESET1.
IOPORT_PIN_P162_PFC_02_CTS0	P16_2 / SCIn / CTS0.
IOPORT_PIN_P162_PFC_03_SPI_RSPCK3	P16_2 / SPIn / SPI_RSPCK3.
IOPORT_PIN_P162_PFC_04_USB_EXICEN	P16_2 / USB_HS / USB_EXICEN.
IOPORT_PIN_P162_PFC_06_HSPI_IO2	P16_2 / SHOSTIF / HSPI_IO2.
IOPORT_PIN_P162_PFC_07_HERROUT	P16_2 / PHOSTIF / HERROUT.
IOPORT_PIN_P163_PFC_00_IRQ7	P16_3 / IRQ / IRQ7.
IOPORT_PIN_P163_PFC_01_XSPI0_RSTO0	P16_3 / XSPIn / XSPI0_RSTO0.
IOPORT_PIN_P163_PFC_02_ETH1_TXER	P16_3 / ETHER_ETHn / ETH1_TXER.
IOPORT_PIN_P163_PFC_03_GTADSMP1	P16_3 / GPT / GTADSMP1.
IOPORT_PIN_P163_PFC_04_SCK0	P16_3 / SCIn / SCK0.
IOPORT_PIN_P163_PFC_05_SPI_SSL30	P16_3 / SPIn / SPI_SSL30.
IOPORT_PIN_P163_PFC_07_ETH1_CRS	P16_3 / ETHER_ETHn / ETH1_CRS.
IOPORT_PIN_P163_PFC_08_CS3	P16_3 / BSC / CS3.
IOPORT_PIN_P163_PFC_09_HSPI_IO3	P16_3 / SHOSTIF / HSPI_IO3.
IOPORT_PIN_P165_PFC_00_MTIC5U	P16_5 / MTU3n / MTIC5U.
IOPORT_PIN_P165_PFC_01_TXD0_SDA0_MOSI0	P16_5 / SCIn / TXD0_SDA0_MOSI0.
IOPORT_PIN_P165_PFC_02_A15	P16_5 / BSC / A15.
IOPORT_PIN_P165_PFC_03_HSPI_IO4	P16_5 / SHOSTIF / HSPI_IO4.
IOPORT_PIN_P166_PFC_00_IRQ8	P16_6 / IRQ / IRQ8.
IOPORT_PIN_P166_PFC_01_MTIC5V	P16_6 / MTU3n / MTIC5V.
IOPORT_PIN_P166_PFC_02_RXD0_SCL0_MISO0	P16_6 / SCIn / RXD0_SCL0_MISO0.
IOPORT_PIN_P166_PFC_03_CS0	P16_6 / BSC / CS0.
IOPORT_PIN_P166_PFC_04_HSPI_IO5	P16_6 / SHOSTIF / HSPI_IO5.
IOPORT_PIN_P166_PFC_05_HCS0	P16_6 / PHOSTIF / HCS0.
IOPORT_PIN_P167_PFC_00_MTIC5W	P16_7 / MTU3n / MTIC5W.
IOPORT_PIN_P167_PFC_01_SCK0	P16_7 / SCIn / SCK0.
IOPORT_PIN_P167_PFC_02_XSPI1_IO0	P16_7 / XSPIn / XSPI1_IO0.
IOPORT_PIN_P167_PFC_03_A13	P16_7 / BSC / A13.
IOPORT_PIN_P167_PFC_04_HA13	P16_7 / PHOSTIF / HA13.
IOPORT_PIN_P170_PFC_00_ESC_IRQ	P17_0 / ETHER_ESC / ESC_IRQ.
IOPORT_PIN_P170_PFC_01_SS0_CTS0_RTS0	P17_0 / SCIn / SS0_CTS0_RTS0.
IOPORT_PIN_P170_PFC_02_XSPI1_IO1	P17_0 / XSPIn / XSPI1_IO1.
IOPORT_PIN_P173_PFC_00_TRACECTL	P17_3 / TRACE / TRACECTL.
IOPORT_PIN_P173_PFC_01_GTETRGA	P17_3 / GPT_POEG / GTETRGA.
IOPORT_PIN_P173_PFC_02_POE0	P17_3 / MTU_POE3 / POE0.
IOPORT_PIN_P173_PFC_03_ADTRG1	P17_3 / ADCn / ADTRG1.
IOPORT_PIN_P173_PFC_04_SPI_SSL31	P17_3 / SPIn / SPI_SSL31.
IOPORT_PIN_P173_PFC_05_DREQ	P17_3 / DMAC / DREQ.
IOPORT_PIN_P173_PFC_07_XSPI1_IO2	P17_3 / XSPIn / XSPI1_IO2.
IOPORT_PIN_P174_PFC_00_TRACECLK	P17_4 / TRACE / TRACECLK.
IOPORT_PIN_P174_PFC_01_MTIOC3C	P17_4 / MTU3n / MTIOC3C.
IOPORT_PIN_P174_PFC_02_GTETRGB	P17_4 / GPT_POEG / GTETRGB.
IOPORT_PIN_P174_PFC_03_GTIOC0A	P17_4 / GPTn / GTIOC0A.
IOPORT_PIN_P174_PFC_04_CTS3	P17_4 / SCIn / CTS3.
IOPORT_PIN_P174_PFC_05_SPI_SSL32	P17_4 / SPIn / SPI_SSL32.
IOPORT_PIN_P174_PFC_07_XSPI1_IO3	P17_4 / XSPIn / XSPI1_IO3.
IOPORT_PIN_P174_PFC_08_DACK	P17_4 / DMAC / DACK.
IOPORT_PIN_P175_PFC_01_MTIOC3A	P17_5 / MTU3n / MTIOC3A.
IOPORT_PIN_P175_PFC_02_GTETRGC	P17_5 / GPT_POEG / GTETRGC.
IOPORT_PIN_P175_PFC_03_GTIOC0B	P17_5 / GPTn / GTIOC0B.
IOPORT_PIN_P175_PFC_04_TEND	P17_5 / DMAC / TEND.
IOPORT_PIN_P175_PFC_05_USB_OVRCUR	P17_5 / USB_HS / USB_OVRCUR.
IOPORT_PIN_P176_PFC_00_MTIOC3B	P17_6 / MTU3n / MTIOC3B.
IOPORT_PIN_P176_PFC_01_GTIOC1A	P17_6 / GPTn / GTIOC1A.
IOPORT_PIN_P176_PFC_02_SCK3	P17_6 / SCIn / SCK3.
IOPORT_PIN_P176_PFC_04_XSPI1_DS	P17_6 / XSPIn / XSPI1_DS.
IOPORT_PIN_P176_PFC_05_RD_WR	P17_6 / BSC / RD_WR.
IOPORT_PIN_P176_PFC_06_HWRSTB	P17_6 / PHOSTIF / HWRSTB.
IOPORT_PIN_P177_PFC_00_MTIOC4A	P17_7 / MTU3n / MTIOC4A.
IOPORT_PIN_P177_PFC_01_MTIOC4C	P17_7 / MTU3n / MTIOC4C.
IOPORT_PIN_P177_PFC_02_GTIOC2A	P17_7 / GPTn / GTIOC2A.
IOPORT_PIN_P177_PFC_03_GTIOC3A	P17_7 / GPTn / GTIOC3A.
IOPORT_PIN_P177_PFC_04_RXD3_SCL3_MISO3	P17_7 / SCIn / RXD3_SCL3_MISO3.
IOPORT_PIN_P177_PFC_05_DACK	P17_7 / DMAC / DACK.
IOPORT_PIN_P177_PFC_07_XSPI1_CKP	P17_7 / XSPIn / XSPI1_CKP.
IOPORT_PIN_P177_PFC_08_RD	P17_7 / BSC / RD.
IOPORT_PIN_P177_PFC_09_HRD	P17_7 / PHOSTIF / HRD.
IOPORT_PIN_P180_PFC_00_MTIOC4C	P18_0 / MTU3n / MTIOC4C.
IOPORT_PIN_P180_PFC_01_MTIOC4A	P18_0 / MTU3n / MTIOC4A.
IOPORT_PIN_P180_PFC_02_GTIOC3A	P18_0 / GPTn / GTIOC3A.
IOPORT_PIN_P180_PFC_03_GTIOC2A	P18_0 / GPTn / GTIOC2A.
IOPORT_PIN_P180_PFC_04_TXD3_SDA3_MOSI3	P18_0 / SCIn / TXD3_SDA3_MOSI3.
IOPORT_PIN_P180_PFC_05_WE0_DQMLL	P18_0 / BSC / WE0_DQMLL.
IOPORT_PIN_P180_PFC_06_HSPI_IO6	P18_0 / SHOSTIF / HSPI_IO6.
IOPORT_PIN_P180_PFC_07_HWR0	P18_0 / PHOSTIF / HWR0.
IOPORT_PIN_P181_PFC_00_IRQ10	P18_1 / IRQ / IRQ10.
IOPORT_PIN_P181_PFC_01_MTIOC3D	P18_1 / MTU3n / MTIOC3D.
IOPORT_PIN_P181_PFC_02_GTIOC1B	P18_1 / GPTn / GTIOC1B.
IOPORT_PIN_P181_PFC_03_ADTRG1	P18_1 / ADCn / ADTRG1.
IOPORT_PIN_P181_PFC_04_SS3_CTS3_RTS3	P18_1 / SCIn / SS3_CTS3_RTS3.
IOPORT_PIN_P181_PFC_06_WE1_DQMLU	P18_1 / BSC / WE1_DQMLU.
IOPORT_PIN_P181_PFC_07_HSPI_IO7	P18_1 / SHOSTIF / HSPI_IO7.
IOPORT_PIN_P181_PFC_08_HWR1	P18_1 / PHOSTIF / HWR1.
IOPORT_PIN_P182_PFC_00_MTIOC4B	P18_2 / MTU3n / MTIOC4B.
IOPORT_PIN_P182_PFC_01_MTIOC4D	P18_2 / MTU3n / MTIOC4D.
IOPORT_PIN_P182_PFC_02_GTIOC2B	P18_2 / GPTn / GTIOC2B.
IOPORT_PIN_P182_PFC_03_GTIOC3B	P18_2 / GPTn / GTIOC3B.
IOPORT_PIN_P182_PFC_05_XSPI1_CS0	P18_2 / XSPIn / XSPI1_CS0.
IOPORT_PIN_P182_PFC_06_ETH1_COL	P18_2 / ETHER_ETHn / ETH1_COL.
IOPORT_PIN_P182_PFC_07_BS	P18_2 / BSC / BS.
IOPORT_PIN_P182_PFC_08_SCK0	P18_2 / SCIn / SCK0.
IOPORT_PIN_P182_PFC_09_IIC_SDA2	P18_2 / IICn / IIC_SDA2.
IOPORT_PIN_P183_PFC_00_IRQ0	P18_3 / IRQ / IRQ0.
IOPORT_PIN_P183_PFC_01_MTIOC4D	P18_3 / MTU3n / MTIOC4D.
IOPORT_PIN_P183_PFC_02_MTIOC4B	P18_3 / MTU3n / MTIOC4B.
IOPORT_PIN_P183_PFC_03_GTIOC3B	P18_3 / GPTn / GTIOC3B.
IOPORT_PIN_P183_PFC_04_GTIOC2B	P18_3 / GPTn / GTIOC2B.
IOPORT_PIN_P183_PFC_05_CMTW1_TIC1	P18_3 / CMTWn / CMTW1_TIC1.
IOPORT_PIN_P183_PFC_06_CANRXDP1	P18_3 / CANFDn / CANRXDP1.
IOPORT_PIN_P183_PFC_08_XSPI1_IO4	P18_3 / XSPIn / XSPI1_IO4.
IOPORT_PIN_P183_PFC_09_ETH2_CRS	P18_3 / ETHER_ETHn / ETH2_CRS.
IOPORT_PIN_P183_PFC_0A_CKE	P18_3 / BSC / CKE.
IOPORT_PIN_P184_PFC_00_IRQ1	P18_4 / IRQ / IRQ1.
IOPORT_PIN_P184_PFC_01_MTIC5U	P18_4 / MTU3n / MTIC5U.
IOPORT_PIN_P184_PFC_02_TXD4_SDA4_MOSI4	P18_4 / SCIn / TXD4_SDA4_MOSI4.
IOPORT_PIN_P184_PFC_03_SPI_RSPCK2	P18_4 / SPIn / SPI_RSPCK2.
IOPORT_PIN_P184_PFC_05_XSPI1_IO5	P18_4 / XSPIn / XSPI1_IO5.
IOPORT_PIN_P184_PFC_06_ETH1_CRS	P18_4 / ETHER_ETHn / ETH1_CRS.
IOPORT_PIN_P184_PFC_07_CAS	P18_4 / BSC / CAS.
IOPORT_PIN_P184_PFC_08_CANTX0	P18_4 / CANFDn / CANTX0.
IOPORT_PIN_P185_PFC_00_TRACECTL	P18_5 / TRACE / TRACECTL.
IOPORT_PIN_P185_PFC_01_MTIC5V	P18_5 / MTU3n / MTIC5V.
IOPORT_PIN_P185_PFC_02_RXD4_SCL4_MISO4	P18_5 / SCIn / RXD4_SCL4_MISO4.
IOPORT_PIN_P185_PFC_03_SPI_MOSI2	P18_5 / SPIn / SPI_MOSI2.
IOPORT_PIN_P185_PFC_05_XSPI1_IO6	P18_5 / XSPIn / XSPI1_IO6.
IOPORT_PIN_P185_PFC_06_ETH2_COL	P18_5 / ETHER_ETHn / ETH2_COL.
IOPORT_PIN_P185_PFC_07_RAS	P18_5 / BSC / RAS.
IOPORT_PIN_P185_PFC_08_CANRX0	P18_5 / CANFDn / CANRX0.
IOPORT_PIN_P186_PFC_00_IRQ11	P18_6 / IRQ / IRQ11.
IOPORT_PIN_P186_PFC_01_TRACECLK	P18_6 / TRACE / TRACECLK.
IOPORT_PIN_P186_PFC_02_MTIC5W	P18_6 / MTU3n / MTIC5W.
IOPORT_PIN_P186_PFC_03_ADTRG0	P18_6 / ADCn / ADTRG0.
IOPORT_PIN_P186_PFC_04_SCK4	P18_6 / SCIn / SCK4.
IOPORT_PIN_P186_PFC_05_SPI_MISO2	P18_6 / SPIn / SPI_MISO2.
IOPORT_PIN_P186_PFC_06_IIC_SCL2	P18_6 / IICn / IIC_SCL2.
IOPORT_PIN_P186_PFC_08_XSPI1_IO7	P18_6 / XSPIn / XSPI1_IO7.
IOPORT_PIN_P186_PFC_09_ETH1_COL	P18_6 / ETHER_ETHn / ETH1_COL.
IOPORT_PIN_P186_PFC_0A_DE4	P18_6 / SCIn / DE4.
IOPORT_PIN_P190_PFC_00_USB_VBUSEN	P19_0 / USB_HS / USB_VBUSEN.
IOPORT_PIN_P201_PFC_00_ETHSW_TDMAOUT0	P20_1 / ETHER_ETHSW / ETHSW_TDMAOUT0.
IOPORT_PIN_P201_PFC_01_ESC_LINKACT0	P20_1 / ETHER_ESC / ESC_LINKACT0.
IOPORT_PIN_P201_PFC_02_ETHSW_PTPOUT3	P20_1 / ETHER_ETHSW / ETHSW_PTPOUT3.
IOPORT_PIN_P202_PFC_00_ETHSW_TDMAOUT1	P20_2 / ETHER_ETHSW / ETHSW_TDMAOUT1.
IOPORT_PIN_P202_PFC_01_ESC_LEDRUN	P20_2 / ETHER_ESC / ESC_LEDRUN.
IOPORT_PIN_P202_PFC_02_ESC_LEDSTER	P20_2 / ETHER_ESC / ESC_LEDSTER.
IOPORT_PIN_P202_PFC_03_DE3	P20_2 / SCIn / DE3.
IOPORT_PIN_P202_PFC_04_ETHSW_PTPOUT2	P20_2 / ETHER_ETHSW / ETHSW_PTPOUT2.
IOPORT_PIN_P203_PFC_00_ETHSW_TDMAOUT2	P20_3 / ETHER_ETHSW / ETHSW_TDMAOUT2.
IOPORT_PIN_P203_PFC_01_ESC_LEDERR	P20_3 / ETHER_ESC / ESC_LEDERR.
IOPORT_PIN_P203_PFC_02_ETHSW_PTPOUT1	P20_3 / ETHER_ETHSW / ETHSW_PTPOUT1.
IOPORT_PIN_P204_PFC_00_ETHSW_TDMAOUT3	P20_4 / ETHER_ETHSW / ETHSW_TDMAOUT3.
IOPORT_PIN_P204_PFC_01_ESC_LINKACT1	P20_4 / ETHER_ESC / ESC_LINKACT1.
IOPORT_PIN_P204_PFC_02_ETHSW_PTPOUT0	P20_4 / ETHER_ETHSW / ETHSW_PTPOUT0.
IOPORT_PIN_P211_PFC_00_TRACEDATA0	P21_1 / TRACE / TRACEDATA0.
IOPORT_PIN_P211_PFC_01_D0	P21_1 / BSC / D0.
IOPORT_PIN_P211_PFC_02_MTIOC6A	P21_1 / MTU3n / MTIOC6A.
IOPORT_PIN_P211_PFC_03_GTIOC14A	P21_1 / GPTn / GTIOC14A.
IOPORT_PIN_P211_PFC_04_CMTW0_TIC0	P21_1 / CMTWn / CMTW0_TIC0.
IOPORT_PIN_P211_PFC_05_SCK5	P21_1 / SCIn / SCK5.
IOPORT_PIN_P211_PFC_06_SPI_SSL20	P21_1 / SPIn / SPI_SSL20.
IOPORT_PIN_P211_PFC_07_IIC_SCL1	P21_1 / IICn / IIC_SCL1.
IOPORT_PIN_P211_PFC_08_MCLK0	P21_1 / DSMIFn / MCLK0.
IOPORT_PIN_P211_PFC_0A_ESC_SYNC0	P21_1 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P211_PFC_0B_ESC_SYNC1	P21_1 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P211_PFC_0C_HSPI_INT	P21_1 / SHOSTIF / HSPI_INT.
IOPORT_PIN_P211_PFC_0D_HD0	P21_1 / PHOSTIF / HD0.
IOPORT_PIN_P212_PFC_00_TRACEDATA1	P21_2 / TRACE / TRACEDATA1.
IOPORT_PIN_P212_PFC_01_D1	P21_2 / BSC / D1.
IOPORT_PIN_P212_PFC_02_MTIOC6B	P21_2 / MTU3n / MTIOC6B.
IOPORT_PIN_P212_PFC_03_GTIOC14B	P21_2 / GPTn / GTIOC14B.
IOPORT_PIN_P212_PFC_04_CMTW0_TIC1	P21_2 / CMTWn / CMTW0_TIC1.
IOPORT_PIN_P212_PFC_05_RXD5_SCL5_MISO5	P21_2 / SCIn / RXD5_SCL5_MISO5.
IOPORT_PIN_P212_PFC_06_SPI_MISO2	P21_2 / SPIn / SPI_MISO2.
IOPORT_PIN_P212_PFC_07_IIC_SDA1	P21_2 / IICn / IIC_SDA1.
IOPORT_PIN_P212_PFC_08_MDAT0	P21_2 / DSMIFn / MDAT0.
IOPORT_PIN_P212_PFC_0A_ESC_SYNC0	P21_2 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P212_PFC_0B_ESC_SYNC1	P21_2 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P212_PFC_0C_HD1	P21_2 / PHOSTIF / HD1.
IOPORT_PIN_P213_PFC_00_TRACEDATA2	P21_3 / TRACE / TRACEDATA2.
IOPORT_PIN_P213_PFC_01_D2	P21_3 / BSC / D2.
IOPORT_PIN_P213_PFC_02_MTIOC6C	P21_3 / MTU3n / MTIOC6C.
IOPORT_PIN_P213_PFC_03_GTIOC15A	P21_3 / GPTn / GTIOC15A.
IOPORT_PIN_P213_PFC_04_TXD5_SDA5_MOSI5	P21_3 / SCIn / TXD5_SDA5_MOSI5.
IOPORT_PIN_P213_PFC_05_SPI_SSL33	P21_3 / SPIn / SPI_SSL33.
IOPORT_PIN_P213_PFC_06_MCLK1	P21_3 / DSMIFn / MCLK1.
IOPORT_PIN_P213_PFC_08_NMI	P21_3 / IRQ / NMI.
IOPORT_PIN_P213_PFC_09_HD2	P21_3 / PHOSTIF / HD2.
IOPORT_PIN_P214_PFC_00_TRACEDATA3	P21_4 / TRACE / TRACEDATA3.
IOPORT_PIN_P214_PFC_01_D3	P21_4 / BSC / D3.
IOPORT_PIN_P214_PFC_02_MTIOC6D	P21_4 / MTU3n / MTIOC6D.
IOPORT_PIN_P214_PFC_03_GTIOC15B	P21_4 / GPTn / GTIOC15B.
IOPORT_PIN_P214_PFC_04_SS5_CTS5_RTS5	P21_4 / SCIn / SS5_CTS5_RTS5.
IOPORT_PIN_P214_PFC_05_SPI_SSL02	P21_4 / SPIn / SPI_SSL02.
IOPORT_PIN_P214_PFC_06_MDAT1	P21_4 / DSMIFn / MDAT1.
IOPORT_PIN_P214_PFC_08_ETHSW_PTPOUT1	P21_4 / ETHER_ETHSW / ETHSW_PTPOUT1.
IOPORT_PIN_P214_PFC_09_ESC_SYNC0	P21_4 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P214_PFC_0A_ESC_SYNC1	P21_4 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P214_PFC_0B_HD3	P21_4 / PHOSTIF / HD3.
IOPORT_PIN_P214_PFC_0C_MBX_HINT	P21_4 / MBXSEM / MBX_HINT.
IOPORT_PIN_P215_PFC_00_IRQ6	P21_5 / IRQ / IRQ6.
IOPORT_PIN_P215_PFC_01_TRACEDATA4	P21_5 / TRACE / TRACEDATA4.
IOPORT_PIN_P215_PFC_02_D4	P21_5 / BSC / D4.
IOPORT_PIN_P215_PFC_03_MTIOC7A	P21_5 / MTU3n / MTIOC7A.
IOPORT_PIN_P215_PFC_04_GTIOC16A	P21_5 / GPTn / GTIOC16A.
IOPORT_PIN_P215_PFC_05_CMTW1_TOC1	P21_5 / CMTWn / CMTW1_TOC1.
IOPORT_PIN_P215_PFC_06_ADTRG1	P21_5 / ADCn / ADTRG1.
IOPORT_PIN_P215_PFC_07_CTS5	P21_5 / SCIn / CTS5.
IOPORT_PIN_P215_PFC_08_SPI_MISO0	P21_5 / SPIn / SPI_MISO0.
IOPORT_PIN_P215_PFC_09_MCLK2	P21_5 / DSMIFn / MCLK2.
IOPORT_PIN_P215_PFC_0B_HD4	P21_5 / PHOSTIF / HD4.
IOPORT_PIN_P216_PFC_00_IRQ9	P21_6 / IRQ / IRQ9.
IOPORT_PIN_P216_PFC_01_TRACEDATA5	P21_6 / TRACE / TRACEDATA5.
IOPORT_PIN_P216_PFC_02_D5	P21_6 / BSC / D5.
IOPORT_PIN_P216_PFC_03_MTIOC7B	P21_6 / MTU3n / MTIOC7B.
IOPORT_PIN_P216_PFC_04_GTIOC16B	P21_6 / GPTn / GTIOC16B.
IOPORT_PIN_P216_PFC_05_CTS0	P21_6 / SCIn / CTS0.
IOPORT_PIN_P216_PFC_06_TEND	P21_6 / DMAC / TEND.
IOPORT_PIN_P216_PFC_07_MDAT2	P21_6 / DSMIFn / MDAT2.
IOPORT_PIN_P216_PFC_08_HD5	P21_6 / PHOSTIF / HD5.
IOPORT_PIN_P217_PFC_00_IRQ10	P21_7 / IRQ / IRQ10.
IOPORT_PIN_P217_PFC_01_TRACEDATA6	P21_7 / TRACE / TRACEDATA6.
IOPORT_PIN_P217_PFC_02_D6	P21_7 / BSC / D6.
IOPORT_PIN_P217_PFC_03_MTIOC7C	P21_7 / MTU3n / MTIOC7C.
IOPORT_PIN_P217_PFC_04_GTIOC17A	P21_7 / GPTn / GTIOC17A.
IOPORT_PIN_P217_PFC_05_DE0	P21_7 / SCIn / DE0.
IOPORT_PIN_P217_PFC_06_DREQ	P21_7 / DMAC / DREQ.
IOPORT_PIN_P217_PFC_07_MCLK3	P21_7 / DSMIFn / MCLK3.
IOPORT_PIN_P217_PFC_08_HD6	P21_7 / PHOSTIF / HD6.
IOPORT_PIN_P220_PFC_00_IRQ15	P22_0 / IRQ / IRQ15.
IOPORT_PIN_P220_PFC_01_TRACEDATA7	P22_0 / TRACE / TRACEDATA7.
IOPORT_PIN_P220_PFC_02_D7	P22_0 / BSC / D7.
IOPORT_PIN_P220_PFC_03_MTIOC7D	P22_0 / MTU3n / MTIOC7D.
IOPORT_PIN_P220_PFC_04_GTIOC17B	P22_0 / GPTn / GTIOC17B.
IOPORT_PIN_P220_PFC_05_DE5	P22_0 / SCIn / DE5.
IOPORT_PIN_P220_PFC_06_MDAT3	P22_0 / DSMIFn / MDAT3.
IOPORT_PIN_P220_PFC_07_HD7	P22_0 / PHOSTIF / HD7.
IOPORT_PIN_P221_PFC_00_TRACECTL	P22_1 / TRACE / TRACECTL.
IOPORT_PIN_P221_PFC_01_D8	P22_1 / BSC / D8.
IOPORT_PIN_P221_PFC_02_ESC_LINKACT2	P22_1 / ETHER_ESC / ESC_LINKACT2.
IOPORT_PIN_P221_PFC_03_POE4	P22_1 / MTU_POE3 / POE4.
IOPORT_PIN_P221_PFC_04_SS4_CTS4_RTS4	P22_1 / SCIn / SS4_CTS4_RTS4.
IOPORT_PIN_P221_PFC_05_HD8	P22_1 / PHOSTIF / HD8.
IOPORT_PIN_P221_PFC_06_GTETRGB	P22_1 / GPT_POEG / GTETRGB.
IOPORT_PIN_P222_PFC_00_IRQ4	P22_2 / IRQ / IRQ4.
IOPORT_PIN_P222_PFC_01_TRACECLK	P22_2 / TRACE / TRACECLK.
IOPORT_PIN_P222_PFC_02_D9	P22_2 / BSC / D9.
IOPORT_PIN_P222_PFC_03_MTIOC8C	P22_2 / MTU3n / MTIOC8C.
IOPORT_PIN_P222_PFC_04_GTETRGSA	P22_2 / GPT_POEG / GTETRGSA.
IOPORT_PIN_P222_PFC_05_SPI_SSL12	P22_2 / SPIn / SPI_SSL12.
IOPORT_PIN_P222_PFC_07_HD9	P22_2 / PHOSTIF / HD9.
IOPORT_PIN_P222_PFC_08_MCLK1	P22_2 / DSMIFn / MCLK1.
IOPORT_PIN_P223_PFC_00_D10	P22_3 / BSC / D10.
IOPORT_PIN_P223_PFC_01_MTIOC8D	P22_3 / MTU3n / MTIOC8D.
IOPORT_PIN_P223_PFC_02_GTETRGSB	P22_3 / GPT_POEG / GTETRGSB.
IOPORT_PIN_P223_PFC_04_RXD5_SCL5_MISO5	P22_3 / SCIn / RXD5_SCL5_MISO5.
IOPORT_PIN_P223_PFC_05_HD10	P22_3 / PHOSTIF / HD10.
IOPORT_PIN_P237_PFC_00_ETH2_RXD0	P23_7 / ETHER_ETHn / ETH2_RXD0.
IOPORT_PIN_P237_PFC_02_D11	P23_7 / BSC / D11.
IOPORT_PIN_P237_PFC_03_BS	P23_7 / BSC / BS.
IOPORT_PIN_P237_PFC_04_MTIOC0A	P23_7 / MTU3n / MTIOC0A.
IOPORT_PIN_P237_PFC_05_GTETRGA	P23_7 / GPT_POEG / GTETRGA.
IOPORT_PIN_P237_PFC_06_SCK1	P23_7 / SCIn / SCK1.
IOPORT_PIN_P237_PFC_07_MCLK4	P23_7 / DSMIFn / MCLK4.
IOPORT_PIN_P237_PFC_09_HD11	P23_7 / PHOSTIF / HD11.
IOPORT_PIN_P240_PFC_00_ETH2_RXD1	P24_0 / ETHER_ETHn / ETH2_RXD1.
IOPORT_PIN_P240_PFC_02_D12	P24_0 / BSC / D12.
IOPORT_PIN_P240_PFC_03_CKE	P24_0 / BSC / CKE.
IOPORT_PIN_P240_PFC_04_MTIOC0B	P24_0 / MTU3n / MTIOC0B.
IOPORT_PIN_P240_PFC_05_GTETRGB	P24_0 / GPT_POEG / GTETRGB.
IOPORT_PIN_P240_PFC_06_RXD1_SCL1_MISO1	P24_0 / SCIn / RXD1_SCL1_MISO1.
IOPORT_PIN_P240_PFC_07_DREQ	P24_0 / DMAC / DREQ.
IOPORT_PIN_P240_PFC_08_MDAT4	P24_0 / DSMIFn / MDAT4.
IOPORT_PIN_P240_PFC_0A_HD12	P24_0 / PHOSTIF / HD12.
IOPORT_PIN_P241_PFC_00_ETH2_RXCLK	P24_1 / ETHER_ETHn / ETH2_RXCLK.
IOPORT_PIN_P241_PFC_02_D13	P24_1 / BSC / D13.
IOPORT_PIN_P241_PFC_03_CAS	P24_1 / BSC / CAS.
IOPORT_PIN_P241_PFC_04_MTIOC0C	P24_1 / MTU3n / MTIOC0C.
IOPORT_PIN_P241_PFC_05_GTETRGC	P24_1 / GPT_POEG / GTETRGC.
IOPORT_PIN_P241_PFC_06_POE8	P24_1 / MTU_POE3 / POE8.
IOPORT_PIN_P241_PFC_07_MCLK5	P24_1 / DSMIFn / MCLK5.
IOPORT_PIN_P241_PFC_09_HD13	P24_1 / PHOSTIF / HD13.
IOPORT_PIN_P242_PFC_00_ETH2_RXD2	P24_2 / ETHER_ETHn / ETH2_RXD2.
IOPORT_PIN_P242_PFC_02_D14	P24_2 / BSC / D14.
IOPORT_PIN_P242_PFC_03_RAS	P24_2 / BSC / RAS.
IOPORT_PIN_P242_PFC_04_MTIOC0D	P24_2 / MTU3n / MTIOC0D.
IOPORT_PIN_P242_PFC_05_GTETRGD	P24_2 / GPT_POEG / GTETRGD.
IOPORT_PIN_P242_PFC_06_TXD1_SDA1_MOSI1	P24_2 / SCIn / TXD1_SDA1_MOSI1.
IOPORT_PIN_P242_PFC_07_MDAT5	P24_2 / DSMIFn / MDAT5.
IOPORT_PIN_P242_PFC_09_HD14	P24_2 / PHOSTIF / HD14.
IOPORT_PERIPHERAL_END	Marks end of enum - used by parameter checking

ioport_cfg_options_t [1/2]

enum ioport_cfg_options_t

Options to configure pin functions

Enumerator
IOPORT_CFG_PORT_DIRECTION_HIZ	Sets the pin direction to Hi-Z.
IOPORT_CFG_PORT_DIRECTION_INPUT	Sets the pin direction to input (default)
IOPORT_CFG_PORT_DIRECTION_OUTPUT	Sets the pin direction to output.
IOPORT_CFG_PORT_DIRECTION_OUTPUT_INPUT	Sets the pin direction to output (data is input to input buffer)
IOPORT_CFG_PORT_OUTPUT_LOW	Sets the pin level to low.
IOPORT_CFG_PORT_OUTPUT_HIGH	Sets the pin level to high.
IOPORT_CFG_PORT_GPIO	Enables pin to operate as an GPIO pin.
IOPORT_CFG_PORT_PERI	Enables pin to operate as a peripheral pin.
IOPORT_CFG_DRIVE_LOW	Sets pin drive output to low.
IOPORT_CFG_DRIVE_MID	Sets pin drive output to medium.
IOPORT_CFG_DRIVE_HIGH	Sets pin drive output to high.
IOPORT_CFG_DRIVE_UHIGH	Sets pin drive output to ultra high.
IOPORT_CFG_PULLUP_DOWN_DISABLE	Disables the pin's pull-up / pull-down.
IOPORT_CFG_PULLUP_ENABLE	Enables the pin's internal pull-up.
IOPORT_CFG_PULLDOWN_ENABLE	Enables the pin's pull-down.
IOPORT_CFG_SCHMITT_TRIGGER_DISABLE	Disables schmitt trigger input.
IOPORT_CFG_SCHMITT_TRIGGER_ENABLE	Enables schmitt trigger input.
IOPORT_CFG_SLEW_RATE_SLOW	Sets the slew rate to slow.
IOPORT_CFG_SLEW_RATE_FAST	Sets the slew rate to fast.
IOPORT_CFG_REGION_SAFETY	Selects safety region.
IOPORT_CFG_REGION_NSAFETY	Selects non safety region.
IOPORT_CFG_PIM_TTL	This macro has been unsupported.
IOPORT_CFG_NMOS_ENABLE	This macro has been unsupported.
IOPORT_CFG_PMOS_ENABLE	This macro has been unsupported.
IOPORT_CFG_DRIVE_HS_HIGH	This macro has been unsupported.
IOPORT_CFG_DRIVE_MID_IIC	This macro has been unsupported.
IOPORT_CFG_EVENT_RISING_EDGE	This macro has been unsupported.
IOPORT_CFG_EVENT_FALLING_EDGE	This macro has been unsupported.
IOPORT_CFG_EVENT_BOTH_EDGES	This macro has been unsupported.
IOPORT_CFG_IRQ_ENABLE	This macro has been unsupported.
IOPORT_CFG_ANALOG_ENABLE	This macro has been unsupported.
IOPORT_CFG_PERIPHERAL_PIN	This macro has been unsupported.
IOPORT_CFG_PORT_DIRECTION_HIZ	Sets the pin direction to Hi-Z.
IOPORT_CFG_PORT_DIRECTION_INPUT	Sets the pin direction to input (default)
IOPORT_CFG_PORT_DIRECTION_OUTPUT	Sets the pin direction to output.
IOPORT_CFG_PORT_DIRECTION_OUTPUT_INPUT	Sets the pin direction to output (data is input to input buffer)
IOPORT_CFG_PORT_OUTPUT_LOW	Sets the pin level to low.
IOPORT_CFG_PORT_OUTPUT_HIGH	Sets the pin level to high.
IOPORT_CFG_PORT_GPIO	Enables pin to operate as an GPIO pin.
IOPORT_CFG_PORT_PERI	Enables pin to operate as a peripheral pin.
IOPORT_CFG_DRIVE_LOW	Sets pin drive output to low.
IOPORT_CFG_DRIVE_MID	Sets pin drive output to medium.
IOPORT_CFG_DRIVE_HIGH	Sets pin drive output to high.
IOPORT_CFG_DRIVE_UHIGH	Sets pin drive output to ultra high.
IOPORT_CFG_PULLUP_DOWN_DISABLE	Disables the pin's pull-up / pull-down.
IOPORT_CFG_PULLUP_ENABLE	Enables the pin's internal pull-up.
IOPORT_CFG_PULLDOWN_ENABLE	Enables the pin's pull-down.
IOPORT_CFG_SCHMITT_TRIGGER_DISABLE	Disables schmitt trigger input.
IOPORT_CFG_SCHMITT_TRIGGER_ENABLE	Enables schmitt trigger input.
IOPORT_CFG_SLEW_RATE_SLOW	Sets the slew rate to slow.
IOPORT_CFG_SLEW_RATE_FAST	Sets the slew rate to fast.
IOPORT_CFG_REGION_SAFETY	Selects safety region.
IOPORT_CFG_REGION_NSAFETY	Selects non safety region.
IOPORT_CFG_PIM_TTL	This macro has been unsupported.
IOPORT_CFG_NMOS_ENABLE	This macro has been unsupported.
IOPORT_CFG_PMOS_ENABLE	This macro has been unsupported.
IOPORT_CFG_DRIVE_HS_HIGH	This macro has been unsupported.
IOPORT_CFG_DRIVE_MID_IIC	This macro has been unsupported.
IOPORT_CFG_EVENT_RISING_EDGE	This macro has been unsupported.
IOPORT_CFG_EVENT_FALLING_EDGE	This macro has been unsupported.
IOPORT_CFG_EVENT_BOTH_EDGES	This macro has been unsupported.
IOPORT_CFG_IRQ_ENABLE	This macro has been unsupported.
IOPORT_CFG_ANALOG_ENABLE	This macro has been unsupported.
IOPORT_CFG_PERIPHERAL_PIN	This macro has been unsupported.

ether_event_t [1/2]

enum ether_event_t

Event code of callback function

Enumerator
ETHER_EVENT_WAKEON_LAN	Magic packet detection event.
ETHER_EVENT_LINK_ON	Link up detection event.
ETHER_EVENT_LINK_OFF	Link down detection event.
ETHER_EVENT_RX_COMPLETE	Receive complete event.
ETHER_EVENT_RX_MESSAGE_LOST	Receive FIFO overflow or Receive descriptor is full.
ETHER_EVENT_TX_COMPLETE	Transmit complete event.
ETHER_EVENT_TX_BUFFER_EMPTY	Transmit descriptor or FIFO is empty.
ETHER_EVENT_TX_ABORTED	Transmit abort event.
ETHER_EVENT_ERR_GLOBAL	Global error has occurred.
ETHER_EVENT_GET_NIC_INFO	Get NIC Info.
ETHER_EVENT_WAKEON_LAN	Magic packet detection event.
ETHER_EVENT_LINK_ON	Link up detection event.
ETHER_EVENT_LINK_OFF	Link down detection event.
ETHER_EVENT_SBD_INTERRUPT	SBD Interrupt event.
ETHER_EVENT_PMT_INTERRUPT	PMT Interrupt event.
ETHER_EVENT_WAKEON_LAN	Magic packet detection event.
ETHER_EVENT_LINK_ON	Link up detection event.
ETHER_EVENT_LINK_OFF	Link down detection event.
ETHER_EVENT_SBD_INTERRUPT	SBD Interrupt event.
ETHER_EVENT_PMT_INTERRUPT	PMT Interrupt event.

ether_switch_event_t [1/2]

enum ether_switch_event_t

Ether Switch Event code of callback function

Enumerator
ETHER_SWITCH_EVENT_RX_COMPLETE	A descriptor complete to receive a flame.
ETHER_SWITCH_EVENT_TX_COMPLETE	A descriptor complete to transmit a flame.
ETHER_SWITCH_EVENT_RX_QUEUE_FULL	A RX descriptor queue is full.
ETHER_SWITCH_EVENT_RX_MESSAGE_LOST	Receive a frame when a RX descriptor queue is full.
ETHER_SWITCH_EVENT_TAS_ERROR	TAS gate error.
ETHER_SWITCH_EVENT_LINK_CHANGE	Change Link status.
ETHER_SWITCH_EVENT_LINK_CHANGE	Change Link status.

ether_phy_lsi_type_t [1/2]

enum ether_phy_lsi_type_t

Phy LSI

Enumerator
ETHER_PHY_LSI_TYPE_DEFAULT	Select default configuration. This type dose not change Phy LSI default setting by strapping option.
ETHER_PHY_LSI_TYPE_KSZ8091RNB	Select configuration for KSZ8091RNB.
ETHER_PHY_LSI_TYPE_KSZ8041	Select configuration for KSZ8041. Select configuration forKSZ8041.
ETHER_PHY_LSI_TYPE_DP83620	Select configuration for DP83620.
ETHER_PHY_LSI_TYPE_ICS1894	Select configuration for ICS1894.
ETHER_PHY_LSI_TYPE_GPY111	Select configuration for GPY111.
ETHER_PHY_LSI_TYPE_CUSTOM	Select configuration for User custom.
ETHER_PHY_LSI_TYPE_DEFAULT	Select default configuration. This type dose not change Phy LSI default setting by strapping option.
ETHER_PHY_LSI_TYPE_VSC8541	Select configuration forVSC8541.
ETHER_PHY_LSI_TYPE_KSZ9131	Select configuration forKSZ9131.
ETHER_PHY_LSI_TYPE_KSZ9031	Select configuration forKSZ9031.
ETHER_PHY_LSI_TYPE_KSZ8081	Select configuration forKSZ8081.
ETHER_PHY_LSI_TYPE_KSZ8041	Select configuration for KSZ8041. Select configuration forKSZ8041.
ETHER_PHY_LSI_TYPE_CUSTOM	Select configuration for User custom.
ETHER_PHY_LSI_TYPE_DEFAULT	Select default configuration. This type dose not change Phy LSI default setting by strapping option.
ETHER_PHY_LSI_TYPE_VSC8541	Select configuration forVSC8541.
ETHER_PHY_LSI_TYPE_KSZ9131	Select configuration forKSZ9131.
ETHER_PHY_LSI_TYPE_KSZ9031	Select configuration forKSZ9031.
ETHER_PHY_LSI_TYPE_KSZ8081	Select configuration forKSZ8081.
ETHER_PHY_LSI_TYPE_KSZ8041	Select configuration for KSZ8041. Select configuration forKSZ8041.
ETHER_PHY_LSI_TYPE_CUSTOM	Select configuration for User custom.

poe3_active_level_t [1/2]

enum poe3_active_level_t

POE3 active level for short circuit detection.

Enumerator
POE3_ACTIVE_LEVEL_HIGH	High level is set as the active level to detect a short circuit.
POE3_ACTIVE_LEVEL_LOW	Low level is set as the active level to detect a short circuit.
POE3_ACTIVE_LEVEL_SETTING_NONE	The active level of the pin is set by the timer peripheral side, not by POE3.
POE3_ACTIVE_LEVEL_HIGH	High level is set as the active level to detect a short circuit.
POE3_ACTIVE_LEVEL_LOW	Low level is set as the active level to detect a short circuit.
POE3_ACTIVE_LEVEL_SETTING_NONE	The active level of the pin is set by the timer peripheral side, not by POE3.
POE3_ACTIVE_LEVEL_HIGH	High level is set as the active level to detect a short circuit.
POE3_ACTIVE_LEVEL_LOW	Low level is set as the active level to detect a short circuit.
POE3_ACTIVE_LEVEL_SETTING_NONE	The active level of the pin is set by the timer peripheral side, not by POE3.

poeg_state_t [1/2]

enum poeg_state_t

POEG states.

Enumerator
POEG_STATE_NO_DISABLE_REQUEST	GPT output is not disabled by POEG.
POEG_STATE_PIN_DISABLE_REQUEST	GPT output disabled due to GTETRG pin level.
POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST	GPT output disabled due to high speed analog comparator or GPT.
POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST	GPT output disabled due to main oscillator stop.
POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST	GPT output disabled due to poeg_api_t::outputDisable()
POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE	GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input.
POEG_STATE_NO_DISABLE_REQUEST	GPT output is not disabled by POEG.
POEG_STATE_PIN_DISABLE_REQUEST	GPT output disabled due to GTETRG pin level.
POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST	GPT output disabled due to high speed analog comparator or GPT.
POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST	GPT output disabled due to main oscillator stop.
POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST	GPT output disabled due to poeg_api_t::outputDisable()
POEG_STATE_DSMIF0_DISABLE_REQUEST	GPT output disabled due to DSMIF0 error 0.
POEG_STATE_DSMIF1_DISABLE_REQUEST	GPT output disabled due to DSMIF1 error 0.
POEG_STATE_DSMIF2_DISABLE_REQUEST	GPT output disabled due to DSMIF2 error 0.
POEG_STATE_DSMIF3_DISABLE_REQUEST	GPT output disabled due to DSMIF3 error 0.
POEG_STATE_DSMIF4_DISABLE_REQUEST	GPT output disabled due to DSMIF4 error 0.
POEG_STATE_DSMIF5_DISABLE_REQUEST	GPT output disabled due to DSMIF5 error 0.
POEG_STATE_DSMIF7_DISABLE_REQUEST	GPT output disabled due to DSMIF7 error 0.
POEG_STATE_DSMIF8_DISABLE_REQUEST	GPT output disabled due to DSMIF8 error 0.
POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE	GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input.
POEG_STATE_DSMIF0_1_DISABLE_REQUEST	GPT output disabled due to DSMIF0 error 1.
POEG_STATE_DSMIF1_1_DISABLE_REQUEST	GPT output disabled due to DSMIF1 error 1.
POEG_STATE_DSMIF2_1_DISABLE_REQUEST	GPT output disabled due to DSMIF2 error 1.
POEG_STATE_DSMIF3_1_DISABLE_REQUEST	GPT output disabled due to DSMIF3 error 1.
POEG_STATE_DSMIF4_1_DISABLE_REQUEST	GPT output disabled due to DSMIF4 error 1.
POEG_STATE_DSMIF5_1_DISABLE_REQUEST	GPT output disabled due to DSMIF5 error 1.
POEG_STATE_DSMIF7_1_DISABLE_REQUEST	GPT output disabled due to DSMIF7 error 1.
POEG_STATE_DSMIF8_1_DISABLE_REQUEST	GPT output disabled due to DSMIF8 error 1.
POEG_STATE_NO_DISABLE_REQUEST	GPT output is not disabled by POEG.
POEG_STATE_PIN_DISABLE_REQUEST	GPT output disabled due to GTETRG pin level.
POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST	GPT output disabled due to high speed analog comparator or GPT.
POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST	GPT output disabled due to main oscillator stop.
POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST	GPT output disabled due to poeg_api_t::outputDisable()
POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE	GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input.
POEG_STATE_DSMIF0_DISABLE_REQUEST	GPT output disabled due to DSMIF0 error 0.
POEG_STATE_DSMIF1_DISABLE_REQUEST	GPT output disabled due to DSMIF1 error 0.

poeg_trigger_t [1/2]

enum poeg_trigger_t

Triggers that will disable GPT output pins.

Enumerator
POEG_TRIGGER_SOFTWARE	Software disable is always supported with POEG. Select this option if no other triggers are used.
POEG_TRIGGER_PIN	Disable GPT output based on GTETRG input level. Disable GPT output based on GTETRG input level(PIDE)
POEG_TRIGGER_GPT_OUTPUT_LEVEL	Disable GPT output based on GPT output pin levels. Disable GPT output based on GPT output pin levels(IOCE)
POEG_TRIGGER_OSCILLATION_STOP	Disable GPT output based on main oscillator stop. Disable GPT output based on main oscillator stop(OSPTE)
POEG_TRIGGER_ACMPHS0	Disable GPT output based on ACMPHS0 comparator result.
POEG_TRIGGER_ACMPHS1	Disable GPT output based on ACMPHS1 comparator result.
POEG_TRIGGER_ACMPHS2	Disable GPT output based on ACMPHS2 comparator result.
POEG_TRIGGER_ACMPHS3	Disable GPT output based on ACMPHS3 comparator result.
POEG_TRIGGER_ACMPHS4	Disable GPT output based on ACMPHS4 comparator result.
POEG_TRIGGER_ACMPHS5	Disable GPT output based on ACMPHS5 comparator result.
POEG_TRIGGER_SOFTWARE	Software disable is always supported with POEG. Select this option if no other triggers are used.
POEG_TRIGGER_PIN	Disable GPT output based on GTETRG input level. Disable GPT output based on GTETRG input level(PIDE)
POEG_TRIGGER_GPT_OUTPUT_LEVEL	Disable GPT output based on GPT output pin levels. Disable GPT output based on GPT output pin levels(IOCE)
POEG_TRIGGER_OSCILLATION_STOP	Disable GPT output based on main oscillator stop. Disable GPT output based on main oscillator stop(OSPTE)
POEG_TRIGGER_ACMPHS0	Disable GPT output based on ACMPHS0 comparator result.
POEG_TRIGGER_ACMPHS1	Disable GPT output based on ACMPHS1 comparator result.
POEG_TRIGGER_ACMPHS2	Disable GPT output based on ACMPHS2 comparator result.
POEG_TRIGGER_ACMPHS3	Disable GPT output based on ACMPHS3 comparator result.
POEG_TRIGGER_ACMPHS4	Disable GPT output based on ACMPHS4 comparator result.
POEG_TRIGGER_ACMPHS5	Disable GPT output based on ACMPHS5 comparator result.
POEG_TRIGGER_D0ERR0E	Permit output disabled by DSMIF0 error detection. The GPT output pins can be disabled when DSMIF error occurs (LLPP only).
POEG_TRIGGER_D1ERR0E	Permit output disabled by DSMIF1 error detection.
POEG_TRIGGER_D2ERR0E	Permit output disabled by DSMIF2 error detection.
POEG_TRIGGER_D3ERR0E	Permit output disabled by DSMIF3 error detection.
POEG_TRIGGER_D4ERR0E	Permit output disabled by DSMIF4 error detection.
POEG_TRIGGER_D5ERR0E	Permit output disabled by DSMIF5 error detection.
POEG_TRIGGER_D7ERR0E	Permit output disabled by DSMIF7 error detection.
POEG_TRIGGER_D8ERR0E	Permit output disabled by DSMIF8 error detection.
POEG_TRIGGER_D0ERR1E	Permit output disabled by DSMIF0 error 1 detection.
POEG_TRIGGER_D1ERR1E	Permit output disabled by DSMIF1 error 1 detection.
POEG_TRIGGER_D2ERR1E	Permit output disabled by DSMIF2 error 1 detection.
POEG_TRIGGER_D3ERR1E	Permit output disabled by DSMIF3 error 1 detection.
POEG_TRIGGER_D4ERR1E	Permit output disabled by DSMIF4 error 1 detection.
POEG_TRIGGER_D5ERR1E	Permit output disabled by DSMIF5 error 1 detection.
POEG_TRIGGER_D7ERR1E	Permit output disabled by DSMIF7 error 1 detection.
POEG_TRIGGER_D8ERR1E	Permit output disabled by DSMIF8 error 1 detection.
POEG_TRIGGER_SOFTWARE	Software disable is always supported with POEG. Select this option if no other triggers are used.
POEG_TRIGGER_PIN	Disable GPT output based on GTETRG input level. Disable GPT output based on GTETRG input level(PIDE)
POEG_TRIGGER_GPT_OUTPUT_LEVEL	Disable GPT output based on GPT output pin levels. Disable GPT output based on GPT output pin levels(IOCE)
POEG_TRIGGER_OSCILLATION_STOP	Disable GPT output based on main oscillator stop. Disable GPT output based on main oscillator stop(OSPTE)
POEG_TRIGGER_ACMPHS0	Disable GPT output based on ACMPHS0 comparator result.
POEG_TRIGGER_ACMPHS1	Disable GPT output based on ACMPHS1 comparator result.
POEG_TRIGGER_ACMPHS2	Disable GPT output based on ACMPHS2 comparator result.
POEG_TRIGGER_ACMPHS3	Disable GPT output based on ACMPHS3 comparator result.
POEG_TRIGGER_ACMPHS4	Disable GPT output based on ACMPHS4 comparator result.
POEG_TRIGGER_ACMPHS5	Disable GPT output based on ACMPHS5 comparator result.
POEG_TRIGGER_DERR0E	Permit output disabled by DSMIF0 error detection. The GPT output pins can be disabled when DSMIF error occurs (LLPP only).
POEG_TRIGGER_DERR1E	Permit output disabled by DSMIF1 error detection.

poe3_state_t [1/2]

enum poe3_state_t

POE3 states.

Enumerator
POE3_STATE_NO_DISABLE_REQUEST	Timer output is not disabled by POE3.
POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE0# pin.
POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE4# pin.
POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE8# pin.
POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE10# pin.
POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE11# pin.
POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST	Timer output disabled due to poe3_api_t::outputDisable()
POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST	Timer output disabled due to main oscillator stop.
POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST	Timer output disabled due to output short circuit 1.
POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST	Timer output disabled due to output short circuit 2.
POE3_STATE_NO_DISABLE_REQUEST	Timer output is not disabled by POE3.
POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE0# pin.
POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE4# pin.
POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE8# pin.
POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE10# pin.
POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE11# pin.
POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST	Timer output disabled due to poe3_api_t::outputDisable()
POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST	Timer output disabled due to main oscillator stop.
POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST	Timer output disabled due to output short circuit 1.
POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST	Timer output disabled due to output short circuit 2.
POE3_STATE_DSMIF0_ERROR_REQUEST	Timer output disabled due to DSMIF0 Error0. Timer output disabled due to DSMIF0 error.
POE3_STATE_DSMIF1_ERROR_REQUEST	Timer output disabled due to DSMIF1 Error0. Timer output disabled due to DSMIF1 error.
POE3_STATE_DSMIF2_ERROR_REQUEST	Timer output disabled due to DSMIF2 Error0.
POE3_STATE_DSMIF3_ERROR_REQUEST	Timer output disabled due to DSMIF3 Error0.
POE3_STATE_DSMIF4_ERROR_REQUEST	Timer output disabled due to DSMIF4 Error0.
POE3_STATE_DSMIF5_ERROR_REQUEST	Timer output disabled due to DSMIF5 Error0.
POE3_STATE_DSMIF7_ERROR_REQUEST	Timer output disabled due to DSMIF7 Error0.
POE3_STATE_DSMIF8_ERROR_REQUEST	Timer output disabled due to DSMIF8 Error0.
POE3_STATE_DSMIF0_1_ERROR_REQUEST	Timer output disabled due to DSMIF0 Error1.
POE3_STATE_DSMIF1_1_ERROR_REQUEST	Timer output disabled due to DSMIF1 Error1.
POE3_STATE_DSMIF2_1_ERROR_REQUEST	Timer output disabled due to DSMIF2 Error1.
POE3_STATE_DSMIF3_1_ERROR_REQUEST	Timer output disabled due to DSMIF3 Error1.
POE3_STATE_DSMIF4_1_ERROR_REQUEST	Timer output disabled due to DSMIF4 Error1.
POE3_STATE_DSMIF5_1_ERROR_REQUEST	Timer output disabled due to DSMIF5 Error1.
POE3_STATE_DSMIF7_1_ERROR_REQUEST	Timer output disabled due to DSMIF7 Error1.
POE3_STATE_DSMIF8_1_ERROR_REQUEST	Timer output disabled due to DSMIF8 Error1.
POE3_STATE_NO_DISABLE_REQUEST	Timer output is not disabled by POE3.
POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE0# pin.
POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE4# pin.
POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE8# pin.
POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE10# pin.
POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE11# pin.
POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST	Timer output disabled due to poe3_api_t::outputDisable()
POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST	Timer output disabled due to main oscillator stop.
POE3_STATE_DSMIF0_ERROR_REQUEST	Timer output disabled due to DSMIF0 Error0. Timer output disabled due to DSMIF0 error.
POE3_STATE_DSMIF1_ERROR_REQUEST	Timer output disabled due to DSMIF1 Error0. Timer output disabled due to DSMIF1 error.
POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST	Timer output disabled due to output short circuit 1.
POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST	Timer output disabled due to output short circuit 2.

transfer_event_t [1/2]

enum transfer_event_t

Events that can trigger a callback function.

Enumerator
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.

transfer_mode_t [1/2]

enum transfer_mode_t

Transfer mode describes what will happen when a transfer request occurs.

Enumerator
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_REPEAT	Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the repeat area and the transfer length will be reset to their initial values. If DMAC is used, the transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is used, the transfer repeats continuously (no limit to the number of repeat transfers).
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_REPEAT_BLOCK	In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets within a block (to split blocks into arrays of their first data, second data, etc.)
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.

transfer_size_t [1/2]

enum transfer_size_t

Transfer size specifies the size of each individual transfer.

Enumerator
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.

transfer_addr_mode_t [1/2]

enum transfer_addr_mode_t

Address mode specifies whether to modify (increment or decrement) pointer after each transfer.

Enumerator
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_OFFSET	Offset is added to the address pointer after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZN::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_DECREMENTED	Address pointer is decremented by associated transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZN::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZN::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.

adc_channel_t [2/2]

enum adc_channel_t

ADC channels

Enumerator
ADC_CHANNEL_0	ADC channel 0.
ADC_CHANNEL_1	ADC channel 1.
ADC_CHANNEL_2	ADC channel 2.
ADC_CHANNEL_3	ADC channel 3.
ADC_CHANNEL_4	ADC channel 4.
ADC_CHANNEL_5	ADC channel 5.
ADC_CHANNEL_6	ADC channel 6.
ADC_CHANNEL_7	ADC channel 7.
ADC_CHANNEL_8	ADC channel 8.
ADC_CHANNEL_9	ADC channel 9.
ADC_CHANNEL_10	ADC channel 10.
ADC_CHANNEL_11	ADC channel 11.
ADC_CHANNEL_12	ADC channel 12.
ADC_CHANNEL_13	ADC channel 13.
ADC_CHANNEL_14	ADC channel 14.
ADC_CHANNEL_15	ADC channel 15.
ADC_CHANNEL_16	ADC channel 16.
ADC_CHANNEL_17	ADC channel 17.
ADC_CHANNEL_18	ADC channel 18.
ADC_CHANNEL_19	ADC channel 19.
ADC_CHANNEL_20	ADC channel 20.
ADC_CHANNEL_21	ADC channel 21.
ADC_CHANNEL_22	ADC channel 22.
ADC_CHANNEL_23	ADC channel 23.
ADC_CHANNEL_24	ADC channel 24.
ADC_CHANNEL_25	ADC channel 25.
ADC_CHANNEL_26	ADC channel 26.
ADC_CHANNEL_27	ADC channel 27.
ADC_CHANNEL_28	ADC channel 28.
ADC_CHANNEL_DUPLEX_A	Data duplexing register A.
ADC_CHANNEL_DUPLEX_B	Data duplexing register B.
ADC_CHANNEL_DUPLEX	Data duplexing register.
ADC_CHANNEL_TEMPERATURE	Temperature sensor output.
ADC_CHANNEL_VOLT	Internal reference voltage.
ADC_CHANNEL_0	ADC channel 0.
ADC_CHANNEL_1	ADC channel 1.
ADC_CHANNEL_2	ADC channel 2.
ADC_CHANNEL_3	ADC channel 3.
ADC_CHANNEL_4	ADC channel 4.
ADC_CHANNEL_5	ADC channel 5.
ADC_CHANNEL_6	ADC channel 6.
ADC_CHANNEL_7	ADC channel 7.
ADC_CHANNEL_8	ADC channel 8.
ADC_CHANNEL_9	ADC channel 9.
ADC_CHANNEL_10	ADC channel 10.
ADC_CHANNEL_11	ADC channel 11.
ADC_CHANNEL_12	ADC channel 12.
ADC_CHANNEL_13	ADC channel 13.
ADC_CHANNEL_14	ADC channel 14.
ADC_CHANNEL_15	ADC channel 15.
ADC_CHANNEL_16	ADC channel 16.
ADC_CHANNEL_17	ADC channel 17.
ADC_CHANNEL_18	ADC channel 18.
ADC_CHANNEL_19	ADC channel 19.
ADC_CHANNEL_20	ADC channel 20.
ADC_CHANNEL_21	ADC channel 21.
ADC_CHANNEL_22	ADC channel 22.
ADC_CHANNEL_23	ADC channel 23.
ADC_CHANNEL_24	ADC channel 24.
ADC_CHANNEL_25	ADC channel 25.
ADC_CHANNEL_26	ADC channel 26.
ADC_CHANNEL_27	ADC channel 27.
ADC_CHANNEL_28	ADC channel 28.
ADC_CHANNEL_DUPLEX_A	Data duplexing register A.
ADC_CHANNEL_DUPLEX_B	Data duplexing register B.
ADC_CHANNEL_DUPLEX	Data duplexing register.
ADC_CHANNEL_TEMPERATURE	Temperature sensor output.
ADC_CHANNEL_VOLT	Internal reference voltage.
ADC_CHANNEL_0_DSMIF_CAPTURE_A	ADC channel 0 Capture Current Data Register A.
ADC_CHANNEL_0_DSMIF_CAPTURE_B	ADC channel 0 Capture Current Data Register B.
ADC_CHANNEL_1_DSMIF_CAPTURE_A	ADC channel 1 Capture Current Data Register A.
ADC_CHANNEL_1_DSMIF_CAPTURE_B	ADC channel 1 Capture Current Data Register B.
ADC_CHANNEL_2_DSMIF_CAPTURE_A	ADC channel 2 Capture Current Data Register A.
ADC_CHANNEL_2_DSMIF_CAPTURE_B	ADC channel 2 Capture Current Data Register B.
ADC_CHANNEL_0	ADC channel 0.
ADC_CHANNEL_1	ADC channel 1.
ADC_CHANNEL_2	ADC channel 2.
ADC_CHANNEL_3	ADC channel 3.
ADC_CHANNEL_4	ADC channel 4.
ADC_CHANNEL_5	ADC channel 5.
ADC_CHANNEL_6	ADC channel 6.
ADC_CHANNEL_7	ADC channel 7.
ADC_CHANNEL_8	ADC channel 8.
ADC_CHANNEL_9	ADC channel 9.
ADC_CHANNEL_10	ADC channel 10.
ADC_CHANNEL_11	ADC channel 11.
ADC_CHANNEL_12	ADC channel 12.
ADC_CHANNEL_13	ADC channel 13.
ADC_CHANNEL_14	ADC channel 14.
ADC_CHANNEL_15	ADC channel 15.
ADC_CHANNEL_16	ADC channel 16.
ADC_CHANNEL_17	ADC channel 17.
ADC_CHANNEL_18	ADC channel 18.
ADC_CHANNEL_19	ADC channel 19.
ADC_CHANNEL_20	ADC channel 20.
ADC_CHANNEL_21	ADC channel 21.
ADC_CHANNEL_22	ADC channel 22.
ADC_CHANNEL_23	ADC channel 23.
ADC_CHANNEL_24	ADC channel 24.
ADC_CHANNEL_25	ADC channel 25.
ADC_CHANNEL_26	ADC channel 26.
ADC_CHANNEL_27	ADC channel 27.
ADC_CHANNEL_DUPLEX_A	Data duplexing register A.
ADC_CHANNEL_DUPLEX_B	Data duplexing register B.
ADC_CHANNEL_DUPLEX	Data duplexing register.
ADC_CHANNEL_TEMPERATURE	Temperature sensor output.
ADC_CHANNEL_VOLT	Internal reference voltage.
ADC_CHANNEL_0_DSMIF_CAPTURE_A	ADC channel 0 Capture Current Data Register A.
ADC_CHANNEL_0_DSMIF_CAPTURE_B	ADC channel 0 Capture Current Data Register B.
ADC_CHANNEL_1_DSMIF_CAPTURE_A	ADC channel 1 Capture Current Data Register A.
ADC_CHANNEL_1_DSMIF_CAPTURE_B	ADC channel 1 Capture Current Data Register B.
ADC_CHANNEL_2_DSMIF_CAPTURE_A	ADC channel 2 Capture Current Data Register A.
ADC_CHANNEL_2_DSMIF_CAPTURE_B	ADC channel 2 Capture Current Data Register B.

cgc_fsel_xspi_clock_div_t [2/2]

enum cgc_fsel_xspi_clock_div_t

Divider values of clock provided to xSPI

Enumerator
CGC_FSEL_XSPI_CLOCK_DIV_6	XSPI_CLKn 133.3MHz (XSPI base clock divided by 3)
CGC_FSEL_XSPI_CLOCK_DIV_8	XSPI_CLKn 100.0MHz / 75.0MHz (XSPI base clock divided by 3 / divided by 4)
CGC_FSEL_XSPI_CLOCK_DIV_16	XSPI_CLKn 50.0MHz / 37.5MHz (XSPI base clock divided by 3 / divided by 4)
CGC_FSEL_XSPI_CLOCK_DIV_32	XSPI_CLKn 25.0MHz (XSPI base clock divided by 3)
CGC_FSEL_XSPI_CLOCK_DIV_64	XSPI_CLKn 12.5MHz (XSPI base clock divided by 3)
CGC_FSEL_XSPI_CLOCK_DIV_6	XSPI_CLKn 133.3MHz (XSPI base clock divided by 3)
CGC_FSEL_XSPI_CLOCK_DIV_8	XSPI_CLKn 100.0MHz / 75.0MHz (XSPI base clock divided by 3 / divided by 4)
CGC_FSEL_XSPI_CLOCK_DIV_16	XSPI_CLKn 50.0MHz / 37.5MHz (XSPI base clock divided by 3 / divided by 4)
CGC_FSEL_XSPI_CLOCK_DIV_32	XSPI_CLKn 25.0MHz (XSPI base clock divided by 3)
CGC_FSEL_XSPI_CLOCK_DIV_64	XSPI_CLKn 12.5MHz (XSPI base clock divided by 3)

cgc_divsel_xspi_clock_div_t [2/2]

enum cgc_divsel_xspi_clock_div_t

Divider values of base clock generated for xSPI

Enumerator
CGC_DIVSEL_XSPI_CLOCK_DIV_3	XSPI base clock divided by 3.
CGC_DIVSEL_XSPI_CLOCK_DIV_4	XSPI base clock divided by 4.
CGC_DIVSEL_XSPI_CLOCK_DIV_3	XSPI base clock divided by 3.
CGC_DIVSEL_XSPI_CLOCK_DIV_4	XSPI base clock divided by 4.

cgc_clock_out_clock_div_t [2/2]

enum cgc_clock_out_clock_div_t

Clock output divider values

Enumerator
CGC_CLOCK_OUT_CLOCK_DIV_2	CKIO 100.0MHz / 75.0MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_3	CKIO 66.7MHz / 50.0MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_4	CKIO 50.0MHz / 37.5MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_5	CKIO 40.0MHz / 30.0MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_6	CKIO 33.3MHz / 25.0MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_7	CKIO 28.6MHz / 21.4MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_8	CKIO 25.0MHz / 18.75MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_2	CKIO 100.0MHz / 75.0MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_3	CKIO 66.7MHz / 50.0MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_4	CKIO 50.0MHz / 37.5MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_5	CKIO 40.0MHz / 30.0MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_6	CKIO 33.3MHz / 25.0MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_7	CKIO 28.6MHz / 21.4MHz (Base clock divided by 3 / divided by 4)
CGC_CLOCK_OUT_CLOCK_DIV_8	CKIO 25.0MHz / 18.75MHz (Base clock divided by 3 / divided by 4)

cgc_canfd_clock_div_t [2/2]

enum cgc_canfd_clock_div_t

CANFD clock divider values

Enumerator
CGC_CANFD_CLOCK_DIV_10	CANFD clock 80.0MHz.
CGC_CANFD_CLOCK_DIV_20	CANFD clock 40.0MHz.
CGC_CANFD_CLOCK_DIV_10	CANFD clock 80.0MHz.
CGC_CANFD_CLOCK_DIV_20	CANFD clock 40.0MHz.

cgc_phy_clock_t [2/2]

enum cgc_phy_clock_t

PHY clock source identifiers

Enumerator
CGC_PHY_CLOCK_PLL1	PLL1 divider clock.
CGC_PHY_CLOCK_MAIN_OSC	Main clock oscillator.
CGC_PHY_CLOCK_PLL1	PLL1 divider clock.
CGC_PHY_CLOCK_MAIN_OSC	Main clock oscillator.

cgc_spi_async_clock_t [2/2]

enum cgc_spi_async_clock_t

SPI asynchronous serial clock frequency

Enumerator
CGC_SPI_ASYNC_CLOCK_75MHZ	SPI asynchronous serial clock 75MHz.
CGC_SPI_ASYNC_CLOCK_80MHZ	SPI asynchronous serial clock 80MHz.
CGC_SPI_ASYNC_CLOCK_96MHZ	SPI asynchronous serial clock 96MHz.
CGC_SPI_ASYNC_CLOCK_100MHZ	SPI asynchronous serial clock 100MHz.
CGC_SPI_ASYNC_CLOCK_75MHZ	SPI asynchronous serial clock 75MHz.
CGC_SPI_ASYNC_CLOCK_96MHZ	SPI asynchronous serial clock 96MHz.

cgc_sci_async_clock_t [2/2]

enum cgc_sci_async_clock_t

SCI asynchronous serial clock frequency

Enumerator
CGC_SCI_ASYNC_CLOCK_75MHZ	SCI asynchronous serial clock 75MHz.
CGC_SCI_ASYNC_CLOCK_80MHZ	SCI asynchronous serial clock 80MHz.
CGC_SCI_ASYNC_CLOCK_96MHZ	SCI asynchronous serial clock 96MHz.
CGC_SCI_ASYNC_CLOCK_100MHZ	SCI asynchronous serial clock 100MHz.
CGC_SCI_ASYNC_CLOCK_75MHZ	SCI asynchronous serial clock 75MHz.
CGC_SCI_ASYNC_CLOCK_96MHZ	SCI asynchronous serial clock 96MHz.

cgc_cpu_clock_div_t [2/2]

enum cgc_cpu_clock_div_t

CPU clock divider values

Enumerator
CGC_CPU_CLOCK_DIV_2	CR52/DSU 500MHz, CA55 600MHz. CPU 200.0MHz / 150.0MHz (Base clock divided by 3 / divided by 4)
CGC_CPU_CLOCK_DIV_1	CR52/DSU 1000MHz, CA55 1200MHz. CPU 400.0MHz / 300.0MHz (Base clock divided by 3 / divided by 4)
CGC_CPU_CLOCK_DIV_2	CR52/DSU 500MHz, CA55 600MHz. CPU 200.0MHz / 150.0MHz (Base clock divided by 3 / divided by 4)
CGC_CPU_CLOCK_DIV_1	CR52/DSU 1000MHz, CA55 1200MHz. CPU 400.0MHz / 300.0MHz (Base clock divided by 3 / divided by 4)

cgc_baseclock_div_t

enum cgc_baseclock_div_t

Base clock divider values

Enumerator
CGC_BASECLOCK_DIV_3	Base clock divided by 3 (ICLK=200.0MHz etc.)
CGC_BASECLOCK_DIV_4	Base clock divided by 4 (ICLK=150.0MHz etc.)

cgc_clock_t [2/2]

enum cgc_clock_t

System clock source identifiers

Enumerator
CGC_CLOCK_HOCO	The high speed on chip oscillator.
CGC_CLOCK_MOCO	The middle speed on chip oscillator.
CGC_CLOCK_LOCO	The low speed on chip oscillator.
CGC_CLOCK_MAIN_OSC	The main oscillator.
CGC_CLOCK_SUBCLOCK	The subclock oscillator.
CGC_CLOCK_PLL	The PLL oscillator.
CGC_CLOCK_PLL2	The PLL2 oscillator.
CGC_CLOCK_LOCO	The low speed on chip oscillator.
CGC_CLOCK_PLL0	The PLL0 oscillator.
CGC_CLOCK_PLL1	The PLL1 oscillator.
CGC_CLOCK_PLL2	The PLL2 oscillator.
CGC_CLOCK_PLL3	The PLL3 oscillator.
CGC_CLOCK_PLL4	The PLL4 oscillator.
CGC_CLOCK_LOCO	The low speed on chip oscillator.
CGC_CLOCK_PLL0	The PLL0 oscillator.
CGC_CLOCK_PLL1	The PLL1 oscillator.

cgc_clock_change_t [2/2]

enum cgc_clock_change_t

Clock options

Enumerator
CGC_CLOCK_CHANGE_START	Start the clock.
CGC_CLOCK_CHANGE_STOP	Stop the clock.
CGC_CLOCK_CHANGE_NONE	No change to the clock.
CGC_CLOCK_CHANGE_START	Start the clock.
CGC_CLOCK_CHANGE_STOP	Stop the clock.
CGC_CLOCK_CHANGE_NONE	No change to the clock.
CGC_CLOCK_CHANGE_START	Start the clock.
CGC_CLOCK_CHANGE_STOP	Stop the clock.
CGC_CLOCK_CHANGE_NONE	No change to the clock.

elc_peripheral_t [2/2]

enum elc_peripheral_t

Possible peripherals to be linked to event signals (not all available on all MPUs)

error_event_t [2/2]

enum error_event_t

Error event source.

Enumerator
ERROR_EVENT_CPU0	Error event from CPU0. Error event from CR520.
ERROR_EVENT_CPU1	Error event from CPU1. Error event from CR521.
ERROR_EVENT_PERIPHERAL_0	Error event from Peripheral 0.
ERROR_EVENT_PERIPHERAL_1	Error event from Peripheral 1.
ERROR_EVENT_CPU0	Error event from CPU0. Error event from CR520.
ERROR_EVENT_CPU1	Error event from CPU1. Error event from CR521.
ERROR_EVENT_CA55	Error event from CA55.
ERROR_EVENT_PERIPHERAL_0	Error event from Peripheral 0.
ERROR_EVENT_PERIPHERAL_1	Error event from Peripheral 1.
ERROR_EVENT_PERIPHERAL_2	Error event from Peripheral 2.
ERROR_EVENT_DSMIF_0	Error event from DSMIF 0.
ERROR_EVENT_DSMIF_1	Error event from DSMIF 1.
ERROR_EVENT_DSMIF_2	Error event from DSMIF 2.
ERROR_EVENT_DSMIF_3	Error event from DSMIF 3.
ERROR_EVENT_DSMIF_4	Error event from DSMIF 4.
ERROR_EVENT_DSMIF_5	Error event from DSMIF 5.
ERROR_EVENT_DSMIF_7	Error event from DSMIF 7.
ERROR_EVENT_DSMIF_8	Error event from DSMIF 8.
ERROR_EVENT_DSMIF_10	Error event from DSMIF 10.
ERROR_EVENT_DSMIF_11	Error event from DSMIF 11.
ERROR_EVENT_ENCIF_0	Error event from ENCIF 0.
ERROR_EVENT_ENCIF_1	Error event from ENCIF 1.
ERROR_EVENT_ENCIF_2	Error event from ENCIF 2.
ERROR_EVENT_ENCIF_3	Error event from ENCIF 3.
ERROR_EVENT_ENCIF_4	Error event from ENCIF 4.
ERROR_EVENT_CPU0	Error event from CPU0. Error event from CR520.
ERROR_EVENT_PERIPHERAL_0	Error event from Peripheral 0.
ERROR_EVENT_PERIPHERAL_1	Error event from Peripheral 1.

ether_event_t [2/2]

enum ether_event_t

Event code of callback function

Enumerator
ETHER_EVENT_WAKEON_LAN	Magic packet detection event.
ETHER_EVENT_LINK_ON	Link up detection event.
ETHER_EVENT_LINK_OFF	Link down detection event.
ETHER_EVENT_RX_COMPLETE	Receive complete event.
ETHER_EVENT_RX_MESSAGE_LOST	Receive FIFO overflow or Receive descriptor is full.
ETHER_EVENT_TX_COMPLETE	Transmit complete event.
ETHER_EVENT_TX_BUFFER_EMPTY	Transmit descriptor or FIFO is empty.
ETHER_EVENT_TX_ABORTED	Transmit abort event.
ETHER_EVENT_ERR_GLOBAL	Global error has occurred.
ETHER_EVENT_GET_NIC_INFO	Get NIC Info.
ETHER_EVENT_WAKEON_LAN	Magic packet detection event.
ETHER_EVENT_LINK_ON	Link up detection event.
ETHER_EVENT_LINK_OFF	Link down detection event.
ETHER_EVENT_SBD_INTERRUPT	SBD Interrupt event.
ETHER_EVENT_PMT_INTERRUPT	PMT Interrupt event.
ETHER_EVENT_WAKEON_LAN	Magic packet detection event.
ETHER_EVENT_LINK_ON	Link up detection event.
ETHER_EVENT_LINK_OFF	Link down detection event.
ETHER_EVENT_SBD_INTERRUPT	SBD Interrupt event.
ETHER_EVENT_PMT_INTERRUPT	PMT Interrupt event.

ether_phy_lsi_type_t [2/2]

enum ether_phy_lsi_type_t

Phy LSI

Enumerator
ETHER_PHY_LSI_TYPE_DEFAULT	Select default configuration. This type dose not change Phy LSI default setting by strapping option.
ETHER_PHY_LSI_TYPE_KSZ8091RNB	Select configuration for KSZ8091RNB.
ETHER_PHY_LSI_TYPE_KSZ8041	Select configuration for KSZ8041. Select configuration forKSZ8041.
ETHER_PHY_LSI_TYPE_DP83620	Select configuration for DP83620.
ETHER_PHY_LSI_TYPE_ICS1894	Select configuration for ICS1894.
ETHER_PHY_LSI_TYPE_GPY111	Select configuration for GPY111.
ETHER_PHY_LSI_TYPE_CUSTOM	Select configuration for User custom.
ETHER_PHY_LSI_TYPE_DEFAULT	Select default configuration. This type dose not change Phy LSI default setting by strapping option.
ETHER_PHY_LSI_TYPE_VSC8541	Select configuration forVSC8541.
ETHER_PHY_LSI_TYPE_KSZ9131	Select configuration forKSZ9131.
ETHER_PHY_LSI_TYPE_KSZ9031	Select configuration forKSZ9031.
ETHER_PHY_LSI_TYPE_KSZ8081	Select configuration forKSZ8081.
ETHER_PHY_LSI_TYPE_KSZ8041	Select configuration for KSZ8041. Select configuration forKSZ8041.
ETHER_PHY_LSI_TYPE_CUSTOM	Select configuration for User custom.
ETHER_PHY_LSI_TYPE_DEFAULT	Select default configuration. This type dose not change Phy LSI default setting by strapping option.
ETHER_PHY_LSI_TYPE_VSC8541	Select configuration forVSC8541.
ETHER_PHY_LSI_TYPE_KSZ9131	Select configuration forKSZ9131.
ETHER_PHY_LSI_TYPE_KSZ9031	Select configuration forKSZ9031.
ETHER_PHY_LSI_TYPE_KSZ8081	Select configuration forKSZ8081.
ETHER_PHY_LSI_TYPE_KSZ8041	Select configuration for KSZ8041. Select configuration forKSZ8041.
ETHER_PHY_LSI_TYPE_CUSTOM	Select configuration for User custom.

ether_switch_event_t [2/2]

enum ether_switch_event_t

Ether Switch Event code of callback function

Enumerator
ETHER_SWITCH_EVENT_RX_COMPLETE	A descriptor complete to receive a flame.
ETHER_SWITCH_EVENT_TX_COMPLETE	A descriptor complete to transmit a flame.
ETHER_SWITCH_EVENT_RX_QUEUE_FULL	A RX descriptor queue is full.
ETHER_SWITCH_EVENT_RX_MESSAGE_LOST	Receive a frame when a RX descriptor queue is full.
ETHER_SWITCH_EVENT_TAS_ERROR	TAS gate error.
ETHER_SWITCH_EVENT_LINK_CHANGE	Change Link status.
ETHER_SWITCH_EVENT_LINK_CHANGE	Change Link status.

ioport_pin_pfc_t [2/2]

enum ioport_pin_pfc_t

Superset of all peripheral functions.

Enumerator
IOPORT_PIN_P000_PFC_00_SEI	P00_0 / IRQ / SEI.
IOPORT_PIN_P000_PFC_04_D0	P00_0 / BSC / D0.
IOPORT_PIN_P000_PFC_06_MTIOC3B	P00_0 / MTU3 / MTIOC3B.
IOPORT_PIN_P000_PFC_09_GTIOC00_0A	P00_0 / GPT / GTIOC00_0A.
IOPORT_PIN_P000_PFC_0F_ETH3_TXER	P00_0 / ETHER_ETHn / ETH3_TXER.
IOPORT_PIN_P000_PFC_13_USB_VBUSEN	P00_0 / USB / USB_VBUSEN.
IOPORT_PIN_P000_PFC_24_DUEI00	P00_0 / ENDATn / DUEI00.
IOPORT_PIN_P000_PFC_25_HDSL00_LINK	P00_0 / HDSLn / HDSL00_LINK.
IOPORT_PIN_P001_PFC_00_IRQ0	P00_1 / IRQ / IRQ0.
IOPORT_PIN_P001_PFC_04_D1	P00_1 / BSC / D1.
IOPORT_PIN_P001_PFC_06_MTIOC3D	P00_1 / MTU3 / MTIOC3D.
IOPORT_PIN_P001_PFC_09_GTIOC00_0B	P00_1 / GPT / GTIOC00_0B.
IOPORT_PIN_P001_PFC_0F_ETH3_RXER	P00_1 / ETHER_ETHn / ETH3_RXER.
IOPORT_PIN_P001_PFC_13_USB_OVRCUR	P00_1 / USB / USB_OVRCUR.
IOPORT_PIN_P001_PFC_24_TST_OUT00	P00_1 / ENDATn / TST_OUT00.
IOPORT_PIN_P001_PFC_25_HDSL00_SMPL	P00_1 / HDSLn / HDSL00_SMPL.
IOPORT_PIN_P002_PFC_00_IRQ1	P00_2 / IRQ / IRQ1.
IOPORT_PIN_P002_PFC_04_D2	P00_2 / BSC / D2.
IOPORT_PIN_P002_PFC_06_MTIOC4A	P00_2 / MTU3 / MTIOC4A.
IOPORT_PIN_P002_PFC_09_GTIOC00_1A	P00_2 / GPT / GTIOC00_1A.
IOPORT_PIN_P002_PFC_0F_ETH3_CRS	P00_2 / ETHER_ETHn / ETH3_CRS.
IOPORT_PIN_P002_PFC_13_USB_EXICEN	P00_2 / USB / USB_EXICEN.
IOPORT_PIN_P002_PFC_1F_ADTRG0	P00_2 / ADCn / ADTRG0.
IOPORT_PIN_P002_PFC_24_SI00	P00_2 / ENDATn / SI00.
IOPORT_PIN_P002_PFC_25_HDSL00_CLK1	P00_2 / HDSLn / HDSL00_CLK1.
IOPORT_PIN_P003_PFC_00_IRQ2	P00_3 / IRQ / IRQ2.
IOPORT_PIN_P003_PFC_04_D3	P00_3 / BSC / D3.
IOPORT_PIN_P003_PFC_06_MTIOC4C	P00_3 / MTU3 / MTIOC4C.
IOPORT_PIN_P003_PFC_09_GTIOC00_1B	P00_3 / GPT / GTIOC00_1B.
IOPORT_PIN_P003_PFC_0F_ETH3_COL	P00_3 / ETHER_ETHn / ETH3_COL.
IOPORT_PIN_P003_PFC_1F_ADTRG1	P00_3 / ADCn / ADTRG1.
IOPORT_PIN_P003_PFC_24_DUEI01	P00_3 / ENDATn / DUEI01.
IOPORT_PIN_P003_PFC_25_HDSL00_SEL1	P00_3 / HDSLn / HDSL00_SEL1.
IOPORT_PIN_P004_PFC_00_IRQ3	P00_4 / IRQ / IRQ3.
IOPORT_PIN_P004_PFC_04_D4	P00_4 / BSC / D4.
IOPORT_PIN_P004_PFC_06_MTIOC4B	P00_4 / MTU3 / MTIOC4B.
IOPORT_PIN_P004_PFC_09_GTIOC00_2A	P00_4 / GPT / GTIOC00_2A.
IOPORT_PIN_P004_PFC_1F_ADTRG2	P00_4 / ADCn / ADTRG2.
IOPORT_PIN_P004_PFC_24_TST_OUT01	P00_4 / ENDATn / TST_OUT01.
IOPORT_PIN_P004_PFC_25_HDSL00_MISO1	P00_4 / HDSLn / HDSL00_MISO1.
IOPORT_PIN_P005_PFC_06_MTIOC4D	P00_5 / MTU3 / MTIOC4D.
IOPORT_PIN_P005_PFC_07_MTIOC8C	P00_5 / MTU3 / MTIOC8C.
IOPORT_PIN_P005_PFC_09_GTIOC00_2B	P00_5 / GPT / GTIOC00_2B.
IOPORT_PIN_P005_PFC_13_USB_VBUSEN	P00_5 / USB / USB_VBUSEN.
IOPORT_PIN_P005_PFC_24_SI01	P00_5 / ENDATn / SI01.
IOPORT_PIN_P005_PFC_25_HDSL00_MOSI1	P00_5 / HDSLn / HDSL00_MOSI1.
IOPORT_PIN_P006_PFC_00_IRQ4	P00_6 / IRQ / IRQ4.
IOPORT_PIN_P006_PFC_06_MTCLKA	P00_6 / MTU3 / MTCLKA.
IOPORT_PIN_P006_PFC_07_MTIOC8D	P00_6 / MTU3 / MTIOC8D.
IOPORT_PIN_P006_PFC_09_GTIOC00_3A	P00_6 / GPT / GTIOC00_3A.
IOPORT_PIN_P006_PFC_13_USB_OVRCUR	P00_6 / USB / USB_OVRCUR.
IOPORT_PIN_P006_PFC_15_SCKE00	P00_6 / SCIEn / SCKE00.
IOPORT_PIN_P006_PFC_16_SCKE04	P00_6 / SCIEn / SCKE04.
IOPORT_PIN_P006_PFC_17_IIC_SCL0	P00_6 / IICn / IIC_SCL0.
IOPORT_PIN_P006_PFC_22_ENCIFCK00	P00_6 / ENCIFn / ENCIFCK00.
IOPORT_PIN_P006_PFC_23_ENCIFCK04	P00_6 / ENCIFn / ENCIFCK04.
IOPORT_PIN_P006_PFC_25_HDSL00_CLK2	P00_6 / HDSLn / HDSL00_CLK2.
IOPORT_PIN_P007_PFC_00_IRQ5	P00_7 / IRQ / IRQ5.
IOPORT_PIN_P007_PFC_06_MTCLKB	P00_7 / MTU3 / MTCLKB.
IOPORT_PIN_P007_PFC_07_MTIOC1B	P00_7 / MTU3 / MTIOC1B.
IOPORT_PIN_P007_PFC_09_GTIOC00_3B	P00_7 / GPT / GTIOC00_3B.
IOPORT_PIN_P007_PFC_13_USB_EXICEN	P00_7 / USB / USB_EXICEN.
IOPORT_PIN_P007_PFC_15_DEE00	P00_7 / SCIEn / DEE00.
IOPORT_PIN_P007_PFC_16_DEE04	P00_7 / SCIEn / DEE04.
IOPORT_PIN_P007_PFC_17_IIC_SDA0	P00_7 / IICn / IIC_SDA0.
IOPORT_PIN_P007_PFC_22_ENCIFOE00	P00_7 / ENCIFn / ENCIFOE00.
IOPORT_PIN_P007_PFC_23_ENCIFOE04	P00_7 / ENCIFn / ENCIFOE04.
IOPORT_PIN_P007_PFC_25_HDSL00_SEL2	P00_7 / HDSLn / HDSL00_SEL2.
IOPORT_PIN_P010_PFC_00_IRQ6	P01_0 / IRQ / IRQ6.
IOPORT_PIN_P010_PFC_06_MTIOC3A	P01_0 / MTU3 / MTIOC3A.
IOPORT_PIN_P010_PFC_07_MTIOC1A	P01_0 / MTU3 / MTIOC1A.
IOPORT_PIN_P010_PFC_09_GTIOC00_4A	P01_0 / GPT / GTIOC00_4A.
IOPORT_PIN_P010_PFC_0A_GTIOC00_2B	P01_0 / GPT / GTIOC00_2B.
IOPORT_PIN_P010_PFC_15_TXDE00	P01_0 / SCIEn / TXDE00.
IOPORT_PIN_P010_PFC_16_TXDE04	P01_0 / SCIEn / TXDE04.
IOPORT_PIN_P010_PFC_17_IIC_SCL1	P01_0 / IICn / IIC_SCL1.
IOPORT_PIN_P010_PFC_1C_XSPI1_CKP	P01_0 / xSPIn / XSPI1_CKP.
IOPORT_PIN_P010_PFC_22_ENCIFDO00	P01_0 / ENCIFn / ENCIFDO00.
IOPORT_PIN_P010_PFC_23_ENCIFDO04	P01_0 / ENCIFn / ENCIFDO04.
IOPORT_PIN_P010_PFC_25_HDSL00_MISO2	P01_0 / HDSLn / HDSL00_MISO2.
IOPORT_PIN_P011_PFC_06_MTIOC3C	P01_1 / MTU3 / MTIOC3C.
IOPORT_PIN_P011_PFC_07_MTIOC8A	P01_1 / MTU3 / MTIOC8A.
IOPORT_PIN_P011_PFC_09_GTIOC00_4B	P01_1 / GPT / GTIOC00_4B.
IOPORT_PIN_P011_PFC_15_RXDE00	P01_1 / SCIEn / RXDE00.
IOPORT_PIN_P011_PFC_16_RXDE04	P01_1 / SCIEn / RXDE04.
IOPORT_PIN_P011_PFC_1C_XSPI1_CS0	P01_1 / xSPIn / XSPI1_CS0.
IOPORT_PIN_P011_PFC_1D_MCLK20	P01_1 / DSMIFn / MCLK20.
IOPORT_PIN_P011_PFC_22_ENCIFDI00	P01_1 / ENCIFn / ENCIFDI00.
IOPORT_PIN_P011_PFC_23_ENCIFDI04	P01_1 / ENCIFn / ENCIFDI04.
IOPORT_PIN_P011_PFC_25_HDSL00_MOSI2	P01_1 / HDSLn / HDSL00_MOSI2.
IOPORT_PIN_P012_PFC_06_MTIOC6B	P01_2 / MTU3 / MTIOC6B.
IOPORT_PIN_P012_PFC_07_MTIOC8B	P01_2 / MTU3 / MTIOC8B.
IOPORT_PIN_P012_PFC_09_GTIOC01_0A	P01_2 / GPT / GTIOC01_0A.
IOPORT_PIN_P012_PFC_0A_GTIOC04_0A	P01_2 / GPT / GTIOC04_0A.
IOPORT_PIN_P012_PFC_1C_XSPI1_CS1	P01_2 / xSPIn / XSPI1_CS1.
IOPORT_PIN_P012_PFC_24_DUEI02	P01_2 / ENDATn / DUEI02.
IOPORT_PIN_P012_PFC_25_HDSL01_LINK	P01_2 / HDSLn / HDSL01_LINK.
IOPORT_PIN_P013_PFC_06_MTIOC6D	P01_3 / MTU3 / MTIOC6D.
IOPORT_PIN_P013_PFC_07_MTIC5U	P01_3 / MTU3 / MTIC5U.
IOPORT_PIN_P013_PFC_09_GTIOC01_0B	P01_3 / GPT / GTIOC01_0B.
IOPORT_PIN_P013_PFC_0A_GTIOC04_0B	P01_3 / GPT / GTIOC04_0B.
IOPORT_PIN_P013_PFC_1C_XSPI1_DS	P01_3 / xSPIn / XSPI1_DS.
IOPORT_PIN_P013_PFC_24_TST_OUT02	P01_3 / ENDATn / TST_OUT02.
IOPORT_PIN_P013_PFC_25_HDSL01_SMPL	P01_3 / HDSLn / HDSL01_SMPL.
IOPORT_PIN_P014_PFC_06_MTIOC7A	P01_4 / MTU3 / MTIOC7A.
IOPORT_PIN_P014_PFC_07_MTIC5V	P01_4 / MTU3 / MTIC5V.
IOPORT_PIN_P014_PFC_09_GTIOC01_1A	P01_4 / GPT / GTIOC01_1A.
IOPORT_PIN_P014_PFC_0A_GTIOC04_1A	P01_4 / GPT / GTIOC04_1A.
IOPORT_PIN_P014_PFC_1C_XSPI1_IO0	P01_4 / xSPIn / XSPI1_IO0.
IOPORT_PIN_P014_PFC_24_SI02	P01_4 / ENDATn / SI02.
IOPORT_PIN_P014_PFC_25_HDSL01_CLK1	P01_4 / HDSLn / HDSL01_CLK1.
IOPORT_PIN_P015_PFC_06_MTIOC7C	P01_5 / MTU3 / MTIOC7C.
IOPORT_PIN_P015_PFC_07_MTIC5W	P01_5 / MTU3 / MTIC5W.
IOPORT_PIN_P015_PFC_09_GTIOC01_1B	P01_5 / GPT / GTIOC01_1B.
IOPORT_PIN_P015_PFC_0A_GTIOC04_1B	P01_5 / GPT / GTIOC04_1B.
IOPORT_PIN_P015_PFC_1C_XSPI1_IO1	P01_5 / xSPIn / XSPI1_IO1.
IOPORT_PIN_P015_PFC_24_DUEI03	P01_5 / ENDATn / DUEI03.
IOPORT_PIN_P015_PFC_25_HDSL01_SEL1	P01_5 / HDSLn / HDSL01_SEL1.
IOPORT_PIN_P016_PFC_06_MTIOC7B	P01_6 / MTU3 / MTIOC7B.
IOPORT_PIN_P016_PFC_07_MTIOC0A	P01_6 / MTU3 / MTIOC0A.
IOPORT_PIN_P016_PFC_09_GTIOC01_2A	P01_6 / GPT / GTIOC01_2A.
IOPORT_PIN_P016_PFC_0A_GTIOC04_2A	P01_6 / GPT / GTIOC04_2A.
IOPORT_PIN_P016_PFC_1C_XSPI1_IO2	P01_6 / xSPIn / XSPI1_IO2.
IOPORT_PIN_P016_PFC_24_TST_OUT03	P01_6 / ENDATn / TST_OUT03.
IOPORT_PIN_P016_PFC_25_HDSL01_MISO1	P01_6 / HDSLn / HDSL01_MISO1.
IOPORT_PIN_P017_PFC_06_MTIOC7D	P01_7 / MTU3 / MTIOC7D.
IOPORT_PIN_P017_PFC_07_MTIOC0B	P01_7 / MTU3 / MTIOC0B.
IOPORT_PIN_P017_PFC_09_GTIOC01_2B	P01_7 / GPT / GTIOC01_2B.
IOPORT_PIN_P017_PFC_0A_GTIOC04_2B	P01_7 / GPT / GTIOC04_2B.
IOPORT_PIN_P017_PFC_1C_XSPI1_IO3	P01_7 / xSPIn / XSPI1_IO3.
IOPORT_PIN_P017_PFC_24_SI03	P01_7 / ENDATn / SI03.
IOPORT_PIN_P017_PFC_25_HDSL01_MOSI1	P01_7 / HDSLn / HDSL01_MOSI1.
IOPORT_PIN_P020_PFC_00_IRQ7	P02_0 / IRQ / IRQ7.
IOPORT_PIN_P020_PFC_06_MTCLKC	P02_0 / MTU3 / MTCLKC.
IOPORT_PIN_P020_PFC_07_MTIOC0C	P02_0 / MTU3 / MTIOC0C.
IOPORT_PIN_P020_PFC_09_GTIOC01_3A	P02_0 / GPT / GTIOC01_3A.
IOPORT_PIN_P020_PFC_0F_ETH3_TXER	P02_0 / ETHER_ETHn / ETH3_TXER.
IOPORT_PIN_P020_PFC_15_SCKE01	P02_0 / SCIEn / SCKE01.
IOPORT_PIN_P020_PFC_17_IIC_SDA1	P02_0 / IICn / IIC_SDA1.
IOPORT_PIN_P020_PFC_1C_XSPI1_IO4	P02_0 / xSPIn / XSPI1_IO4.
IOPORT_PIN_P020_PFC_1D_MCLK21	P02_0 / DSMIFn / MCLK21.
IOPORT_PIN_P020_PFC_22_ENCIFCK01	P02_0 / ENCIFn / ENCIFCK01.
IOPORT_PIN_P020_PFC_25_HDSL01_CLK2	P02_0 / HDSLn / HDSL01_CLK2.
IOPORT_PIN_P021_PFC_00_IRQ8	P02_1 / IRQ / IRQ8.
IOPORT_PIN_P021_PFC_06_MTCLKD	P02_1 / MTU3 / MTCLKD.
IOPORT_PIN_P021_PFC_07_MTIOC0D	P02_1 / MTU3 / MTIOC0D.
IOPORT_PIN_P021_PFC_09_GTIOC01_3B	P02_1 / GPT / GTIOC01_3B.
IOPORT_PIN_P021_PFC_0F_ETH3_RXER	P02_1 / ETHER_ETHn / ETH3_RXER.
IOPORT_PIN_P021_PFC_15_DEE01	P02_1 / SCIEn / DEE01.
IOPORT_PIN_P021_PFC_17_IIC_SCL2	P02_1 / IICn / IIC_SCL2.
IOPORT_PIN_P021_PFC_1C_XSPI1_IO5	P02_1 / xSPIn / XSPI1_IO5.
IOPORT_PIN_P021_PFC_1D_MDAT21	P02_1 / DSMIFn / MDAT21.
IOPORT_PIN_P021_PFC_22_ENCIFOE01	P02_1 / ENCIFn / ENCIFOE01.
IOPORT_PIN_P021_PFC_25_HDSL01_SEL2	P02_1 / HDSLn / HDSL01_SEL2.
IOPORT_PIN_P022_PFC_00_IRQ9	P02_2 / IRQ / IRQ9.
IOPORT_PIN_P022_PFC_06_MTIOC6A	P02_2 / MTU3 / MTIOC6A.
IOPORT_PIN_P022_PFC_07_MTIOC1A	P02_2 / MTU3 / MTIOC1A.
IOPORT_PIN_P022_PFC_09_GTIOC01_4A	P02_2 / GPT / GTIOC01_4A.
IOPORT_PIN_P022_PFC_0F_ETH3_CRS	P02_2 / ETHER_ETHn / ETH3_CRS.
IOPORT_PIN_P022_PFC_13_USB_VBUSEN	P02_2 / USB / USB_VBUSEN.
IOPORT_PIN_P022_PFC_15_TXDE01	P02_2 / SCIEn / TXDE01.
IOPORT_PIN_P022_PFC_17_IIC_SDA2	P02_2 / IICn / IIC_SDA2.
IOPORT_PIN_P022_PFC_1C_XSPI1_IO6	P02_2 / xSPIn / XSPI1_IO6.
IOPORT_PIN_P022_PFC_1D_MCLK22	P02_2 / DSMIFn / MCLK22.
IOPORT_PIN_P022_PFC_22_ENCIFDO01	P02_2 / ENCIFn / ENCIFDO01.
IOPORT_PIN_P022_PFC_25_HDSL01_MISO2	P02_2 / HDSLn / HDSL01_MISO2.
IOPORT_PIN_P023_PFC_00_IRQ10	P02_3 / IRQ / IRQ10.
IOPORT_PIN_P023_PFC_06_MTIOC6C	P02_3 / MTU3 / MTIOC6C.
IOPORT_PIN_P023_PFC_07_MTIOC1B	P02_3 / MTU3 / MTIOC1B.
IOPORT_PIN_P023_PFC_09_GTIOC01_4B	P02_3 / GPT / GTIOC01_4B.
IOPORT_PIN_P023_PFC_0F_ETH3_COL	P02_3 / ETHER_ETHn / ETH3_COL.
IOPORT_PIN_P023_PFC_13_USB_OVRCUR	P02_3 / USB / USB_OVRCUR.
IOPORT_PIN_P023_PFC_15_RXDE01	P02_3 / SCIEn / RXDE01.
IOPORT_PIN_P023_PFC_17_IIC_SCL0	P02_3 / IICn / IIC_SCL0.
IOPORT_PIN_P023_PFC_18_IIC_SCL2	P02_3 / IICn / IIC_SCL2.
IOPORT_PIN_P023_PFC_1C_XSPI1_IO7	P02_3 / xSPIn / XSPI1_IO7.
IOPORT_PIN_P023_PFC_1D_MDAT22	P02_3 / DSMIFn / MDAT22.
IOPORT_PIN_P023_PFC_22_ENCIFDI01	P02_3 / ENCIFn / ENCIFDI01.
IOPORT_PIN_P023_PFC_25_HDSL01_MOSI2	P02_3 / HDSLn / HDSL01_MOSI2.
IOPORT_PIN_P024_PFC_00_IRQ11	P02_4 / IRQ / IRQ11.
IOPORT_PIN_P024_PFC_08_POE0	P02_4 / POE3 / POE0.
IOPORT_PIN_P024_PFC_13_USB_EXICEN	P02_4 / USB / USB_EXICEN.
IOPORT_PIN_P024_PFC_17_IIC_SDA0	P02_4 / IICn / IIC_SDA0.
IOPORT_PIN_P024_PFC_1D_MDAT20	P02_4 / DSMIFn / MDAT20.
IOPORT_PIN_P024_PFC_21_MBX_HINT	P02_4 / MBXSEM / MBX_HINT.
IOPORT_PIN_P024_PFC_25_HDSL02_LINK	P02_4 / HDSLn / HDSL02_LINK.
IOPORT_PIN_P025_PFC_04_D5	P02_5 / BSC / D5.
IOPORT_PIN_P025_PFC_06_MTIOC3B	P02_5 / MTU3 / MTIOC3B.
IOPORT_PIN_P025_PFC_07_MTIOC8A	P02_5 / MTU3 / MTIOC8A.
IOPORT_PIN_P025_PFC_09_GTIOC02_0A	P02_5 / GPT / GTIOC02_0A.
IOPORT_PIN_P025_PFC_0A_GTADSM06_0	P02_5 / GPT / GTADSM06_0.
IOPORT_PIN_P025_PFC_0D_CMTW0_TIC0	P02_5 / CMTW / CMTW0_TIC0.
IOPORT_PIN_P025_PFC_17_IIC_SCL0	P02_5 / IICn / IIC_SCL0.
IOPORT_PIN_P025_PFC_1D_MCLK00	P02_5 / DSMIFn / MCLK00.
IOPORT_PIN_P025_PFC_25_HDSL02_SMPL	P02_5 / HDSLn / HDSL02_SMPL.
IOPORT_PIN_P025_PFC_26_POUTA	P02_5 / ENCOUT / POUTA.
IOPORT_PIN_P025_PFC_29_SD0_PWEN	P02_5 / SDHI / SD0_PWEN.
IOPORT_PIN_P026_PFC_04_D6	P02_6 / BSC / D6.
IOPORT_PIN_P026_PFC_06_MTIOC3D	P02_6 / MTU3 / MTIOC3D.
IOPORT_PIN_P026_PFC_07_MTIOC8B	P02_6 / MTU3 / MTIOC8B.
IOPORT_PIN_P026_PFC_09_GTIOC02_0B	P02_6 / GPT / GTIOC02_0B.
IOPORT_PIN_P026_PFC_0A_GTADSM06_1	P02_6 / GPT / GTADSM06_1.
IOPORT_PIN_P026_PFC_0D_CMTW0_TOC0	P02_6 / CMTW / CMTW0_TOC0.
IOPORT_PIN_P026_PFC_1D_MDAT00	P02_6 / DSMIFn / MDAT00.
IOPORT_PIN_P026_PFC_25_HDSL02_CLK1	P02_6 / HDSLn / HDSL02_CLK1.
IOPORT_PIN_P026_PFC_26_POUTB	P02_6 / ENCOUT / POUTB.
IOPORT_PIN_P026_PFC_29_SD0_IOVS	P02_6 / SDHI / SD0_IOVS.
IOPORT_PIN_P027_PFC_04_D7	P02_7 / BSC / D7.
IOPORT_PIN_P027_PFC_06_MTIOC4A	P02_7 / MTU3 / MTIOC4A.
IOPORT_PIN_P027_PFC_07_MTIC5U	P02_7 / MTU3 / MTIC5U.
IOPORT_PIN_P027_PFC_09_GTIOC02_1A	P02_7 / GPT / GTIOC02_1A.
IOPORT_PIN_P027_PFC_0A_GTADSM07_0	P02_7 / GPT / GTADSM07_0.
IOPORT_PIN_P027_PFC_0D_CMTW0_TIC1	P02_7 / CMTW / CMTW0_TIC1.
IOPORT_PIN_P027_PFC_1D_MCLK01	P02_7 / DSMIFn / MCLK01.
IOPORT_PIN_P027_PFC_25_HDSL02_SEL1	P02_7 / HDSLn / HDSL02_SEL1.
IOPORT_PIN_P027_PFC_26_POUTZ	P02_7 / ENCOUT / POUTZ.
IOPORT_PIN_P030_PFC_04_D8	P03_0 / BSC / D8.
IOPORT_PIN_P030_PFC_06_MTIOC4C	P03_0 / MTU3 / MTIOC4C.
IOPORT_PIN_P030_PFC_07_MTIC5V	P03_0 / MTU3 / MTIC5V.
IOPORT_PIN_P030_PFC_09_GTIOC02_1B	P03_0 / GPT / GTIOC02_1B.
IOPORT_PIN_P030_PFC_0A_GTADSM07_1	P03_0 / GPT / GTADSM07_1.
IOPORT_PIN_P030_PFC_0D_CMTW0_TOC1	P03_0 / CMTW / CMTW0_TOC1.
IOPORT_PIN_P030_PFC_1D_MDAT01	P03_0 / DSMIFn / MDAT01.
IOPORT_PIN_P030_PFC_25_HDSL02_MISO1	P03_0 / HDSLn / HDSL02_MISO1.
IOPORT_PIN_P031_PFC_04_D9	P03_1 / BSC / D9.
IOPORT_PIN_P031_PFC_06_MTIOC4B	P03_1 / MTU3 / MTIOC4B.
IOPORT_PIN_P031_PFC_07_MTIOC1B	P03_1 / MTU3 / MTIOC1B.
IOPORT_PIN_P031_PFC_09_GTIOC02_2A	P03_1 / GPT / GTIOC02_2A.
IOPORT_PIN_P031_PFC_0A_GTADSM08_0	P03_1 / GPT / GTADSM08_0.
IOPORT_PIN_P031_PFC_0D_CMTW1_TIC0	P03_1 / CMTW / CMTW1_TIC0.
IOPORT_PIN_P031_PFC_15_TXDE02	P03_1 / SCIEn / TXDE02.
IOPORT_PIN_P031_PFC_22_ENCIFDO02	P03_1 / ENCIFn / ENCIFDO02.
IOPORT_PIN_P031_PFC_25_HDSL02_MOSI1	P03_1 / HDSLn / HDSL02_MOSI1.
IOPORT_PIN_P032_PFC_00_IRQ12	P03_2 / IRQ / IRQ12.
IOPORT_PIN_P032_PFC_04_D10	P03_2 / BSC / D10.
IOPORT_PIN_P032_PFC_06_MTIOC4D	P03_2 / MTU3 / MTIOC4D.
IOPORT_PIN_P032_PFC_07_MTIOC1A	P03_2 / MTU3 / MTIOC1A.
IOPORT_PIN_P032_PFC_09_GTIOC02_2B	P03_2 / GPT / GTIOC02_2B.
IOPORT_PIN_P032_PFC_0A_GTADSM08_1	P03_2 / GPT / GTADSM08_1.
IOPORT_PIN_P032_PFC_0D_CMTW1_TOC0	P03_2 / CMTW / CMTW1_TOC0.
IOPORT_PIN_P032_PFC_15_RXDE02	P03_2 / SCIEn / RXDE02.
IOPORT_PIN_P032_PFC_22_ENCIFDI02	P03_2 / ENCIFn / ENCIFDI02.
IOPORT_PIN_P032_PFC_25_HDSL02_CLK2	P03_2 / HDSLn / HDSL02_CLK2.
IOPORT_PIN_P033_PFC_00_IRQ13	P03_3 / IRQ / IRQ13.
IOPORT_PIN_P033_PFC_04_D11	P03_3 / BSC / D11.
IOPORT_PIN_P033_PFC_06_MTCLKA	P03_3 / MTU3 / MTCLKA.
IOPORT_PIN_P033_PFC_07_MTIOC8C	P03_3 / MTU3 / MTIOC8C.
IOPORT_PIN_P033_PFC_09_GTIOC02_3A	P03_3 / GPT / GTIOC02_3A.
IOPORT_PIN_P033_PFC_0A_GTADSM09_0	P03_3 / GPT / GTADSM09_0.
IOPORT_PIN_P033_PFC_0D_CMTW1_TIC1	P03_3 / CMTW / CMTW1_TIC1.
IOPORT_PIN_P033_PFC_15_SCKE02	P03_3 / SCIEn / SCKE02.
IOPORT_PIN_P033_PFC_17_IIC_SCL1	P03_3 / IICn / IIC_SCL1.
IOPORT_PIN_P033_PFC_22_ENCIFCK02	P03_3 / ENCIFn / ENCIFCK02.
IOPORT_PIN_P033_PFC_25_HDSL02_SEL2	P03_3 / HDSLn / HDSL02_SEL2.
IOPORT_PIN_P034_PFC_00_IRQ14	P03_4 / IRQ / IRQ14.
IOPORT_PIN_P034_PFC_04_D12	P03_4 / BSC / D12.
IOPORT_PIN_P034_PFC_06_MTCLKB	P03_4 / MTU3 / MTCLKB.
IOPORT_PIN_P034_PFC_07_MTIOC8D	P03_4 / MTU3 / MTIOC8D.
IOPORT_PIN_P034_PFC_09_GTIOC02_3B	P03_4 / GPT / GTIOC02_3B.
IOPORT_PIN_P034_PFC_0A_GTADSM09_1	P03_4 / GPT / GTADSM09_1.
IOPORT_PIN_P034_PFC_0D_CMTW1_TOC1	P03_4 / CMTW / CMTW1_TOC1.
IOPORT_PIN_P034_PFC_0E_RTCAT1HZ	P03_4 / RTC / RTCAT1HZ.
IOPORT_PIN_P034_PFC_15_DEE02	P03_4 / SCIEn / DEE02.
IOPORT_PIN_P034_PFC_17_IIC_SDA1	P03_4 / IICn / IIC_SDA1.
IOPORT_PIN_P034_PFC_22_ENCIFOE02	P03_4 / ENCIFn / ENCIFOE02.
IOPORT_PIN_P034_PFC_25_HDSL02_MISO2	P03_4 / HDSLn / HDSL02_MISO2.
IOPORT_PIN_P035_PFC_00_IRQ15	P03_5 / IRQ / IRQ15.
IOPORT_PIN_P035_PFC_06_MTIOC3A	P03_5 / MTU3 / MTIOC3A.
IOPORT_PIN_P035_PFC_07_MTIC5W	P03_5 / MTU3 / MTIC5W.
IOPORT_PIN_P035_PFC_09_GTIOC02_4A	P03_5 / GPT / GTIOC02_4A.
IOPORT_PIN_P035_PFC_15_TXDE02	P03_5 / SCIEn / TXDE02.
IOPORT_PIN_P035_PFC_17_IIC_SCL2	P03_5 / IICn / IIC_SCL2.
IOPORT_PIN_P035_PFC_22_ENCIFDO02	P03_5 / ENCIFn / ENCIFDO02.
IOPORT_PIN_P035_PFC_25_HDSL02_MOSI2	P03_5 / HDSLn / HDSL02_MOSI2.
IOPORT_PIN_P036_PFC_06_MTIOC3C	P03_6 / MTU3 / MTIOC3C.
IOPORT_PIN_P036_PFC_07_MTIOC1A	P03_6 / MTU3 / MTIOC1A.
IOPORT_PIN_P036_PFC_09_GTIOC02_4B	P03_6 / GPT / GTIOC02_4B.
IOPORT_PIN_P036_PFC_15_RXDE02	P03_6 / SCIEn / RXDE02.
IOPORT_PIN_P036_PFC_17_IIC_SDA2	P03_6 / IICn / IIC_SDA2.
IOPORT_PIN_P036_PFC_22_ENCIFDI02	P03_6 / ENCIFn / ENCIFDI02.
IOPORT_PIN_P036_PFC_25_HDSL03_LINK	P03_6 / HDSLn / HDSL03_LINK.
IOPORT_PIN_P037_PFC_06_MTIOC6B	P03_7 / MTU3 / MTIOC6B.
IOPORT_PIN_P037_PFC_07_MTIOC1B	P03_7 / MTU3 / MTIOC1B.
IOPORT_PIN_P037_PFC_09_GTIOC03_0A	P03_7 / GPT / GTIOC03_0A.
IOPORT_PIN_P037_PFC_0D_CMTW0_TIC0	P03_7 / CMTW / CMTW0_TIC0.
IOPORT_PIN_P037_PFC_24_DUEI04	P03_7 / ENDATn / DUEI04.
IOPORT_PIN_P037_PFC_25_HDSL03_SMPL	P03_7 / HDSLn / HDSL03_SMPL.
IOPORT_PIN_P040_PFC_06_MTIOC6D	P04_0 / MTU3 / MTIOC6D.
IOPORT_PIN_P040_PFC_09_GTIOC03_0B	P04_0 / GPT / GTIOC03_0B.
IOPORT_PIN_P040_PFC_0D_CMTW0_TOC0	P04_0 / CMTW / CMTW0_TOC0.
IOPORT_PIN_P040_PFC_24_TST_OUT04	P04_0 / ENDATn / TST_OUT04.
IOPORT_PIN_P040_PFC_25_HDSL03_CLK1	P04_0 / HDSLn / HDSL03_CLK1.
IOPORT_PIN_P041_PFC_06_MTIOC7A	P04_1 / MTU3 / MTIOC7A.
IOPORT_PIN_P041_PFC_09_GTIOC03_1A	P04_1 / GPT / GTIOC03_1A.
IOPORT_PIN_P041_PFC_0D_CMTW0_TIC1	P04_1 / CMTW / CMTW0_TIC1.
IOPORT_PIN_P041_PFC_24_SI04	P04_1 / ENDATn / SI04.
IOPORT_PIN_P041_PFC_25_HDSL03_SEL1	P04_1 / HDSLn / HDSL03_SEL1.
IOPORT_PIN_P042_PFC_06_MTIOC7C	P04_2 / MTU3 / MTIOC7C.
IOPORT_PIN_P042_PFC_09_GTIOC03_1B	P04_2 / GPT / GTIOC03_1B.
IOPORT_PIN_P042_PFC_0D_CMTW0_TOC1	P04_2 / CMTW / CMTW0_TOC1.
IOPORT_PIN_P042_PFC_24_DUEI05	P04_2 / ENDATn / DUEI05.
IOPORT_PIN_P042_PFC_25_HDSL03_MISO1	P04_2 / HDSLn / HDSL03_MISO1.
IOPORT_PIN_P043_PFC_06_MTIOC7B	P04_3 / MTU3 / MTIOC7B.
IOPORT_PIN_P043_PFC_09_GTIOC03_2A	P04_3 / GPT / GTIOC03_2A.
IOPORT_PIN_P043_PFC_0D_CMTW1_TIC0	P04_3 / CMTW / CMTW1_TIC0.
IOPORT_PIN_P043_PFC_24_TST_OUT05	P04_3 / ENDATn / TST_OUT05.
IOPORT_PIN_P043_PFC_25_HDSL03_MOSI1	P04_3 / HDSLn / HDSL03_MOSI1.
IOPORT_PIN_P044_PFC_06_MTIOC7D	P04_4 / MTU3 / MTIOC7D.
IOPORT_PIN_P044_PFC_09_GTIOC03_2B	P04_4 / GPT / GTIOC03_2B.
IOPORT_PIN_P044_PFC_0D_CMTW1_TOC0	P04_4 / CMTW / CMTW1_TOC0.
IOPORT_PIN_P044_PFC_1F_ADTRG0	P04_4 / ADCn / ADTRG0.
IOPORT_PIN_P044_PFC_24_SI05	P04_4 / ENDATn / SI05.
IOPORT_PIN_P044_PFC_25_HDSL03_CLK2	P04_4 / HDSLn / HDSL03_CLK2.
IOPORT_PIN_P045_PFC_00_SEI	P04_5 / IRQ / SEI.
IOPORT_PIN_P045_PFC_06_MTCLKC	P04_5 / MTU3 / MTCLKC.
IOPORT_PIN_P045_PFC_07_MTIOC0C	P04_5 / MTU3 / MTIOC0C.
IOPORT_PIN_P045_PFC_09_GTIOC03_3A	P04_5 / GPT / GTIOC03_3A.
IOPORT_PIN_P045_PFC_0D_CMTW1_TIC1	P04_5 / CMTW / CMTW1_TIC1.
IOPORT_PIN_P045_PFC_15_SCKE03	P04_5 / SCIEn / SCKE03.
IOPORT_PIN_P045_PFC_17_IIC_SCL0	P04_5 / IICn / IIC_SCL0.
IOPORT_PIN_P045_PFC_1F_ADTRG1	P04_5 / ADCn / ADTRG1.
IOPORT_PIN_P045_PFC_22_ENCIFCK03	P04_5 / ENCIFn / ENCIFCK03.
IOPORT_PIN_P045_PFC_25_HDSL03_SEL2	P04_5 / HDSLn / HDSL03_SEL2.
IOPORT_PIN_P046_PFC_00_IRQ0	P04_6 / IRQ / IRQ0.
IOPORT_PIN_P046_PFC_06_MTCLKD	P04_6 / MTU3 / MTCLKD.
IOPORT_PIN_P046_PFC_07_MTIOC0D	P04_6 / MTU3 / MTIOC0D.
IOPORT_PIN_P046_PFC_09_GTIOC03_3B	P04_6 / GPT / GTIOC03_3B.
IOPORT_PIN_P046_PFC_0D_CMTW1_TOC1	P04_6 / CMTW / CMTW1_TOC1.
IOPORT_PIN_P046_PFC_15_DEE03	P04_6 / SCIEn / DEE03.
IOPORT_PIN_P046_PFC_17_IIC_SDA0	P04_6 / IICn / IIC_SDA0.
IOPORT_PIN_P046_PFC_1F_ADTRG2	P04_6 / ADCn / ADTRG2.
IOPORT_PIN_P046_PFC_21_MBX_HINT	P04_6 / MBXSEM / MBX_HINT.
IOPORT_PIN_P046_PFC_22_ENCIFOE03	P04_6 / ENCIFn / ENCIFOE03.
IOPORT_PIN_P046_PFC_25_HDSL03_MISO2	P04_6 / HDSLn / HDSL03_MISO2.
IOPORT_PIN_P047_PFC_00_IRQ1	P04_7 / IRQ / IRQ1.
IOPORT_PIN_P047_PFC_06_MTIOC6A	P04_7 / MTU3 / MTIOC6A.
IOPORT_PIN_P047_PFC_07_MTIOC0A	P04_7 / MTU3 / MTIOC0A.
IOPORT_PIN_P047_PFC_09_GTIOC03_4A	P04_7 / GPT / GTIOC03_4A.
IOPORT_PIN_P047_PFC_15_TXDE03	P04_7 / SCIEn / TXDE03.
IOPORT_PIN_P047_PFC_17_IIC_SCL1	P04_7 / IICn / IIC_SCL1.
IOPORT_PIN_P047_PFC_22_ENCIFDO03	P04_7 / ENCIFn / ENCIFDO03.
IOPORT_PIN_P047_PFC_25_HDSL03_MOSI2	P04_7 / HDSLn / HDSL03_MOSI2.
IOPORT_PIN_P050_PFC_00_IRQ2	P05_0 / IRQ / IRQ2.
IOPORT_PIN_P050_PFC_06_MTIOC6C	P05_0 / MTU3 / MTIOC6C.
IOPORT_PIN_P050_PFC_07_MTIOC0B	P05_0 / MTU3 / MTIOC0B.
IOPORT_PIN_P050_PFC_09_GTIOC03_4B	P05_0 / GPT / GTIOC03_4B.
IOPORT_PIN_P050_PFC_15_RXDE03	P05_0 / SCIEn / RXDE03.
IOPORT_PIN_P050_PFC_17_IIC_SDA1	P05_0 / IICn / IIC_SDA1.
IOPORT_PIN_P050_PFC_22_ENCIFDI03	P05_0 / ENCIFn / ENCIFDI03.
IOPORT_PIN_P050_PFC_25_HDSL04_LINK	P05_0 / HDSLn / HDSL04_LINK.
IOPORT_PIN_P051_PFC_00_IRQ3	P05_1 / IRQ / IRQ3.
IOPORT_PIN_P051_PFC_1C_XSPI0_CKP	P05_1 / xSPIn / XSPI0_CKP.
IOPORT_PIN_P051_PFC_24_DUEI06	P05_1 / ENDATn / DUEI06.
IOPORT_PIN_P051_PFC_25_HDSL04_SMPL	P05_1 / HDSLn / HDSL04_SMPL.
IOPORT_PIN_P052_PFC_00_IRQ4	P05_2 / IRQ / IRQ4.
IOPORT_PIN_P052_PFC_17_IIC_SCL2	P05_2 / IICn / IIC_SCL2.
IOPORT_PIN_P052_PFC_1C_XSPI0_CKN	P05_2 / xSPIn / XSPI0_CKN.
IOPORT_PIN_P052_PFC_24_TST_OUT06	P05_2 / ENDATn / TST_OUT06.
IOPORT_PIN_P052_PFC_25_HDSL04_CLK1	P05_2 / HDSLn / HDSL04_CLK1.
IOPORT_PIN_P053_PFC_00_IRQ5	P05_3 / IRQ / IRQ5.
IOPORT_PIN_P053_PFC_1C_XSPI0_CS0	P05_3 / xSPIn / XSPI0_CS0.
IOPORT_PIN_P053_PFC_24_SI06	P05_3 / ENDATn / SI06.
IOPORT_PIN_P053_PFC_25_HDSL04_SEL1	P05_3 / HDSLn / HDSL04_SEL1.
IOPORT_PIN_P054_PFC_00_IRQ6	P05_4 / IRQ / IRQ6.
IOPORT_PIN_P054_PFC_17_IIC_SDA2	P05_4 / IICn / IIC_SDA2.
IOPORT_PIN_P054_PFC_1C_XSPI0_CS1	P05_4 / xSPIn / XSPI0_CS1.
IOPORT_PIN_P054_PFC_24_DUEI07	P05_4 / ENDATn / DUEI07.
IOPORT_PIN_P054_PFC_25_HDSL04_MISO1	P05_4 / HDSLn / HDSL04_MISO1.
IOPORT_PIN_P055_PFC_1C_XSPI0_DS	P05_5 / xSPIn / XSPI0_DS.
IOPORT_PIN_P055_PFC_24_TST_OUT07	P05_5 / ENDATn / TST_OUT07.
IOPORT_PIN_P055_PFC_25_HDSL04_MOSI1	P05_5 / HDSLn / HDSL04_MOSI1.
IOPORT_PIN_P056_PFC_1C_XSPI0_IO0	P05_6 / xSPIn / XSPI0_IO0.
IOPORT_PIN_P056_PFC_24_SI07	P05_6 / ENDATn / SI07.
IOPORT_PIN_P056_PFC_25_HDSL04_CLK2	P05_6 / HDSLn / HDSL04_CLK2.
IOPORT_PIN_P057_PFC_1C_XSPI0_IO1	P05_7 / xSPIn / XSPI0_IO1.
IOPORT_PIN_P057_PFC_24_DUEI08	P05_7 / ENDATn / DUEI08.
IOPORT_PIN_P057_PFC_25_HDSL04_SEL2	P05_7 / HDSLn / HDSL04_SEL2.
IOPORT_PIN_P060_PFC_1C_XSPI0_IO2	P06_0 / xSPIn / XSPI0_IO2.
IOPORT_PIN_P060_PFC_24_TST_OUT08	P06_0 / ENDATn / TST_OUT08.
IOPORT_PIN_P060_PFC_25_HDSL04_MISO2	P06_0 / HDSLn / HDSL04_MISO2.
IOPORT_PIN_P061_PFC_1C_XSPI0_IO3	P06_1 / xSPIn / XSPI0_IO3.
IOPORT_PIN_P061_PFC_24_SI08	P06_1 / ENDATn / SI08.
IOPORT_PIN_P061_PFC_25_HDSL04_MOSI2	P06_1 / HDSLn / HDSL04_MOSI2.
IOPORT_PIN_P062_PFC_00_IRQ8	P06_2 / IRQ / IRQ8.
IOPORT_PIN_P062_PFC_17_IIC_SCL0	P06_2 / IICn / IIC_SCL0.
IOPORT_PIN_P062_PFC_1C_XSPI0_IO4	P06_2 / xSPIn / XSPI0_IO4.
IOPORT_PIN_P062_PFC_24_DUEI09	P06_2 / ENDATn / DUEI09.
IOPORT_PIN_P062_PFC_25_HDSL05_LINK	P06_2 / HDSLn / HDSL05_LINK.
IOPORT_PIN_P063_PFC_00_IRQ9	P06_3 / IRQ / IRQ9.
IOPORT_PIN_P063_PFC_0C_GTETRGA	P06_3 / POEG / GTETRGA.
IOPORT_PIN_P063_PFC_17_IIC_SDA0	P06_3 / IICn / IIC_SDA0.
IOPORT_PIN_P063_PFC_1C_XSPI0_IO5	P06_3 / xSPIn / XSPI0_IO5.
IOPORT_PIN_P063_PFC_24_TST_OUT09	P06_3 / ENDATn / TST_OUT09.
IOPORT_PIN_P063_PFC_25_HDSL05_SMPL	P06_3 / HDSLn / HDSL05_SMPL.
IOPORT_PIN_P064_PFC_00_IRQ10	P06_4 / IRQ / IRQ10.
IOPORT_PIN_P064_PFC_0C_GTETRGB	P06_4 / POEG / GTETRGB.
IOPORT_PIN_P064_PFC_17_IIC_SCL1	P06_4 / IICn / IIC_SCL1.
IOPORT_PIN_P064_PFC_1C_XSPI0_IO6	P06_4 / xSPIn / XSPI0_IO6.
IOPORT_PIN_P064_PFC_24_SI09	P06_4 / ENDATn / SI09.
IOPORT_PIN_P064_PFC_25_HDSL05_CLK1	P06_4 / HDSLn / HDSL05_CLK1.
IOPORT_PIN_P065_PFC_00_IRQ11	P06_5 / IRQ / IRQ11.
IOPORT_PIN_P065_PFC_0C_GTETRGC	P06_5 / POEG / GTETRGC.
IOPORT_PIN_P065_PFC_17_IIC_SDA1	P06_5 / IICn / IIC_SDA1.
IOPORT_PIN_P065_PFC_1C_XSPI0_IO7	P06_5 / xSPIn / XSPI0_IO7.
IOPORT_PIN_P065_PFC_25_HDSL05_SEL1	P06_5 / HDSLn / HDSL05_SEL1.
IOPORT_PIN_P066_PFC_1C_XSPI0_RESET0	P06_6 / xSPIn / XSPI0_RESET0.
IOPORT_PIN_P067_PFC_00_IRQ12	P06_7 / IRQ / IRQ12.
IOPORT_PIN_P067_PFC_08_POE4	P06_7 / POE3 / POE4.
IOPORT_PIN_P067_PFC_0C_GTETRGD	P06_7 / POEG / GTETRGD.
IOPORT_PIN_P067_PFC_10_GMAC1_MDC	P06_7 / ETHER_GMACn / GMAC1_MDC.
IOPORT_PIN_P067_PFC_17_IIC_SCL2	P06_7 / IICn / IIC_SCL2.
IOPORT_PIN_P067_PFC_25_HDSL05_MISO1	P06_7 / HDSLn / HDSL05_MISO1.
IOPORT_PIN_P070_PFC_00_IRQ13	P07_0 / IRQ / IRQ13.
IOPORT_PIN_P070_PFC_10_GMAC1_MDIO	P07_0 / ETHER_GMACn / GMAC1_MDIO.
IOPORT_PIN_P070_PFC_17_IIC_SDA2	P07_0 / IICn / IIC_SDA2.
IOPORT_PIN_P070_PFC_1C_XSPI0_RESET1	P07_0 / xSPIn / XSPI0_RESET1.
IOPORT_PIN_P070_PFC_25_HDSL05_MOSI1	P07_0 / HDSLn / HDSL05_MOSI1.
IOPORT_PIN_P071_PFC_00_IRQ14	P07_1 / IRQ / IRQ14.
IOPORT_PIN_P071_PFC_08_POE8	P07_1 / POE3 / POE8.
IOPORT_PIN_P071_PFC_15_SCKE04	P07_1 / SCIEn / SCKE04.
IOPORT_PIN_P071_PFC_16_SCKE08	P07_1 / SCIEn / SCKE08.
IOPORT_PIN_P071_PFC_17_IIC_SCL0	P07_1 / IICn / IIC_SCL0.
IOPORT_PIN_P071_PFC_1C_XSPI0_RSTO0	P07_1 / xSPIn / XSPI0_RSTO0.
IOPORT_PIN_P071_PFC_1D_MCLK00	P07_1 / DSMIFn / MCLK00.
IOPORT_PIN_P071_PFC_22_ENCIFCK04	P07_1 / ENCIFn / ENCIFCK04.
IOPORT_PIN_P071_PFC_23_ENCIFCK12	P07_1 / ENCIFn / ENCIFCK12.
IOPORT_PIN_P071_PFC_25_HDSL05_CLK2	P07_1 / HDSLn / HDSL05_CLK2.
IOPORT_PIN_P072_PFC_00_IRQ15	P07_2 / IRQ / IRQ15.
IOPORT_PIN_P072_PFC_08_POE10	P07_2 / POE3 / POE10.
IOPORT_PIN_P072_PFC_15_DEE04	P07_2 / SCIEn / DEE04.
IOPORT_PIN_P072_PFC_16_DEE08	P07_2 / SCIEn / DEE08.
IOPORT_PIN_P072_PFC_17_IIC_SDA0	P07_2 / IICn / IIC_SDA0.
IOPORT_PIN_P072_PFC_1C_XSPI0_RSTO1	P07_2 / xSPIn / XSPI0_RSTO1.
IOPORT_PIN_P072_PFC_1D_MDAT00	P07_2 / DSMIFn / MDAT00.
IOPORT_PIN_P072_PFC_22_ENCIFOE04	P07_2 / ENCIFn / ENCIFOE04.
IOPORT_PIN_P072_PFC_23_ENCIFOE12	P07_2 / ENCIFn / ENCIFOE12.
IOPORT_PIN_P072_PFC_25_HDSL05_SEL2	P07_2 / HDSLn / HDSL05_SEL2.
IOPORT_PIN_P073_PFC_08_POE11	P07_3 / POE3 / POE11.
IOPORT_PIN_P073_PFC_15_TXDE04	P07_3 / SCIEn / TXDE04.
IOPORT_PIN_P073_PFC_16_TXDE08	P07_3 / SCIEn / TXDE08.
IOPORT_PIN_P073_PFC_17_IIC_SCL1	P07_3 / IICn / IIC_SCL1.
IOPORT_PIN_P073_PFC_1C_XSPI0_INT0	P07_3 / xSPIn / XSPI0_INT0.
IOPORT_PIN_P073_PFC_1D_MCLK01	P07_3 / DSMIFn / MCLK01.
IOPORT_PIN_P073_PFC_22_ENCIFDO04	P07_3 / ENCIFn / ENCIFDO04.
IOPORT_PIN_P073_PFC_23_ENCIFDO12	P07_3 / ENCIFn / ENCIFDO12.
IOPORT_PIN_P073_PFC_25_HDSL05_MISO2	P07_3 / HDSLn / HDSL05_MISO2.
IOPORT_PIN_P074_PFC_15_RXDE04	P07_4 / SCIEn / RXDE04.
IOPORT_PIN_P074_PFC_16_RXDE08	P07_4 / SCIEn / RXDE08.
IOPORT_PIN_P074_PFC_17_IIC_SDA1	P07_4 / IICn / IIC_SDA1.
IOPORT_PIN_P074_PFC_1C_XSPI0_INT1	P07_4 / xSPIn / XSPI0_INT1.
IOPORT_PIN_P074_PFC_1D_MDAT01	P07_4 / DSMIFn / MDAT01.
IOPORT_PIN_P074_PFC_22_ENCIFDI04	P07_4 / ENCIFn / ENCIFDI04.
IOPORT_PIN_P074_PFC_23_ENCIFDI12	P07_4 / ENCIFn / ENCIFDI12.
IOPORT_PIN_P074_PFC_25_HDSL05_MOSI2	P07_4 / HDSLn / HDSL05_MOSI2.
IOPORT_PIN_P075_PFC_15_SCKE05	P07_5 / SCIEn / SCKE05.
IOPORT_PIN_P075_PFC_17_IIC_SCL2	P07_5 / IICn / IIC_SCL2.
IOPORT_PIN_P075_PFC_1C_XSPI0_ECS0	P07_5 / xSPIn / XSPI0_ECS0.
IOPORT_PIN_P075_PFC_1D_MCLK02	P07_5 / DSMIFn / MCLK02.
IOPORT_PIN_P075_PFC_22_ENCIFCK05	P07_5 / ENCIFn / ENCIFCK05.
IOPORT_PIN_P075_PFC_25_HDSL06_LINK	P07_5 / HDSLn / HDSL06_LINK.
IOPORT_PIN_P076_PFC_15_DEE05	P07_6 / SCIEn / DEE05.
IOPORT_PIN_P076_PFC_17_IIC_SDA2	P07_6 / IICn / IIC_SDA2.
IOPORT_PIN_P076_PFC_1C_XSPI0_ECS1	P07_6 / xSPIn / XSPI0_ECS1.
IOPORT_PIN_P076_PFC_1D_MDAT02	P07_6 / DSMIFn / MDAT02.
IOPORT_PIN_P076_PFC_22_ENCIFOE05	P07_6 / ENCIFn / ENCIFOE05.
IOPORT_PIN_P076_PFC_25_HDSL06_SMPL	P07_6 / HDSLn / HDSL06_SMPL.
IOPORT_PIN_P077_PFC_15_TXDE05	P07_7 / SCIEn / TXDE05.
IOPORT_PIN_P077_PFC_17_IIC_SCL0	P07_7 / IICn / IIC_SCL0.
IOPORT_PIN_P077_PFC_1C_XSPI0_WP0	P07_7 / xSPIn / XSPI0_WP0.
IOPORT_PIN_P077_PFC_1D_MCLK10	P07_7 / DSMIFn / MCLK10.
IOPORT_PIN_P077_PFC_22_ENCIFDO05	P07_7 / ENCIFn / ENCIFDO05.
IOPORT_PIN_P077_PFC_25_HDSL06_CLK1	P07_7 / HDSLn / HDSL06_CLK1.
IOPORT_PIN_P080_PFC_0E_RTCAT1HZ	P08_0 / RTC / RTCAT1HZ.
IOPORT_PIN_P080_PFC_15_RXDE05	P08_0 / SCIEn / RXDE05.
IOPORT_PIN_P080_PFC_17_IIC_SDA0	P08_0 / IICn / IIC_SDA0.
IOPORT_PIN_P080_PFC_1C_XSPI0_WP1	P08_0 / xSPIn / XSPI0_WP1.
IOPORT_PIN_P080_PFC_1D_MDAT10	P08_0 / DSMIFn / MDAT10.
IOPORT_PIN_P080_PFC_21_MBX_HINT	P08_0 / MBXSEM / MBX_HINT.
IOPORT_PIN_P080_PFC_22_ENCIFDI05	P08_0 / ENCIFn / ENCIFDI05.
IOPORT_PIN_P080_PFC_25_HDSL06_SEL1	P08_0 / HDSLn / HDSL06_SEL1.
IOPORT_PIN_P081_PFC_01_TMS	P08_1 / JTAG/SWD / TMS.
IOPORT_PIN_P081_PFC_24_DUEI10	P08_1 / ENDATn / DUEI10.
IOPORT_PIN_P081_PFC_25_HDSL06_MISO1	P08_1 / HDSLn / HDSL06_MISO1.
IOPORT_PIN_P082_PFC_01_TDI	P08_2 / JTAG/SWD / TDI.
IOPORT_PIN_P082_PFC_24_TST_OUT10	P08_2 / ENDATn / TST_OUT10.
IOPORT_PIN_P082_PFC_25_HDSL06_MOSI1	P08_2 / HDSLn / HDSL06_MOSI1.
IOPORT_PIN_P083_PFC_01_TCK	P08_3 / JTAG/SWD / TCK.
IOPORT_PIN_P083_PFC_24_SI10	P08_3 / ENDATn / SI10.
IOPORT_PIN_P083_PFC_25_HDSL06_CLK2	P08_3 / HDSLn / HDSL06_CLK2.
IOPORT_PIN_P084_PFC_01_TDO	P08_4 / JTAG/SWD / TDO.
IOPORT_PIN_P084_PFC_25_HDSL06_SEL2	P08_4 / HDSLn / HDSL06_SEL2.
IOPORT_PIN_P085_PFC_00_IRQ8	P08_5 / IRQ / IRQ8.
IOPORT_PIN_P085_PFC_01_RSTOUT	P08_5 / JTAG/SWD / RSTOUT.
IOPORT_PIN_P085_PFC_0C_GTETRGSA	P08_5 / POEG / GTETRGSA.
IOPORT_PIN_P085_PFC_17_IIC_SCL1	P08_5 / IICn / IIC_SCL1.
IOPORT_PIN_P085_PFC_1D_MCLK02	P08_5 / DSMIFn / MCLK02.
IOPORT_PIN_P085_PFC_25_HDSL06_MISO2	P08_5 / HDSLn / HDSL06_MISO2.
IOPORT_PIN_P085_PFC_29_SD1_PWEN	P08_5 / SDHI / SD1_PWEN.
IOPORT_PIN_P086_PFC_00_SEI	P08_6 / IRQ / SEI.
IOPORT_PIN_P086_PFC_02_CKIO	P08_6 / BSC / CKIO.
IOPORT_PIN_P086_PFC_0B_GTIOC08_3A	P08_6 / GPT / GTIOC08_3A.
IOPORT_PIN_P086_PFC_0C_GTETRGSB	P08_6 / POEG / GTETRGSB.
IOPORT_PIN_P086_PFC_17_IIC_SDA1	P08_6 / IICn / IIC_SDA1.
IOPORT_PIN_P086_PFC_1D_MDAT02	P08_6 / DSMIFn / MDAT02.
IOPORT_PIN_P086_PFC_1E_MCLK11	P08_6 / DSMIFn / MCLK11.
IOPORT_PIN_P086_PFC_24_DUEI11	P08_6 / ENDATn / DUEI11.
IOPORT_PIN_P086_PFC_25_HDSL06_MOSI2	P08_6 / HDSLn / HDSL06_MOSI2.
IOPORT_PIN_P086_PFC_29_SD1_IOVS	P08_6 / SDHI / SD1_IOVS.
IOPORT_PIN_P087_PFC_00_IRQ0	P08_7 / IRQ / IRQ0.
IOPORT_PIN_P087_PFC_04_A0	P08_7 / BSC / A0.
IOPORT_PIN_P087_PFC_0B_GTIOC08_3B	P08_7 / GPT / GTIOC08_3B.
IOPORT_PIN_P087_PFC_17_IIC_SCL2	P08_7 / IICn / IIC_SCL2.
IOPORT_PIN_P087_PFC_18_IIC_SCL1	P08_7 / IICn / IIC_SCL1.
IOPORT_PIN_P087_PFC_1E_MDAT11	P08_7 / DSMIFn / MDAT11.
IOPORT_PIN_P087_PFC_24_TST_OUT11	P08_7 / ENDATn / TST_OUT11.
IOPORT_PIN_P087_PFC_25_HDSL07_LINK	P08_7 / HDSLn / HDSL07_LINK.
IOPORT_PIN_P090_PFC_17_IIC_SDA2	P09_0 / IICn / IIC_SDA2.
IOPORT_PIN_P090_PFC_1D_MCLK12	P09_0 / DSMIFn / MCLK12.
IOPORT_PIN_P090_PFC_24_SI11	P09_0 / ENDATn / SI11.
IOPORT_PIN_P090_PFC_25_HDSL07_SMPL	P09_0 / HDSLn / HDSL07_SMPL.
IOPORT_PIN_P091_PFC_1D_MDAT12	P09_1 / DSMIFn / MDAT12.
IOPORT_PIN_P091_PFC_24_DUEI12	P09_1 / ENDATn / DUEI12.
IOPORT_PIN_P091_PFC_25_HDSL07_CLK1	P09_1 / HDSLn / HDSL07_CLK1.
IOPORT_PIN_P092_PFC_1D_MCLK20	P09_2 / DSMIFn / MCLK20.
IOPORT_PIN_P092_PFC_24_TST_OUT12	P09_2 / ENDATn / TST_OUT12.
IOPORT_PIN_P092_PFC_25_HDSL07_SEL1	P09_2 / HDSLn / HDSL07_SEL1.
IOPORT_PIN_P093_PFC_1D_MDAT20	P09_3 / DSMIFn / MDAT20.
IOPORT_PIN_P093_PFC_24_SI12	P09_3 / ENDATn / SI12.
IOPORT_PIN_P093_PFC_25_HDSL07_MISO1	P09_3 / HDSLn / HDSL07_MISO1.
IOPORT_PIN_P094_PFC_04_D13	P09_4 / BSC / D13.
IOPORT_PIN_P094_PFC_06_MTIOC6B	P09_4 / MTU3 / MTIOC6B.
IOPORT_PIN_P094_PFC_09_GTIOC04_0A	P09_4 / GPT / GTIOC04_0A.
IOPORT_PIN_P094_PFC_0A_GTIOC10_0A	P09_4 / GPT / GTIOC10_0A.
IOPORT_PIN_P094_PFC_1D_MCLK70	P09_4 / DSMIFn / MCLK70.
IOPORT_PIN_P094_PFC_24_DUEI13	P09_4 / ENDATn / DUEI13.
IOPORT_PIN_P094_PFC_25_HDSL07_MOSI1	P09_4 / HDSLn / HDSL07_MOSI1.
IOPORT_PIN_P094_PFC_28_DISP_CLK	P09_4 / LCDC / DISP_CLK.
IOPORT_PIN_P095_PFC_04_D14	P09_5 / BSC / D14.
IOPORT_PIN_P095_PFC_06_MTIOC6D	P09_5 / MTU3 / MTIOC6D.
IOPORT_PIN_P095_PFC_09_GTIOC04_0B	P09_5 / GPT / GTIOC04_0B.
IOPORT_PIN_P095_PFC_0A_GTIOC10_0B	P09_5 / GPT / GTIOC10_0B.
IOPORT_PIN_P095_PFC_1D_MDAT70	P09_5 / DSMIFn / MDAT70.
IOPORT_PIN_P095_PFC_24_TST_OUT13	P09_5 / ENDATn / TST_OUT13.
IOPORT_PIN_P095_PFC_25_HDSL07_CLK2	P09_5 / HDSLn / HDSL07_CLK2.
IOPORT_PIN_P095_PFC_28_DISP_HSYNC	P09_5 / LCDC / DISP_HSYNC.
IOPORT_PIN_P096_PFC_04_D15	P09_6 / BSC / D15.
IOPORT_PIN_P096_PFC_06_MTIOC7A	P09_6 / MTU3 / MTIOC7A.
IOPORT_PIN_P096_PFC_09_GTIOC04_1A	P09_6 / GPT / GTIOC04_1A.
IOPORT_PIN_P096_PFC_0A_GTIOC10_1A	P09_6 / GPT / GTIOC10_1A.
IOPORT_PIN_P096_PFC_1D_MCLK71	P09_6 / DSMIFn / MCLK71.
IOPORT_PIN_P096_PFC_24_SI13	P09_6 / ENDATn / SI13.
IOPORT_PIN_P096_PFC_25_HDSL07_SEL2	P09_6 / HDSLn / HDSL07_SEL2.
IOPORT_PIN_P096_PFC_28_DISP_VSYNC	P09_6 / LCDC / DISP_VSYNC.
IOPORT_PIN_P097_PFC_04_WE0	P09_7 / BSC / WE0.
IOPORT_PIN_P097_PFC_06_MTIOC7C	P09_7 / MTU3 / MTIOC7C.
IOPORT_PIN_P097_PFC_09_GTIOC04_1B	P09_7 / GPT / GTIOC04_1B.
IOPORT_PIN_P097_PFC_0A_GTIOC10_1B	P09_7 / GPT / GTIOC10_1B.
IOPORT_PIN_P097_PFC_1D_MDAT71	P09_7 / DSMIFn / MDAT71.
IOPORT_PIN_P097_PFC_24_DUEI14	P09_7 / ENDATn / DUEI14.
IOPORT_PIN_P097_PFC_25_HDSL07_MISO2	P09_7 / HDSLn / HDSL07_MISO2.
IOPORT_PIN_P097_PFC_28_DISP_DE	P09_7 / LCDC / DISP_DE.
IOPORT_PIN_P100_PFC_00_IRQ4	P10_0 / IRQ / IRQ4.
IOPORT_PIN_P100_PFC_04_WE1	P10_0 / BSC / WE1.
IOPORT_PIN_P100_PFC_06_MTIOC7B	P10_0 / MTU3 / MTIOC7B.
IOPORT_PIN_P100_PFC_09_GTIOC04_2A	P10_0 / GPT / GTIOC04_2A.
IOPORT_PIN_P100_PFC_0A_GTIOC10_2A	P10_0 / GPT / GTIOC10_2A.
IOPORT_PIN_P100_PFC_1D_MCLK72	P10_0 / DSMIFn / MCLK72.
IOPORT_PIN_P100_PFC_24_TST_OUT14	P10_0 / ENDATn / TST_OUT14.
IOPORT_PIN_P100_PFC_25_HDSL07_MOSI2	P10_0 / HDSLn / HDSL07_MOSI2.
IOPORT_PIN_P100_PFC_28_DISP_DATAR0	P10_0 / LCDC / DISP_DATAR0.
IOPORT_PIN_P101_PFC_00_IRQ7	P10_1 / IRQ / IRQ7.
IOPORT_PIN_P101_PFC_04_WAIT	P10_1 / BSC / WAIT.
IOPORT_PIN_P101_PFC_06_MTIOC7D	P10_1 / MTU3 / MTIOC7D.
IOPORT_PIN_P101_PFC_09_GTIOC04_2B	P10_1 / GPT / GTIOC04_2B.
IOPORT_PIN_P101_PFC_0A_GTIOC10_2B	P10_1 / GPT / GTIOC10_2B.
IOPORT_PIN_P101_PFC_14_SCK0	P10_1 / SCIn / SCK0.
IOPORT_PIN_P101_PFC_1D_MDAT72	P10_1 / DSMIFn / MDAT72.
IOPORT_PIN_P101_PFC_24_SI14	P10_1 / ENDATn / SI14.
IOPORT_PIN_P101_PFC_25_HDSL08_LINK	P10_1 / HDSLn / HDSL08_LINK.
IOPORT_PIN_P101_PFC_28_DISP_DATAR1	P10_1 / LCDC / DISP_DATAR1.
IOPORT_PIN_P102_PFC_00_IRQ1	P10_2 / IRQ / IRQ1.
IOPORT_PIN_P102_PFC_04_CS0	P10_2 / BSC / CS0.
IOPORT_PIN_P102_PFC_06_MTCLKC	P10_2 / MTU3 / MTCLKC.
IOPORT_PIN_P102_PFC_07_MTIOC2A	P10_2 / MTU3 / MTIOC2A.
IOPORT_PIN_P102_PFC_09_GTIOC04_3A	P10_2 / GPT / GTIOC04_3A.
IOPORT_PIN_P102_PFC_0A_GTIOC10_3A	P10_2 / GPT / GTIOC10_3A.
IOPORT_PIN_P102_PFC_14_RXD0_SCL0_MISO0	P10_2 / SCIn / RXD0_SCL0_MISO0.
IOPORT_PIN_P102_PFC_15_SCKE04	P10_2 / SCIEn / SCKE04.
IOPORT_PIN_P102_PFC_1D_MCLK10	P10_2 / DSMIFn / MCLK10.
IOPORT_PIN_P102_PFC_1E_MCLK00	P10_2 / DSMIFn / MCLK00.
IOPORT_PIN_P102_PFC_22_ENCIFCK04	P10_2 / ENCIFn / ENCIFCK04.
IOPORT_PIN_P102_PFC_25_HDSL08_SMPL	P10_2 / HDSLn / HDSL08_SMPL.
IOPORT_PIN_P102_PFC_28_DISP_DATAR2	P10_2 / LCDC / DISP_DATAR2.
IOPORT_PIN_P103_PFC_00_IRQ2	P10_3 / IRQ / IRQ2.
IOPORT_PIN_P103_PFC_04_RD	P10_3 / BSC / RD.
IOPORT_PIN_P103_PFC_06_MTCLKD	P10_3 / MTU3 / MTCLKD.
IOPORT_PIN_P103_PFC_07_MTIOC2B	P10_3 / MTU3 / MTIOC2B.
IOPORT_PIN_P103_PFC_09_GTIOC04_3B	P10_3 / GPT / GTIOC04_3B.
IOPORT_PIN_P103_PFC_0A_GTIOC10_3B	P10_3 / GPT / GTIOC10_3B.
IOPORT_PIN_P103_PFC_14_TXD0_SDA0_MOSI0	P10_3 / SCIn / TXD0_SDA0_MOSI0.
IOPORT_PIN_P103_PFC_15_DEE04	P10_3 / SCIEn / DEE04.
IOPORT_PIN_P103_PFC_1D_MDAT10	P10_3 / DSMIFn / MDAT10.
IOPORT_PIN_P103_PFC_1E_MDAT00	P10_3 / DSMIFn / MDAT00.
IOPORT_PIN_P103_PFC_22_ENCIFOE04	P10_3 / ENCIFn / ENCIFOE04.
IOPORT_PIN_P103_PFC_25_HDSL08_CLK1	P10_3 / HDSLn / HDSL08_CLK1.
IOPORT_PIN_P103_PFC_28_DISP_DATAR3	P10_3 / LCDC / DISP_DATAR3.
IOPORT_PIN_P104_PFC_00_IRQ3	P10_4 / IRQ / IRQ3.
IOPORT_PIN_P104_PFC_04_A1	P10_4 / BSC / A1.
IOPORT_PIN_P104_PFC_06_MTIOC1A	P10_4 / MTU3 / MTIOC1A.
IOPORT_PIN_P104_PFC_09_GTIOC04_4A	P10_4 / GPT / GTIOC04_4A.
IOPORT_PIN_P104_PFC_14_SS0_CTS0_RTS0	P10_4 / SCIn / SS0_CTS0_RTS0.
IOPORT_PIN_P104_PFC_15_TXDE04	P10_4 / SCIEn / TXDE04.
IOPORT_PIN_P104_PFC_1D_MCLK11	P10_4 / DSMIFn / MCLK11.
IOPORT_PIN_P104_PFC_1E_MCLK01	P10_4 / DSMIFn / MCLK01.
IOPORT_PIN_P104_PFC_22_ENCIFDO04	P10_4 / ENCIFn / ENCIFDO04.
IOPORT_PIN_P104_PFC_25_HDSL08_SEL1	P10_4 / HDSLn / HDSL08_SEL1.
IOPORT_PIN_P104_PFC_28_DISP_DATAR4	P10_4 / LCDC / DISP_DATAR4.
IOPORT_PIN_P105_PFC_04_A2	P10_5 / BSC / A2.
IOPORT_PIN_P105_PFC_06_MTIOC1B	P10_5 / MTU3 / MTIOC1B.
IOPORT_PIN_P105_PFC_07_MTIOC0A	P10_5 / MTU3 / MTIOC0A.
IOPORT_PIN_P105_PFC_09_GTIOC04_4B	P10_5 / GPT / GTIOC04_4B.
IOPORT_PIN_P105_PFC_14_CTS0	P10_5 / SCIn / CTS0.
IOPORT_PIN_P105_PFC_15_RXDE04	P10_5 / SCIEn / RXDE04.
IOPORT_PIN_P105_PFC_1D_MDAT11	P10_5 / DSMIFn / MDAT11.
IOPORT_PIN_P105_PFC_1E_MDAT01	P10_5 / DSMIFn / MDAT01.
IOPORT_PIN_P105_PFC_22_ENCIFDI04	P10_5 / ENCIFn / ENCIFDI04.
IOPORT_PIN_P105_PFC_25_HDSL08_MISO1	P10_5 / HDSLn / HDSL08_MISO1.
IOPORT_PIN_P105_PFC_28_DISP_DATAR5	P10_5 / LCDC / DISP_DATAR5.
IOPORT_PIN_P106_PFC_00_IRQ0	P10_6 / IRQ / IRQ0.
IOPORT_PIN_P106_PFC_04_A3	P10_6 / BSC / A3.
IOPORT_PIN_P106_PFC_07_MTIOC0B	P10_6 / MTU3 / MTIOC0B.
IOPORT_PIN_P106_PFC_09_GTIOC05_0A	P10_6 / GPT / GTIOC05_0A.
IOPORT_PIN_P106_PFC_14_DE0	P10_6 / SCIn / DE0.
IOPORT_PIN_P106_PFC_1D_MCLK21	P10_6 / DSMIFn / MCLK21.
IOPORT_PIN_P106_PFC_25_HDSL08_MOSI1	P10_6 / HDSLn / HDSL08_MOSI1.
IOPORT_PIN_P106_PFC_26_POUTA	P10_6 / ENCOUT / POUTA.
IOPORT_PIN_P106_PFC_28_DISP_DATAR6	P10_6 / LCDC / DISP_DATAR6.
IOPORT_PIN_P107_PFC_00_IRQ9	P10_7 / IRQ / IRQ9.
IOPORT_PIN_P107_PFC_04_A4	P10_7 / BSC / A4.
IOPORT_PIN_P107_PFC_07_MTIC5U	P10_7 / MTU3 / MTIC5U.
IOPORT_PIN_P107_PFC_09_GTIOC05_0B	P10_7 / GPT / GTIOC05_0B.
IOPORT_PIN_P107_PFC_0B_GTIOC00_3A	P10_7 / GPT / GTIOC00_3A.
IOPORT_PIN_P107_PFC_14_SCK1	P10_7 / SCIn / SCK1.
IOPORT_PIN_P107_PFC_1D_MDAT21	P10_7 / DSMIFn / MDAT21.
IOPORT_PIN_P107_PFC_25_HDSL08_CLK2	P10_7 / HDSLn / HDSL08_CLK2.
IOPORT_PIN_P107_PFC_26_POUTB	P10_7 / ENCOUT / POUTB.
IOPORT_PIN_P107_PFC_28_DISP_DATAR7	P10_7 / LCDC / DISP_DATAR7.
IOPORT_PIN_P110_PFC_00_IRQ13	P11_0 / IRQ / IRQ13.
IOPORT_PIN_P110_PFC_04_A5	P11_0 / BSC / A5.
IOPORT_PIN_P110_PFC_0B_GTIOC00_3B	P11_0 / GPT / GTIOC00_3B.
IOPORT_PIN_P110_PFC_12_ESC_RESETOUT_N	P11_0 / ETHER_ESC / ESC_RESETOUT_N.
IOPORT_PIN_P110_PFC_14_RXD1_SCL1_MISO1	P11_0 / SCIn / RXD1_SCL1_MISO1.
IOPORT_PIN_P110_PFC_1D_MCLK22	P11_0 / DSMIFn / MCLK22.
IOPORT_PIN_P110_PFC_25_HDSL08_SEL2	P11_0 / HDSLn / HDSL08_SEL2.
IOPORT_PIN_P110_PFC_26_POUTZ	P11_0 / ENCOUT / POUTZ.
IOPORT_PIN_P110_PFC_28_DISP_DATAG0	P11_0 / LCDC / DISP_DATAG0.
IOPORT_PIN_P111_PFC_00_IRQ4	P11_1 / IRQ / IRQ4.
IOPORT_PIN_P111_PFC_12_ESC_LEDRUN	P11_1 / ETHER_ESC / ESC_LEDRUN.
IOPORT_PIN_P111_PFC_14_TXD1_SDA1_MOSI1	P11_1 / SCIn / TXD1_SDA1_MOSI1.
IOPORT_PIN_P111_PFC_1D_MDAT22	P11_1 / DSMIFn / MDAT22.
IOPORT_PIN_P111_PFC_24_DUEI15	P11_1 / ENDATn / DUEI15.
IOPORT_PIN_P111_PFC_25_HDSL08_MISO2	P11_1 / HDSLn / HDSL08_MISO2.
IOPORT_PIN_P112_PFC_00_IRQ5	P11_2 / IRQ / IRQ5.
IOPORT_PIN_P112_PFC_14_SS1_CTS1_RTS1	P11_2 / SCIn / SS1_CTS1_RTS1.
IOPORT_PIN_P112_PFC_1D_MCLK30	P11_2 / DSMIFn / MCLK30.
IOPORT_PIN_P112_PFC_24_TST_OUT15	P11_2 / ENDATn / TST_OUT15.
IOPORT_PIN_P112_PFC_25_HDSL08_MOSI2	P11_2 / HDSLn / HDSL08_MOSI2.
IOPORT_PIN_P113_PFC_00_IRQ6	P11_3 / IRQ / IRQ6.
IOPORT_PIN_P113_PFC_14_CTS1	P11_3 / SCIn / CTS1.
IOPORT_PIN_P113_PFC_1D_MDAT30	P11_3 / DSMIFn / MDAT30.
IOPORT_PIN_P113_PFC_24_SI15	P11_3 / ENDATn / SI15.
IOPORT_PIN_P113_PFC_25_HDSL09_LINK	P11_3 / HDSLn / HDSL09_LINK.
IOPORT_PIN_P114_PFC_00_IRQ7	P11_4 / IRQ / IRQ7.
IOPORT_PIN_P114_PFC_14_DE1	P11_4 / SCIn / DE1.
IOPORT_PIN_P114_PFC_1D_MCLK31	P11_4 / DSMIFn / MCLK31.
IOPORT_PIN_P114_PFC_25_HDSL09_SMPL	P11_4 / HDSLn / HDSL09_SMPL.
IOPORT_PIN_P115_PFC_1D_MDAT31	P11_5 / DSMIFn / MDAT31.
IOPORT_PIN_P115_PFC_24_DUEI00	P11_5 / ENDATn / DUEI00.
IOPORT_PIN_P115_PFC_25_HDSL09_CLK1	P11_5 / HDSLn / HDSL09_CLK1.
IOPORT_PIN_P116_PFC_09_GTIOC05_0A	P11_6 / GPT / GTIOC05_0A.
IOPORT_PIN_P116_PFC_24_TST_OUT00	P11_6 / ENDATn / TST_OUT00.
IOPORT_PIN_P116_PFC_25_HDSL09_SEL1	P11_6 / HDSLn / HDSL09_SEL1.
IOPORT_PIN_P117_PFC_09_GTIOC05_0B	P11_7 / GPT / GTIOC05_0B.
IOPORT_PIN_P117_PFC_24_SI00	P11_7 / ENDATn / SI00.
IOPORT_PIN_P117_PFC_25_HDSL09_MISO1	P11_7 / HDSLn / HDSL09_MISO1.
IOPORT_PIN_P120_PFC_04_D16	P12_0 / BSC / D16.
IOPORT_PIN_P120_PFC_07_MTIC5V	P12_0 / MTU3 / MTIC5V.
IOPORT_PIN_P120_PFC_09_GTIOC05_1A	P12_0 / GPT / GTIOC05_1A.
IOPORT_PIN_P120_PFC_0D_CMTW0_TIC0	P12_0 / CMTW / CMTW0_TIC0.
IOPORT_PIN_P120_PFC_19_CANRX1	P12_0 / CANFDn / CANRX1.
IOPORT_PIN_P120_PFC_24_DUEI01	P12_0 / ENDATn / DUEI01.
IOPORT_PIN_P120_PFC_25_HDSL09_MOSI1	P12_0 / HDSLn / HDSL09_MOSI1.
IOPORT_PIN_P120_PFC_29_SD0_CLK	P12_0 / SDHI / SD0_CLK.
IOPORT_PIN_P121_PFC_04_D17	P12_1 / BSC / D17.
IOPORT_PIN_P121_PFC_07_MTIC5W	P12_1 / MTU3 / MTIC5W.
IOPORT_PIN_P121_PFC_09_GTIOC05_1B	P12_1 / GPT / GTIOC05_1B.
IOPORT_PIN_P121_PFC_0D_CMTW0_TOC0	P12_1 / CMTW / CMTW0_TOC0.
IOPORT_PIN_P121_PFC_19_CANTX1	P12_1 / CANFDn / CANTX1.
IOPORT_PIN_P121_PFC_24_TST_OUT01	P12_1 / ENDATn / TST_OUT01.
IOPORT_PIN_P121_PFC_25_HDSL09_CLK2	P12_1 / HDSLn / HDSL09_CLK2.
IOPORT_PIN_P121_PFC_29_SD0_CMD	P12_1 / SDHI / SD0_CMD.
IOPORT_PIN_P122_PFC_04_D18	P12_2 / BSC / D18.
IOPORT_PIN_P122_PFC_09_GTIOC05_2A	P12_2 / GPT / GTIOC05_2A.
IOPORT_PIN_P122_PFC_0D_CMTW0_TIC1	P12_2 / CMTW / CMTW0_TIC1.
IOPORT_PIN_P122_PFC_19_CANRXDP1	P12_2 / CANFDn / CANRXDP1.
IOPORT_PIN_P122_PFC_24_SI01	P12_2 / ENDATn / SI01.
IOPORT_PIN_P122_PFC_25_HDSL09_SEL2	P12_2 / HDSLn / HDSL09_SEL2.
IOPORT_PIN_P122_PFC_29_SD0_DATA0	P12_2 / SDHI / SD0_DATA0.
IOPORT_PIN_P123_PFC_04_D19	P12_3 / BSC / D19.
IOPORT_PIN_P123_PFC_09_GTIOC05_2B	P12_3 / GPT / GTIOC05_2B.
IOPORT_PIN_P123_PFC_0D_CMTW0_TOC1	P12_3 / CMTW / CMTW0_TOC1.
IOPORT_PIN_P123_PFC_14_SCK2	P12_3 / SCIn / SCK2.
IOPORT_PIN_P123_PFC_19_CANTXDP1	P12_3 / CANFDn / CANTXDP1.
IOPORT_PIN_P123_PFC_25_HDSL09_MISO2	P12_3 / HDSLn / HDSL09_MISO2.
IOPORT_PIN_P123_PFC_29_SD0_DATA1	P12_3 / SDHI / SD0_DATA1.
IOPORT_PIN_P124_PFC_00_IRQ1	P12_4 / IRQ / IRQ1.
IOPORT_PIN_P124_PFC_04_D20	P12_4 / BSC / D20.
IOPORT_PIN_P124_PFC_09_GTIOC05_3A	P12_4 / GPT / GTIOC05_3A.
IOPORT_PIN_P124_PFC_0D_CMTW1_TIC0	P12_4 / CMTW / CMTW1_TIC0.
IOPORT_PIN_P124_PFC_14_RXD2_SCL2_MISO2	P12_4 / SCIn / RXD2_SCL2_MISO2.
IOPORT_PIN_P124_PFC_15_SCKE05	P12_4 / SCIEn / SCKE05.
IOPORT_PIN_P124_PFC_1D_MCLK02	P12_4 / DSMIFn / MCLK02.
IOPORT_PIN_P124_PFC_22_ENCIFCK05	P12_4 / ENCIFn / ENCIFCK05.
IOPORT_PIN_P124_PFC_25_HDSL09_MOSI2	P12_4 / HDSLn / HDSL09_MOSI2.
IOPORT_PIN_P124_PFC_29_SD0_DATA2	P12_4 / SDHI / SD0_DATA2.
IOPORT_PIN_P125_PFC_04_D21	P12_5 / BSC / D21.
IOPORT_PIN_P125_PFC_09_GTIOC05_3B	P12_5 / GPT / GTIOC05_3B.
IOPORT_PIN_P125_PFC_0B_GTIOC01_3A	P12_5 / GPT / GTIOC01_3A.
IOPORT_PIN_P125_PFC_0D_CMTW1_TOC0	P12_5 / CMTW / CMTW1_TOC0.
IOPORT_PIN_P125_PFC_14_TXD2_SDA2_MOSI2	P12_5 / SCIn / TXD2_SDA2_MOSI2.
IOPORT_PIN_P125_PFC_15_DEE05	P12_5 / SCIEn / DEE05.
IOPORT_PIN_P125_PFC_1D_MDAT02	P12_5 / DSMIFn / MDAT02.
IOPORT_PIN_P125_PFC_22_ENCIFOE05	P12_5 / ENCIFn / ENCIFOE05.
IOPORT_PIN_P125_PFC_25_HDSL10_LINK	P12_5 / HDSLn / HDSL10_LINK.
IOPORT_PIN_P125_PFC_29_SD0_DATA3	P12_5 / SDHI / SD0_DATA3.
IOPORT_PIN_P126_PFC_04_D22	P12_6 / BSC / D22.
IOPORT_PIN_P126_PFC_09_GTIOC05_4A	P12_6 / GPT / GTIOC05_4A.
IOPORT_PIN_P126_PFC_0B_GTIOC01_3B	P12_6 / GPT / GTIOC01_3B.
IOPORT_PIN_P126_PFC_0D_CMTW1_TIC1	P12_6 / CMTW / CMTW1_TIC1.
IOPORT_PIN_P126_PFC_14_SS2_CTS2_RTS2	P12_6 / SCIn / SS2_CTS2_RTS2.
IOPORT_PIN_P126_PFC_15_TXDE05	P12_6 / SCIEn / TXDE05.
IOPORT_PIN_P126_PFC_1D_MCLK10	P12_6 / DSMIFn / MCLK10.
IOPORT_PIN_P126_PFC_22_ENCIFDO05	P12_6 / ENCIFn / ENCIFDO05.
IOPORT_PIN_P126_PFC_25_HDSL10_SMPL	P12_6 / HDSLn / HDSL10_SMPL.
IOPORT_PIN_P126_PFC_29_SD0_DATA4	P12_6 / SDHI / SD0_DATA4.
IOPORT_PIN_P127_PFC_00_IRQ2	P12_7 / IRQ / IRQ2.
IOPORT_PIN_P127_PFC_04_D23	P12_7 / BSC / D23.
IOPORT_PIN_P127_PFC_09_GTIOC05_4B	P12_7 / GPT / GTIOC05_4B.
IOPORT_PIN_P127_PFC_0D_CMTW1_TOC1	P12_7 / CMTW / CMTW1_TOC1.
IOPORT_PIN_P127_PFC_14_CTS2	P12_7 / SCIn / CTS2.
IOPORT_PIN_P127_PFC_15_RXDE05	P12_7 / SCIEn / RXDE05.
IOPORT_PIN_P127_PFC_1D_MDAT10	P12_7 / DSMIFn / MDAT10.
IOPORT_PIN_P127_PFC_22_ENCIFDI05	P12_7 / ENCIFn / ENCIFDI05.
IOPORT_PIN_P127_PFC_25_HDSL10_CLK1	P12_7 / HDSLn / HDSL10_CLK1.
IOPORT_PIN_P127_PFC_29_SD0_DATA5	P12_7 / SDHI / SD0_DATA5.
IOPORT_PIN_P130_PFC_04_D24	P13_0 / BSC / D24.
IOPORT_PIN_P130_PFC_0B_GTIOC02_3A	P13_0 / GPT / GTIOC02_3A.
IOPORT_PIN_P130_PFC_14_DE2	P13_0 / SCIn / DE2.
IOPORT_PIN_P130_PFC_15_SCKE08	P13_0 / SCIEn / SCKE08.
IOPORT_PIN_P130_PFC_16_SCKE03	P13_0 / SCIEn / SCKE03.
IOPORT_PIN_P130_PFC_1A_SPI_RSPCK3	P13_0 / SPIn / SPI_RSPCK3.
IOPORT_PIN_P130_PFC_1D_MCLK00	P13_0 / DSMIFn / MCLK00.
IOPORT_PIN_P130_PFC_22_ENCIFCK12	P13_0 / ENCIFn / ENCIFCK12.
IOPORT_PIN_P130_PFC_23_ENCIFCK03	P13_0 / ENCIFn / ENCIFCK03.
IOPORT_PIN_P130_PFC_25_HDSL10_SEL1	P13_0 / HDSLn / HDSL10_SEL1.
IOPORT_PIN_P130_PFC_29_SD0_DATA6	P13_0 / SDHI / SD0_DATA6.
IOPORT_PIN_P131_PFC_04_D25	P13_1 / BSC / D25.
IOPORT_PIN_P131_PFC_0B_GTIOC02_3B	P13_1 / GPT / GTIOC02_3B.
IOPORT_PIN_P131_PFC_15_DEE08	P13_1 / SCIEn / DEE08.
IOPORT_PIN_P131_PFC_16_DEE03	P13_1 / SCIEn / DEE03.
IOPORT_PIN_P131_PFC_1A_SPI_MOSI3	P13_1 / SPIn / SPI_MOSI3.
IOPORT_PIN_P131_PFC_1D_MDAT00	P13_1 / DSMIFn / MDAT00.
IOPORT_PIN_P131_PFC_22_ENCIFOE12	P13_1 / ENCIFn / ENCIFOE12.
IOPORT_PIN_P131_PFC_23_ENCIFOE03	P13_1 / ENCIFn / ENCIFOE03.
IOPORT_PIN_P131_PFC_25_HDSL10_MISO1	P13_1 / HDSLn / HDSL10_MISO1.
IOPORT_PIN_P131_PFC_29_SD0_DATA7	P13_1 / SDHI / SD0_DATA7.
IOPORT_PIN_P132_PFC_00_IRQ3	P13_2 / IRQ / IRQ3.
IOPORT_PIN_P132_PFC_04_D26	P13_2 / BSC / D26.
IOPORT_PIN_P132_PFC_15_TXDE08	P13_2 / SCIEn / TXDE08.
IOPORT_PIN_P132_PFC_16_TXDE03	P13_2 / SCIEn / TXDE03.
IOPORT_PIN_P132_PFC_1A_SPI_MISO3	P13_2 / SPIn / SPI_MISO3.
IOPORT_PIN_P132_PFC_1D_MCLK01	P13_2 / DSMIFn / MCLK01.
IOPORT_PIN_P132_PFC_22_ENCIFDO12	P13_2 / ENCIFn / ENCIFDO12.
IOPORT_PIN_P132_PFC_23_ENCIFDO03	P13_2 / ENCIFn / ENCIFDO03.
IOPORT_PIN_P132_PFC_25_HDSL10_MOSI1	P13_2 / HDSLn / HDSL10_MOSI1.
IOPORT_PIN_P132_PFC_29_SD0_RST	P13_2 / SDHI / SD0_RST.
IOPORT_PIN_P133_PFC_04_D27	P13_3 / BSC / D27.
IOPORT_PIN_P133_PFC_0B_GTIOC03_3A	P13_3 / GPT / GTIOC03_3A.
IOPORT_PIN_P133_PFC_14_SCK3	P13_3 / SCIn / SCK3.
IOPORT_PIN_P133_PFC_15_RXDE08	P13_3 / SCIEn / RXDE08.
IOPORT_PIN_P133_PFC_16_RXDE03	P13_3 / SCIEn / RXDE03.
IOPORT_PIN_P133_PFC_1A_SPI_SSL30	P13_3 / SPIn / SPI_SSL30.
IOPORT_PIN_P133_PFC_1D_MDAT01	P13_3 / DSMIFn / MDAT01.
IOPORT_PIN_P133_PFC_22_ENCIFDI12	P13_3 / ENCIFn / ENCIFDI12.
IOPORT_PIN_P133_PFC_23_ENCIFDI03	P13_3 / ENCIFn / ENCIFDI03.
IOPORT_PIN_P133_PFC_25_HDSL10_CLK2	P13_3 / HDSLn / HDSL10_CLK2.
IOPORT_PIN_P134_PFC_04_D28	P13_4 / BSC / D28.
IOPORT_PIN_P134_PFC_0B_GTIOC03_3B	P13_4 / GPT / GTIOC03_3B.
IOPORT_PIN_P134_PFC_14_RXD3_SCL3_MISO3	P13_4 / SCIn / RXD3_SCL3_MISO3.
IOPORT_PIN_P134_PFC_15_SCKE09	P13_4 / SCIEn / SCKE09.
IOPORT_PIN_P134_PFC_1A_SPI_SSL31	P13_4 / SPIn / SPI_SSL31.
IOPORT_PIN_P134_PFC_1D_MCLK40	P13_4 / DSMIFn / MCLK40.
IOPORT_PIN_P134_PFC_22_ENCIFCK13	P13_4 / ENCIFn / ENCIFCK13.
IOPORT_PIN_P134_PFC_25_HDSL10_SEL2	P13_4 / HDSLn / HDSL10_SEL2.
IOPORT_PIN_P135_PFC_00_IRQ4	P13_5 / IRQ / IRQ4.
IOPORT_PIN_P135_PFC_04_D29	P13_5 / BSC / D29.
IOPORT_PIN_P135_PFC_09_GTIOC06_3A	P13_5 / GPT / GTIOC06_3A.
IOPORT_PIN_P135_PFC_14_TXD3_SDA3_MOSI3	P13_5 / SCIn / TXD3_SDA3_MOSI3.
IOPORT_PIN_P135_PFC_15_DEE09	P13_5 / SCIEn / DEE09.
IOPORT_PIN_P135_PFC_1A_SPI_SSL32	P13_5 / SPIn / SPI_SSL32.
IOPORT_PIN_P135_PFC_1D_MDAT40	P13_5 / DSMIFn / MDAT40.
IOPORT_PIN_P135_PFC_22_ENCIFOE13	P13_5 / ENCIFn / ENCIFOE13.
IOPORT_PIN_P135_PFC_25_HDSL10_MISO2	P13_5 / HDSLn / HDSL10_MISO2.
IOPORT_PIN_P136_PFC_04_D30	P13_6 / BSC / D30.
IOPORT_PIN_P136_PFC_09_GTIOC06_3B	P13_6 / GPT / GTIOC06_3B.
IOPORT_PIN_P136_PFC_0B_GTIOC04_3A	P13_6 / GPT / GTIOC04_3A.
IOPORT_PIN_P136_PFC_14_SS3_CTS3_RTS3	P13_6 / SCIn / SS3_CTS3_RTS3.
IOPORT_PIN_P136_PFC_15_TXDE09	P13_6 / SCIEn / TXDE09.
IOPORT_PIN_P136_PFC_1A_SPI_SSL23	P13_6 / SPIn / SPI_SSL23.
IOPORT_PIN_P136_PFC_1D_MCLK41	P13_6 / DSMIFn / MCLK41.
IOPORT_PIN_P136_PFC_22_ENCIFDO13	P13_6 / ENCIFn / ENCIFDO13.
IOPORT_PIN_P136_PFC_25_HDSL10_MOSI2	P13_6 / HDSLn / HDSL10_MOSI2.
IOPORT_PIN_P137_PFC_00_IRQ14	P13_7 / IRQ / IRQ14.
IOPORT_PIN_P137_PFC_04_D31	P13_7 / BSC / D31.
IOPORT_PIN_P137_PFC_09_GTIOC06_4A	P13_7 / GPT / GTIOC06_4A.
IOPORT_PIN_P137_PFC_0B_GTIOC04_3B	P13_7 / GPT / GTIOC04_3B.
IOPORT_PIN_P137_PFC_14_CTS3	P13_7 / SCIn / CTS3.
IOPORT_PIN_P137_PFC_15_RXDE09	P13_7 / SCIEn / RXDE09.
IOPORT_PIN_P137_PFC_1D_MDAT41	P13_7 / DSMIFn / MDAT41.
IOPORT_PIN_P137_PFC_22_ENCIFDI13	P13_7 / ENCIFn / ENCIFDI13.
IOPORT_PIN_P137_PFC_25_HDSL11_LINK	P13_7 / HDSLn / HDSL11_LINK.
IOPORT_PIN_P140_PFC_00_IRQ5	P14_0 / IRQ / IRQ5.
IOPORT_PIN_P140_PFC_04_A0	P14_0 / BSC / A0.
IOPORT_PIN_P140_PFC_09_GTIOC06_4B	P14_0 / GPT / GTIOC06_4B.
IOPORT_PIN_P140_PFC_11_ETHSW_PTPOUT2	P14_0 / ETHER_ETHSW / ETHSW_PTPOUT2.
IOPORT_PIN_P140_PFC_12_ESC_SYNC0	P14_0 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P140_PFC_14_DE3	P14_0 / SCIn / DE3.
IOPORT_PIN_P140_PFC_1D_MCLK42	P14_0 / DSMIFn / MCLK42.
IOPORT_PIN_P140_PFC_25_HDSL11_SMPL	P14_0 / HDSLn / HDSL11_SMPL.
IOPORT_PIN_P141_PFC_04_RD_WR	P14_1 / BSC / RD_WR.
IOPORT_PIN_P141_PFC_09_GTIOC06_0A	P14_1 / GPT / GTIOC06_0A.
IOPORT_PIN_P141_PFC_0A_GTIOC09_0A	P14_1 / GPT / GTIOC09_0A.
IOPORT_PIN_P141_PFC_0B_GTIOC05_3A	P14_1 / GPT / GTIOC05_3A.
IOPORT_PIN_P141_PFC_0E_RTCAT1HZ	P14_1 / RTC / RTCAT1HZ.
IOPORT_PIN_P141_PFC_14_SCK4	P14_1 / SCIn / SCK4.
IOPORT_PIN_P141_PFC_1D_MDAT42	P14_1 / DSMIFn / MDAT42.
IOPORT_PIN_P141_PFC_24_DUEI02	P14_1 / ENDATn / DUEI02.
IOPORT_PIN_P141_PFC_25_HDSL11_CLK1	P14_1 / HDSLn / HDSL11_CLK1.
IOPORT_PIN_P141_PFC_28_DISP_DATAG1	P14_1 / LCDC / DISP_DATAG1.
IOPORT_PIN_P141_PFC_29_SD0_CD	P14_1 / SDHI / SD0_CD.
IOPORT_PIN_P142_PFC_04_BS	P14_2 / BSC / BS.
IOPORT_PIN_P142_PFC_09_GTIOC06_0B	P14_2 / GPT / GTIOC06_0B.
IOPORT_PIN_P142_PFC_0A_GTIOC09_0B	P14_2 / GPT / GTIOC09_0B.
IOPORT_PIN_P142_PFC_0B_GTIOC05_3B	P14_2 / GPT / GTIOC05_3B.
IOPORT_PIN_P142_PFC_14_RXD4_SCL4_MISO4	P14_2 / SCIn / RXD4_SCL4_MISO4.
IOPORT_PIN_P142_PFC_15_SCKE00	P14_2 / SCIEn / SCKE00.
IOPORT_PIN_P142_PFC_22_ENCIFCK00	P14_2 / ENCIFn / ENCIFCK00.
IOPORT_PIN_P142_PFC_25_HDSL11_SEL1	P14_2 / HDSLn / HDSL11_SEL1.
IOPORT_PIN_P142_PFC_28_DISP_DATAG2	P14_2 / LCDC / DISP_DATAG2.
IOPORT_PIN_P142_PFC_29_SD0_WP	P14_2 / SDHI / SD0_WP.
IOPORT_PIN_P143_PFC_00_IRQ6	P14_3 / IRQ / IRQ6.
IOPORT_PIN_P143_PFC_05_DREQ	P14_3 / DMAC / DREQ.
IOPORT_PIN_P143_PFC_08_POE0	P14_3 / POE3 / POE0.
IOPORT_PIN_P143_PFC_09_GTIOC06_1A	P14_3 / GPT / GTIOC06_1A.
IOPORT_PIN_P143_PFC_0A_GTIOC09_1A	P14_3 / GPT / GTIOC09_1A.
IOPORT_PIN_P143_PFC_12_ESC_LINKACT2	P14_3 / ETHER_ESC / ESC_LINKACT2.
IOPORT_PIN_P143_PFC_14_TXD4_SDA4_MOSI4	P14_3 / SCIn / TXD4_SDA4_MOSI4.
IOPORT_PIN_P143_PFC_15_DEE00	P14_3 / SCIEn / DEE00.
IOPORT_PIN_P143_PFC_22_ENCIFOE00	P14_3 / ENCIFn / ENCIFOE00.
IOPORT_PIN_P143_PFC_25_HDSL11_MISO1	P14_3 / HDSLn / HDSL11_MISO1.
IOPORT_PIN_P143_PFC_28_DISP_DATAG3	P14_3 / LCDC / DISP_DATAG3.
IOPORT_PIN_P143_PFC_29_SD1_CD	P14_3 / SDHI / SD1_CD.
IOPORT_PIN_P144_PFC_05_DACK	P14_4 / DMAC / DACK.
IOPORT_PIN_P144_PFC_08_POE4	P14_4 / POE3 / POE4.
IOPORT_PIN_P144_PFC_09_GTIOC06_1B	P14_4 / GPT / GTIOC06_1B.
IOPORT_PIN_P144_PFC_0A_GTIOC09_1B	P14_4 / GPT / GTIOC09_1B.
IOPORT_PIN_P144_PFC_0B_GTIOC06_3A	P14_4 / GPT / GTIOC06_3A.
IOPORT_PIN_P144_PFC_0D_CMTW0_TIC0	P14_4 / CMTW / CMTW0_TIC0.
IOPORT_PIN_P144_PFC_12_ESC_IRQ	P14_4 / ETHER_ESC / ESC_IRQ.
IOPORT_PIN_P144_PFC_14_SS4_CTS4_RTS4	P14_4 / SCIn / SS4_CTS4_RTS4.
IOPORT_PIN_P144_PFC_15_TXDE00	P14_4 / SCIEn / TXDE00.
IOPORT_PIN_P144_PFC_21_MBX_HINT	P14_4 / MBXSEM / MBX_HINT.
IOPORT_PIN_P144_PFC_22_ENCIFDO00	P14_4 / ENCIFn / ENCIFDO00.
IOPORT_PIN_P144_PFC_25_HDSL11_MOSI1	P14_4 / HDSLn / HDSL11_MOSI1.
IOPORT_PIN_P144_PFC_28_DISP_DATAG4	P14_4 / LCDC / DISP_DATAG4.
IOPORT_PIN_P144_PFC_29_SD1_WP	P14_4 / SDHI / SD1_WP.
IOPORT_PIN_P145_PFC_05_TEND	P14_5 / DMAC / TEND.
IOPORT_PIN_P145_PFC_08_POE8	P14_5 / POE3 / POE8.
IOPORT_PIN_P145_PFC_09_GTIOC06_2A	P14_5 / GPT / GTIOC06_2A.
IOPORT_PIN_P145_PFC_0A_GTIOC09_2A	P14_5 / GPT / GTIOC09_2A.
IOPORT_PIN_P145_PFC_0B_GTIOC06_3B	P14_5 / GPT / GTIOC06_3B.
IOPORT_PIN_P145_PFC_0D_CMTW0_TOC0	P14_5 / CMTW / CMTW0_TOC0.
IOPORT_PIN_P145_PFC_12_ESC_RESETOUT_N	P14_5 / ETHER_ESC / ESC_RESETOUT_N.
IOPORT_PIN_P145_PFC_14_CTS4	P14_5 / SCIn / CTS4.
IOPORT_PIN_P145_PFC_15_RXDE00	P14_5 / SCIEn / RXDE00.
IOPORT_PIN_P145_PFC_22_ENCIFDI00	P14_5 / ENCIFn / ENCIFDI00.
IOPORT_PIN_P145_PFC_25_HDSL11_CLK2	P14_5 / HDSLn / HDSL11_CLK2.
IOPORT_PIN_P145_PFC_28_DISP_DATAG5	P14_5 / LCDC / DISP_DATAG5.
IOPORT_PIN_P146_PFC_00_IRQ8	P14_6 / IRQ / IRQ8.
IOPORT_PIN_P146_PFC_08_POE10	P14_6 / POE3 / POE10.
IOPORT_PIN_P146_PFC_09_GTIOC06_2B	P14_6 / GPT / GTIOC06_2B.
IOPORT_PIN_P146_PFC_0A_GTIOC09_2B	P14_6 / GPT / GTIOC09_2B.
IOPORT_PIN_P146_PFC_0D_CMTW0_TIC1	P14_6 / CMTW / CMTW0_TIC1.
IOPORT_PIN_P146_PFC_12_ESC_I2CCLK	P14_6 / ETHER_ESC / ESC_I2CCLK.
IOPORT_PIN_P146_PFC_14_DE4	P14_6 / SCIn / DE4.
IOPORT_PIN_P146_PFC_17_IIC_SCL0	P14_6 / IICn / IIC_SCL0.
IOPORT_PIN_P146_PFC_24_TST_OUT02	P14_6 / ENDATn / TST_OUT02.
IOPORT_PIN_P146_PFC_25_HDSL11_SEL2	P14_6 / HDSLn / HDSL11_SEL2.
IOPORT_PIN_P146_PFC_28_DISP_DATAG6	P14_6 / LCDC / DISP_DATAG6.
IOPORT_PIN_P146_PFC_29_SD0_PWEN	P14_6 / SDHI / SD0_PWEN.
IOPORT_PIN_P147_PFC_00_IRQ9	P14_7 / IRQ / IRQ9.
IOPORT_PIN_P147_PFC_08_POE11	P14_7 / POE3 / POE11.
IOPORT_PIN_P147_PFC_0A_GTIOC09_3A	P14_7 / GPT / GTIOC09_3A.
IOPORT_PIN_P147_PFC_0D_CMTW0_TOC1	P14_7 / CMTW / CMTW0_TOC1.
IOPORT_PIN_P147_PFC_12_ESC_I2CDATA	P14_7 / ETHER_ESC / ESC_I2CDATA.
IOPORT_PIN_P147_PFC_17_IIC_SDA0	P14_7 / IICn / IIC_SDA0.
IOPORT_PIN_P147_PFC_1D_MCLK32	P14_7 / DSMIFn / MCLK32.
IOPORT_PIN_P147_PFC_24_SI02	P14_7 / ENDATn / SI02.
IOPORT_PIN_P147_PFC_25_HDSL11_MISO2	P14_7 / HDSLn / HDSL11_MISO2.
IOPORT_PIN_P147_PFC_29_SD0_IOVS	P14_7 / SDHI / SD0_IOVS.
IOPORT_PIN_P150_PFC_0A_GTIOC09_3B	P15_0 / GPT / GTIOC09_3B.
IOPORT_PIN_P150_PFC_15_SCKE06	P15_0 / SCIEn / SCKE06.
IOPORT_PIN_P150_PFC_1D_MDAT32	P15_0 / DSMIFn / MDAT32.
IOPORT_PIN_P150_PFC_22_ENCIFCK06	P15_0 / ENCIFn / ENCIFCK06.
IOPORT_PIN_P150_PFC_25_HDSL11_MOSI2	P15_0 / HDSLn / HDSL11_MOSI2.
IOPORT_PIN_P151_PFC_0A_GTIOC09_4A	P15_1 / GPT / GTIOC09_4A.
IOPORT_PIN_P151_PFC_15_DEE06	P15_1 / SCIEn / DEE06.
IOPORT_PIN_P151_PFC_1D_MCLK40	P15_1 / DSMIFn / MCLK40.
IOPORT_PIN_P151_PFC_22_ENCIFOE06	P15_1 / ENCIFn / ENCIFOE06.
IOPORT_PIN_P151_PFC_25_HDSL12_LINK	P15_1 / HDSLn / HDSL12_LINK.
IOPORT_PIN_P152_PFC_0A_GTIOC09_4B	P15_2 / GPT / GTIOC09_4B.
IOPORT_PIN_P152_PFC_15_TXDE06	P15_2 / SCIEn / TXDE06.
IOPORT_PIN_P152_PFC_1D_MDAT40	P15_2 / DSMIFn / MDAT40.
IOPORT_PIN_P152_PFC_22_ENCIFDO06	P15_2 / ENCIFn / ENCIFDO06.
IOPORT_PIN_P152_PFC_25_HDSL12_SMPL	P15_2 / HDSLn / HDSL12_SMPL.
IOPORT_PIN_P153_PFC_0A_GTIOC09_5A	P15_3 / GPT / GTIOC09_5A.
IOPORT_PIN_P153_PFC_15_RXDE06	P15_3 / SCIEn / RXDE06.
IOPORT_PIN_P153_PFC_1D_MCLK41	P15_3 / DSMIFn / MCLK41.
IOPORT_PIN_P153_PFC_22_ENCIFDI06	P15_3 / ENCIFn / ENCIFDI06.
IOPORT_PIN_P153_PFC_25_HDSL12_CLK1	P15_3 / HDSLn / HDSL12_CLK1.
IOPORT_PIN_P154_PFC_0A_GTIOC09_5B	P15_4 / GPT / GTIOC09_5B.
IOPORT_PIN_P154_PFC_15_SCKE07	P15_4 / SCIEn / SCKE07.
IOPORT_PIN_P154_PFC_1D_MDAT41	P15_4 / DSMIFn / MDAT41.
IOPORT_PIN_P154_PFC_22_ENCIFCK07	P15_4 / ENCIFn / ENCIFCK07.
IOPORT_PIN_P154_PFC_25_HDSL12_SEL1	P15_4 / HDSLn / HDSL12_SEL1.
IOPORT_PIN_P155_PFC_00_IRQ0	P15_5 / IRQ / IRQ0.
IOPORT_PIN_P155_PFC_0A_GTIOC09_6A	P15_5 / GPT / GTIOC09_6A.
IOPORT_PIN_P155_PFC_15_DEE07	P15_5 / SCIEn / DEE07.
IOPORT_PIN_P155_PFC_1D_MCLK42	P15_5 / DSMIFn / MCLK42.
IOPORT_PIN_P155_PFC_22_ENCIFOE07	P15_5 / ENCIFn / ENCIFOE07.
IOPORT_PIN_P155_PFC_25_HDSL12_MISO1	P15_5 / HDSLn / HDSL12_MISO1.
IOPORT_PIN_P156_PFC_00_IRQ1	P15_6 / IRQ / IRQ1.
IOPORT_PIN_P156_PFC_0A_GTIOC09_6B	P15_6 / GPT / GTIOC09_6B.
IOPORT_PIN_P156_PFC_15_TXDE07	P15_6 / SCIEn / TXDE07.
IOPORT_PIN_P156_PFC_1D_MDAT42	P15_6 / DSMIFn / MDAT42.
IOPORT_PIN_P156_PFC_22_ENCIFDO07	P15_6 / ENCIFn / ENCIFDO07.
IOPORT_PIN_P156_PFC_25_HDSL12_MOSI1	P15_6 / HDSLn / HDSL12_MOSI1.
IOPORT_PIN_P157_PFC_14_SS5_CTS5_RTS5	P15_7 / SCIn / SS5_CTS5_RTS5.
IOPORT_PIN_P157_PFC_15_RXDE07	P15_7 / SCIEn / RXDE07.
IOPORT_PIN_P157_PFC_1D_MCLK50	P15_7 / DSMIFn / MCLK50.
IOPORT_PIN_P157_PFC_22_ENCIFDI07	P15_7 / ENCIFn / ENCIFDI07.
IOPORT_PIN_P157_PFC_25_HDSL12_CLK2	P15_7 / HDSLn / HDSL12_CLK2.
IOPORT_PIN_P160_PFC_00_IRQ2	P16_0 / IRQ / IRQ2.
IOPORT_PIN_P160_PFC_14_CTS5	P16_0 / SCIn / CTS5.
IOPORT_PIN_P160_PFC_15_TXDE07	P16_0 / SCIEn / TXDE07.
IOPORT_PIN_P160_PFC_1D_MDAT50	P16_0 / DSMIFn / MDAT50.
IOPORT_PIN_P160_PFC_24_DUEI03	P16_0 / ENDATn / DUEI03.
IOPORT_PIN_P160_PFC_25_HDSL12_SEL2	P16_0 / HDSLn / HDSL12_SEL2.
IOPORT_PIN_P161_PFC_14_DE5	P16_1 / SCIn / DE5.
IOPORT_PIN_P161_PFC_1D_MCLK51	P16_1 / DSMIFn / MCLK51.
IOPORT_PIN_P161_PFC_24_TST_OUT03	P16_1 / ENDATn / TST_OUT03.
IOPORT_PIN_P161_PFC_25_HDSL12_MISO2	P16_1 / HDSLn / HDSL12_MISO2.
IOPORT_PIN_P162_PFC_14_SCK5	P16_2 / SCIn / SCK5.
IOPORT_PIN_P162_PFC_1D_MDAT51	P16_2 / DSMIFn / MDAT51.
IOPORT_PIN_P162_PFC_24_SI03	P16_2 / ENDATn / SI03.
IOPORT_PIN_P162_PFC_25_HDSL12_MOSI2	P16_2 / HDSLn / HDSL12_MOSI2.
IOPORT_PIN_P163_PFC_00_IRQ10	P16_3 / IRQ / IRQ10.
IOPORT_PIN_P163_PFC_0C_GTETRGSA	P16_3 / POEG / GTETRGSA.
IOPORT_PIN_P163_PFC_12_ESC_LINKACT0	P16_3 / ETHER_ESC / ESC_LINKACT0.
IOPORT_PIN_P163_PFC_14_RXD5_SCL5_MISO5	P16_3 / SCIn / RXD5_SCL5_MISO5.
IOPORT_PIN_P163_PFC_24_DUEI04	P16_3 / ENDATn / DUEI04.
IOPORT_PIN_P163_PFC_25_HDSL13_LINK	P16_3 / HDSLn / HDSL13_LINK.
IOPORT_PIN_P164_PFC_00_IRQ11	P16_4 / IRQ / IRQ11.
IOPORT_PIN_P164_PFC_0C_GTETRGSB	P16_4 / POEG / GTETRGSB.
IOPORT_PIN_P164_PFC_12_ESC_LINKACT1	P16_4 / ETHER_ESC / ESC_LINKACT1.
IOPORT_PIN_P164_PFC_14_TXD5_SDA5_MOSI5	P16_4 / SCIn / TXD5_SDA5_MOSI5.
IOPORT_PIN_P164_PFC_24_TST_OUT04	P16_4 / ENDATn / TST_OUT04.
IOPORT_PIN_P164_PFC_25_HDSL13_SMPL	P16_4 / HDSLn / HDSL13_SMPL.
IOPORT_PIN_P165_PFC_09_GTIOC03_0A	P16_5 / GPT / GTIOC03_0A.
IOPORT_PIN_P165_PFC_24_SI04	P16_5 / ENDATn / SI04.
IOPORT_PIN_P165_PFC_25_HDSL13_CLK1	P16_5 / HDSLn / HDSL13_CLK1.
IOPORT_PIN_P165_PFC_29_SD1_CLK	P16_5 / SDHI / SD1_CLK.
IOPORT_PIN_P166_PFC_09_GTIOC03_0B	P16_6 / GPT / GTIOC03_0B.
IOPORT_PIN_P166_PFC_24_DUEI05	P16_6 / ENDATn / DUEI05.
IOPORT_PIN_P166_PFC_25_HDSL13_SEL1	P16_6 / HDSLn / HDSL13_SEL1.
IOPORT_PIN_P166_PFC_29_SD1_CMD	P16_6 / SDHI / SD1_CMD.
IOPORT_PIN_P167_PFC_09_GTIOC03_1A	P16_7 / GPT / GTIOC03_1A.
IOPORT_PIN_P167_PFC_24_TST_OUT05	P16_7 / ENDATn / TST_OUT05.
IOPORT_PIN_P167_PFC_25_HDSL13_MISO1	P16_7 / HDSLn / HDSL13_MISO1.
IOPORT_PIN_P167_PFC_29_SD1_DATA0	P16_7 / SDHI / SD1_DATA0.
IOPORT_PIN_P170_PFC_00_IRQ12	P17_0 / IRQ / IRQ12.
IOPORT_PIN_P170_PFC_09_GTIOC03_1B	P17_0 / GPT / GTIOC03_1B.
IOPORT_PIN_P170_PFC_24_SI05	P17_0 / ENDATn / SI05.
IOPORT_PIN_P170_PFC_25_HDSL13_MOSI1	P17_0 / HDSLn / HDSL13_MOSI1.
IOPORT_PIN_P170_PFC_29_SD1_DATA1	P17_0 / SDHI / SD1_DATA1.
IOPORT_PIN_P171_PFC_00_IRQ13	P17_1 / IRQ / IRQ13.
IOPORT_PIN_P171_PFC_09_GTIOC03_2A	P17_1 / GPT / GTIOC03_2A.
IOPORT_PIN_P171_PFC_24_DUEI06	P17_1 / ENDATn / DUEI06.
IOPORT_PIN_P171_PFC_25_HDSL13_CLK2	P17_1 / HDSLn / HDSL13_CLK2.
IOPORT_PIN_P171_PFC_29_SD1_DATA2	P17_1 / SDHI / SD1_DATA2.
IOPORT_PIN_P172_PFC_00_IRQ14	P17_2 / IRQ / IRQ14.
IOPORT_PIN_P172_PFC_09_GTIOC03_2B	P17_2 / GPT / GTIOC03_2B.
IOPORT_PIN_P172_PFC_24_TST_OUT06	P17_2 / ENDATn / TST_OUT06.
IOPORT_PIN_P172_PFC_25_HDSL13_SEL2	P17_2 / HDSLn / HDSL13_SEL2.
IOPORT_PIN_P172_PFC_29_SD1_DATA3	P17_2 / SDHI / SD1_DATA3.
IOPORT_PIN_P173_PFC_00_IRQ15	P17_3 / IRQ / IRQ15.
IOPORT_PIN_P173_PFC_0C_GTETRGA	P17_3 / POEG / GTETRGA.
IOPORT_PIN_P173_PFC_24_SI06	P17_3 / ENDATn / SI06.
IOPORT_PIN_P173_PFC_25_HDSL13_MISO2	P17_3 / HDSLn / HDSL13_MISO2.
IOPORT_PIN_P174_PFC_04_A6	P17_4 / BSC / A6.
IOPORT_PIN_P174_PFC_05_DREQ	P17_4 / DMAC / DREQ.
IOPORT_PIN_P174_PFC_0A_GTADSM00_0	P17_4 / GPT / GTADSM00_0.
IOPORT_PIN_P174_PFC_0C_GTETRGB	P17_4 / POEG / GTETRGB.
IOPORT_PIN_P174_PFC_0D_CMTW1_TIC0	P17_4 / CMTW / CMTW1_TIC0.
IOPORT_PIN_P174_PFC_14_DE0	P17_4 / SCIn / DE0.
IOPORT_PIN_P174_PFC_19_CANRX0	P17_4 / CANFDn / CANRX0.
IOPORT_PIN_P174_PFC_24_DUEI07	P17_4 / ENDATn / DUEI07.
IOPORT_PIN_P174_PFC_25_HDSL13_MOSI2	P17_4 / HDSLn / HDSL13_MOSI2.
IOPORT_PIN_P174_PFC_29_SD1_CD	P17_4 / SDHI / SD1_CD.
IOPORT_PIN_P175_PFC_04_A7	P17_5 / BSC / A7.
IOPORT_PIN_P175_PFC_05_DACK	P17_5 / DMAC / DACK.
IOPORT_PIN_P175_PFC_0A_GTADSM00_1	P17_5 / GPT / GTADSM00_1.
IOPORT_PIN_P175_PFC_0C_GTETRGC	P17_5 / POEG / GTETRGC.
IOPORT_PIN_P175_PFC_0D_CMTW1_TOC0	P17_5 / CMTW / CMTW1_TOC0.
IOPORT_PIN_P175_PFC_14_SCK0	P17_5 / SCIn / SCK0.
IOPORT_PIN_P175_PFC_19_CANTX0	P17_5 / CANFDn / CANTX0.
IOPORT_PIN_P175_PFC_24_TST_OUT07	P17_5 / ENDATn / TST_OUT07.
IOPORT_PIN_P175_PFC_25_HDSL14_LINK	P17_5 / HDSLn / HDSL14_LINK.
IOPORT_PIN_P175_PFC_29_SD1_WP	P17_5 / SDHI / SD1_WP.
IOPORT_PIN_P176_PFC_04_WE2	P17_6 / BSC / WE2.
IOPORT_PIN_P176_PFC_0A_GTADSM01_0	P17_6 / GPT / GTADSM01_0.
IOPORT_PIN_P176_PFC_0C_GTETRGD	P17_6 / POEG / GTETRGD.
IOPORT_PIN_P176_PFC_0D_CMTW1_TIC1	P17_6 / CMTW / CMTW1_TIC1.
IOPORT_PIN_P176_PFC_11_ETHSW_PTPOUT0	P17_6 / ETHER_ETHSW / ETHSW_PTPOUT0.
IOPORT_PIN_P176_PFC_12_ESC_SYNC0	P17_6 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P176_PFC_14_RXD0_SCL0_MISO0	P17_6 / SCIn / RXD0_SCL0_MISO0.
IOPORT_PIN_P176_PFC_24_SI07	P17_6 / ENDATn / SI07.
IOPORT_PIN_P176_PFC_25_HDSL14_SMPL	P17_6 / HDSLn / HDSL14_SMPL.
IOPORT_PIN_P176_PFC_28_DISP_DATAG7	P17_6 / LCDC / DISP_DATAG7.
IOPORT_PIN_P176_PFC_29_SD1_PWEN	P17_6 / SDHI / SD1_PWEN.
IOPORT_PIN_P177_PFC_04_WE3_AH	P17_7 / BSC / WE3_AH.
IOPORT_PIN_P177_PFC_0A_GTADSM01_1	P17_7 / GPT / GTADSM01_1.
IOPORT_PIN_P177_PFC_0D_CMTW1_TOC1	P17_7 / CMTW / CMTW1_TOC1.
IOPORT_PIN_P177_PFC_11_ETHSW_PTPOUT1	P17_7 / ETHER_ETHSW / ETHSW_PTPOUT1.
IOPORT_PIN_P177_PFC_12_ESC_SYNC1	P17_7 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P177_PFC_14_TXD0_SDA0_MOSI0	P17_7 / SCIn / TXD0_SDA0_MOSI0.
IOPORT_PIN_P177_PFC_24_DUEI08	P17_7 / ENDATn / DUEI08.
IOPORT_PIN_P177_PFC_25_HDSL14_CLK1	P17_7 / HDSLn / HDSL14_CLK1.
IOPORT_PIN_P177_PFC_28_DISP_DATAB0	P17_7 / LCDC / DISP_DATAB0.
IOPORT_PIN_P177_PFC_29_SD1_IOVS	P17_7 / SDHI / SD1_IOVS.
IOPORT_PIN_P180_PFC_00_IRQ7	P18_0 / IRQ / IRQ7.
IOPORT_PIN_P180_PFC_04_A8	P18_0 / BSC / A8.
IOPORT_PIN_P180_PFC_05_TEND	P18_0 / DMAC / TEND.
IOPORT_PIN_P180_PFC_0A_GTADSM02_0	P18_0 / GPT / GTADSM02_0.
IOPORT_PIN_P180_PFC_12_ESC_LEDRUN	P18_0 / ETHER_ESC / ESC_LEDRUN.
IOPORT_PIN_P180_PFC_14_SS0_CTS0_RTS0	P18_0 / SCIn / SS0_CTS0_RTS0.
IOPORT_PIN_P180_PFC_19_CANRXDP0	P18_0 / CANFDn / CANRXDP0.
IOPORT_PIN_P180_PFC_24_TST_OUT08	P18_0 / ENDATn / TST_OUT08.
IOPORT_PIN_P180_PFC_25_HDSL14_SEL1	P18_0 / HDSLn / HDSL14_SEL1.
IOPORT_PIN_P180_PFC_28_DISP_DATAB1	P18_0 / LCDC / DISP_DATAB1.
IOPORT_PIN_P180_PFC_29_SD1_PWEN	P18_0 / SDHI / SD1_PWEN.
IOPORT_PIN_P181_PFC_00_IRQ15	P18_1 / IRQ / IRQ15.
IOPORT_PIN_P181_PFC_04_A9	P18_1 / BSC / A9.
IOPORT_PIN_P181_PFC_0A_GTADSM02_1	P18_1 / GPT / GTADSM02_1.
IOPORT_PIN_P181_PFC_0B_GTIOC07_3A	P18_1 / GPT / GTIOC07_3A.
IOPORT_PIN_P181_PFC_12_ESC_LEDERR	P18_1 / ETHER_ESC / ESC_LEDERR.
IOPORT_PIN_P181_PFC_14_CTS0	P18_1 / SCIn / CTS0.
IOPORT_PIN_P181_PFC_19_CANTXDP0	P18_1 / CANFDn / CANTXDP0.
IOPORT_PIN_P181_PFC_24_SI08	P18_1 / ENDATn / SI08.
IOPORT_PIN_P181_PFC_25_HDSL14_MISO1	P18_1 / HDSLn / HDSL14_MISO1.
IOPORT_PIN_P181_PFC_28_DISP_DATAB2	P18_1 / LCDC / DISP_DATAB2.
IOPORT_PIN_P181_PFC_29_SD1_IOVS	P18_1 / SDHI / SD1_IOVS.
IOPORT_PIN_P182_PFC_00_SEI	P18_2 / IRQ / SEI.
IOPORT_PIN_P182_PFC_04_A10	P18_2 / BSC / A10.
IOPORT_PIN_P182_PFC_0A_GTADSM03_0	P18_2 / GPT / GTADSM03_0.
IOPORT_PIN_P182_PFC_0B_GTIOC07_3B	P18_2 / GPT / GTIOC07_3B.
IOPORT_PIN_P182_PFC_0F_ETH1_CRS	P18_2 / ETHER_ETHn / ETH1_CRS.
IOPORT_PIN_P182_PFC_10_GMAC1_MDC	P18_2 / ETHER_GMACn / GMAC1_MDC.
IOPORT_PIN_P182_PFC_14_SCK1	P18_2 / SCIn / SCK1.
IOPORT_PIN_P182_PFC_19_CANRX0	P18_2 / CANFDn / CANRX0.
IOPORT_PIN_P182_PFC_1D_MCLK10	P18_2 / DSMIFn / MCLK10.
IOPORT_PIN_P182_PFC_25_HDSL14_MOSI1	P18_2 / HDSLn / HDSL14_MOSI1.
IOPORT_PIN_P182_PFC_28_DISP_DATAB3	P18_2 / LCDC / DISP_DATAB3.
IOPORT_PIN_P182_PFC_29_SD1_PWEN	P18_2 / SDHI / SD1_PWEN.
IOPORT_PIN_P183_PFC_00_IRQ0	P18_3 / IRQ / IRQ0.
IOPORT_PIN_P183_PFC_04_A11	P18_3 / BSC / A11.
IOPORT_PIN_P183_PFC_0A_GTADSM03_1	P18_3 / GPT / GTADSM03_1.
IOPORT_PIN_P183_PFC_0E_RTCAT1HZ	P18_3 / RTC / RTCAT1HZ.
IOPORT_PIN_P183_PFC_0F_ETH1_COL	P18_3 / ETHER_ETHn / ETH1_COL.
IOPORT_PIN_P183_PFC_10_GMAC1_MDIO	P18_3 / ETHER_GMACn / GMAC1_MDIO.
IOPORT_PIN_P183_PFC_14_RXD1_SCL1_MISO1	P18_3 / SCIn / RXD1_SCL1_MISO1.
IOPORT_PIN_P183_PFC_19_CANTX0	P18_3 / CANFDn / CANTX0.
IOPORT_PIN_P183_PFC_1D_MDAT10	P18_3 / DSMIFn / MDAT10.
IOPORT_PIN_P183_PFC_25_HDSL14_CLK2	P18_3 / HDSLn / HDSL14_CLK2.
IOPORT_PIN_P183_PFC_28_DISP_DATAB4	P18_3 / LCDC / DISP_DATAB4.
IOPORT_PIN_P183_PFC_29_SD1_IOVS	P18_3 / SDHI / SD1_IOVS.
IOPORT_PIN_P184_PFC_00_IRQ1	P18_4 / IRQ / IRQ1.
IOPORT_PIN_P184_PFC_04_A12	P18_4 / BSC / A12.
IOPORT_PIN_P184_PFC_09_GTIOC07_3A	P18_4 / GPT / GTIOC07_3A.
IOPORT_PIN_P184_PFC_0A_GTADSM04_0	P18_4 / GPT / GTADSM04_0.
IOPORT_PIN_P184_PFC_12_ESC_LEDSTER	P18_4 / ETHER_ESC / ESC_LEDSTER.
IOPORT_PIN_P184_PFC_14_TXD1_SDA1_MOSI1	P18_4 / SCIn / TXD1_SDA1_MOSI1.
IOPORT_PIN_P184_PFC_15_SCKE09	P18_4 / SCIEn / SCKE09.
IOPORT_PIN_P184_PFC_16_SCKE10	P18_4 / SCIEn / SCKE10.
IOPORT_PIN_P184_PFC_19_CANRX1	P18_4 / CANFDn / CANRX1.
IOPORT_PIN_P184_PFC_1D_MCLK11	P18_4 / DSMIFn / MCLK11.
IOPORT_PIN_P184_PFC_22_ENCIFCK13	P18_4 / ENCIFn / ENCIFCK13.
IOPORT_PIN_P184_PFC_23_ENCIFCK14	P18_4 / ENCIFn / ENCIFCK14.
IOPORT_PIN_P184_PFC_25_HDSL14_SEL2	P18_4 / HDSLn / HDSL14_SEL2.
IOPORT_PIN_P184_PFC_28_DISP_DATAB5	P18_4 / LCDC / DISP_DATAB5.
IOPORT_PIN_P185_PFC_00_IRQ2	P18_5 / IRQ / IRQ2.
IOPORT_PIN_P185_PFC_04_A13	P18_5 / BSC / A13.
IOPORT_PIN_P185_PFC_09_GTIOC07_3B	P18_5 / GPT / GTIOC07_3B.
IOPORT_PIN_P185_PFC_0A_GTADSM04_1	P18_5 / GPT / GTADSM04_1.
IOPORT_PIN_P185_PFC_14_SS1_CTS1_RTS1	P18_5 / SCIn / SS1_CTS1_RTS1.
IOPORT_PIN_P185_PFC_15_DEE09	P18_5 / SCIEn / DEE09.
IOPORT_PIN_P185_PFC_16_DEE10	P18_5 / SCIEn / DEE10.
IOPORT_PIN_P185_PFC_19_CANTX1	P18_5 / CANFDn / CANTX1.
IOPORT_PIN_P185_PFC_1D_MDAT11	P18_5 / DSMIFn / MDAT11.
IOPORT_PIN_P185_PFC_22_ENCIFOE13	P18_5 / ENCIFn / ENCIFOE13.
IOPORT_PIN_P185_PFC_23_ENCIFOE14	P18_5 / ENCIFn / ENCIFOE14.
IOPORT_PIN_P185_PFC_25_HDSL14_MISO2	P18_5 / HDSLn / HDSL14_MISO2.
IOPORT_PIN_P185_PFC_28_DISP_DATAB6	P18_5 / LCDC / DISP_DATAB6.
IOPORT_PIN_P186_PFC_00_IRQ3	P18_6 / IRQ / IRQ3.
IOPORT_PIN_P186_PFC_04_A14	P18_6 / BSC / A14.
IOPORT_PIN_P186_PFC_09_GTIOC07_4A	P18_6 / GPT / GTIOC07_4A.
IOPORT_PIN_P186_PFC_0A_GTADSM05_0	P18_6 / GPT / GTADSM05_0.
IOPORT_PIN_P186_PFC_14_CTS1	P18_6 / SCIn / CTS1.
IOPORT_PIN_P186_PFC_15_TXDE09	P18_6 / SCIEn / TXDE09.
IOPORT_PIN_P186_PFC_16_TXDE10	P18_6 / SCIEn / TXDE10.
IOPORT_PIN_P186_PFC_19_CANRXDP1	P18_6 / CANFDn / CANRXDP1.
IOPORT_PIN_P186_PFC_1D_MCLK12	P18_6 / DSMIFn / MCLK12.
IOPORT_PIN_P186_PFC_22_ENCIFDO13	P18_6 / ENCIFn / ENCIFDO13.
IOPORT_PIN_P186_PFC_23_ENCIFDO14	P18_6 / ENCIFn / ENCIFDO14.
IOPORT_PIN_P186_PFC_25_HDSL14_MOSI2	P18_6 / HDSLn / HDSL14_MOSI2.
IOPORT_PIN_P186_PFC_28_DISP_DATAB7	P18_6 / LCDC / DISP_DATAB7.
IOPORT_PIN_P187_PFC_00_IRQ4	P18_7 / IRQ / IRQ4.
IOPORT_PIN_P187_PFC_04_A15	P18_7 / BSC / A15.
IOPORT_PIN_P187_PFC_09_GTIOC07_4B	P18_7 / GPT / GTIOC07_4B.
IOPORT_PIN_P187_PFC_0A_GTADSM05_1	P18_7 / GPT / GTADSM05_1.
IOPORT_PIN_P187_PFC_11_ETHSW_PTPOUT3	P18_7 / ETHER_ETHSW / ETHSW_PTPOUT3.
IOPORT_PIN_P187_PFC_12_ESC_SYNC1	P18_7 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P187_PFC_14_DE1	P18_7 / SCIn / DE1.
IOPORT_PIN_P187_PFC_15_RXDE09	P18_7 / SCIEn / RXDE09.
IOPORT_PIN_P187_PFC_16_RXDE10	P18_7 / SCIEn / RXDE10.
IOPORT_PIN_P187_PFC_19_CANTXDP1	P18_7 / CANFDn / CANTXDP1.
IOPORT_PIN_P187_PFC_1D_MDAT12	P18_7 / DSMIFn / MDAT12.
IOPORT_PIN_P187_PFC_22_ENCIFDI13	P18_7 / ENCIFn / ENCIFDI13.
IOPORT_PIN_P187_PFC_23_ENCIFDI14	P18_7 / ENCIFn / ENCIFDI14.
IOPORT_PIN_P187_PFC_25_HDSL15_LINK	P18_7 / HDSLn / HDSL15_LINK.
IOPORT_PIN_P190_PFC_09_GTIOC07_0A	P19_0 / GPT / GTIOC07_0A.
IOPORT_PIN_P190_PFC_24_DUEI09	P19_0 / ENDATn / DUEI09.
IOPORT_PIN_P190_PFC_25_HDSL15_SMPL	P19_0 / HDSLn / HDSL15_SMPL.
IOPORT_PIN_P191_PFC_09_GTIOC07_0B	P19_1 / GPT / GTIOC07_0B.
IOPORT_PIN_P191_PFC_24_TST_OUT09	P19_1 / ENDATn / TST_OUT09.
IOPORT_PIN_P191_PFC_25_HDSL15_CLK1	P19_1 / HDSLn / HDSL15_CLK1.
IOPORT_PIN_P192_PFC_09_GTIOC07_1A	P19_2 / GPT / GTIOC07_1A.
IOPORT_PIN_P192_PFC_24_SI09	P19_2 / ENDATn / SI09.
IOPORT_PIN_P192_PFC_25_HDSL15_SEL1	P19_2 / HDSLn / HDSL15_SEL1.
IOPORT_PIN_P193_PFC_09_GTIOC07_1B	P19_3 / GPT / GTIOC07_1B.
IOPORT_PIN_P193_PFC_24_DUEI10	P19_3 / ENDATn / DUEI10.
IOPORT_PIN_P193_PFC_25_HDSL15_MISO1	P19_3 / HDSLn / HDSL15_MISO1.
IOPORT_PIN_P194_PFC_09_GTIOC07_2A	P19_4 / GPT / GTIOC07_2A.
IOPORT_PIN_P194_PFC_24_TST_OUT10	P19_4 / ENDATn / TST_OUT10.
IOPORT_PIN_P194_PFC_25_HDSL15_MOSI1	P19_4 / HDSLn / HDSL15_MOSI1.
IOPORT_PIN_P195_PFC_09_GTIOC07_2B	P19_5 / GPT / GTIOC07_2B.
IOPORT_PIN_P195_PFC_24_SI10	P19_5 / ENDATn / SI10.
IOPORT_PIN_P195_PFC_25_HDSL15_CLK2	P19_5 / HDSLn / HDSL15_CLK2.
IOPORT_PIN_P196_PFC_1D_MCLK52	P19_6 / DSMIFn / MCLK52.
IOPORT_PIN_P196_PFC_25_HDSL15_SEL2	P19_6 / HDSLn / HDSL15_SEL2.
IOPORT_PIN_P197_PFC_1D_MDAT52	P19_7 / DSMIFn / MDAT52.
IOPORT_PIN_P197_PFC_25_HDSL15_MISO2	P19_7 / HDSLn / HDSL15_MISO2.
IOPORT_PIN_P200_PFC_0F_ETH0_TXCLK	P20_0 / ETHER_ETHn / ETH0_TXCLK.
IOPORT_PIN_P200_PFC_25_HDSL15_MOSI2	P20_0 / HDSLn / HDSL15_MOSI2.
IOPORT_PIN_P201_PFC_0F_ETH0_TXD0	P20_1 / ETHER_ETHn / ETH0_TXD0.
IOPORT_PIN_P202_PFC_0F_ETH0_TXD1	P20_2 / ETHER_ETHn / ETH0_TXD1.
IOPORT_PIN_P203_PFC_0F_ETH0_TXD2	P20_3 / ETHER_ETHn / ETH0_TXD2.
IOPORT_PIN_P203_PFC_19_CANRX0	P20_3 / CANFDn / CANRX0.
IOPORT_PIN_P204_PFC_0F_ETH0_TXD3	P20_4 / ETHER_ETHn / ETH0_TXD3.
IOPORT_PIN_P204_PFC_19_CANTX0	P20_4 / CANFDn / CANTX0.
IOPORT_PIN_P205_PFC_0F_ETH0_TXEN	P20_5 / ETHER_ETHn / ETH0_TXEN.
IOPORT_PIN_P205_PFC_24_DUEI11	P20_5 / ENDATn / DUEI11.
IOPORT_PIN_P205_PFC_25_HDSL00_LINK	P20_5 / HDSLn / HDSL00_LINK.
IOPORT_PIN_P206_PFC_0F_ETH0_RXCLK	P20_6 / ETHER_ETHn / ETH0_RXCLK.
IOPORT_PIN_P206_PFC_24_TST_OUT11	P20_6 / ENDATn / TST_OUT11.
IOPORT_PIN_P206_PFC_25_HDSL00_SMPL	P20_6 / HDSLn / HDSL00_SMPL.
IOPORT_PIN_P207_PFC_0F_ETH0_RXD0	P20_7 / ETHER_ETHn / ETH0_RXD0.
IOPORT_PIN_P207_PFC_24_SI11	P20_7 / ENDATn / SI11.
IOPORT_PIN_P207_PFC_25_HDSL00_CLK1	P20_7 / HDSLn / HDSL00_CLK1.
IOPORT_PIN_P210_PFC_0F_ETH0_RXD1	P21_0 / ETHER_ETHn / ETH0_RXD1.
IOPORT_PIN_P210_PFC_24_DUEI12	P21_0 / ENDATn / DUEI12.
IOPORT_PIN_P210_PFC_25_HDSL00_SEL1	P21_0 / HDSLn / HDSL00_SEL1.
IOPORT_PIN_P211_PFC_0F_ETH0_RXD2	P21_1 / ETHER_ETHn / ETH0_RXD2.
IOPORT_PIN_P211_PFC_19_CANRXDP0	P21_1 / CANFDn / CANRXDP0.
IOPORT_PIN_P211_PFC_24_TST_OUT12	P21_1 / ENDATn / TST_OUT12.
IOPORT_PIN_P211_PFC_25_HDSL00_MISO1	P21_1 / HDSLn / HDSL00_MISO1.
IOPORT_PIN_P212_PFC_0F_ETH0_RXD3	P21_2 / ETHER_ETHn / ETH0_RXD3.
IOPORT_PIN_P212_PFC_19_CANTXDP0	P21_2 / CANFDn / CANTXDP0.
IOPORT_PIN_P212_PFC_24_SI12	P21_2 / ENDATn / SI12.
IOPORT_PIN_P212_PFC_25_HDSL00_MOSI1	P21_2 / HDSLn / HDSL00_MOSI1.
IOPORT_PIN_P213_PFC_0F_ETH0_RXDV	P21_3 / ETHER_ETHn / ETH0_RXDV.
IOPORT_PIN_P213_PFC_24_DUEI13	P21_3 / ENDATn / DUEI13.
IOPORT_PIN_P213_PFC_25_HDSL00_CLK2	P21_3 / HDSLn / HDSL00_CLK2.
IOPORT_PIN_P214_PFC_10_GMAC0_MDC	P21_4 / ETHER_GMACn / GMAC0_MDC.
IOPORT_PIN_P214_PFC_11_ETHSW_MDC	P21_4 / ETHER_ETHSW / ETHSW_MDC.
IOPORT_PIN_P214_PFC_12_ESC_MDC	P21_4 / ETHER_ESC / ESC_MDC.
IOPORT_PIN_P214_PFC_19_CANRX1	P21_4 / CANFDn / CANRX1.
IOPORT_PIN_P214_PFC_24_TST_OUT13	P21_4 / ENDATn / TST_OUT13.
IOPORT_PIN_P214_PFC_25_HDSL00_SEL2	P21_4 / HDSLn / HDSL00_SEL2.
IOPORT_PIN_P215_PFC_10_GMAC0_MDIO	P21_5 / ETHER_GMACn / GMAC0_MDIO.
IOPORT_PIN_P215_PFC_11_ETHSW_MDIO	P21_5 / ETHER_ETHSW / ETHSW_MDIO.
IOPORT_PIN_P215_PFC_12_ESC_MDIO	P21_5 / ETHER_ESC / ESC_MDIO.
IOPORT_PIN_P215_PFC_19_CANTX1	P21_5 / CANFDn / CANTX1.
IOPORT_PIN_P215_PFC_24_SI13	P21_5 / ENDATn / SI13.
IOPORT_PIN_P215_PFC_25_HDSL00_MISO2	P21_5 / HDSLn / HDSL00_MISO2.
IOPORT_PIN_P216_PFC_11_ETHSW_PHYLINK0	P21_6 / ETHER_ETHSW / ETHSW_PHYLINK0.
IOPORT_PIN_P216_PFC_12_ESC_PHYLINK0	P21_6 / ETHER_ESC / ESC_PHYLINK0.
IOPORT_PIN_P216_PFC_19_CANRXDP1	P21_6 / CANFDn / CANRXDP1.
IOPORT_PIN_P216_PFC_25_HDSL00_MOSI2	P21_6 / HDSLn / HDSL00_MOSI2.
IOPORT_PIN_P217_PFC_02_ETH0_REFCLK	P21_7 / ETHER_ETHn / ETH0_REFCLK.
IOPORT_PIN_P217_PFC_03_RMII0_REFCLK	P21_7 / ETHER_ETHn / RMII0_REFCLK.
IOPORT_PIN_P217_PFC_19_CANTXDP1	P21_7 / CANFDn / CANTXDP1.
IOPORT_PIN_P217_PFC_25_HDSL01_LINK	P21_7 / HDSLn / HDSL01_LINK.
IOPORT_PIN_P220_PFC_00_IRQ11	P22_0 / IRQ / IRQ11.
IOPORT_PIN_P220_PFC_25_HDSL01_SMPL	P22_0 / HDSLn / HDSL01_SMPL.
IOPORT_PIN_P221_PFC_0C_GTETRGA	P22_1 / POEG / GTETRGA.
IOPORT_PIN_P221_PFC_0F_ETH0_TXER	P22_1 / ETHER_ETHn / ETH0_TXER.
IOPORT_PIN_P221_PFC_14_TXD5_SDA5_MOSI5	P22_1 / SCIn / TXD5_SDA5_MOSI5.
IOPORT_PIN_P221_PFC_19_CANTX0	P22_1 / CANFDn / CANTX0.
IOPORT_PIN_P221_PFC_25_HDSL01_CLK1	P22_1 / HDSLn / HDSL01_CLK1.
IOPORT_PIN_P222_PFC_04_A23	P22_2 / BSC / A23.
IOPORT_PIN_P222_PFC_0C_GTETRGB	P22_2 / POEG / GTETRGB.
IOPORT_PIN_P222_PFC_0F_ETH0_RXER	P22_2 / ETHER_ETHn / ETH0_RXER.
IOPORT_PIN_P222_PFC_14_RXD5_SCL5_MISO5	P22_2 / SCIn / RXD5_SCL5_MISO5.
IOPORT_PIN_P222_PFC_19_CANRX0	P22_2 / CANFDn / CANRX0.
IOPORT_PIN_P222_PFC_25_HDSL01_SEL1	P22_2 / HDSLn / HDSL01_SEL1.
IOPORT_PIN_P223_PFC_00_IRQ5	P22_3 / IRQ / IRQ5.
IOPORT_PIN_P223_PFC_04_A22	P22_3 / BSC / A22.
IOPORT_PIN_P223_PFC_0C_GTETRGC	P22_3 / POEG / GTETRGC.
IOPORT_PIN_P223_PFC_0F_ETH0_CRS	P22_3 / ETHER_ETHn / ETH0_CRS.
IOPORT_PIN_P223_PFC_14_SCK5	P22_3 / SCIn / SCK5.
IOPORT_PIN_P223_PFC_19_CANRXDP0	P22_3 / CANFDn / CANRXDP0.
IOPORT_PIN_P223_PFC_24_DUEI14	P22_3 / ENDATn / DUEI14.
IOPORT_PIN_P223_PFC_25_HDSL01_MISO1	P22_3 / HDSLn / HDSL01_MISO1.
IOPORT_PIN_P224_PFC_00_IRQ6	P22_4 / IRQ / IRQ6.
IOPORT_PIN_P224_PFC_04_A21	P22_4 / BSC / A21.
IOPORT_PIN_P224_PFC_0C_GTETRGD	P22_4 / POEG / GTETRGD.
IOPORT_PIN_P224_PFC_0F_ETH0_COL	P22_4 / ETHER_ETHn / ETH0_COL.
IOPORT_PIN_P224_PFC_14_SS5_CTS5_RTS5	P22_4 / SCIn / SS5_CTS5_RTS5.
IOPORT_PIN_P224_PFC_19_CANTXDP0	P22_4 / CANFDn / CANTXDP0.
IOPORT_PIN_P224_PFC_24_TST_OUT14	P22_4 / ENDATn / TST_OUT14.
IOPORT_PIN_P224_PFC_25_HDSL01_MOSI1	P22_4 / HDSLn / HDSL01_MOSI1.
IOPORT_PIN_P225_PFC_00_IRQ7	P22_5 / IRQ / IRQ7.
IOPORT_PIN_P225_PFC_04_A20	P22_5 / BSC / A20.
IOPORT_PIN_P225_PFC_0C_GTETRGSA	P22_5 / POEG / GTETRGSA.
IOPORT_PIN_P225_PFC_10_GMAC0_PTPTRG0	P22_5 / ETHER_GMACn / GMAC0_PTPTRG0.
IOPORT_PIN_P225_PFC_12_ESC_LATCH0	P22_5 / ETHER_ESC / ESC_LATCH0.
IOPORT_PIN_P225_PFC_14_CTS5	P22_5 / SCIn / CTS5.
IOPORT_PIN_P225_PFC_19_CANRX1	P22_5 / CANFDn / CANRX1.
IOPORT_PIN_P225_PFC_24_SI14	P22_5 / ENDATn / SI14.
IOPORT_PIN_P225_PFC_25_HDSL01_CLK2	P22_5 / HDSLn / HDSL01_CLK2.
IOPORT_PIN_P225_PFC_29_SD0_CD	P22_5 / SDHI / SD0_CD.
IOPORT_PIN_P226_PFC_00_IRQ8	P22_6 / IRQ / IRQ8.
IOPORT_PIN_P226_PFC_04_A19	P22_6 / BSC / A19.
IOPORT_PIN_P226_PFC_0C_GTETRGSB	P22_6 / POEG / GTETRGSB.
IOPORT_PIN_P226_PFC_10_GMAC0_PTPTRG1	P22_6 / ETHER_GMACn / GMAC0_PTPTRG1.
IOPORT_PIN_P226_PFC_12_ESC_LATCH1	P22_6 / ETHER_ESC / ESC_LATCH1.
IOPORT_PIN_P226_PFC_14_DE5	P22_6 / SCIn / DE5.
IOPORT_PIN_P226_PFC_19_CANTX1	P22_6 / CANFDn / CANTX1.
IOPORT_PIN_P226_PFC_24_DUEI15	P22_6 / ENDATn / DUEI15.
IOPORT_PIN_P226_PFC_25_HDSL01_SEL2	P22_6 / HDSLn / HDSL01_SEL2.
IOPORT_PIN_P226_PFC_29_SD0_WP	P22_6 / SDHI / SD0_WP.
IOPORT_PIN_P227_PFC_00_IRQ9	P22_7 / IRQ / IRQ9.
IOPORT_PIN_P227_PFC_04_A18	P22_7 / BSC / A18.
IOPORT_PIN_P227_PFC_09_GTIOC06_0A	P22_7 / GPT / GTIOC06_0A.
IOPORT_PIN_P227_PFC_0F_ETH1_CRS	P22_7 / ETHER_ETHn / ETH1_CRS.
IOPORT_PIN_P227_PFC_11_ETHSW_TDMAOUT2	P22_7 / ETHER_ETHSW / ETHSW_TDMAOUT2.
IOPORT_PIN_P227_PFC_12_ESC_LINKACT0	P22_7 / ETHER_ESC / ESC_LINKACT0.
IOPORT_PIN_P227_PFC_19_CANRXDP1	P22_7 / CANFDn / CANRXDP1.
IOPORT_PIN_P227_PFC_24_TST_OUT15	P22_7 / ENDATn / TST_OUT15.
IOPORT_PIN_P227_PFC_25_HDSL01_MISO2	P22_7 / HDSLn / HDSL01_MISO2.
IOPORT_PIN_P230_PFC_00_IRQ10	P23_0 / IRQ / IRQ10.
IOPORT_PIN_P230_PFC_04_A17	P23_0 / BSC / A17.
IOPORT_PIN_P230_PFC_09_GTIOC06_0B	P23_0 / GPT / GTIOC06_0B.
IOPORT_PIN_P230_PFC_0F_ETH1_COL	P23_0 / ETHER_ETHn / ETH1_COL.
IOPORT_PIN_P230_PFC_11_ETHSW_TDMAOUT3	P23_0 / ETHER_ETHSW / ETHSW_TDMAOUT3.
IOPORT_PIN_P230_PFC_12_ESC_LINKACT1	P23_0 / ETHER_ESC / ESC_LINKACT1.
IOPORT_PIN_P230_PFC_19_CANTXDP1	P23_0 / CANFDn / CANTXDP1.
IOPORT_PIN_P230_PFC_24_SI15	P23_0 / ENDATn / SI15.
IOPORT_PIN_P230_PFC_25_HDSL01_MOSI2	P23_0 / HDSLn / HDSL01_MOSI2.
IOPORT_PIN_P231_PFC_09_GTIOC06_1A	P23_1 / GPT / GTIOC06_1A.
IOPORT_PIN_P231_PFC_12_ESC_IRQ	P23_1 / ETHER_ESC / ESC_IRQ.
IOPORT_PIN_P231_PFC_24_DUEI00	P23_1 / ENDATn / DUEI00.
IOPORT_PIN_P231_PFC_25_HDSL02_LINK	P23_1 / HDSLn / HDSL02_LINK.
IOPORT_PIN_P232_PFC_09_GTIOC06_1B	P23_2 / GPT / GTIOC06_1B.
IOPORT_PIN_P232_PFC_12_ESC_RESETOUT_N	P23_2 / ETHER_ESC / ESC_RESETOUT_N.
IOPORT_PIN_P232_PFC_24_TST_OUT00	P23_2 / ENDATn / TST_OUT00.
IOPORT_PIN_P232_PFC_25_HDSL02_SMPL	P23_2 / HDSLn / HDSL02_SMPL.
IOPORT_PIN_P233_PFC_09_GTIOC06_2A	P23_3 / GPT / GTIOC06_2A.
IOPORT_PIN_P233_PFC_12_ESC_I2CCLK	P23_3 / ETHER_ESC / ESC_I2CCLK.
IOPORT_PIN_P233_PFC_17_IIC_SCL0	P23_3 / IICn / IIC_SCL0.
IOPORT_PIN_P233_PFC_24_SI00	P23_3 / ENDATn / SI00.
IOPORT_PIN_P233_PFC_25_HDSL02_CLK1	P23_3 / HDSLn / HDSL02_CLK1.
IOPORT_PIN_P234_PFC_09_GTIOC06_2B	P23_4 / GPT / GTIOC06_2B.
IOPORT_PIN_P234_PFC_12_ESC_I2CDATA	P23_4 / ETHER_ESC / ESC_I2CDATA.
IOPORT_PIN_P234_PFC_17_IIC_SDA0	P23_4 / IICn / IIC_SDA0.
IOPORT_PIN_P234_PFC_24_DUEI01	P23_4 / ENDATn / DUEI01.
IOPORT_PIN_P234_PFC_25_HDSL02_SEL1	P23_4 / HDSLn / HDSL02_SEL1.
IOPORT_PIN_P235_PFC_12_ESC_LINKACT2	P23_5 / ETHER_ESC / ESC_LINKACT2.
IOPORT_PIN_P235_PFC_1D_MCLK60	P23_5 / DSMIFn / MCLK60.
IOPORT_PIN_P235_PFC_24_TST_OUT01	P23_5 / ENDATn / TST_OUT01.
IOPORT_PIN_P235_PFC_25_HDSL02_MISO1	P23_5 / HDSLn / HDSL02_MISO1.
IOPORT_PIN_P236_PFC_11_ETHSW_LPI0	P23_6 / ETHER_ETHSW / ETHSW_LPI0.
IOPORT_PIN_P236_PFC_1D_MDAT60	P23_6 / DSMIFn / MDAT60.
IOPORT_PIN_P236_PFC_24_SI01	P23_6 / ENDATn / SI01.
IOPORT_PIN_P236_PFC_25_HDSL02_MOSI1	P23_6 / HDSLn / HDSL02_MOSI1.
IOPORT_PIN_P237_PFC_11_ETHSW_LPI1	P23_7 / ETHER_ETHSW / ETHSW_LPI1.
IOPORT_PIN_P237_PFC_1D_MCLK61	P23_7 / DSMIFn / MCLK61.
IOPORT_PIN_P237_PFC_24_DUEI02	P23_7 / ENDATn / DUEI02.
IOPORT_PIN_P237_PFC_25_HDSL02_CLK2	P23_7 / HDSLn / HDSL02_CLK2.
IOPORT_PIN_P240_PFC_00_IRQ11	P24_0 / IRQ / IRQ11.
IOPORT_PIN_P240_PFC_11_ETHSW_LPI2	P24_0 / ETHER_ETHSW / ETHSW_LPI2.
IOPORT_PIN_P240_PFC_1D_MDAT61	P24_0 / DSMIFn / MDAT61.
IOPORT_PIN_P240_PFC_24_TST_OUT02	P24_0 / ENDATn / TST_OUT02.
IOPORT_PIN_P240_PFC_25_HDSL02_SEL2	P24_0 / HDSLn / HDSL02_SEL2.
IOPORT_PIN_P241_PFC_00_IRQ12	P24_1 / IRQ / IRQ12.
IOPORT_PIN_P241_PFC_1D_MCLK62	P24_1 / DSMIFn / MCLK62.
IOPORT_PIN_P241_PFC_24_SI02	P24_1 / ENDATn / SI02.
IOPORT_PIN_P241_PFC_25_HDSL02_MISO2	P24_1 / HDSLn / HDSL02_MISO2.
IOPORT_PIN_P242_PFC_00_IRQ13	P24_2 / IRQ / IRQ13.
IOPORT_PIN_P242_PFC_1D_MDAT62	P24_2 / DSMIFn / MDAT62.
IOPORT_PIN_P242_PFC_25_HDSL02_MOSI2	P24_2 / HDSLn / HDSL02_MOSI2.
IOPORT_PIN_P243_PFC_00_IRQ14	P24_3 / IRQ / IRQ14.
IOPORT_PIN_P243_PFC_12_ESC_I2CCLK	P24_3 / ETHER_ESC / ESC_I2CCLK.
IOPORT_PIN_P243_PFC_17_IIC_SCL1	P24_3 / IICn / IIC_SCL1.
IOPORT_PIN_P243_PFC_19_CANRX0	P24_3 / CANFDn / CANRX0.
IOPORT_PIN_P243_PFC_1D_MCLK70	P24_3 / DSMIFn / MCLK70.
IOPORT_PIN_P243_PFC_25_HDSL03_LINK	P24_3 / HDSLn / HDSL03_LINK.
IOPORT_PIN_P244_PFC_00_IRQ15	P24_4 / IRQ / IRQ15.
IOPORT_PIN_P244_PFC_12_ESC_I2CDATA	P24_4 / ETHER_ESC / ESC_I2CDATA.
IOPORT_PIN_P244_PFC_17_IIC_SDA1	P24_4 / IICn / IIC_SDA1.
IOPORT_PIN_P244_PFC_19_CANTX0	P24_4 / CANFDn / CANTX0.
IOPORT_PIN_P244_PFC_1D_MDAT70	P24_4 / DSMIFn / MDAT70.
IOPORT_PIN_P244_PFC_25_HDSL03_SMPL	P24_4 / HDSLn / HDSL03_SMPL.
IOPORT_PIN_P245_PFC_0F_ETH1_TXCLK	P24_5 / ETHER_ETHn / ETH1_TXCLK.
IOPORT_PIN_P245_PFC_25_HDSL03_CLK1	P24_5 / HDSLn / HDSL03_CLK1.
IOPORT_PIN_P246_PFC_0F_ETH1_TXD0	P24_6 / ETHER_ETHn / ETH1_TXD0.
IOPORT_PIN_P247_PFC_0F_ETH1_TXD1	P24_7 / ETHER_ETHn / ETH1_TXD1.
IOPORT_PIN_P250_PFC_0F_ETH1_TXD2	P25_0 / ETHER_ETHn / ETH1_TXD2.
IOPORT_PIN_P250_PFC_19_CANRXDP0	P25_0 / CANFDn / CANRXDP0.
IOPORT_PIN_P251_PFC_0F_ETH1_TXD3	P25_1 / ETHER_ETHn / ETH1_TXD3.
IOPORT_PIN_P251_PFC_19_CANTXDP0	P25_1 / CANFDn / CANTXDP0.
IOPORT_PIN_P252_PFC_0F_ETH1_TXEN	P25_2 / ETHER_ETHn / ETH1_TXEN.
IOPORT_PIN_P253_PFC_0F_ETH1_RXCLK	P25_3 / ETHER_ETHn / ETH1_RXCLK.
IOPORT_PIN_P253_PFC_24_DUEI03	P25_3 / ENDATn / DUEI03.
IOPORT_PIN_P253_PFC_25_HDSL03_SEL1	P25_3 / HDSLn / HDSL03_SEL1.
IOPORT_PIN_P254_PFC_0F_ETH1_RXD0	P25_4 / ETHER_ETHn / ETH1_RXD0.
IOPORT_PIN_P254_PFC_24_TST_OUT03	P25_4 / ENDATn / TST_OUT03.
IOPORT_PIN_P254_PFC_25_HDSL03_MISO1	P25_4 / HDSLn / HDSL03_MISO1.
IOPORT_PIN_P255_PFC_0F_ETH1_RXD1	P25_5 / ETHER_ETHn / ETH1_RXD1.
IOPORT_PIN_P255_PFC_24_SI03	P25_5 / ENDATn / SI03.
IOPORT_PIN_P255_PFC_25_HDSL03_MOSI1	P25_5 / HDSLn / HDSL03_MOSI1.
IOPORT_PIN_P256_PFC_0F_ETH1_RXD2	P25_6 / ETHER_ETHn / ETH1_RXD2.
IOPORT_PIN_P256_PFC_19_CANRX1	P25_6 / CANFDn / CANRX1.
IOPORT_PIN_P256_PFC_24_DUEI04	P25_6 / ENDATn / DUEI04.
IOPORT_PIN_P256_PFC_25_HDSL03_CLK2	P25_6 / HDSLn / HDSL03_CLK2.
IOPORT_PIN_P257_PFC_0F_ETH1_RXD3	P25_7 / ETHER_ETHn / ETH1_RXD3.
IOPORT_PIN_P257_PFC_19_CANTX1	P25_7 / CANFDn / CANTX1.
IOPORT_PIN_P257_PFC_24_TST_OUT04	P25_7 / ENDATn / TST_OUT04.
IOPORT_PIN_P257_PFC_25_HDSL03_SEL2	P25_7 / HDSLn / HDSL03_SEL2.
IOPORT_PIN_P260_PFC_0F_ETH1_RXDV	P26_0 / ETHER_ETHn / ETH1_RXDV.
IOPORT_PIN_P260_PFC_24_SI04	P26_0 / ENDATn / SI04.
IOPORT_PIN_P260_PFC_25_HDSL03_MISO2	P26_0 / HDSLn / HDSL03_MISO2.
IOPORT_PIN_P261_PFC_10_GMAC1_MDC	P26_1 / ETHER_GMACn / GMAC1_MDC.
IOPORT_PIN_P261_PFC_11_ETHSW_MDC	P26_1 / ETHER_ETHSW / ETHSW_MDC.
IOPORT_PIN_P261_PFC_12_ESC_MDC	P26_1 / ETHER_ESC / ESC_MDC.
IOPORT_PIN_P261_PFC_19_CANRXDP1	P26_1 / CANFDn / CANRXDP1.
IOPORT_PIN_P261_PFC_25_HDSL03_MOSI2	P26_1 / HDSLn / HDSL03_MOSI2.
IOPORT_PIN_P262_PFC_10_GMAC1_MDIO	P26_2 / ETHER_GMACn / GMAC1_MDIO.
IOPORT_PIN_P262_PFC_11_ETHSW_MDIO	P26_2 / ETHER_ETHSW / ETHSW_MDIO.
IOPORT_PIN_P262_PFC_12_ESC_MDIO	P26_2 / ETHER_ESC / ESC_MDIO.
IOPORT_PIN_P262_PFC_19_CANTXDP1	P26_2 / CANFDn / CANTXDP1.
IOPORT_PIN_P262_PFC_25_HDSL04_LINK	P26_2 / HDSLn / HDSL04_LINK.
IOPORT_PIN_P263_PFC_11_ETHSW_PHYLINK1	P26_3 / ETHER_ETHSW / ETHSW_PHYLINK1.
IOPORT_PIN_P263_PFC_12_ESC_PHYLINK1	P26_3 / ETHER_ESC / ESC_PHYLINK1.
IOPORT_PIN_P263_PFC_25_HDSL04_SMPL	P26_3 / HDSLn / HDSL04_SMPL.
IOPORT_PIN_P264_PFC_02_ETH1_REFCLK	P26_4 / ETHER_ETHn / ETH1_REFCLK.
IOPORT_PIN_P264_PFC_03_RMII1_REFCLK	P26_4 / ETHER_ETHn / RMII1_REFCLK.
IOPORT_PIN_P265_PFC_00_IRQ12	P26_5 / IRQ / IRQ12.
IOPORT_PIN_P265_PFC_15_SCKE01	P26_5 / SCIEn / SCKE01.
IOPORT_PIN_P265_PFC_19_CANTX0	P26_5 / CANFDn / CANTX0.
IOPORT_PIN_P265_PFC_22_ENCIFCK01	P26_5 / ENCIFn / ENCIFCK01.
IOPORT_PIN_P265_PFC_25_HDSL04_CLK1	P26_5 / HDSLn / HDSL04_CLK1.
IOPORT_PIN_P266_PFC_00_SEI	P26_6 / IRQ / SEI.
IOPORT_PIN_P266_PFC_04_CS2	P26_6 / BSC / CS2.
IOPORT_PIN_P266_PFC_0F_ETH1_TXER	P26_6 / ETHER_ETHn / ETH1_TXER.
IOPORT_PIN_P266_PFC_12_ESC_RESETOUT_N	P26_6 / ETHER_ESC / ESC_RESETOUT_N.
IOPORT_PIN_P266_PFC_15_DEE01	P26_6 / SCIEn / DEE01.
IOPORT_PIN_P266_PFC_19_CANRX0	P26_6 / CANFDn / CANRX0.
IOPORT_PIN_P266_PFC_22_ENCIFOE01	P26_6 / ENCIFn / ENCIFOE01.
IOPORT_PIN_P266_PFC_25_HDSL04_SEL1	P26_6 / HDSLn / HDSL04_SEL1.
IOPORT_PIN_P267_PFC_00_IRQ0	P26_7 / IRQ / IRQ0.
IOPORT_PIN_P267_PFC_04_CS3	P26_7 / BSC / CS3.
IOPORT_PIN_P267_PFC_0F_ETH1_RXER	P26_7 / ETHER_ETHn / ETH1_RXER.
IOPORT_PIN_P267_PFC_12_ESC_LEDSTER	P26_7 / ETHER_ESC / ESC_LEDSTER.
IOPORT_PIN_P267_PFC_15_TXDE01	P26_7 / SCIEn / TXDE01.
IOPORT_PIN_P267_PFC_19_CANRXDP0	P26_7 / CANFDn / CANRXDP0.
IOPORT_PIN_P267_PFC_1A_SPI_SSL01	P26_7 / SPIn / SPI_SSL01.
IOPORT_PIN_P267_PFC_22_ENCIFDO01	P26_7 / ENCIFn / ENCIFDO01.
IOPORT_PIN_P267_PFC_25_HDSL04_MISO1	P26_7 / HDSLn / HDSL04_MISO1.
IOPORT_PIN_P270_PFC_00_IRQ1	P27_0 / IRQ / IRQ1.
IOPORT_PIN_P270_PFC_04_CS5	P27_0 / BSC / CS5.
IOPORT_PIN_P270_PFC_0F_ETH1_CRS	P27_0 / ETHER_ETHn / ETH1_CRS.
IOPORT_PIN_P270_PFC_15_RXDE01	P27_0 / SCIEn / RXDE01.
IOPORT_PIN_P270_PFC_19_CANTXDP0	P27_0 / CANFDn / CANTXDP0.
IOPORT_PIN_P270_PFC_1A_SPI_SSL02	P27_0 / SPIn / SPI_SSL02.
IOPORT_PIN_P270_PFC_20_HSPI_INT	P27_0 / SHOSTIF / HSPI_INT.
IOPORT_PIN_P270_PFC_22_ENCIFDI01	P27_0 / ENCIFn / ENCIFDI01.
IOPORT_PIN_P270_PFC_25_HDSL04_MOSI1	P27_0 / HDSLn / HDSL04_MOSI1.
IOPORT_PIN_P271_PFC_00_IRQ2	P27_1 / IRQ / IRQ2.
IOPORT_PIN_P271_PFC_0A_GTIOC02_0A	P27_1 / GPT / GTIOC02_0A.
IOPORT_PIN_P271_PFC_0F_ETH1_COL	P27_1 / ETHER_ETHn / ETH1_COL.
IOPORT_PIN_P271_PFC_19_CANRX1	P27_1 / CANFDn / CANRX1.
IOPORT_PIN_P271_PFC_1A_SPI_SSL03	P27_1 / SPIn / SPI_SSL03.
IOPORT_PIN_P271_PFC_20_HSPI_CS	P27_1 / SHOSTIF / HSPI_CS.
IOPORT_PIN_P271_PFC_25_HDSL04_CLK2	P27_1 / HDSLn / HDSL04_CLK2.
IOPORT_PIN_P272_PFC_00_IRQ3	P27_2 / IRQ / IRQ3.
IOPORT_PIN_P272_PFC_0A_GTIOC02_0B	P27_2 / GPT / GTIOC02_0B.
IOPORT_PIN_P272_PFC_10_GMAC1_PTPTRG0	P27_2 / ETHER_GMACn / GMAC1_PTPTRG0.
IOPORT_PIN_P272_PFC_12_ESC_LEDERR	P27_2 / ETHER_ESC / ESC_LEDERR.
IOPORT_PIN_P272_PFC_19_CANTX1	P27_2 / CANFDn / CANTX1.
IOPORT_PIN_P272_PFC_1A_SPI_RSPCK0	P27_2 / SPIn / SPI_RSPCK0.
IOPORT_PIN_P272_PFC_20_HSPI_IO0	P27_2 / SHOSTIF / HSPI_IO0.
IOPORT_PIN_P272_PFC_25_HDSL04_SEL2	P27_2 / HDSLn / HDSL04_SEL2.
IOPORT_PIN_P273_PFC_06_MTIOC2A	P27_3 / MTU3 / MTIOC2A.
IOPORT_PIN_P273_PFC_09_GTIOC08_3A	P27_3 / GPT / GTIOC08_3A.
IOPORT_PIN_P273_PFC_0A_GTIOC02_1A	P27_3 / GPT / GTIOC02_1A.
IOPORT_PIN_P273_PFC_10_GMAC1_PTPTRG1	P27_3 / ETHER_GMACn / GMAC1_PTPTRG1.
IOPORT_PIN_P273_PFC_14_SCK0	P27_3 / SCIn / SCK0.
IOPORT_PIN_P273_PFC_15_SCKE10	P27_3 / SCIEn / SCKE10.
IOPORT_PIN_P273_PFC_19_CANRXDP1	P27_3 / CANFDn / CANRXDP1.
IOPORT_PIN_P273_PFC_1A_SPI_MOSI0	P27_3 / SPIn / SPI_MOSI0.
IOPORT_PIN_P273_PFC_20_HSPI_IO1	P27_3 / SHOSTIF / HSPI_IO1.
IOPORT_PIN_P273_PFC_22_ENCIFCK14	P27_3 / ENCIFn / ENCIFCK14.
IOPORT_PIN_P273_PFC_25_HDSL04_MISO2	P27_3 / HDSLn / HDSL04_MISO2.
IOPORT_PIN_P274_PFC_06_MTIOC2B	P27_4 / MTU3 / MTIOC2B.
IOPORT_PIN_P274_PFC_09_GTIOC08_3B	P27_4 / GPT / GTIOC08_3B.
IOPORT_PIN_P274_PFC_0A_GTIOC02_1B	P27_4 / GPT / GTIOC02_1B.
IOPORT_PIN_P274_PFC_14_RXD0_SCL0_MISO0	P27_4 / SCIn / RXD0_SCL0_MISO0.
IOPORT_PIN_P274_PFC_15_DEE10	P27_4 / SCIEn / DEE10.
IOPORT_PIN_P274_PFC_19_CANTXDP1	P27_4 / CANFDn / CANTXDP1.
IOPORT_PIN_P274_PFC_1A_SPI_MISO0	P27_4 / SPIn / SPI_MISO0.
IOPORT_PIN_P274_PFC_20_HSPI_IO2	P27_4 / SHOSTIF / HSPI_IO2.
IOPORT_PIN_P274_PFC_22_ENCIFOE14	P27_4 / ENCIFn / ENCIFOE14.
IOPORT_PIN_P274_PFC_25_HDSL04_MOSI2	P27_4 / HDSLn / HDSL04_MOSI2.
IOPORT_PIN_P275_PFC_06_MTIOC1A	P27_5 / MTU3 / MTIOC1A.
IOPORT_PIN_P275_PFC_09_GTIOC08_4A	P27_5 / GPT / GTIOC08_4A.
IOPORT_PIN_P275_PFC_0A_GTIOC02_2A	P27_5 / GPT / GTIOC02_2A.
IOPORT_PIN_P275_PFC_14_TXD0_SDA0_MOSI0	P27_5 / SCIn / TXD0_SDA0_MOSI0.
IOPORT_PIN_P275_PFC_15_TXDE10	P27_5 / SCIEn / TXDE10.
IOPORT_PIN_P275_PFC_1A_SPI_SSL00	P27_5 / SPIn / SPI_SSL00.
IOPORT_PIN_P275_PFC_20_HSPI_IO3	P27_5 / SHOSTIF / HSPI_IO3.
IOPORT_PIN_P275_PFC_22_ENCIFDO14	P27_5 / ENCIFn / ENCIFDO14.
IOPORT_PIN_P275_PFC_25_HDSL05_LINK	P27_5 / HDSLn / HDSL05_LINK.
IOPORT_PIN_P276_PFC_06_MTIOC1B	P27_6 / MTU3 / MTIOC1B.
IOPORT_PIN_P276_PFC_09_GTIOC08_4B	P27_6 / GPT / GTIOC08_4B.
IOPORT_PIN_P276_PFC_0A_GTIOC02_2B	P27_6 / GPT / GTIOC02_2B.
IOPORT_PIN_P276_PFC_15_RXDE10	P27_6 / SCIEn / RXDE10.
IOPORT_PIN_P276_PFC_20_HSPI_CK	P27_6 / SHOSTIF / HSPI_CK.
IOPORT_PIN_P276_PFC_22_ENCIFDI14	P27_6 / ENCIFn / ENCIFDI14.
IOPORT_PIN_P276_PFC_25_HDSL05_SMPL	P27_6 / HDSLn / HDSL05_SMPL.
IOPORT_PIN_P277_PFC_00_IRQ4	P27_7 / IRQ / IRQ4.
IOPORT_PIN_P277_PFC_09_GTIOC08_0A	P27_7 / GPT / GTIOC08_0A.
IOPORT_PIN_P277_PFC_11_ETHSW_TDMAOUT0	P27_7 / ETHER_ETHSW / ETHSW_TDMAOUT0.
IOPORT_PIN_P277_PFC_1A_SPI_RSPCK1	P27_7 / SPIn / SPI_RSPCK1.
IOPORT_PIN_P277_PFC_24_DUEI05	P27_7 / ENDATn / DUEI05.
IOPORT_PIN_P277_PFC_25_HDSL05_CLK1	P27_7 / HDSLn / HDSL05_CLK1.
IOPORT_PIN_P280_PFC_00_IRQ5	P28_0 / IRQ / IRQ5.
IOPORT_PIN_P280_PFC_09_GTIOC08_0B	P28_0 / GPT / GTIOC08_0B.
IOPORT_PIN_P280_PFC_11_ETHSW_TDMAOUT1	P28_0 / ETHER_ETHSW / ETHSW_TDMAOUT1.
IOPORT_PIN_P280_PFC_1A_SPI_MOSI1	P28_0 / SPIn / SPI_MOSI1.
IOPORT_PIN_P280_PFC_24_TST_OUT05	P28_0 / ENDATn / TST_OUT05.
IOPORT_PIN_P280_PFC_25_HDSL05_SEL1	P28_0 / HDSLn / HDSL05_SEL1.
IOPORT_PIN_P281_PFC_00_IRQ6	P28_1 / IRQ / IRQ6.
IOPORT_PIN_P281_PFC_09_GTIOC08_1A	P28_1 / GPT / GTIOC08_1A.
IOPORT_PIN_P281_PFC_11_ETHSW_TDMAOUT2	P28_1 / ETHER_ETHSW / ETHSW_TDMAOUT2.
IOPORT_PIN_P281_PFC_1A_SPI_MISO1	P28_1 / SPIn / SPI_MISO1.
IOPORT_PIN_P281_PFC_24_SI05	P28_1 / ENDATn / SI05.
IOPORT_PIN_P281_PFC_25_HDSL05_MISO1	P28_1 / HDSLn / HDSL05_MISO1.
IOPORT_PIN_P282_PFC_00_IRQ7	P28_2 / IRQ / IRQ7.
IOPORT_PIN_P282_PFC_09_GTIOC08_1B	P28_2 / GPT / GTIOC08_1B.
IOPORT_PIN_P282_PFC_11_ETHSW_TDMAOUT3	P28_2 / ETHER_ETHSW / ETHSW_TDMAOUT3.
IOPORT_PIN_P282_PFC_1A_SPI_SSL10	P28_2 / SPIn / SPI_SSL10.
IOPORT_PIN_P282_PFC_24_DUEI06	P28_2 / ENDATn / DUEI06.
IOPORT_PIN_P282_PFC_25_HDSL05_MOSI1	P28_2 / HDSLn / HDSL05_MOSI1.
IOPORT_PIN_P283_PFC_09_GTIOC08_2A	P28_3 / GPT / GTIOC08_2A.
IOPORT_PIN_P283_PFC_1A_SPI_SSL11	P28_3 / SPIn / SPI_SSL11.
IOPORT_PIN_P283_PFC_24_TST_OUT06	P28_3 / ENDATn / TST_OUT06.
IOPORT_PIN_P283_PFC_25_HDSL05_CLK2	P28_3 / HDSLn / HDSL05_CLK2.
IOPORT_PIN_P284_PFC_09_GTIOC08_2B	P28_4 / GPT / GTIOC08_2B.
IOPORT_PIN_P284_PFC_1A_SPI_SSL12	P28_4 / SPIn / SPI_SSL12.
IOPORT_PIN_P284_PFC_24_SI06	P28_4 / ENDATn / SI06.
IOPORT_PIN_P284_PFC_25_HDSL05_SEL2	P28_4 / HDSLn / HDSL05_SEL2.
IOPORT_PIN_P285_PFC_15_SCKE08	P28_5 / SCIEn / SCKE08.
IOPORT_PIN_P285_PFC_16_SCKE00	P28_5 / SCIEn / SCKE00.
IOPORT_PIN_P285_PFC_19_CANRX0	P28_5 / CANFDn / CANRX0.
IOPORT_PIN_P285_PFC_1A_SPI_SSL13	P28_5 / SPIn / SPI_SSL13.
IOPORT_PIN_P285_PFC_1D_MCLK71	P28_5 / DSMIFn / MCLK71.
IOPORT_PIN_P285_PFC_22_ENCIFCK08	P28_5 / ENCIFn / ENCIFCK08.
IOPORT_PIN_P285_PFC_23_ENCIFCK00	P28_5 / ENCIFn / ENCIFCK00.
IOPORT_PIN_P285_PFC_25_HDSL05_MISO2	P28_5 / HDSLn / HDSL05_MISO2.
IOPORT_PIN_P286_PFC_15_DEE08	P28_6 / SCIEn / DEE08.
IOPORT_PIN_P286_PFC_16_DEE00	P28_6 / SCIEn / DEE00.
IOPORT_PIN_P286_PFC_19_CANTX0	P28_6 / CANFDn / CANTX0.
IOPORT_PIN_P286_PFC_1D_MDAT71	P28_6 / DSMIFn / MDAT71.
IOPORT_PIN_P286_PFC_22_ENCIFOE08	P28_6 / ENCIFn / ENCIFOE08.
IOPORT_PIN_P286_PFC_23_ENCIFOE00	P28_6 / ENCIFn / ENCIFOE00.
IOPORT_PIN_P286_PFC_25_HDSL05_MOSI2	P28_6 / HDSLn / HDSL05_MOSI2.
IOPORT_PIN_P287_PFC_15_TXDE08	P28_7 / SCIEn / TXDE08.
IOPORT_PIN_P287_PFC_16_TXDE00	P28_7 / SCIEn / TXDE00.
IOPORT_PIN_P287_PFC_19_CANRXDP0	P28_7 / CANFDn / CANRXDP0.
IOPORT_PIN_P287_PFC_1D_MCLK72	P28_7 / DSMIFn / MCLK72.
IOPORT_PIN_P287_PFC_22_ENCIFDO08	P28_7 / ENCIFn / ENCIFDO08.
IOPORT_PIN_P287_PFC_23_ENCIFDO00	P28_7 / ENCIFn / ENCIFDO00.
IOPORT_PIN_P287_PFC_25_HDSL06_LINK	P28_7 / HDSLn / HDSL06_LINK.
IOPORT_PIN_P290_PFC_15_RXDE08	P29_0 / SCIEn / RXDE08.
IOPORT_PIN_P290_PFC_16_RXDE00	P29_0 / SCIEn / RXDE00.
IOPORT_PIN_P290_PFC_19_CANTXDP0	P29_0 / CANFDn / CANTXDP0.
IOPORT_PIN_P290_PFC_1D_MDAT72	P29_0 / DSMIFn / MDAT72.
IOPORT_PIN_P290_PFC_22_ENCIFDI08	P29_0 / ENCIFn / ENCIFDI08.
IOPORT_PIN_P290_PFC_23_ENCIFDI00	P29_0 / ENCIFn / ENCIFDI00.
IOPORT_PIN_P290_PFC_25_HDSL06_SMPL	P29_0 / HDSLn / HDSL06_SMPL.
IOPORT_PIN_P291_PFC_09_GTIOC09_0A	P29_1 / GPT / GTIOC09_0A.
IOPORT_PIN_P291_PFC_0F_ETH2_TXCLK	P29_1 / ETHER_ETHn / ETH2_TXCLK.
IOPORT_PIN_P291_PFC_15_SCKE09	P29_1 / SCIEn / SCKE09.
IOPORT_PIN_P291_PFC_22_ENCIFCK09	P29_1 / ENCIFn / ENCIFCK09.
IOPORT_PIN_P291_PFC_25_HDSL06_CLK1	P29_1 / HDSLn / HDSL06_CLK1.
IOPORT_PIN_P292_PFC_09_GTIOC09_0B	P29_2 / GPT / GTIOC09_0B.
IOPORT_PIN_P292_PFC_0F_ETH2_TXD0	P29_2 / ETHER_ETHn / ETH2_TXD0.
IOPORT_PIN_P292_PFC_15_DEE09	P29_2 / SCIEn / DEE09.
IOPORT_PIN_P292_PFC_22_ENCIFOE09	P29_2 / ENCIFn / ENCIFOE09.
IOPORT_PIN_P292_PFC_25_HDSL06_SEL1	P29_2 / HDSLn / HDSL06_SEL1.
IOPORT_PIN_P293_PFC_09_GTIOC09_1A	P29_3 / GPT / GTIOC09_1A.
IOPORT_PIN_P293_PFC_0F_ETH2_TXD1	P29_3 / ETHER_ETHn / ETH2_TXD1.
IOPORT_PIN_P293_PFC_15_TXDE09	P29_3 / SCIEn / TXDE09.
IOPORT_PIN_P293_PFC_22_ENCIFDO09	P29_3 / ENCIFn / ENCIFDO09.
IOPORT_PIN_P293_PFC_25_HDSL06_MISO1	P29_3 / HDSLn / HDSL06_MISO1.
IOPORT_PIN_P294_PFC_00_IRQ8	P29_4 / IRQ / IRQ8.
IOPORT_PIN_P294_PFC_09_GTIOC09_1B	P29_4 / GPT / GTIOC09_1B.
IOPORT_PIN_P294_PFC_0F_ETH2_TXD2	P29_4 / ETHER_ETHn / ETH2_TXD2.
IOPORT_PIN_P294_PFC_15_RXDE09	P29_4 / SCIEn / RXDE09.
IOPORT_PIN_P294_PFC_1A_SPI_SSL20	P29_4 / SPIn / SPI_SSL20.
IOPORT_PIN_P294_PFC_22_ENCIFDI09	P29_4 / ENCIFn / ENCIFDI09.
IOPORT_PIN_P294_PFC_25_HDSL06_MOSI1	P29_4 / HDSLn / HDSL06_MOSI1.
IOPORT_PIN_P295_PFC_00_IRQ9	P29_5 / IRQ / IRQ9.
IOPORT_PIN_P295_PFC_09_GTIOC09_2A	P29_5 / GPT / GTIOC09_2A.
IOPORT_PIN_P295_PFC_0F_ETH2_TXD3	P29_5 / ETHER_ETHn / ETH2_TXD3.
IOPORT_PIN_P295_PFC_15_SCKE10	P29_5 / SCIEn / SCKE10.
IOPORT_PIN_P295_PFC_1A_SPI_SSL21	P29_5 / SPIn / SPI_SSL21.
IOPORT_PIN_P295_PFC_22_ENCIFCK10	P29_5 / ENCIFn / ENCIFCK10.
IOPORT_PIN_P295_PFC_25_HDSL06_CLK2	P29_5 / HDSLn / HDSL06_CLK2.
IOPORT_PIN_P296_PFC_09_GTIOC09_2B	P29_6 / GPT / GTIOC09_2B.
IOPORT_PIN_P296_PFC_0F_ETH2_TXEN	P29_6 / ETHER_ETHn / ETH2_TXEN.
IOPORT_PIN_P296_PFC_15_DEE10	P29_6 / SCIEn / DEE10.
IOPORT_PIN_P296_PFC_1A_SPI_SSL22	P29_6 / SPIn / SPI_SSL22.
IOPORT_PIN_P296_PFC_22_ENCIFOE10	P29_6 / ENCIFn / ENCIFOE10.
IOPORT_PIN_P296_PFC_25_HDSL06_SEL2	P29_6 / HDSLn / HDSL06_SEL2.
IOPORT_PIN_P297_PFC_09_GTIOC09_3A	P29_7 / GPT / GTIOC09_3A.
IOPORT_PIN_P297_PFC_0F_ETH2_RXCLK	P29_7 / ETHER_ETHn / ETH2_RXCLK.
IOPORT_PIN_P297_PFC_15_TXDE10	P29_7 / SCIEn / TXDE10.
IOPORT_PIN_P297_PFC_1A_SPI_SSL23	P29_7 / SPIn / SPI_SSL23.
IOPORT_PIN_P297_PFC_22_ENCIFDO10	P29_7 / ENCIFn / ENCIFDO10.
IOPORT_PIN_P297_PFC_25_HDSL06_MISO2	P29_7 / HDSLn / HDSL06_MISO2.
IOPORT_PIN_P300_PFC_09_GTIOC09_3B	P30_0 / GPT / GTIOC09_3B.
IOPORT_PIN_P300_PFC_0F_ETH2_RXD0	P30_0 / ETHER_ETHn / ETH2_RXD0.
IOPORT_PIN_P300_PFC_15_RXDE10	P30_0 / SCIEn / RXDE10.
IOPORT_PIN_P300_PFC_22_ENCIFDI10	P30_0 / ENCIFn / ENCIFDI10.
IOPORT_PIN_P300_PFC_25_HDSL06_MOSI2	P30_0 / HDSLn / HDSL06_MOSI2.
IOPORT_PIN_P301_PFC_09_GTIOC09_4A	P30_1 / GPT / GTIOC09_4A.
IOPORT_PIN_P301_PFC_0F_ETH2_RXD1	P30_1 / ETHER_ETHn / ETH2_RXD1.
IOPORT_PIN_P301_PFC_15_SCKE11	P30_1 / SCIEn / SCKE11.
IOPORT_PIN_P301_PFC_22_ENCIFCK11	P30_1 / ENCIFn / ENCIFCK11.
IOPORT_PIN_P301_PFC_25_HDSL07_LINK	P30_1 / HDSLn / HDSL07_LINK.
IOPORT_PIN_P302_PFC_00_IRQ10	P30_2 / IRQ / IRQ10.
IOPORT_PIN_P302_PFC_09_GTIOC09_4B	P30_2 / GPT / GTIOC09_4B.
IOPORT_PIN_P302_PFC_0F_ETH2_RXD2	P30_2 / ETHER_ETHn / ETH2_RXD2.
IOPORT_PIN_P302_PFC_15_DEE11	P30_2 / SCIEn / DEE11.
IOPORT_PIN_P302_PFC_1A_SPI_MOSI2	P30_2 / SPIn / SPI_MOSI2.
IOPORT_PIN_P302_PFC_22_ENCIFOE11	P30_2 / ENCIFn / ENCIFOE11.
IOPORT_PIN_P302_PFC_25_HDSL07_SMPL	P30_2 / HDSLn / HDSL07_SMPL.
IOPORT_PIN_P303_PFC_00_IRQ11	P30_3 / IRQ / IRQ11.
IOPORT_PIN_P303_PFC_09_GTIOC09_5A	P30_3 / GPT / GTIOC09_5A.
IOPORT_PIN_P303_PFC_0F_ETH2_RXD3	P30_3 / ETHER_ETHn / ETH2_RXD3.
IOPORT_PIN_P303_PFC_15_TXDE11	P30_3 / SCIEn / TXDE11.
IOPORT_PIN_P303_PFC_1A_SPI_MISO2	P30_3 / SPIn / SPI_MISO2.
IOPORT_PIN_P303_PFC_22_ENCIFDO11	P30_3 / ENCIFn / ENCIFDO11.
IOPORT_PIN_P303_PFC_25_HDSL07_CLK1	P30_3 / HDSLn / HDSL07_CLK1.
IOPORT_PIN_P304_PFC_09_GTIOC09_5B	P30_4 / GPT / GTIOC09_5B.
IOPORT_PIN_P304_PFC_0F_ETH2_RXDV	P30_4 / ETHER_ETHn / ETH2_RXDV.
IOPORT_PIN_P304_PFC_15_RXDE11	P30_4 / SCIEn / RXDE11.
IOPORT_PIN_P304_PFC_22_ENCIFDI11	P30_4 / ENCIFn / ENCIFDI11.
IOPORT_PIN_P304_PFC_25_HDSL07_SEL1	P30_4 / HDSLn / HDSL07_SEL1.
IOPORT_PIN_P305_PFC_09_GTIOC09_6A	P30_5 / GPT / GTIOC09_6A.
IOPORT_PIN_P305_PFC_10_GMAC2_MDC	P30_5 / ETHER_GMACn / GMAC2_MDC.
IOPORT_PIN_P305_PFC_11_ETHSW_MDC	P30_5 / ETHER_ETHSW / ETHSW_MDC.
IOPORT_PIN_P305_PFC_12_ESC_MDC	P30_5 / ETHER_ESC / ESC_MDC.
IOPORT_PIN_P305_PFC_1A_SPI_RSPCK3	P30_5 / SPIn / SPI_RSPCK3.
IOPORT_PIN_P305_PFC_24_DUEI07	P30_5 / ENDATn / DUEI07.
IOPORT_PIN_P305_PFC_25_HDSL07_MISO1	P30_5 / HDSLn / HDSL07_MISO1.
IOPORT_PIN_P306_PFC_09_GTIOC09_6B	P30_6 / GPT / GTIOC09_6B.
IOPORT_PIN_P306_PFC_10_GMAC2_MDIO	P30_6 / ETHER_GMACn / GMAC2_MDIO.
IOPORT_PIN_P306_PFC_11_ETHSW_MDIO	P30_6 / ETHER_ETHSW / ETHSW_MDIO.
IOPORT_PIN_P306_PFC_12_ESC_MDIO	P30_6 / ETHER_ESC / ESC_MDIO.
IOPORT_PIN_P306_PFC_1A_SPI_MOSI3	P30_6 / SPIn / SPI_MOSI3.
IOPORT_PIN_P306_PFC_24_TST_OUT07	P30_6 / ENDATn / TST_OUT07.
IOPORT_PIN_P306_PFC_25_HDSL07_MOSI1	P30_6 / HDSLn / HDSL07_MOSI1.
IOPORT_PIN_P307_PFC_00_IRQ14	P30_7 / IRQ / IRQ14.
IOPORT_PIN_P307_PFC_11_ETHSW_PHYLINK2	P30_7 / ETHER_ETHSW / ETHSW_PHYLINK2.
IOPORT_PIN_P307_PFC_12_ESC_PHYLINK2	P30_7 / ETHER_ESC / ESC_PHYLINK2.
IOPORT_PIN_P307_PFC_1A_SPI_MISO3	P30_7 / SPIn / SPI_MISO3.
IOPORT_PIN_P307_PFC_1E_MCLK30	P30_7 / DSMIFn / MCLK30.
IOPORT_PIN_P307_PFC_24_SI07	P30_7 / ENDATn / SI07.
IOPORT_PIN_P307_PFC_25_HDSL07_CLK2	P30_7 / HDSLn / HDSL07_CLK2.
IOPORT_PIN_P307_PFC_29_SD1_IOVS	P30_7 / SDHI / SD1_IOVS.
IOPORT_PIN_P310_PFC_02_ETH2_REFCLK	P31_0 / ETHER_ETHn / ETH2_REFCLK.
IOPORT_PIN_P310_PFC_03_RMII2_REFCLK	P31_0 / ETHER_ETHn / RMII2_REFCLK.
IOPORT_PIN_P310_PFC_0C_GTETRGSA	P31_0 / POEG / GTETRGSA.
IOPORT_PIN_P310_PFC_1A_SPI_SSL30	P31_0 / SPIn / SPI_SSL30.
IOPORT_PIN_P310_PFC_25_HDSL07_SEL2	P31_0 / HDSLn / HDSL07_SEL2.
IOPORT_PIN_P311_PFC_00_IRQ13	P31_1 / IRQ / IRQ13.
IOPORT_PIN_P311_PFC_0C_GTETRGSB	P31_1 / POEG / GTETRGSB.
IOPORT_PIN_P311_PFC_0F_ETH2_RXER	P31_1 / ETHER_ETHn / ETH2_RXER.
IOPORT_PIN_P311_PFC_1A_SPI_SSL31	P31_1 / SPIn / SPI_SSL31.
IOPORT_PIN_P311_PFC_25_HDSL07_MISO2	P31_1 / HDSLn / HDSL07_MISO2.
IOPORT_PIN_P312_PFC_08_POE0	P31_2 / POE3 / POE0.
IOPORT_PIN_P312_PFC_0F_ETH2_TXER	P31_2 / ETHER_ETHn / ETH2_TXER.
IOPORT_PIN_P312_PFC_15_SCKE09	P31_2 / SCIEn / SCKE09.
IOPORT_PIN_P312_PFC_1A_SPI_SSL32	P31_2 / SPIn / SPI_SSL32.
IOPORT_PIN_P312_PFC_1D_MCLK80	P31_2 / DSMIFn / MCLK80.
IOPORT_PIN_P312_PFC_1E_MDAT30	P31_2 / DSMIFn / MDAT30.
IOPORT_PIN_P312_PFC_20_HSPI_IO4	P31_2 / SHOSTIF / HSPI_IO4.
IOPORT_PIN_P312_PFC_22_ENCIFCK09	P31_2 / ENCIFn / ENCIFCK09.
IOPORT_PIN_P312_PFC_25_HDSL07_MOSI2	P31_2 / HDSLn / HDSL07_MOSI2.
IOPORT_PIN_P312_PFC_26_POUTA	P31_2 / ENCOUT / POUTA.
IOPORT_PIN_P313_PFC_08_POE4	P31_3 / POE3 / POE4.
IOPORT_PIN_P313_PFC_0F_ETH2_RXER	P31_3 / ETHER_ETHn / ETH2_RXER.
IOPORT_PIN_P313_PFC_11_ETHSW_TDMAOUT1	P31_3 / ETHER_ETHSW / ETHSW_TDMAOUT1.
IOPORT_PIN_P313_PFC_12_ESC_LEDERR	P31_3 / ETHER_ESC / ESC_LEDERR.
IOPORT_PIN_P313_PFC_15_DEE09	P31_3 / SCIEn / DEE09.
IOPORT_PIN_P313_PFC_1A_SPI_SSL33	P31_3 / SPIn / SPI_SSL33.
IOPORT_PIN_P313_PFC_1D_MDAT80	P31_3 / DSMIFn / MDAT80.
IOPORT_PIN_P313_PFC_1E_MCLK31	P31_3 / DSMIFn / MCLK31.
IOPORT_PIN_P313_PFC_20_HSPI_IO5	P31_3 / SHOSTIF / HSPI_IO5.
IOPORT_PIN_P313_PFC_22_ENCIFOE09	P31_3 / ENCIFn / ENCIFOE09.
IOPORT_PIN_P313_PFC_25_HDSL08_LINK	P31_3 / HDSLn / HDSL08_LINK.
IOPORT_PIN_P314_PFC_05_DREQ	P31_4 / DMAC / DREQ.
IOPORT_PIN_P314_PFC_08_POE8	P31_4 / POE3 / POE8.
IOPORT_PIN_P314_PFC_0F_ETH2_CRS	P31_4 / ETHER_ETHn / ETH2_CRS.
IOPORT_PIN_P314_PFC_11_ETHSW_PTPOUT2	P31_4 / ETHER_ETHSW / ETHSW_PTPOUT2.
IOPORT_PIN_P314_PFC_12_ESC_SYNC0	P31_4 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P314_PFC_15_TXDE09	P31_4 / SCIEn / TXDE09.
IOPORT_PIN_P314_PFC_1A_SPI_RSPCK0	P31_4 / SPIn / SPI_RSPCK0.
IOPORT_PIN_P314_PFC_1B_SPI_SSL30	P31_4 / SPIn / SPI_SSL30.
IOPORT_PIN_P314_PFC_1D_MCLK81	P31_4 / DSMIFn / MCLK81.
IOPORT_PIN_P314_PFC_1E_MDAT31	P31_4 / DSMIFn / MDAT31.
IOPORT_PIN_P314_PFC_20_HSPI_IO6	P31_4 / SHOSTIF / HSPI_IO6.
IOPORT_PIN_P314_PFC_22_ENCIFDO09	P31_4 / ENCIFn / ENCIFDO09.
IOPORT_PIN_P314_PFC_25_HDSL08_SMPL	P31_4 / HDSLn / HDSL08_SMPL.
IOPORT_PIN_P314_PFC_26_POUTB	P31_4 / ENCOUT / POUTB.
IOPORT_PIN_P315_PFC_05_DACK	P31_5 / DMAC / DACK.
IOPORT_PIN_P315_PFC_08_POE10	P31_5 / POE3 / POE10.
IOPORT_PIN_P315_PFC_0F_ETH2_COL	P31_5 / ETHER_ETHn / ETH2_COL.
IOPORT_PIN_P315_PFC_11_ETHSW_PTPOUT3	P31_5 / ETHER_ETHSW / ETHSW_PTPOUT3.
IOPORT_PIN_P315_PFC_12_ESC_SYNC1	P31_5 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P315_PFC_15_RXDE09	P31_5 / SCIEn / RXDE09.
IOPORT_PIN_P315_PFC_1A_SPI_MOSI0	P31_5 / SPIn / SPI_MOSI0.
IOPORT_PIN_P315_PFC_1B_SPI_SSL31	P31_5 / SPIn / SPI_SSL31.
IOPORT_PIN_P315_PFC_1D_MDAT81	P31_5 / DSMIFn / MDAT81.
IOPORT_PIN_P315_PFC_1E_MCLK32	P31_5 / DSMIFn / MCLK32.
IOPORT_PIN_P315_PFC_20_HSPI_IO7	P31_5 / SHOSTIF / HSPI_IO7.
IOPORT_PIN_P315_PFC_22_ENCIFDI09	P31_5 / ENCIFn / ENCIFDI09.
IOPORT_PIN_P315_PFC_25_HDSL08_CLK1	P31_5 / HDSLn / HDSL08_CLK1.
IOPORT_PIN_P315_PFC_26_POUTZ	P31_5 / ENCOUT / POUTZ.
IOPORT_PIN_P316_PFC_04_A16	P31_6 / BSC / A16.
IOPORT_PIN_P316_PFC_05_TEND	P31_6 / DMAC / TEND.
IOPORT_PIN_P316_PFC_08_POE11	P31_6 / POE3 / POE11.
IOPORT_PIN_P316_PFC_10_GMAC2_PTPTRG0	P31_6 / ETHER_GMACn / GMAC2_PTPTRG0.
IOPORT_PIN_P316_PFC_11_ETHSW_TDMAOUT0	P31_6 / ETHER_ETHSW / ETHSW_TDMAOUT0.
IOPORT_PIN_P316_PFC_12_ESC_LEDRUN	P31_6 / ETHER_ESC / ESC_LEDRUN.
IOPORT_PIN_P316_PFC_15_SCKE11	P31_6 / SCIEn / SCKE11.
IOPORT_PIN_P316_PFC_16_SCKE01	P31_6 / SCIEn / SCKE01.
IOPORT_PIN_P316_PFC_1A_SPI_MISO0	P31_6 / SPIn / SPI_MISO0.
IOPORT_PIN_P316_PFC_1E_MDAT32	P31_6 / DSMIFn / MDAT32.
IOPORT_PIN_P316_PFC_22_ENCIFCK15	P31_6 / ENCIFn / ENCIFCK15.
IOPORT_PIN_P316_PFC_23_ENCIFCK01	P31_6 / ENCIFn / ENCIFCK01.
IOPORT_PIN_P316_PFC_25_HDSL08_SEL1	P31_6 / HDSLn / HDSL08_SEL1.
IOPORT_PIN_P317_PFC_10_GMAC2_PTPTRG1	P31_7 / ETHER_GMACn / GMAC2_PTPTRG1.
IOPORT_PIN_P317_PFC_15_DEE11	P31_7 / SCIEn / DEE11.
IOPORT_PIN_P317_PFC_16_DEE01	P31_7 / SCIEn / DEE01.
IOPORT_PIN_P317_PFC_1A_SPI_SSL00	P31_7 / SPIn / SPI_SSL00.
IOPORT_PIN_P317_PFC_22_ENCIFOE15	P31_7 / ENCIFn / ENCIFOE15.
IOPORT_PIN_P317_PFC_23_ENCIFOE01	P31_7 / ENCIFn / ENCIFOE01.
IOPORT_PIN_P317_PFC_25_HDSL08_MISO1	P31_7 / HDSLn / HDSL08_MISO1.
IOPORT_PIN_P320_PFC_15_TXDE11	P32_0 / SCIEn / TXDE11.
IOPORT_PIN_P320_PFC_16_TXDE01	P32_0 / SCIEn / TXDE01.
IOPORT_PIN_P320_PFC_1A_SPI_SSL01	P32_0 / SPIn / SPI_SSL01.
IOPORT_PIN_P320_PFC_22_ENCIFDO15	P32_0 / ENCIFn / ENCIFDO15.
IOPORT_PIN_P320_PFC_23_ENCIFDO01	P32_0 / ENCIFn / ENCIFDO01.
IOPORT_PIN_P320_PFC_25_HDSL08_MOSI1	P32_0 / HDSLn / HDSL08_MOSI1.
IOPORT_PIN_P321_PFC_15_RXDE11	P32_1 / SCIEn / RXDE11.
IOPORT_PIN_P321_PFC_16_RXDE01	P32_1 / SCIEn / RXDE01.
IOPORT_PIN_P321_PFC_1A_SPI_SSL02	P32_1 / SPIn / SPI_SSL02.
IOPORT_PIN_P321_PFC_22_ENCIFDI15	P32_1 / ENCIFn / ENCIFDI15.
IOPORT_PIN_P321_PFC_23_ENCIFDI01	P32_1 / ENCIFn / ENCIFDI01.
IOPORT_PIN_P321_PFC_25_HDSL08_CLK2	P32_1 / HDSLn / HDSL08_CLK2.
IOPORT_PIN_P322_PFC_09_GTIOC10_0A	P32_2 / GPT / GTIOC10_0A.
IOPORT_PIN_P322_PFC_0A_GTIOC01_0A	P32_2 / GPT / GTIOC01_0A.
IOPORT_PIN_P322_PFC_15_SCKE10	P32_2 / SCIEn / SCKE10.
IOPORT_PIN_P322_PFC_1A_SPI_SSL03	P32_2 / SPIn / SPI_SSL03.
IOPORT_PIN_P322_PFC_22_ENCIFCK10	P32_2 / ENCIFn / ENCIFCK10.
IOPORT_PIN_P322_PFC_25_HDSL08_SEL2	P32_2 / HDSLn / HDSL08_SEL2.
IOPORT_PIN_P323_PFC_09_GTIOC10_0B	P32_3 / GPT / GTIOC10_0B.
IOPORT_PIN_P323_PFC_0A_GTIOC01_0B	P32_3 / GPT / GTIOC01_0B.
IOPORT_PIN_P323_PFC_15_DEE10	P32_3 / SCIEn / DEE10.
IOPORT_PIN_P323_PFC_1A_SPI_RSPCK1	P32_3 / SPIn / SPI_RSPCK1.
IOPORT_PIN_P323_PFC_22_ENCIFOE10	P32_3 / ENCIFn / ENCIFOE10.
IOPORT_PIN_P323_PFC_25_HDSL08_MISO2	P32_3 / HDSLn / HDSL08_MISO2.
IOPORT_PIN_P324_PFC_09_GTIOC10_1A	P32_4 / GPT / GTIOC10_1A.
IOPORT_PIN_P324_PFC_0A_GTIOC01_1A	P32_4 / GPT / GTIOC01_1A.
IOPORT_PIN_P324_PFC_15_TXDE10	P32_4 / SCIEn / TXDE10.
IOPORT_PIN_P324_PFC_1A_SPI_MOSI1	P32_4 / SPIn / SPI_MOSI1.
IOPORT_PIN_P324_PFC_22_ENCIFDO10	P32_4 / ENCIFn / ENCIFDO10.
IOPORT_PIN_P324_PFC_25_HDSL08_MOSI2	P32_4 / HDSLn / HDSL08_MOSI2.
IOPORT_PIN_P325_PFC_09_GTIOC10_1B	P32_5 / GPT / GTIOC10_1B.
IOPORT_PIN_P325_PFC_0A_GTIOC01_1B	P32_5 / GPT / GTIOC01_1B.
IOPORT_PIN_P325_PFC_15_RXDE10	P32_5 / SCIEn / RXDE10.
IOPORT_PIN_P325_PFC_1A_SPI_MISO1	P32_5 / SPIn / SPI_MISO1.
IOPORT_PIN_P325_PFC_22_ENCIFDI10	P32_5 / ENCIFn / ENCIFDI10.
IOPORT_PIN_P325_PFC_25_HDSL09_LINK	P32_5 / HDSLn / HDSL09_LINK.
IOPORT_PIN_P326_PFC_09_GTIOC10_2A	P32_6 / GPT / GTIOC10_2A.
IOPORT_PIN_P326_PFC_0A_GTIOC01_2A	P32_6 / GPT / GTIOC01_2A.
IOPORT_PIN_P326_PFC_15_SCKE11	P32_6 / SCIEn / SCKE11.
IOPORT_PIN_P326_PFC_1A_SPI_SSL10	P32_6 / SPIn / SPI_SSL10.
IOPORT_PIN_P326_PFC_22_ENCIFCK11	P32_6 / ENCIFn / ENCIFCK11.
IOPORT_PIN_P326_PFC_25_HDSL09_SMPL	P32_6 / HDSLn / HDSL09_SMPL.
IOPORT_PIN_P327_PFC_09_GTIOC10_2B	P32_7 / GPT / GTIOC10_2B.
IOPORT_PIN_P327_PFC_0A_GTIOC01_2B	P32_7 / GPT / GTIOC01_2B.
IOPORT_PIN_P327_PFC_15_DEE11	P32_7 / SCIEn / DEE11.
IOPORT_PIN_P327_PFC_1A_SPI_SSL11	P32_7 / SPIn / SPI_SSL11.
IOPORT_PIN_P327_PFC_22_ENCIFOE11	P32_7 / ENCIFn / ENCIFOE11.
IOPORT_PIN_P327_PFC_25_HDSL09_CLK1	P32_7 / HDSLn / HDSL09_CLK1.
IOPORT_PIN_P330_PFC_09_GTIOC10_3A	P33_0 / GPT / GTIOC10_3A.
IOPORT_PIN_P330_PFC_15_TXDE11	P33_0 / SCIEn / TXDE11.
IOPORT_PIN_P330_PFC_1A_SPI_SSL12	P33_0 / SPIn / SPI_SSL12.
IOPORT_PIN_P330_PFC_1D_MCLK82	P33_0 / DSMIFn / MCLK82.
IOPORT_PIN_P330_PFC_22_ENCIFDO11	P33_0 / ENCIFn / ENCIFDO11.
IOPORT_PIN_P330_PFC_25_HDSL09_SEL1	P33_0 / HDSLn / HDSL09_SEL1.
IOPORT_PIN_P331_PFC_09_GTIOC10_3B	P33_1 / GPT / GTIOC10_3B.
IOPORT_PIN_P331_PFC_15_RXDE11	P33_1 / SCIEn / RXDE11.
IOPORT_PIN_P331_PFC_1A_SPI_SSL13	P33_1 / SPIn / SPI_SSL13.
IOPORT_PIN_P331_PFC_1D_MDAT82	P33_1 / DSMIFn / MDAT82.
IOPORT_PIN_P331_PFC_22_ENCIFDI11	P33_1 / ENCIFn / ENCIFDI11.
IOPORT_PIN_P331_PFC_25_HDSL09_MISO1	P33_1 / HDSLn / HDSL09_MISO1.
IOPORT_PIN_P332_PFC_04_A16	P33_2 / BSC / A16.
IOPORT_PIN_P332_PFC_09_GTADSM00_0	P33_2 / GPT / GTADSM00_0.
IOPORT_PIN_P332_PFC_0F_ETH3_TXCLK	P33_2 / ETHER_ETHn / ETH3_TXCLK.
IOPORT_PIN_P332_PFC_14_SCK1	P33_2 / SCIn / SCK1.
IOPORT_PIN_P332_PFC_15_SCKE01	P33_2 / SCIEn / SCKE01.
IOPORT_PIN_P332_PFC_1A_SPI_RSPCK1	P33_2 / SPIn / SPI_RSPCK1.
IOPORT_PIN_P332_PFC_1B_SPI_SSL30	P33_2 / SPIn / SPI_SSL30.
IOPORT_PIN_P332_PFC_1D_MCLK50	P33_2 / DSMIFn / MCLK50.
IOPORT_PIN_P332_PFC_22_ENCIFCK01	P33_2 / ENCIFn / ENCIFCK01.
IOPORT_PIN_P332_PFC_25_HDSL09_MOSI1	P33_2 / HDSLn / HDSL09_MOSI1.
IOPORT_PIN_P333_PFC_00_IRQ12	P33_3 / IRQ / IRQ12.
IOPORT_PIN_P333_PFC_04_A17	P33_3 / BSC / A17.
IOPORT_PIN_P333_PFC_09_GTADSM00_1	P33_3 / GPT / GTADSM00_1.
IOPORT_PIN_P333_PFC_0F_ETH3_TXD0	P33_3 / ETHER_ETHn / ETH3_TXD0.
IOPORT_PIN_P333_PFC_14_RXD1_SCL1_MISO1	P33_3 / SCIn / RXD1_SCL1_MISO1.
IOPORT_PIN_P333_PFC_15_DEE01	P33_3 / SCIEn / DEE01.
IOPORT_PIN_P333_PFC_1A_SPI_MOSI1	P33_3 / SPIn / SPI_MOSI1.
IOPORT_PIN_P333_PFC_1B_SPI_RSPCK0	P33_3 / SPIn / SPI_RSPCK0.
IOPORT_PIN_P333_PFC_1D_MDAT50	P33_3 / DSMIFn / MDAT50.
IOPORT_PIN_P333_PFC_22_ENCIFOE01	P33_3 / ENCIFn / ENCIFOE01.
IOPORT_PIN_P333_PFC_25_HDSL09_CLK2	P33_3 / HDSLn / HDSL09_CLK2.
IOPORT_PIN_P333_PFC_27_PCIE_RSTOUT0B	P33_3 / PCIE / PCIE_RSTOUT0B.
IOPORT_PIN_P334_PFC_00_IRQ13	P33_4 / IRQ / IRQ13.
IOPORT_PIN_P334_PFC_04_A18	P33_4 / BSC / A18.
IOPORT_PIN_P334_PFC_09_GTADSM01_0	P33_4 / GPT / GTADSM01_0.
IOPORT_PIN_P334_PFC_0F_ETH3_TXD1	P33_4 / ETHER_ETHn / ETH3_TXD1.
IOPORT_PIN_P334_PFC_14_TXD1_SDA1_MOSI1	P33_4 / SCIn / TXD1_SDA1_MOSI1.
IOPORT_PIN_P334_PFC_15_TXDE01	P33_4 / SCIEn / TXDE01.
IOPORT_PIN_P334_PFC_1A_SPI_MISO1	P33_4 / SPIn / SPI_MISO1.
IOPORT_PIN_P334_PFC_1B_SPI_MOSI0	P33_4 / SPIn / SPI_MOSI0.
IOPORT_PIN_P334_PFC_1D_MCLK51	P33_4 / DSMIFn / MCLK51.
IOPORT_PIN_P334_PFC_22_ENCIFDO01	P33_4 / ENCIFn / ENCIFDO01.
IOPORT_PIN_P334_PFC_25_HDSL09_SEL2	P33_4 / HDSLn / HDSL09_SEL2.
IOPORT_PIN_P334_PFC_27_PCIE_RSTOUT1B	P33_4 / PCIE / PCIE_RSTOUT1B.
IOPORT_PIN_P335_PFC_00_IRQ14	P33_5 / IRQ / IRQ14.
IOPORT_PIN_P335_PFC_04_A19	P33_5 / BSC / A19.
IOPORT_PIN_P335_PFC_09_GTADSM01_1	P33_5 / GPT / GTADSM01_1.
IOPORT_PIN_P335_PFC_0F_ETH3_TXD2	P33_5 / ETHER_ETHn / ETH3_TXD2.
IOPORT_PIN_P335_PFC_14_RXD2_SCL2_MISO2	P33_5 / SCIn / RXD2_SCL2_MISO2.
IOPORT_PIN_P335_PFC_15_RXDE01	P33_5 / SCIEn / RXDE01.
IOPORT_PIN_P335_PFC_1A_SPI_SSL10	P33_5 / SPIn / SPI_SSL10.
IOPORT_PIN_P335_PFC_1B_SPI_MISO0	P33_5 / SPIn / SPI_MISO0.
IOPORT_PIN_P335_PFC_1D_MDAT51	P33_5 / DSMIFn / MDAT51.
IOPORT_PIN_P335_PFC_22_ENCIFDI01	P33_5 / ENCIFn / ENCIFDI01.
IOPORT_PIN_P335_PFC_25_HDSL09_MISO2	P33_5 / HDSLn / HDSL09_MISO2.
IOPORT_PIN_P336_PFC_00_IRQ15	P33_6 / IRQ / IRQ15.
IOPORT_PIN_P336_PFC_04_A20	P33_6 / BSC / A20.
IOPORT_PIN_P336_PFC_09_GTADSM02_0	P33_6 / GPT / GTADSM02_0.
IOPORT_PIN_P336_PFC_0F_ETH3_TXD3	P33_6 / ETHER_ETHn / ETH3_TXD3.
IOPORT_PIN_P336_PFC_14_TXD2_SDA2_MOSI2	P33_6 / SCIn / TXD2_SDA2_MOSI2.
IOPORT_PIN_P336_PFC_15_SCKE06	P33_6 / SCIEn / SCKE06.
IOPORT_PIN_P336_PFC_1A_SPI_SSL11	P33_6 / SPIn / SPI_SSL11.
IOPORT_PIN_P336_PFC_1B_SPI_SSL00	P33_6 / SPIn / SPI_SSL00.
IOPORT_PIN_P336_PFC_1D_MCLK52	P33_6 / DSMIFn / MCLK52.
IOPORT_PIN_P336_PFC_22_ENCIFCK06	P33_6 / ENCIFn / ENCIFCK06.
IOPORT_PIN_P336_PFC_25_HDSL09_MOSI2	P33_6 / HDSLn / HDSL09_MOSI2.
IOPORT_PIN_P337_PFC_04_A21	P33_7 / BSC / A21.
IOPORT_PIN_P337_PFC_09_GTADSM02_1	P33_7 / GPT / GTADSM02_1.
IOPORT_PIN_P337_PFC_0F_ETH3_TXEN	P33_7 / ETHER_ETHn / ETH3_TXEN.
IOPORT_PIN_P337_PFC_15_DEE06	P33_7 / SCIEn / DEE06.
IOPORT_PIN_P337_PFC_1A_SPI_RSPCK2	P33_7 / SPIn / SPI_RSPCK2.
IOPORT_PIN_P337_PFC_1D_MDAT52	P33_7 / DSMIFn / MDAT52.
IOPORT_PIN_P337_PFC_22_ENCIFOE06	P33_7 / ENCIFn / ENCIFOE06.
IOPORT_PIN_P337_PFC_25_HDSL10_LINK	P33_7 / HDSLn / HDSL10_LINK.
IOPORT_PIN_P340_PFC_04_A22	P34_0 / BSC / A22.
IOPORT_PIN_P340_PFC_09_GTADSM03_0	P34_0 / GPT / GTADSM03_0.
IOPORT_PIN_P340_PFC_0A_GTIOC03_0A	P34_0 / GPT / GTIOC03_0A.
IOPORT_PIN_P340_PFC_0F_ETH3_RXCLK	P34_0 / ETHER_ETHn / ETH3_RXCLK.
IOPORT_PIN_P340_PFC_15_TXDE06	P34_0 / SCIEn / TXDE06.
IOPORT_PIN_P340_PFC_1A_SPI_MOSI2	P34_0 / SPIn / SPI_MOSI2.
IOPORT_PIN_P340_PFC_22_ENCIFDO06	P34_0 / ENCIFn / ENCIFDO06.
IOPORT_PIN_P340_PFC_25_HDSL10_SMPL	P34_0 / HDSLn / HDSL10_SMPL.
IOPORT_PIN_P341_PFC_04_A23	P34_1 / BSC / A23.
IOPORT_PIN_P341_PFC_09_GTADSM03_1	P34_1 / GPT / GTADSM03_1.
IOPORT_PIN_P341_PFC_0A_GTIOC03_0B	P34_1 / GPT / GTIOC03_0B.
IOPORT_PIN_P341_PFC_0F_ETH3_RXD0	P34_1 / ETHER_ETHn / ETH3_RXD0.
IOPORT_PIN_P341_PFC_15_RXDE06	P34_1 / SCIEn / RXDE06.
IOPORT_PIN_P341_PFC_1A_SPI_MISO2	P34_1 / SPIn / SPI_MISO2.
IOPORT_PIN_P341_PFC_22_ENCIFDI06	P34_1 / ENCIFn / ENCIFDI06.
IOPORT_PIN_P341_PFC_25_HDSL10_CLK1	P34_1 / HDSLn / HDSL10_CLK1.
IOPORT_PIN_P342_PFC_04_A24	P34_2 / BSC / A24.
IOPORT_PIN_P342_PFC_09_GTADSM04_0	P34_2 / GPT / GTADSM04_0.
IOPORT_PIN_P342_PFC_0A_GTIOC03_1A	P34_2 / GPT / GTIOC03_1A.
IOPORT_PIN_P342_PFC_0F_ETH3_RXD1	P34_2 / ETHER_ETHn / ETH3_RXD1.
IOPORT_PIN_P342_PFC_15_SCKE07	P34_2 / SCIEn / SCKE07.
IOPORT_PIN_P342_PFC_1A_SPI_SSL20	P34_2 / SPIn / SPI_SSL20.
IOPORT_PIN_P342_PFC_22_ENCIFCK07	P34_2 / ENCIFn / ENCIFCK07.
IOPORT_PIN_P342_PFC_25_HDSL10_SEL1	P34_2 / HDSLn / HDSL10_SEL1.
IOPORT_PIN_P343_PFC_04_A25	P34_3 / BSC / A25.
IOPORT_PIN_P343_PFC_09_GTADSM04_1	P34_3 / GPT / GTADSM04_1.
IOPORT_PIN_P343_PFC_0A_GTIOC03_1B	P34_3 / GPT / GTIOC03_1B.
IOPORT_PIN_P343_PFC_0F_ETH3_RXD2	P34_3 / ETHER_ETHn / ETH3_RXD2.
IOPORT_PIN_P343_PFC_15_DEE07	P34_3 / SCIEn / DEE07.
IOPORT_PIN_P343_PFC_1A_SPI_SSL21	P34_3 / SPIn / SPI_SSL21.
IOPORT_PIN_P343_PFC_22_ENCIFOE07	P34_3 / ENCIFn / ENCIFOE07.
IOPORT_PIN_P343_PFC_25_HDSL10_MISO1	P34_3 / HDSLn / HDSL10_MISO1.
IOPORT_PIN_P343_PFC_29_SD1_PWEN	P34_3 / SDHI / SD1_PWEN.
IOPORT_PIN_P344_PFC_04_CS2	P34_4 / BSC / CS2.
IOPORT_PIN_P344_PFC_09_GTADSM05_0	P34_4 / GPT / GTADSM05_0.
IOPORT_PIN_P344_PFC_0A_GTIOC03_2A	P34_4 / GPT / GTIOC03_2A.
IOPORT_PIN_P344_PFC_0F_ETH3_RXD3	P34_4 / ETHER_ETHn / ETH3_RXD3.
IOPORT_PIN_P344_PFC_14_RXD3_SCL3_MISO3	P34_4 / SCIn / RXD3_SCL3_MISO3.
IOPORT_PIN_P344_PFC_15_TXDE07	P34_4 / SCIEn / TXDE07.
IOPORT_PIN_P344_PFC_1A_SPI_SSL22	P34_4 / SPIn / SPI_SSL22.
IOPORT_PIN_P344_PFC_1F_ADTRG0	P34_4 / ADCn / ADTRG0.
IOPORT_PIN_P344_PFC_22_ENCIFDO07	P34_4 / ENCIFn / ENCIFDO07.
IOPORT_PIN_P344_PFC_25_HDSL10_MOSI1	P34_4 / HDSLn / HDSL10_MOSI1.
IOPORT_PIN_P344_PFC_29_SD1_IOVS	P34_4 / SDHI / SD1_IOVS.
IOPORT_PIN_P345_PFC_04_CS3	P34_5 / BSC / CS3.
IOPORT_PIN_P345_PFC_09_GTADSM05_1	P34_5 / GPT / GTADSM05_1.
IOPORT_PIN_P345_PFC_0A_GTIOC03_2B	P34_5 / GPT / GTIOC03_2B.
IOPORT_PIN_P345_PFC_0F_ETH3_RXDV	P34_5 / ETHER_ETHn / ETH3_RXDV.
IOPORT_PIN_P345_PFC_12_ESC_I2CCLK	P34_5 / ETHER_ESC / ESC_I2CCLK.
IOPORT_PIN_P345_PFC_14_TXD3_SDA3_MOSI3	P34_5 / SCIn / TXD3_SDA3_MOSI3.
IOPORT_PIN_P345_PFC_15_RXDE07	P34_5 / SCIEn / RXDE07.
IOPORT_PIN_P345_PFC_17_IIC_SCL1	P34_5 / IICn / IIC_SCL1.
IOPORT_PIN_P345_PFC_1A_SPI_SSL23	P34_5 / SPIn / SPI_SSL23.
IOPORT_PIN_P345_PFC_1F_ADTRG1	P34_5 / ADCn / ADTRG1.
IOPORT_PIN_P345_PFC_22_ENCIFDI07	P34_5 / ENCIFn / ENCIFDI07.
IOPORT_PIN_P345_PFC_25_HDSL10_CLK2	P34_5 / HDSLn / HDSL10_CLK2.
IOPORT_PIN_P346_PFC_02_ETH3_REFCLK	P34_6 / ETHER_ETHn / ETH3_REFCLK.
IOPORT_PIN_P346_PFC_03_RMII3_REFCLK	P34_6 / ETHER_ETHn / RMII3_REFCLK.
IOPORT_PIN_P346_PFC_04_CS5	P34_6 / BSC / CS5.
IOPORT_PIN_P346_PFC_0F_ETH1_RXER	P34_6 / ETHER_ETHn / ETH1_RXER.
IOPORT_PIN_P346_PFC_12_ESC_I2CDATA	P34_6 / ETHER_ESC / ESC_I2CDATA.
IOPORT_PIN_P346_PFC_17_IIC_SDA1	P34_6 / IICn / IIC_SDA1.
IOPORT_PIN_P346_PFC_1A_SPI_RSPCK3	P34_6 / SPIn / SPI_RSPCK3.
IOPORT_PIN_P346_PFC_1F_ADTRG2	P34_6 / ADCn / ADTRG2.
IOPORT_PIN_P346_PFC_24_DUEI08	P34_6 / ENDATn / DUEI08.
IOPORT_PIN_P346_PFC_25_HDSL10_SEL2	P34_6 / HDSLn / HDSL10_SEL2.
IOPORT_PIN_P347_PFC_00_IRQ14	P34_7 / IRQ / IRQ14.
IOPORT_PIN_P347_PFC_05_DREQ	P34_7 / DMAC / DREQ.
IOPORT_PIN_P347_PFC_09_GTADSM06_0	P34_7 / GPT / GTADSM06_0.
IOPORT_PIN_P347_PFC_0F_ETH3_TXER	P34_7 / ETHER_ETHn / ETH3_TXER.
IOPORT_PIN_P347_PFC_12_ESC_RESETOUT_N	P34_7 / ETHER_ESC / ESC_RESETOUT_N.
IOPORT_PIN_P347_PFC_1A_SPI_MOSI3	P34_7 / SPIn / SPI_MOSI3.
IOPORT_PIN_P347_PFC_24_TST_OUT08	P34_7 / ENDATn / TST_OUT08.
IOPORT_PIN_P347_PFC_25_HDSL10_MISO2	P34_7 / HDSLn / HDSL10_MISO2.
IOPORT_PIN_P350_PFC_05_DACK	P35_0 / DMAC / DACK.
IOPORT_PIN_P350_PFC_09_GTADSM06_1	P35_0 / GPT / GTADSM06_1.
IOPORT_PIN_P350_PFC_0F_ETH3_RXER	P35_0 / ETHER_ETHn / ETH3_RXER.
IOPORT_PIN_P350_PFC_1A_SPI_MISO3	P35_0 / SPIn / SPI_MISO3.
IOPORT_PIN_P350_PFC_24_SI08	P35_0 / ENDATn / SI08.
IOPORT_PIN_P350_PFC_25_HDSL10_MOSI2	P35_0 / HDSLn / HDSL10_MOSI2.
IOPORT_PIN_P351_PFC_05_TEND	P35_1 / DMAC / TEND.
IOPORT_PIN_P351_PFC_09_GTADSM07_0	P35_1 / GPT / GTADSM07_0.
IOPORT_PIN_P351_PFC_0F_ETH3_CRS	P35_1 / ETHER_ETHn / ETH3_CRS.
IOPORT_PIN_P351_PFC_1A_SPI_SSL30	P35_1 / SPIn / SPI_SSL30.
IOPORT_PIN_P351_PFC_1B_SPI_MISO1	P35_1 / SPIn / SPI_MISO1.
IOPORT_PIN_P351_PFC_1D_MCLK90	P35_1 / DSMIFn / MCLK90.
IOPORT_PIN_P351_PFC_24_DUEI09	P35_1 / ENDATn / DUEI09.
IOPORT_PIN_P351_PFC_25_HDSL11_LINK	P35_1 / HDSLn / HDSL11_LINK.
IOPORT_PIN_P352_PFC_09_GTADSM07_1	P35_2 / GPT / GTADSM07_1.
IOPORT_PIN_P352_PFC_0F_ETH3_COL	P35_2 / ETHER_ETHn / ETH3_COL.
IOPORT_PIN_P352_PFC_1A_SPI_SSL31	P35_2 / SPIn / SPI_SSL31.
IOPORT_PIN_P352_PFC_1B_SPI_SSL10	P35_2 / SPIn / SPI_SSL10.
IOPORT_PIN_P352_PFC_1D_MDAT90	P35_2 / DSMIFn / MDAT90.
IOPORT_PIN_P352_PFC_1F_ADTRG2	P35_2 / ADCn / ADTRG2.
IOPORT_PIN_P352_PFC_24_TST_OUT09	P35_2 / ENDATn / TST_OUT09.
IOPORT_PIN_P352_PFC_25_HDSL11_SMPL	P35_2 / HDSLn / HDSL11_SMPL.
IOPORT_PIN_P353_PFC_09_GTADSM08_0	P35_3 / GPT / GTADSM08_0.
IOPORT_PIN_P353_PFC_1A_SPI_SSL32	P35_3 / SPIn / SPI_SSL32.
IOPORT_PIN_P353_PFC_1B_SPI_MOSI1	P35_3 / SPIn / SPI_MOSI1.
IOPORT_PIN_P353_PFC_1D_MCLK91	P35_3 / DSMIFn / MCLK91.
IOPORT_PIN_P353_PFC_1F_ADTRG0	P35_3 / ADCn / ADTRG0.
IOPORT_PIN_P353_PFC_24_SI09	P35_3 / ENDATn / SI09.
IOPORT_PIN_P353_PFC_25_HDSL11_CLK1	P35_3 / HDSLn / HDSL11_CLK1.
IOPORT_PIN_P354_PFC_09_GTADSM08_1	P35_4 / GPT / GTADSM08_1.
IOPORT_PIN_P354_PFC_1A_SPI_SSL33	P35_4 / SPIn / SPI_SSL33.
IOPORT_PIN_P354_PFC_1B_SPI_SSL11	P35_4 / SPIn / SPI_SSL11.
IOPORT_PIN_P354_PFC_1D_MDAT91	P35_4 / DSMIFn / MDAT91.
IOPORT_PIN_P354_PFC_1F_ADTRG1	P35_4 / ADCn / ADTRG1.
IOPORT_PIN_P354_PFC_24_DUEI10	P35_4 / ENDATn / DUEI10.
IOPORT_PIN_P354_PFC_25_HDSL11_SEL1	P35_4 / HDSLn / HDSL11_SEL1.
IOPORT_PIN_P355_PFC_09_GTADSM09_0	P35_5 / GPT / GTADSM09_0.
IOPORT_PIN_P355_PFC_14_RXD4_SCL4_MISO4	P35_5 / SCIn / RXD4_SCL4_MISO4.
IOPORT_PIN_P355_PFC_1B_SPI_RSPCK1	P35_5 / SPIn / SPI_RSPCK1.
IOPORT_PIN_P355_PFC_1D_MCLK92	P35_5 / DSMIFn / MCLK92.
IOPORT_PIN_P355_PFC_24_TST_OUT10	P35_5 / ENDATn / TST_OUT10.
IOPORT_PIN_P355_PFC_25_HDSL11_MISO1	P35_5 / HDSLn / HDSL11_MISO1.
IOPORT_PIN_P356_PFC_09_GTADSM09_1	P35_6 / GPT / GTADSM09_1.
IOPORT_PIN_P356_PFC_14_TXD4_SDA4_MOSI4	P35_6 / SCIn / TXD4_SDA4_MOSI4.
IOPORT_PIN_P356_PFC_1B_SPI_SSL12	P35_6 / SPIn / SPI_SSL12.
IOPORT_PIN_P356_PFC_1D_MDAT92	P35_6 / DSMIFn / MDAT92.
IOPORT_PIN_P356_PFC_24_SI10	P35_6 / ENDATn / SI10.
IOPORT_PIN_P356_PFC_25_HDSL11_MOSI1	P35_6 / HDSLn / HDSL11_MOSI1.
IOPORT_PERIPHERAL_END	Marks end of enum - used by parameter checking
IOPORT_PIN_P000_PFC_00_ETH2_RXD3	P00_0 / ETHER_ETHn / ETH2_RXD3.
IOPORT_PIN_P000_PFC_02_D15	P00_0 / BSC / D15.
IOPORT_PIN_P000_PFC_03_SCK2	P00_0 / SCIn / SCK2.
IOPORT_PIN_P000_PFC_04_DE2	P00_0 / SCIn / DE2.
IOPORT_PIN_P000_PFC_05_HD15	P00_0 / PHOSTIF / HD15.
IOPORT_PIN_P001_PFC_00_IRQ0	P00_1 / IRQ / IRQ0.
IOPORT_PIN_P001_PFC_01_ETH2_RXDV	P00_1 / ETHER_ETHn / ETH2_RXDV.
IOPORT_PIN_P001_PFC_03_A13	P00_1 / BSC / A13.
IOPORT_PIN_P001_PFC_04_MTIC5U	P00_1 / MTU3n / MTIC5U.
IOPORT_PIN_P001_PFC_05_RXD2_SCL2_MISO2	P00_1 / SCIn / RXD2_SCL2_MISO2.
IOPORT_PIN_P002_PFC_00_ETH2_TXEN	P00_2 / ETHER_ETHn / ETH2_TXEN.
IOPORT_PIN_P002_PFC_02_RD	P00_2 / BSC / RD.
IOPORT_PIN_P002_PFC_03_MTIC5V	P00_2 / MTU3n / MTIC5V.
IOPORT_PIN_P002_PFC_04_TXD2_SDA2_MOSI2	P00_2 / SCIn / TXD2_SDA2_MOSI2.
IOPORT_PIN_P002_PFC_05_USB_OVRCUR	P00_2 / USB_HS / USB_OVRCUR.
IOPORT_PIN_P003_PFC_00_IRQ1	P00_3 / IRQ / IRQ1.
IOPORT_PIN_P003_PFC_01_ETH2_REFCLK	P00_3 / ETHER_ETHn / ETH2_REFCLK.
IOPORT_PIN_P003_PFC_02_RMII2_REFCLK	P00_3 / ETHER_ETHn / RMII2_REFCLK.
IOPORT_PIN_P003_PFC_04_RD_WR	P00_3 / BSC / RD_WR.
IOPORT_PIN_P003_PFC_05_MTIC5W	P00_3 / MTU3n / MTIC5W.
IOPORT_PIN_P003_PFC_06_SS2_CTS2_RTS2	P00_3 / SCIn / SS2_CTS2_RTS2.
IOPORT_PIN_P004_PFC_00_IRQ13	P00_4 / IRQ / IRQ13.
IOPORT_PIN_P004_PFC_01_ETH2_RXER	P00_4 / ETHER_ETHn / ETH2_RXER.
IOPORT_PIN_P004_PFC_03_WAIT	P00_4 / BSC / WAIT.
IOPORT_PIN_P004_PFC_04_MTIOC3A	P00_4 / MTU3n / MTIOC3A.
IOPORT_PIN_P004_PFC_05_GTIOC0A	P00_4 / GPTn / GTIOC0A.
IOPORT_PIN_P004_PFC_06_MCLK0	P00_4 / DSMIFn / MCLK0.
IOPORT_PIN_P004_PFC_07_HWAIT	P00_4 / PHOSTIF / HWAIT.
IOPORT_PIN_P005_PFC_00_ETHSW_PHYLINK2	P00_5 / ETHER_ETHSW / ETHSW_PHYLINK2.
IOPORT_PIN_P005_PFC_02_CS0	P00_5 / BSC / CS0.
IOPORT_PIN_P005_PFC_03_ESC_PHYLINK2	P00_5 / ETHER_ESC / ESC_PHYLINK2.
IOPORT_PIN_P005_PFC_04_MTIOC3C	P00_5 / MTU3n / MTIOC3C.
IOPORT_PIN_P005_PFC_05_GTIOC0B	P00_5 / GPTn / GTIOC0B.
IOPORT_PIN_P005_PFC_06_MDAT0	P00_5 / DSMIFn / MDAT0.
IOPORT_PIN_P005_PFC_07_ETHSW_PHYLINK0	P00_5 / ETHER_ETHSW / ETHSW_PHYLINK0.
IOPORT_PIN_P005_PFC_08_ESC_PHYLINK0	P00_5 / ETHER_ESC / ESC_PHYLINK0.
IOPORT_PIN_P006_PFC_00_ETH2_TXCLK	P00_6 / ETHER_ETHn / ETH2_TXCLK.
IOPORT_PIN_P006_PFC_01_CS5	P00_6 / BSC / CS5.
IOPORT_PIN_P006_PFC_02_MTIOC3B	P00_6 / MTU3n / MTIOC3B.
IOPORT_PIN_P006_PFC_03_GTIOC1A	P00_6 / GPTn / GTIOC1A.
IOPORT_PIN_P007_PFC_00_IRQ13	P00_7 / IRQ / IRQ13.
IOPORT_PIN_P007_PFC_01_RAS	P00_7 / BSC / RAS.
IOPORT_PIN_P007_PFC_02_MTIOC4A	P00_7 / MTU3n / MTIOC4A.
IOPORT_PIN_P007_PFC_03_GTIOC2A	P00_7 / GPTn / GTIOC2A.
IOPORT_PIN_P010_PFC_00_GMAC_MDIO	P01_0 / ETHER_GMAC / GMAC_MDIO.
IOPORT_PIN_P010_PFC_01_ETHSW_MDIO	P01_0 / ETHER_ETHSW / ETHSW_MDIO.
IOPORT_PIN_P010_PFC_02_CAS	P01_0 / BSC / CAS.
IOPORT_PIN_P010_PFC_03_ESC_MDIO	P01_0 / ETHER_ESC / ESC_MDIO.
IOPORT_PIN_P010_PFC_04_MTIOC4C	P01_0 / MTU3n / MTIOC4C.
IOPORT_PIN_P010_PFC_05_GTIOC3A	P01_0 / GPTn / GTIOC3A.
IOPORT_PIN_P010_PFC_06_CTS2	P01_0 / SCIn / CTS2.
IOPORT_PIN_P010_PFC_07_MCLK1	P01_0 / DSMIFn / MCLK1.
IOPORT_PIN_P011_PFC_00_GMAC_MDC	P01_1 / ETHER_GMAC / GMAC_MDC.
IOPORT_PIN_P011_PFC_01_ETHSW_MDC	P01_1 / ETHER_ETHSW / ETHSW_MDC.
IOPORT_PIN_P011_PFC_02_CKE	P01_1 / BSC / CKE.
IOPORT_PIN_P011_PFC_03_ESC_MDC	P01_1 / ETHER_ESC / ESC_MDC.
IOPORT_PIN_P011_PFC_04_MTIOC3D	P01_1 / MTU3n / MTIOC3D.
IOPORT_PIN_P011_PFC_05_GTIOC1B	P01_1 / GPTn / GTIOC1B.
IOPORT_PIN_P011_PFC_06_DE2	P01_1 / SCIn / DE2.
IOPORT_PIN_P011_PFC_07_MDAT1	P01_1 / DSMIFn / MDAT1.
IOPORT_PIN_P012_PFC_00_IRQ2	P01_2 / IRQ / IRQ2.
IOPORT_PIN_P012_PFC_01_ETH2_TXD3	P01_2 / ETHER_ETHn / ETH2_TXD3.
IOPORT_PIN_P012_PFC_02_CS2	P01_2 / BSC / CS2.
IOPORT_PIN_P012_PFC_03_MTIOC4B	P01_2 / MTU3n / MTIOC4B.
IOPORT_PIN_P012_PFC_04_GTIOC2B	P01_2 / GPTn / GTIOC2B.
IOPORT_PIN_P013_PFC_00_ETH2_TXD2	P01_3 / ETHER_ETHn / ETH2_TXD2.
IOPORT_PIN_P013_PFC_01_AH	P01_3 / BSC / AH.
IOPORT_PIN_P013_PFC_02_MTIOC4D	P01_3 / MTU3n / MTIOC4D.
IOPORT_PIN_P013_PFC_03_GTIOC3B	P01_3 / GPTn / GTIOC3B.
IOPORT_PIN_P014_PFC_00_IRQ3	P01_4 / IRQ / IRQ3.
IOPORT_PIN_P014_PFC_01_ETH2_TXD1	P01_4 / ETHER_ETHn / ETH2_TXD1.
IOPORT_PIN_P014_PFC_02_WE1_DQMLU	P01_4 / BSC / WE1_DQMLU.
IOPORT_PIN_P014_PFC_03_POE0	P01_4 / MTU_POE3 / POE0.
IOPORT_PIN_P015_PFC_00_ETH2_TXD0	P01_5 / ETHER_ETHn / ETH2_TXD0.
IOPORT_PIN_P015_PFC_01_WE0_DQMLL	P01_5 / BSC / WE0_DQMLL.
IOPORT_PIN_P016_PFC_00_GMAC_PTPTRG1	P01_6 / ETHER_GMAC / GMAC_PTPTRG1.
IOPORT_PIN_P016_PFC_01_TRACEDATA0	P01_6 / TRACE / TRACEDATA0.
IOPORT_PIN_P016_PFC_02_A20	P01_6 / BSC / A20.
IOPORT_PIN_P016_PFC_03_ESC_LATCH1	P01_6 / ETHER_ESC / ESC_LATCH1.
IOPORT_PIN_P016_PFC_04_ESC_LATCH0	P01_6 / ETHER_ESC / ESC_LATCH0.
IOPORT_PIN_P016_PFC_05_MTIOC1A	P01_6 / MTU3n / MTIOC1A.
IOPORT_PIN_P016_PFC_06_GTIOC9A	P01_6 / GPTn / GTIOC9A.
IOPORT_PIN_P016_PFC_07_CTS1	P01_6 / SCIn / CTS1.
IOPORT_PIN_P016_PFC_08_CANTXDP1	P01_6 / CANFDn / CANTXDP1.
IOPORT_PIN_P016_PFC_0A_HA20	P01_6 / PHOSTIF / HA20.
IOPORT_PIN_P017_PFC_00_ETHSW_LPI1	P01_7 / ETHER_ETHSW / ETHSW_LPI1.
IOPORT_PIN_P017_PFC_01_TRACEDATA1	P01_7 / TRACE / TRACEDATA1.
IOPORT_PIN_P017_PFC_02_A19	P01_7 / BSC / A19.
IOPORT_PIN_P017_PFC_03_MTIOC1B	P01_7 / MTU3n / MTIOC1B.
IOPORT_PIN_P017_PFC_04_GTIOC9B	P01_7 / GPTn / GTIOC9B.
IOPORT_PIN_P017_PFC_05_ADTRG0	P01_7 / ADCn / ADTRG0.
IOPORT_PIN_P017_PFC_06_SCK1	P01_7 / SCIn / SCK1.
IOPORT_PIN_P017_PFC_07_SPI_RSPCK3	P01_7 / SPIn / SPI_RSPCK3.
IOPORT_PIN_P017_PFC_08_CANRX0	P01_7 / CANFDn / CANRX0.
IOPORT_PIN_P017_PFC_0A_HA19	P01_7 / PHOSTIF / HA19.
IOPORT_PIN_P020_PFC_00_IRQ4	P02_0 / IRQ / IRQ4.
IOPORT_PIN_P020_PFC_01_ETHSW_LPI2	P02_0 / ETHER_ETHSW / ETHSW_LPI2.
IOPORT_PIN_P020_PFC_02_TRACEDATA2	P02_0 / TRACE / TRACEDATA2.
IOPORT_PIN_P020_PFC_03_A18	P02_0 / BSC / A18.
IOPORT_PIN_P020_PFC_04_GTADSML0	P02_0 / GPT / GTADSML0.
IOPORT_PIN_P020_PFC_05_RXD1_SCL1_MISO1	P02_0 / SCIn / RXD1_SCL1_MISO1.
IOPORT_PIN_P020_PFC_06_SPI_MISO3	P02_0 / SPIn / SPI_MISO3.
IOPORT_PIN_P020_PFC_07_CANTX1	P02_0 / CANFDn / CANTX1.
IOPORT_PIN_P020_PFC_08_USB_OTGID	P02_0 / USB_HS / USB_OTGID.
IOPORT_PIN_P020_PFC_0A_HA18	P02_0 / PHOSTIF / HA18.
IOPORT_PIN_P021_PFC_00_ETHSW_PTPOUT1	P02_1 / ETHER_ETHSW / ETHSW_PTPOUT1.
IOPORT_PIN_P021_PFC_01_A17	P02_1 / BSC / A17.
IOPORT_PIN_P021_PFC_02_ESC_SYNC1	P02_1 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P021_PFC_03_ESC_SYNC0	P02_1 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P021_PFC_04_DE1	P02_1 / SCIn / DE1.
IOPORT_PIN_P021_PFC_05_HA17	P02_1 / PHOSTIF / HA17.
IOPORT_PIN_P022_PFC_00_IRQ14	P02_2 / IRQ / IRQ14.
IOPORT_PIN_P022_PFC_01_ETHSW_TDMAOUT0	P02_2 / ETHER_ETHSW / ETHSW_TDMAOUT0.
IOPORT_PIN_P022_PFC_02_A16	P02_2 / BSC / A16.
IOPORT_PIN_P022_PFC_03_MTIOC2A	P02_2 / MTU3n / MTIOC2A.
IOPORT_PIN_P022_PFC_04_GTIOC10A	P02_2 / GPTn / GTIOC10A.
IOPORT_PIN_P022_PFC_05_POE10	P02_2 / MTU_POE3 / POE10.
IOPORT_PIN_P022_PFC_06_TXD1_SDA1_MOSI1	P02_2 / SCIn / TXD1_SDA1_MOSI1.
IOPORT_PIN_P022_PFC_07_SPI_MOSI3	P02_2 / SPIn / SPI_MOSI3.
IOPORT_PIN_P022_PFC_08_CANTX0	P02_2 / CANFDn / CANTX0.
IOPORT_PIN_P022_PFC_0A_RTCAT1HZ	P02_2 / RTC / RTCAT1HZ.
IOPORT_PIN_P022_PFC_0B_HA16	P02_2 / PHOSTIF / HA16.
IOPORT_PIN_P023_PFC_00_IRQ15	P02_3 / IRQ / IRQ15.
IOPORT_PIN_P023_PFC_01_ETHSW_TDMAOUT1	P02_3 / ETHER_ETHSW / ETHSW_TDMAOUT1.
IOPORT_PIN_P023_PFC_02_A15	P02_3 / BSC / A15.
IOPORT_PIN_P023_PFC_03_AH	P02_3 / BSC / AH.
IOPORT_PIN_P023_PFC_04_MTIOC2B	P02_3 / MTU3n / MTIOC2B.
IOPORT_PIN_P023_PFC_05_GTIOC10B	P02_3 / GPTn / GTIOC10B.
IOPORT_PIN_P023_PFC_06_POE11	P02_3 / MTU_POE3 / POE11.
IOPORT_PIN_P023_PFC_07_SS1_CTS1_RTS1	P02_3 / SCIn / SS1_CTS1_RTS1.
IOPORT_PIN_P023_PFC_08_SPI_SSL30	P02_3 / SPIn / SPI_SSL30.
IOPORT_PIN_P023_PFC_09_CANRX1	P02_3 / CANFDn / CANRX1.
IOPORT_PIN_P023_PFC_0B_HA15	P02_3 / PHOSTIF / HA15.
IOPORT_PIN_P024_PFC_00_TDO	P02_4 / JTAG/SWD / TDO.
IOPORT_PIN_P024_PFC_01_WE0_DQMLL	P02_4 / BSC / WE0_DQMLL.
IOPORT_PIN_P024_PFC_02_DE1	P02_4 / SCIn / DE1.
IOPORT_PIN_P024_PFC_03_SPI_SSL33	P02_4 / SPIn / SPI_SSL33.
IOPORT_PIN_P025_PFC_00_ETHSW_TDMAOUT3	P02_5 / ETHER_ETHSW / ETHSW_TDMAOUT3.
IOPORT_PIN_P025_PFC_01_TDI	P02_5 / JTAG/SWD / TDI.
IOPORT_PIN_P025_PFC_02_WE1_DQMLU	P02_5 / BSC / WE1_DQMLU.
IOPORT_PIN_P025_PFC_03_SCK5	P02_5 / SCIn / SCK5.
IOPORT_PIN_P025_PFC_04_SPI_SSL31	P02_5 / SPIn / SPI_SSL31.
IOPORT_PIN_P026_PFC_00_TMS_SWDIO	P02_6 / JTAG/SWD / TMS_SWDIO.
IOPORT_PIN_P026_PFC_01_RXD5_SCL5_MISO5	P02_6 / SCIn / RXD5_SCL5_MISO5.
IOPORT_PIN_P027_PFC_00_TCK_SWCLK	P02_7 / JTAG/SWD / TCK_SWCLK.
IOPORT_PIN_P027_PFC_01_TXD5_SDA5_MOSI5	P02_7 / SCIn / TXD5_SDA5_MOSI5.
IOPORT_PIN_P030_PFC_00_IRQ14	P03_0 / IRQ / IRQ14.
IOPORT_PIN_P030_PFC_01_TRACEDATA3	P03_0 / TRACE / TRACEDATA3.
IOPORT_PIN_P030_PFC_02_A14	P03_0 / BSC / A14.
IOPORT_PIN_P030_PFC_03_CS5	P03_0 / BSC / CS5.
IOPORT_PIN_P030_PFC_04_GTADSML1	P03_0 / GPT / GTADSML1.
IOPORT_PIN_P030_PFC_05_SCK2	P03_0 / SCIn / SCK2.
IOPORT_PIN_P030_PFC_06_SPI_SSL32	P03_0 / SPIn / SPI_SSL32.
IOPORT_PIN_P030_PFC_07_CANTXDP1	P03_0 / CANFDn / CANTXDP1.
IOPORT_PIN_P030_PFC_09_HA14	P03_0 / PHOSTIF / HA14.
IOPORT_PIN_P035_PFC_00_IRQ5	P03_5 / IRQ / IRQ5.
IOPORT_PIN_P035_PFC_01_ETH2_CRS	P03_5 / ETHER_ETHn / ETH2_CRS.
IOPORT_PIN_P035_PFC_02_A12	P03_5 / BSC / A12.
IOPORT_PIN_P035_PFC_03_MTIOC3A	P03_5 / MTU3n / MTIOC3A.
IOPORT_PIN_P035_PFC_04_GTIOC4A	P03_5 / GPTn / GTIOC4A.
IOPORT_PIN_P035_PFC_05_RXD2_SCL2_MISO2	P03_5 / SCIn / RXD2_SCL2_MISO2.
IOPORT_PIN_P035_PFC_06_MCLK2	P03_5 / DSMIFn / MCLK2.
IOPORT_PIN_P035_PFC_07_HA12	P03_5 / PHOSTIF / HA12.
IOPORT_PIN_P036_PFC_00_IRQ8	P03_6 / IRQ / IRQ8.
IOPORT_PIN_P036_PFC_01_ETH2_COL	P03_6 / ETHER_ETHn / ETH2_COL.
IOPORT_PIN_P036_PFC_02_TRACEDATA4	P03_6 / TRACE / TRACEDATA4.
IOPORT_PIN_P036_PFC_03_A11	P03_6 / BSC / A11.
IOPORT_PIN_P036_PFC_04_MTIOC3B	P03_6 / MTU3n / MTIOC3B.
IOPORT_PIN_P036_PFC_05_GTIOC4B	P03_6 / GPTn / GTIOC4B.
IOPORT_PIN_P036_PFC_06_TXD2_SDA2_MOSI2	P03_6 / SCIn / TXD2_SDA2_MOSI2.
IOPORT_PIN_P036_PFC_07_SPI_SSL13	P03_6 / SPIn / SPI_SSL13.
IOPORT_PIN_P036_PFC_08_MDAT2	P03_6 / DSMIFn / MDAT2.
IOPORT_PIN_P036_PFC_09_HA11	P03_6 / PHOSTIF / HA11.
IOPORT_PIN_P037_PFC_00_IRQ9	P03_7 / IRQ / IRQ9.
IOPORT_PIN_P037_PFC_01_ETH2_TXER	P03_7 / ETHER_ETHn / ETH2_TXER.
IOPORT_PIN_P037_PFC_02_TRACEDATA5	P03_7 / TRACE / TRACEDATA5.
IOPORT_PIN_P037_PFC_03_A10	P03_7 / BSC / A10.
IOPORT_PIN_P037_PFC_04_MTIOC3C	P03_7 / MTU3n / MTIOC3C.
IOPORT_PIN_P037_PFC_05_GTIOC5A	P03_7 / GPTn / GTIOC5A.
IOPORT_PIN_P037_PFC_06_SCK3	P03_7 / SCIn / SCK3.
IOPORT_PIN_P037_PFC_07_HA10	P03_7 / PHOSTIF / HA10.
IOPORT_PIN_P040_PFC_00_TRACEDATA6	P04_0 / TRACE / TRACEDATA6.
IOPORT_PIN_P040_PFC_01_A9	P04_0 / BSC / A9.
IOPORT_PIN_P040_PFC_02_MTIOC3D	P04_0 / MTU3n / MTIOC3D.
IOPORT_PIN_P040_PFC_03_GTIOC5B	P04_0 / GPTn / GTIOC5B.
IOPORT_PIN_P040_PFC_04_RXD3_SCL3_MISO3	P04_0 / SCIn / RXD3_SCL3_MISO3.
IOPORT_PIN_P040_PFC_05_HA9	P04_0 / PHOSTIF / HA9.
IOPORT_PIN_P041_PFC_00_CKIO	P04_1 / BSC / CKIO.
IOPORT_PIN_P041_PFC_01_TXD3_SDA3_MOSI3	P04_1 / SCIn / TXD3_SDA3_MOSI3.
IOPORT_PIN_P041_PFC_02_SPI_MOSI0	P04_1 / SPIn / SPI_MOSI0.
IOPORT_PIN_P041_PFC_03_IIC_SDA2	P04_1 / IICn / IIC_SDA2.
IOPORT_PIN_P041_PFC_04_HCKIO	P04_1 / PHOSTIF / HCKIO.
IOPORT_PIN_P044_PFC_00_IRQ10	P04_4 / IRQ / IRQ10.
IOPORT_PIN_P044_PFC_01_TRACEDATA7	P04_4 / TRACE / TRACEDATA7.
IOPORT_PIN_P044_PFC_02_A8	P04_4 / BSC / A8.
IOPORT_PIN_P044_PFC_03_GTADSMP0	P04_4 / GPT / GTADSMP0.
IOPORT_PIN_P044_PFC_04_POE10	P04_4 / MTU_POE3 / POE10.
IOPORT_PIN_P044_PFC_05_CTS3	P04_4 / SCIn / CTS3.
IOPORT_PIN_P044_PFC_06_SPI_RSPCK1	P04_4 / SPIn / SPI_RSPCK1.
IOPORT_PIN_P044_PFC_08_HA8	P04_4 / PHOSTIF / HA8.
IOPORT_PIN_P045_PFC_00_A7	P04_5 / BSC / A7.
IOPORT_PIN_P045_PFC_01_DE3	P04_5 / SCIn / DE3.
IOPORT_PIN_P045_PFC_02_ETHSW_PTPOUT0	P04_5 / ETHER_ETHSW / ETHSW_PTPOUT0.
IOPORT_PIN_P045_PFC_03_ESC_SYNC0	P04_5 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P045_PFC_04_ESC_SYNC1	P04_5 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P045_PFC_05_HA7	P04_5 / PHOSTIF / HA7.
IOPORT_PIN_P046_PFC_00_ETH1_TXER	P04_6 / ETHER_ETHn / ETH1_TXER.
IOPORT_PIN_P046_PFC_01_A6	P04_6 / BSC / A6.
IOPORT_PIN_P046_PFC_02_DACK	P04_6 / DMAC / DACK.
IOPORT_PIN_P046_PFC_03_RTCAT1HZ	P04_6 / RTC / RTCAT1HZ.
IOPORT_PIN_P046_PFC_04_HA6	P04_6 / PHOSTIF / HA6.
IOPORT_PIN_P047_PFC_00_ETH0_TXER	P04_7 / ETHER_ETHn / ETH0_TXER.
IOPORT_PIN_P047_PFC_01_A5	P04_7 / BSC / A5.
IOPORT_PIN_P047_PFC_02_SPI_SSL21	P04_7 / SPIn / SPI_SSL21.
IOPORT_PIN_P047_PFC_03_ETH2_TXER	P04_7 / ETHER_ETHn / ETH2_TXER.
IOPORT_PIN_P047_PFC_04_HA5	P04_7 / PHOSTIF / HA5.
IOPORT_PIN_P050_PFC_00_IRQ12	P05_0 / IRQ / IRQ12.
IOPORT_PIN_P050_PFC_01_ETH1_CRS	P05_0 / ETHER_ETHn / ETH1_CRS.
IOPORT_PIN_P050_PFC_02_A4	P05_0 / BSC / A4.
IOPORT_PIN_P050_PFC_03_MTIOC4A	P05_0 / MTU3n / MTIOC4A.
IOPORT_PIN_P050_PFC_04_GTIOC6A	P05_0 / GPTn / GTIOC6A.
IOPORT_PIN_P050_PFC_05_CMTW0_TOC0	P05_0 / CMTWn / CMTW0_TOC0.
IOPORT_PIN_P050_PFC_06_SS5_CTS5_RTS5	P05_0 / SCIn / SS5_CTS5_RTS5.
IOPORT_PIN_P050_PFC_07_CANTXDP0	P05_0 / CANFDn / CANTXDP0.
IOPORT_PIN_P050_PFC_08_USB_VBUSEN	P05_0 / USB_HS / USB_VBUSEN.
IOPORT_PIN_P050_PFC_09_MCLK3	P05_0 / DSMIFn / MCLK3.
IOPORT_PIN_P050_PFC_0B_HA4	P05_0 / PHOSTIF / HA4.
IOPORT_PIN_P051_PFC_00_IRQ13	P05_1 / IRQ / IRQ13.
IOPORT_PIN_P051_PFC_01_ETH1_COL	P05_1 / ETHER_ETHn / ETH1_COL.
IOPORT_PIN_P051_PFC_02_A3	P05_1 / BSC / A3.
IOPORT_PIN_P051_PFC_03_MTIOC4B	P05_1 / MTU3n / MTIOC4B.
IOPORT_PIN_P051_PFC_04_GTIOC6B	P05_1 / GPTn / GTIOC6B.
IOPORT_PIN_P051_PFC_05_CMTW0_TIC1	P05_1 / CMTWn / CMTW0_TIC1.
IOPORT_PIN_P051_PFC_06_CTS5	P05_1 / SCIn / CTS5.
IOPORT_PIN_P051_PFC_07_CANRXDP0	P05_1 / CANFDn / CANRXDP0.
IOPORT_PIN_P051_PFC_08_USB_EXICEN	P05_1 / USB_HS / USB_EXICEN.
IOPORT_PIN_P051_PFC_09_MDAT3	P05_1 / DSMIFn / MDAT3.
IOPORT_PIN_P051_PFC_0B_HA3	P05_1 / PHOSTIF / HA3.
IOPORT_PIN_P052_PFC_00_IRQ14	P05_2 / IRQ / IRQ14.
IOPORT_PIN_P052_PFC_01_ETH0_CRS	P05_2 / ETHER_ETHn / ETH0_CRS.
IOPORT_PIN_P052_PFC_02_A2	P05_2 / BSC / A2.
IOPORT_PIN_P052_PFC_03_MTIOC4C	P05_2 / MTU3n / MTIOC4C.
IOPORT_PIN_P052_PFC_04_GTETRGSA	P05_2 / GPT_POEG / GTETRGSA.
IOPORT_PIN_P052_PFC_05_GTIOC7A	P05_2 / GPTn / GTIOC7A.
IOPORT_PIN_P052_PFC_06_CMTW0_TOC0	P05_2 / CMTWn / CMTW0_TOC0.
IOPORT_PIN_P052_PFC_07_DE5	P05_2 / SCIn / DE5.
IOPORT_PIN_P052_PFC_08_IIC_SCL1	P05_2 / IICn / IIC_SCL1.
IOPORT_PIN_P052_PFC_09_CANRX0	P05_2 / CANFDn / CANRX0.
IOPORT_PIN_P052_PFC_0A_DREQ	P05_2 / DMAC / DREQ.
IOPORT_PIN_P052_PFC_0B_USB_VBUSEN	P05_2 / USB_HS / USB_VBUSEN.
IOPORT_PIN_P052_PFC_0D_HA2	P05_2 / PHOSTIF / HA2.
IOPORT_PIN_P053_PFC_00_IRQ15	P05_3 / IRQ / IRQ15.
IOPORT_PIN_P053_PFC_01_ETH0_COL	P05_3 / ETHER_ETHn / ETH0_COL.
IOPORT_PIN_P053_PFC_02_A1	P05_3 / BSC / A1.
IOPORT_PIN_P053_PFC_03_MTIOC4D	P05_3 / MTU3n / MTIOC4D.
IOPORT_PIN_P053_PFC_04_GTETRGSB	P05_3 / GPT_POEG / GTETRGSB.
IOPORT_PIN_P053_PFC_05_GTIOC7B	P05_3 / GPTn / GTIOC7B.
IOPORT_PIN_P053_PFC_06_POE11	P05_3 / MTU_POE3 / POE11.
IOPORT_PIN_P053_PFC_07_CMTW0_TIC0	P05_3 / CMTWn / CMTW0_TIC0.
IOPORT_PIN_P053_PFC_08_SCK4	P05_3 / SCIn / SCK4.
IOPORT_PIN_P053_PFC_09_IIC_SDA1	P05_3 / IICn / IIC_SDA1.
IOPORT_PIN_P053_PFC_0A_CANTX0	P05_3 / CANFDn / CANTX0.
IOPORT_PIN_P053_PFC_0B_USB_EXICEN	P05_3 / USB_HS / USB_EXICEN.
IOPORT_PIN_P053_PFC_0D_HA1	P05_3 / PHOSTIF / HA1.
IOPORT_PIN_P054_PFC_00_IRQ12	P05_4 / IRQ / IRQ12.
IOPORT_PIN_P054_PFC_01_ETHSW_LPI0	P05_4 / ETHER_ETHSW / ETHSW_LPI0.
IOPORT_PIN_P054_PFC_02_A0	P05_4 / BSC / A0.
IOPORT_PIN_P054_PFC_03_GTIOC14A	P05_4 / GPTn / GTIOC14A.
IOPORT_PIN_P054_PFC_04_RXD4_SCL4_MISO4	P05_4 / SCIn / RXD4_SCL4_MISO4.
IOPORT_PIN_P054_PFC_05_SPI_SSL00	P05_4 / SPIn / SPI_SSL00.
IOPORT_PIN_P054_PFC_06_CANTXDP0	P05_4 / CANFDn / CANTXDP0.
IOPORT_PIN_P054_PFC_07_DACK	P05_4 / DMAC / DACK.
IOPORT_PIN_P054_PFC_08_USB_OVRCUR	P05_4 / USB_HS / USB_OVRCUR.
IOPORT_PIN_P054_PFC_0A_HA0	P05_4 / PHOSTIF / HA0.
IOPORT_PIN_P055_PFC_00_ETHSW_PHYLINK1	P05_5 / ETHER_ETHSW / ETHSW_PHYLINK1.
IOPORT_PIN_P055_PFC_02_ESC_PHYLINK1	P05_5 / ETHER_ESC / ESC_PHYLINK1.
IOPORT_PIN_P055_PFC_03_GTIOC14B	P05_5 / GPTn / GTIOC14B.
IOPORT_PIN_P055_PFC_04_CMTW0_TOC1	P05_5 / CMTWn / CMTW0_TOC1.
IOPORT_PIN_P055_PFC_05_SPI_RSPCK2	P05_5 / SPIn / SPI_RSPCK2.
IOPORT_PIN_P056_PFC_00_IRQ12	P05_6 / IRQ / IRQ12.
IOPORT_PIN_P056_PFC_01_ETH1_RXER	P05_6 / ETHER_ETHn / ETH1_RXER.
IOPORT_PIN_P056_PFC_03_GTIOC15A	P05_6 / GPTn / GTIOC15A.
IOPORT_PIN_P056_PFC_04_CMTW1_TIC0	P05_6 / CMTWn / CMTW1_TIC0.
IOPORT_PIN_P056_PFC_05_SPI_SSL22	P05_6 / SPIn / SPI_SSL22.
IOPORT_PIN_P057_PFC_00_ETH1_TXD2	P05_7 / ETHER_ETHn / ETH1_TXD2.
IOPORT_PIN_P057_PFC_02_GTIOC15B	P05_7 / GPTn / GTIOC15B.
IOPORT_PIN_P057_PFC_03_CMTW1_TOC1	P05_7 / CMTWn / CMTW1_TOC1.
IOPORT_PIN_P057_PFC_04_TXD4_SDA4_MOSI4	P05_7 / SCIn / TXD4_SDA4_MOSI4.
IOPORT_PIN_P057_PFC_05_SPI_SSL23	P05_7 / SPIn / SPI_SSL23.
IOPORT_PIN_P060_PFC_00_ETH1_TXD3	P06_0 / ETHER_ETHn / ETH1_TXD3.
IOPORT_PIN_P060_PFC_02_GTIOC16A	P06_0 / GPTn / GTIOC16A.
IOPORT_PIN_P060_PFC_03_CMTW1_TOC0	P06_0 / CMTWn / CMTW1_TOC0.
IOPORT_PIN_P060_PFC_04_SS4_CTS4_RTS4	P06_0 / SCIn / SS4_CTS4_RTS4.
IOPORT_PIN_P060_PFC_05_SPI_SSL23	P06_0 / SPIn / SPI_SSL23.
IOPORT_PIN_P060_PFC_06_CANRX1	P06_0 / CANFDn / CANRX1.
IOPORT_PIN_P061_PFC_00_ETH1_REFCLK	P06_1 / ETHER_ETHn / ETH1_REFCLK.
IOPORT_PIN_P061_PFC_01_RMII1_REFCLK	P06_1 / ETHER_ETHn / RMII1_REFCLK.
IOPORT_PIN_P061_PFC_03_GTIOC16B	P06_1 / GPTn / GTIOC16B.
IOPORT_PIN_P061_PFC_04_CTS4	P06_1 / SCIn / CTS4.
IOPORT_PIN_P061_PFC_05_SPI_SSL22	P06_1 / SPIn / SPI_SSL22.
IOPORT_PIN_P061_PFC_06_CANTX1	P06_1 / CANFDn / CANTX1.
IOPORT_PIN_P062_PFC_00_ETH1_TXD1	P06_2 / ETHER_ETHn / ETH1_TXD1.
IOPORT_PIN_P062_PFC_02_GTIOC17A	P06_2 / GPTn / GTIOC17A.
IOPORT_PIN_P062_PFC_03_CANRXDP1	P06_2 / CANFDn / CANRXDP1.
IOPORT_PIN_P063_PFC_00_ETH1_TXD0	P06_3 / ETHER_ETHn / ETH1_TXD0.
IOPORT_PIN_P063_PFC_02_GTIOC17B	P06_3 / GPTn / GTIOC17B.
IOPORT_PIN_P063_PFC_03_CMTW1_TIC1	P06_3 / CMTWn / CMTW1_TIC1.
IOPORT_PIN_P063_PFC_04_DE4	P06_3 / SCIn / DE4.
IOPORT_PIN_P063_PFC_05_SPI_MISO1	P06_3 / SPIn / SPI_MISO1.
IOPORT_PIN_P063_PFC_06_CANTXDP1	P06_3 / CANFDn / CANTXDP1.
IOPORT_PIN_P064_PFC_00_ETH1_TXCLK	P06_4 / ETHER_ETHn / ETH1_TXCLK.
IOPORT_PIN_P064_PFC_02_GTIOC11A	P06_4 / GPTn / GTIOC11A.
IOPORT_PIN_P064_PFC_03_SPI_MOSI1	P06_4 / SPIn / SPI_MOSI1.
IOPORT_PIN_P065_PFC_00_ETH1_TXEN	P06_5 / ETHER_ETHn / ETH1_TXEN.
IOPORT_PIN_P065_PFC_02_GTIOC11B	P06_5 / GPTn / GTIOC11B.
IOPORT_PIN_P066_PFC_00_ETH1_RXD0	P06_6 / ETHER_ETHn / ETH1_RXD0.
IOPORT_PIN_P066_PFC_02_GTIOC12A	P06_6 / GPTn / GTIOC12A.
IOPORT_PIN_P066_PFC_03_SPI_SSL10	P06_6 / SPIn / SPI_SSL10.
IOPORT_PIN_P067_PFC_00_ETH1_RXD1	P06_7 / ETHER_ETHn / ETH1_RXD1.
IOPORT_PIN_P067_PFC_02_GTIOC12B	P06_7 / GPTn / GTIOC12B.
IOPORT_PIN_P067_PFC_03_SPI_SSL11	P06_7 / SPIn / SPI_SSL11.
IOPORT_PIN_P070_PFC_00_ETH1_RXD2	P07_0 / ETHER_ETHn / ETH1_RXD2.
IOPORT_PIN_P070_PFC_02_GTIOC13A	P07_0 / GPTn / GTIOC13A.
IOPORT_PIN_P071_PFC_00_ETH1_RXD3	P07_1 / ETHER_ETHn / ETH1_RXD3.
IOPORT_PIN_P071_PFC_02_GTIOC13B	P07_1 / GPTn / GTIOC13B.
IOPORT_PIN_P072_PFC_00_ETH1_RXDV	P07_2 / ETHER_ETHn / ETH1_RXDV.
IOPORT_PIN_P073_PFC_00_ETH1_RXCLK	P07_3 / ETHER_ETHn / ETH1_RXCLK.
IOPORT_PIN_P074_PFC_00_IRQ1	P07_4 / IRQ / IRQ1.
IOPORT_PIN_P074_PFC_01_ADTRG0	P07_4 / ADCn / ADTRG0.
IOPORT_PIN_P074_PFC_02_USB_VBUSIN	P07_4 / USB_HS / USB_VBUSIN.
IOPORT_PIN_P084_PFC_00_ETH0_RXD3	P08_4 / ETHER_ETHn / ETH0_RXD3.
IOPORT_PIN_P084_PFC_02_MTIOC6A	P08_4 / MTU3n / MTIOC6A.
IOPORT_PIN_P085_PFC_00_ETH0_RXDV	P08_5 / ETHER_ETHn / ETH0_RXDV.
IOPORT_PIN_P085_PFC_01_MTIOC6B	P08_5 / MTU3n / MTIOC6B.
IOPORT_PIN_P086_PFC_00_ETH0_RXCLK	P08_6 / ETHER_ETHn / ETH0_RXCLK.
IOPORT_PIN_P086_PFC_01_MTIOC6C	P08_6 / MTU3n / MTIOC6C.
IOPORT_PIN_P087_PFC_00_GMAC_MDC	P08_7 / ETHER_GMAC / GMAC_MDC.
IOPORT_PIN_P087_PFC_01_ETHSW_MDC	P08_7 / ETHER_ETHSW / ETHSW_MDC.
IOPORT_PIN_P087_PFC_03_ESC_MDC	P08_7 / ETHER_ESC / ESC_MDC.
IOPORT_PIN_P087_PFC_04_MTIOC6D	P08_7 / MTU3n / MTIOC6D.
IOPORT_PIN_P090_PFC_00_GMAC_MDIO	P09_0 / ETHER_GMAC / GMAC_MDIO.
IOPORT_PIN_P090_PFC_01_ETHSW_MDIO	P09_0 / ETHER_ETHSW / ETHSW_MDIO.
IOPORT_PIN_P090_PFC_03_ESC_MDIO	P09_0 / ETHER_ESC / ESC_MDIO.
IOPORT_PIN_P090_PFC_04_MTIOC7A	P09_0 / MTU3n / MTIOC7A.
IOPORT_PIN_P091_PFC_00_ETH0_REFCLK	P09_1 / ETHER_ETHn / ETH0_REFCLK.
IOPORT_PIN_P091_PFC_01_RMII0_REFCLK	P09_1 / ETHER_ETHn / RMII0_REFCLK.
IOPORT_PIN_P091_PFC_02_MTIOC7B	P09_1 / MTU3n / MTIOC7B.
IOPORT_PIN_P092_PFC_00_IRQ0	P09_2 / IRQ / IRQ0.
IOPORT_PIN_P092_PFC_01_ETH0_RXER	P09_2 / ETHER_ETHn / ETH0_RXER.
IOPORT_PIN_P092_PFC_03_MTIOC7C	P09_2 / MTU3n / MTIOC7C.
IOPORT_PIN_P093_PFC_00_ETH0_TXD3	P09_3 / ETHER_ETHn / ETH0_TXD3.
IOPORT_PIN_P093_PFC_01_MTIOC7D	P09_3 / MTU3n / MTIOC7D.
IOPORT_PIN_P094_PFC_00_ETH0_TXD2	P09_4 / ETHER_ETHn / ETH0_TXD2.
IOPORT_PIN_P095_PFC_00_ETH0_TXD1	P09_5 / ETHER_ETHn / ETH0_TXD1.
IOPORT_PIN_P096_PFC_00_ETH0_TXD0	P09_6 / ETHER_ETHn / ETH0_TXD0.
IOPORT_PIN_P097_PFC_00_ETH0_TXCLK	P09_7 / ETHER_ETHn / ETH0_TXCLK.
IOPORT_PIN_P100_PFC_00_ETH0_TXEN	P10_0 / ETHER_ETHn / ETH0_TXEN.
IOPORT_PIN_P101_PFC_00_ETH0_RXD0	P10_1 / ETHER_ETHn / ETH0_RXD0.
IOPORT_PIN_P102_PFC_00_ETH0_RXD1	P10_2 / ETHER_ETHn / ETH0_RXD1.
IOPORT_PIN_P103_PFC_00_ETH0_RXD2	P10_3 / ETHER_ETHn / ETH0_RXD2.
IOPORT_PIN_P103_PFC_01_RTCAT1HZ	P10_3 / RTC / RTCAT1HZ.
IOPORT_PIN_P104_PFC_00_IRQ11	P10_4 / IRQ / IRQ11.
IOPORT_PIN_P104_PFC_01_ETHSW_PHYLINK0	P10_4 / ETHER_ETHSW / ETHSW_PHYLINK0.
IOPORT_PIN_P104_PFC_03_ESC_PHYLINK0	P10_4 / ETHER_ESC / ESC_PHYLINK0.
IOPORT_PIN_P124_PFC_01_ETH1_CRS	P12_4 / ETHER_ETHn / ETH1_CRS.
IOPORT_PIN_P124_PFC_02_TRACEDATA0	P12_4 / TRACE / TRACEDATA0.
IOPORT_PIN_P124_PFC_03_D15	P12_4 / BSC / D15.
IOPORT_PIN_P124_PFC_04_MTIOC8B	P12_4 / MTU3n / MTIOC8B.
IOPORT_PIN_P124_PFC_05_GTIOC8B	P12_4 / GPTn / GTIOC8B.
IOPORT_PIN_P124_PFC_06_SPI_SSL01	P12_4 / SPIn / SPI_SSL01.
IOPORT_PIN_P124_PFC_08_MBX_HINT	P12_4 / MBXSEM / MBX_HINT.
IOPORT_PIN_P132_PFC_00_IRQ5	P13_2 / IRQ / IRQ5.
IOPORT_PIN_P132_PFC_02_ETHSW_PTPOUT2	P13_2 / ETHER_ETHSW / ETHSW_PTPOUT2.
IOPORT_PIN_P132_PFC_03_TRACEDATA6	P13_2 / TRACE / TRACEDATA6.
IOPORT_PIN_P132_PFC_04_D9	P13_2 / BSC / D9.
IOPORT_PIN_P132_PFC_05_ESC_I2CCLK	P13_2 / ETHER_ESC / ESC_I2CCLK.
IOPORT_PIN_P132_PFC_06_MTIOC0A	P13_2 / MTU3n / MTIOC0A.
IOPORT_PIN_P132_PFC_07_GTIOC10A	P13_2 / GPTn / GTIOC10A.
IOPORT_PIN_P132_PFC_08_POE8	P13_2 / MTU_POE3 / POE8.
IOPORT_PIN_P132_PFC_09_SS1_CTS1_RTS1	P13_2 / SCIn / SS1_CTS1_RTS1.
IOPORT_PIN_P132_PFC_0A_SPI_MISO0	P13_2 / SPIn / SPI_MISO0.
IOPORT_PIN_P132_PFC_0B_IIC_SCL0	P13_2 / IICn / IIC_SCL0.
IOPORT_PIN_P132_PFC_0C_MCLK4	P13_2 / DSMIFn / MCLK4.
IOPORT_PIN_P132_PFC_0E_A13	P13_2 / BSC / A13.
IOPORT_PIN_P133_PFC_01_ETHSW_PTPOUT3	P13_3 / ETHER_ETHSW / ETHSW_PTPOUT3.
IOPORT_PIN_P133_PFC_02_TRACEDATA7	P13_3 / TRACE / TRACEDATA7.
IOPORT_PIN_P133_PFC_03_D8	P13_3 / BSC / D8.
IOPORT_PIN_P133_PFC_04_ESC_I2CDATA	P13_3 / ETHER_ESC / ESC_I2CDATA.
IOPORT_PIN_P133_PFC_05_MTIOC0C	P13_3 / MTU3n / MTIOC0C.
IOPORT_PIN_P133_PFC_06_MTIOC0B	P13_3 / MTU3n / MTIOC0B.
IOPORT_PIN_P133_PFC_07_GTIOC10B	P13_3 / GPTn / GTIOC10B.
IOPORT_PIN_P133_PFC_08_CMTW1_TOC0	P13_3 / CMTWn / CMTW1_TOC0.
IOPORT_PIN_P133_PFC_09_CTS1	P13_3 / SCIn / CTS1.
IOPORT_PIN_P133_PFC_0A_SPI_RSPCK0	P13_3 / SPIn / SPI_RSPCK0.
IOPORT_PIN_P133_PFC_0B_IIC_SDA0	P13_3 / IICn / IIC_SDA0.
IOPORT_PIN_P133_PFC_0C_MDAT4	P13_3 / DSMIFn / MDAT4.
IOPORT_PIN_P133_PFC_0E_RD	P13_3 / BSC / RD.
IOPORT_PIN_P134_PFC_01_ESC_RESETOUT	P13_4 / ETHER_ESC / ESC_RESETOUT.
IOPORT_PIN_P134_PFC_02_MTIOC0D	P13_4 / MTU3n / MTIOC0D.
IOPORT_PIN_P134_PFC_03_GTIOC8B	P13_4 / GPTn / GTIOC8B.
IOPORT_PIN_P134_PFC_05_A0	P13_4 / BSC / A0.
IOPORT_PIN_P135_PFC_00_XSPI0_WP1	P13_5 / XSPIn / XSPI0_WP1.
IOPORT_PIN_P135_PFC_01_GMAC_PTPTRG0	P13_5 / ETHER_GMAC / GMAC_PTPTRG0.
IOPORT_PIN_P135_PFC_02_ESC_LATCH0	P13_5 / ETHER_ESC / ESC_LATCH0.
IOPORT_PIN_P135_PFC_03_ESC_LATCH1	P13_5 / ETHER_ESC / ESC_LATCH1.
IOPORT_PIN_P135_PFC_04_MTCLKA	P13_5 / MTU3 / MTCLKA.
IOPORT_PIN_P135_PFC_05_SPI_RSPCK1	P13_5 / SPIn / SPI_RSPCK1.
IOPORT_PIN_P135_PFC_06_IIC_SCL2	P13_5 / IICn / IIC_SCL2.
IOPORT_PIN_P136_PFC_00_XSPI0_WP0	P13_6 / XSPIn / XSPI0_WP0.
IOPORT_PIN_P136_PFC_01_ETHSW_PTPOUT0	P13_6 / ETHER_ETHSW / ETHSW_PTPOUT0.
IOPORT_PIN_P136_PFC_02_ESC_SYNC0	P13_6 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P136_PFC_03_ESC_SYNC1	P13_6 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P136_PFC_04_MTCLKB	P13_6 / MTU3 / MTCLKB.
IOPORT_PIN_P137_PFC_00_XSPI0_ECS1	P13_7 / XSPIn / XSPI0_ECS1.
IOPORT_PIN_P137_PFC_01_GMAC_PTPTRG1	P13_7 / ETHER_GMAC / GMAC_PTPTRG1.
IOPORT_PIN_P137_PFC_02_ESC_LATCH1	P13_7 / ETHER_ESC / ESC_LATCH1.
IOPORT_PIN_P137_PFC_03_ESC_LATCH0	P13_7 / ETHER_ESC / ESC_LATCH0.
IOPORT_PIN_P137_PFC_04_MTCLKC	P13_7 / MTU3 / MTCLKC.
IOPORT_PIN_P137_PFC_05_MBX_HINT	P13_7 / MBXSEM / MBX_HINT.
IOPORT_PIN_P140_PFC_00_XSPI0_INT0	P14_0 / XSPIn / XSPI0_INT0.
IOPORT_PIN_P140_PFC_01_ETHSW_PTPOUT1	P14_0 / ETHER_ETHSW / ETHSW_PTPOUT1.
IOPORT_PIN_P140_PFC_02_ESC_SYNC1	P14_0 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P140_PFC_03_ESC_SYNC0	P14_0 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P140_PFC_04_MTCLKD	P14_0 / MTU3 / MTCLKD.
IOPORT_PIN_P141_PFC_00_XSPI0_INT1	P14_1 / XSPIn / XSPI0_INT1.
IOPORT_PIN_P141_PFC_01_ETH1_COL	P14_1 / ETHER_ETHn / ETH1_COL.
IOPORT_PIN_P141_PFC_03_MTIOC8A	P14_1 / MTU3n / MTIOC8A.
IOPORT_PIN_P141_PFC_04_GTIOC8A	P14_1 / GPTn / GTIOC8A.
IOPORT_PIN_P141_PFC_06_GMAC_PTPTRG1	P14_1 / ETHER_GMAC / GMAC_PTPTRG1.
IOPORT_PIN_P141_PFC_07_ESC_LATCH0	P14_1 / ETHER_ESC / ESC_LATCH0.
IOPORT_PIN_P141_PFC_08_ESC_LATCH1	P14_1 / ETHER_ESC / ESC_LATCH1.
IOPORT_PIN_P141_PFC_09_HSPI_IO0	P14_1 / SHOSTIF / HSPI_IO0.
IOPORT_PIN_P142_PFC_00_IRQ6	P14_2 / IRQ / IRQ6.
IOPORT_PIN_P142_PFC_01_XSPI0_ECS0	P14_2 / XSPIn / XSPI0_ECS0.
IOPORT_PIN_P142_PFC_02_ETH0_CRS	P14_2 / ETHER_ETHn / ETH0_CRS.
IOPORT_PIN_P142_PFC_04_MTIOC8B	P14_2 / MTU3n / MTIOC8B.
IOPORT_PIN_P142_PFC_05_GTIOC8B	P14_2 / GPTn / GTIOC8B.
IOPORT_PIN_P142_PFC_07_ETH2_CRS	P14_2 / ETHER_ETHn / ETH2_CRS.
IOPORT_PIN_P142_PFC_08_HSPI_CK	P14_2 / SHOSTIF / HSPI_CK.
IOPORT_PIN_P143_PFC_00_XSPI0_RSTO1	P14_3 / XSPIn / XSPI0_RSTO1.
IOPORT_PIN_P143_PFC_01_ETH0_COL	P14_3 / ETHER_ETHn / ETH0_COL.
IOPORT_PIN_P143_PFC_04_MTIOC0A	P14_3 / MTU3n / MTIOC0A.
IOPORT_PIN_P143_PFC_06_ETH2_COL	P14_3 / ETHER_ETHn / ETH2_COL.
IOPORT_PIN_P143_PFC_07_HSPI_IO1	P14_3 / SHOSTIF / HSPI_IO1.
IOPORT_PIN_P144_PFC_00_XSPI0_DS	P14_4 / XSPIn / XSPI0_DS.
IOPORT_PIN_P144_PFC_01_BS	P14_4 / BSC / BS.
IOPORT_PIN_P144_PFC_02_ESC_IRQ	P14_4 / ETHER_ESC / ESC_IRQ.
IOPORT_PIN_P144_PFC_03_MTIOC0B	P14_4 / MTU3n / MTIOC0B.
IOPORT_PIN_P144_PFC_04_HBS	P14_4 / PHOSTIF / HBS.
IOPORT_PIN_P145_PFC_00_XSPI0_CKN	P14_5 / XSPIn / XSPI0_CKN.
IOPORT_PIN_P145_PFC_01_CS3	P14_5 / BSC / CS3.
IOPORT_PIN_P145_PFC_02_POE8	P14_5 / MTU_POE3 / POE8.
IOPORT_PIN_P145_PFC_03_HSPI_INT	P14_5 / SHOSTIF / HSPI_INT.
IOPORT_PIN_P146_PFC_00_XSPI0_CKP	P14_6 / XSPIn / XSPI0_CKP.
IOPORT_PIN_P146_PFC_01_A21	P14_6 / BSC / A21.
IOPORT_PIN_P147_PFC_00_XSPI0_IO0	P14_7 / XSPIn / XSPI0_IO0.
IOPORT_PIN_P147_PFC_01_A22	P14_7 / BSC / A22.
IOPORT_PIN_P147_PFC_02_SCK5	P14_7 / SCIn / SCK5.
IOPORT_PIN_P147_PFC_03_SPI_MISO1	P14_7 / SPIn / SPI_MISO1.
IOPORT_PIN_P147_PFC_04_BS	P14_7 / BSC / BS.
IOPORT_PIN_P150_PFC_00_XSPI0_IO1	P15_0 / XSPIn / XSPI0_IO1.
IOPORT_PIN_P150_PFC_01_A23	P15_0 / BSC / A23.
IOPORT_PIN_P150_PFC_02_RXD5_SCL5_MISO5	P15_0 / SCIn / RXD5_SCL5_MISO5.
IOPORT_PIN_P150_PFC_03_SPI_MOSI1	P15_0 / SPIn / SPI_MOSI1.
IOPORT_PIN_P150_PFC_04_CKE	P15_0 / BSC / CKE.
IOPORT_PIN_P151_PFC_00_XSPI0_IO2	P15_1 / XSPIn / XSPI0_IO2.
IOPORT_PIN_P151_PFC_01_A24	P15_1 / BSC / A24.
IOPORT_PIN_P151_PFC_02_MTIOC0C	P15_1 / MTU3n / MTIOC0C.
IOPORT_PIN_P151_PFC_03_TXD5_SDA5_MOSI5	P15_1 / SCIn / TXD5_SDA5_MOSI5.
IOPORT_PIN_P151_PFC_04_SPI_SSL10	P15_1 / SPIn / SPI_SSL10.
IOPORT_PIN_P151_PFC_05_CAS	P15_1 / BSC / CAS.
IOPORT_PIN_P152_PFC_00_XSPI0_IO3	P15_2 / XSPIn / XSPI0_IO3.
IOPORT_PIN_P152_PFC_01_A25	P15_2 / BSC / A25.
IOPORT_PIN_P152_PFC_02_MTIOC0D	P15_2 / MTU3n / MTIOC0D.
IOPORT_PIN_P152_PFC_03_SS5_CTS5_RTS5	P15_2 / SCIn / SS5_CTS5_RTS5.
IOPORT_PIN_P152_PFC_04_SPI_SSL11	P15_2 / SPIn / SPI_SSL11.
IOPORT_PIN_P152_PFC_05_RAS	P15_2 / BSC / RAS.
IOPORT_PIN_P153_PFC_00_XSPI0_IO4	P15_3 / XSPIn / XSPI0_IO4.
IOPORT_PIN_P153_PFC_01_MTIOC8C	P15_3 / MTU3n / MTIOC8C.
IOPORT_PIN_P153_PFC_02_MCLK1	P15_3 / DSMIFn / MCLK1.
IOPORT_PIN_P153_PFC_03_D11	P15_3 / BSC / D11.
IOPORT_PIN_P154_PFC_00_XSPI0_IO5	P15_4 / XSPIn / XSPI0_IO5.
IOPORT_PIN_P154_PFC_01_MTIOC8D	P15_4 / MTU3n / MTIOC8D.
IOPORT_PIN_P154_PFC_02_MDAT1	P15_4 / DSMIFn / MDAT1.
IOPORT_PIN_P154_PFC_03_D12	P15_4 / BSC / D12.
IOPORT_PIN_P155_PFC_00_XSPI0_IO6	P15_5 / XSPIn / XSPI0_IO6.
IOPORT_PIN_P155_PFC_01_MCLK2	P15_5 / DSMIFn / MCLK2.
IOPORT_PIN_P155_PFC_02_D13	P15_5 / BSC / D13.
IOPORT_PIN_P156_PFC_00_XSPI0_IO7	P15_6 / XSPIn / XSPI0_IO7.
IOPORT_PIN_P156_PFC_01_SPI_SSL12	P15_6 / SPIn / SPI_SSL12.
IOPORT_PIN_P156_PFC_02_MDAT2	P15_6 / DSMIFn / MDAT2.
IOPORT_PIN_P156_PFC_03_D14	P15_6 / BSC / D14.
IOPORT_PIN_P157_PFC_00_XSPI0_CS0	P15_7 / XSPIn / XSPI0_CS0.
IOPORT_PIN_P157_PFC_01_CTS5	P15_7 / SCIn / CTS5.
IOPORT_PIN_P157_PFC_02_SPI_SSL13	P15_7 / SPIn / SPI_SSL13.
IOPORT_PIN_P157_PFC_03_TEND	P15_7 / DMAC / TEND.
IOPORT_PIN_P160_PFC_00_XSPI0_CS1	P16_0 / XSPIn / XSPI0_CS1.
IOPORT_PIN_P160_PFC_01_ETH0_TXER	P16_0 / ETHER_ETHn / ETH0_TXER.
IOPORT_PIN_P160_PFC_02_TXD0_SDA0_MOSI0	P16_0 / SCIn / TXD0_SDA0_MOSI0.
IOPORT_PIN_P160_PFC_03_SPI_MOSI3	P16_0 / SPIn / SPI_MOSI3.
IOPORT_PIN_P160_PFC_04_MCLK3	P16_0 / DSMIFn / MCLK3.
IOPORT_PIN_P160_PFC_06_ETH2_REFCLK	P16_0 / ETHER_ETHn / ETH2_REFCLK.
IOPORT_PIN_P160_PFC_07_HSPI_CS	P16_0 / SHOSTIF / HSPI_CS.
IOPORT_PIN_P161_PFC_00_XSPI0_RESET0	P16_1 / XSPIn / XSPI0_RESET0.
IOPORT_PIN_P161_PFC_01_CMTW0_TOC1	P16_1 / CMTWn / CMTW0_TOC1.
IOPORT_PIN_P161_PFC_02_ADTRG0	P16_1 / ADCn / ADTRG0.
IOPORT_PIN_P161_PFC_03_RXD0_SCL0_MISO0	P16_1 / SCIn / RXD0_SCL0_MISO0.
IOPORT_PIN_P161_PFC_04_SPI_MISO3	P16_1 / SPIn / SPI_MISO3.
IOPORT_PIN_P161_PFC_05_MDAT3	P16_1 / DSMIFn / MDAT3.
IOPORT_PIN_P161_PFC_07_CS2	P16_1 / BSC / CS2.
IOPORT_PIN_P161_PFC_08_HCS1	P16_1 / PHOSTIF / HCS1.
IOPORT_PIN_P162_PFC_00_NMI	P16_2 / IRQ / NMI.
IOPORT_PIN_P162_PFC_01_XSPI0_RESET1	P16_2 / XSPIn / XSPI0_RESET1.
IOPORT_PIN_P162_PFC_02_CTS0	P16_2 / SCIn / CTS0.
IOPORT_PIN_P162_PFC_03_SPI_RSPCK3	P16_2 / SPIn / SPI_RSPCK3.
IOPORT_PIN_P162_PFC_04_USB_EXICEN	P16_2 / USB_HS / USB_EXICEN.
IOPORT_PIN_P162_PFC_06_HSPI_IO2	P16_2 / SHOSTIF / HSPI_IO2.
IOPORT_PIN_P162_PFC_07_HERROUT	P16_2 / PHOSTIF / HERROUT.
IOPORT_PIN_P163_PFC_00_IRQ7	P16_3 / IRQ / IRQ7.
IOPORT_PIN_P163_PFC_01_XSPI0_RSTO0	P16_3 / XSPIn / XSPI0_RSTO0.
IOPORT_PIN_P163_PFC_02_ETH1_TXER	P16_3 / ETHER_ETHn / ETH1_TXER.
IOPORT_PIN_P163_PFC_03_GTADSMP1	P16_3 / GPT / GTADSMP1.
IOPORT_PIN_P163_PFC_04_SCK0	P16_3 / SCIn / SCK0.
IOPORT_PIN_P163_PFC_05_SPI_SSL30	P16_3 / SPIn / SPI_SSL30.
IOPORT_PIN_P163_PFC_07_ETH1_CRS	P16_3 / ETHER_ETHn / ETH1_CRS.
IOPORT_PIN_P163_PFC_08_CS3	P16_3 / BSC / CS3.
IOPORT_PIN_P163_PFC_09_HSPI_IO3	P16_3 / SHOSTIF / HSPI_IO3.
IOPORT_PIN_P165_PFC_00_MTIC5U	P16_5 / MTU3n / MTIC5U.
IOPORT_PIN_P165_PFC_01_TXD0_SDA0_MOSI0	P16_5 / SCIn / TXD0_SDA0_MOSI0.
IOPORT_PIN_P165_PFC_02_A15	P16_5 / BSC / A15.
IOPORT_PIN_P165_PFC_03_HSPI_IO4	P16_5 / SHOSTIF / HSPI_IO4.
IOPORT_PIN_P166_PFC_00_IRQ8	P16_6 / IRQ / IRQ8.
IOPORT_PIN_P166_PFC_01_MTIC5V	P16_6 / MTU3n / MTIC5V.
IOPORT_PIN_P166_PFC_02_RXD0_SCL0_MISO0	P16_6 / SCIn / RXD0_SCL0_MISO0.
IOPORT_PIN_P166_PFC_03_CS0	P16_6 / BSC / CS0.
IOPORT_PIN_P166_PFC_04_HSPI_IO5	P16_6 / SHOSTIF / HSPI_IO5.
IOPORT_PIN_P166_PFC_05_HCS0	P16_6 / PHOSTIF / HCS0.
IOPORT_PIN_P167_PFC_00_MTIC5W	P16_7 / MTU3n / MTIC5W.
IOPORT_PIN_P167_PFC_01_SCK0	P16_7 / SCIn / SCK0.
IOPORT_PIN_P167_PFC_02_XSPI1_IO0	P16_7 / XSPIn / XSPI1_IO0.
IOPORT_PIN_P167_PFC_03_A13	P16_7 / BSC / A13.
IOPORT_PIN_P167_PFC_04_HA13	P16_7 / PHOSTIF / HA13.
IOPORT_PIN_P170_PFC_00_ESC_IRQ	P17_0 / ETHER_ESC / ESC_IRQ.
IOPORT_PIN_P170_PFC_01_SS0_CTS0_RTS0	P17_0 / SCIn / SS0_CTS0_RTS0.
IOPORT_PIN_P170_PFC_02_XSPI1_IO1	P17_0 / XSPIn / XSPI1_IO1.
IOPORT_PIN_P173_PFC_00_TRACECTL	P17_3 / TRACE / TRACECTL.
IOPORT_PIN_P173_PFC_01_GTETRGA	P17_3 / GPT_POEG / GTETRGA.
IOPORT_PIN_P173_PFC_02_POE0	P17_3 / MTU_POE3 / POE0.
IOPORT_PIN_P173_PFC_03_ADTRG1	P17_3 / ADCn / ADTRG1.
IOPORT_PIN_P173_PFC_04_SPI_SSL31	P17_3 / SPIn / SPI_SSL31.
IOPORT_PIN_P173_PFC_05_DREQ	P17_3 / DMAC / DREQ.
IOPORT_PIN_P173_PFC_07_XSPI1_IO2	P17_3 / XSPIn / XSPI1_IO2.
IOPORT_PIN_P174_PFC_00_TRACECLK	P17_4 / TRACE / TRACECLK.
IOPORT_PIN_P174_PFC_01_MTIOC3C	P17_4 / MTU3n / MTIOC3C.
IOPORT_PIN_P174_PFC_02_GTETRGB	P17_4 / GPT_POEG / GTETRGB.
IOPORT_PIN_P174_PFC_03_GTIOC0A	P17_4 / GPTn / GTIOC0A.
IOPORT_PIN_P174_PFC_04_CTS3	P17_4 / SCIn / CTS3.
IOPORT_PIN_P174_PFC_05_SPI_SSL32	P17_4 / SPIn / SPI_SSL32.
IOPORT_PIN_P174_PFC_07_XSPI1_IO3	P17_4 / XSPIn / XSPI1_IO3.
IOPORT_PIN_P174_PFC_08_DACK	P17_4 / DMAC / DACK.
IOPORT_PIN_P175_PFC_01_MTIOC3A	P17_5 / MTU3n / MTIOC3A.
IOPORT_PIN_P175_PFC_02_GTETRGC	P17_5 / GPT_POEG / GTETRGC.
IOPORT_PIN_P175_PFC_03_GTIOC0B	P17_5 / GPTn / GTIOC0B.
IOPORT_PIN_P175_PFC_04_TEND	P17_5 / DMAC / TEND.
IOPORT_PIN_P175_PFC_05_USB_OVRCUR	P17_5 / USB_HS / USB_OVRCUR.
IOPORT_PIN_P176_PFC_00_MTIOC3B	P17_6 / MTU3n / MTIOC3B.
IOPORT_PIN_P176_PFC_01_GTIOC1A	P17_6 / GPTn / GTIOC1A.
IOPORT_PIN_P176_PFC_02_SCK3	P17_6 / SCIn / SCK3.
IOPORT_PIN_P176_PFC_04_XSPI1_DS	P17_6 / XSPIn / XSPI1_DS.
IOPORT_PIN_P176_PFC_05_RD_WR	P17_6 / BSC / RD_WR.
IOPORT_PIN_P176_PFC_06_HWRSTB	P17_6 / PHOSTIF / HWRSTB.
IOPORT_PIN_P177_PFC_00_MTIOC4A	P17_7 / MTU3n / MTIOC4A.
IOPORT_PIN_P177_PFC_01_MTIOC4C	P17_7 / MTU3n / MTIOC4C.
IOPORT_PIN_P177_PFC_02_GTIOC2A	P17_7 / GPTn / GTIOC2A.
IOPORT_PIN_P177_PFC_03_GTIOC3A	P17_7 / GPTn / GTIOC3A.
IOPORT_PIN_P177_PFC_04_RXD3_SCL3_MISO3	P17_7 / SCIn / RXD3_SCL3_MISO3.
IOPORT_PIN_P177_PFC_05_DACK	P17_7 / DMAC / DACK.
IOPORT_PIN_P177_PFC_07_XSPI1_CKP	P17_7 / XSPIn / XSPI1_CKP.
IOPORT_PIN_P177_PFC_08_RD	P17_7 / BSC / RD.
IOPORT_PIN_P177_PFC_09_HRD	P17_7 / PHOSTIF / HRD.
IOPORT_PIN_P180_PFC_00_MTIOC4C	P18_0 / MTU3n / MTIOC4C.
IOPORT_PIN_P180_PFC_01_MTIOC4A	P18_0 / MTU3n / MTIOC4A.
IOPORT_PIN_P180_PFC_02_GTIOC3A	P18_0 / GPTn / GTIOC3A.
IOPORT_PIN_P180_PFC_03_GTIOC2A	P18_0 / GPTn / GTIOC2A.
IOPORT_PIN_P180_PFC_04_TXD3_SDA3_MOSI3	P18_0 / SCIn / TXD3_SDA3_MOSI3.
IOPORT_PIN_P180_PFC_05_WE0_DQMLL	P18_0 / BSC / WE0_DQMLL.
IOPORT_PIN_P180_PFC_06_HSPI_IO6	P18_0 / SHOSTIF / HSPI_IO6.
IOPORT_PIN_P180_PFC_07_HWR0	P18_0 / PHOSTIF / HWR0.
IOPORT_PIN_P181_PFC_00_IRQ10	P18_1 / IRQ / IRQ10.
IOPORT_PIN_P181_PFC_01_MTIOC3D	P18_1 / MTU3n / MTIOC3D.
IOPORT_PIN_P181_PFC_02_GTIOC1B	P18_1 / GPTn / GTIOC1B.
IOPORT_PIN_P181_PFC_03_ADTRG1	P18_1 / ADCn / ADTRG1.
IOPORT_PIN_P181_PFC_04_SS3_CTS3_RTS3	P18_1 / SCIn / SS3_CTS3_RTS3.
IOPORT_PIN_P181_PFC_06_WE1_DQMLU	P18_1 / BSC / WE1_DQMLU.
IOPORT_PIN_P181_PFC_07_HSPI_IO7	P18_1 / SHOSTIF / HSPI_IO7.
IOPORT_PIN_P181_PFC_08_HWR1	P18_1 / PHOSTIF / HWR1.
IOPORT_PIN_P182_PFC_00_MTIOC4B	P18_2 / MTU3n / MTIOC4B.
IOPORT_PIN_P182_PFC_01_MTIOC4D	P18_2 / MTU3n / MTIOC4D.
IOPORT_PIN_P182_PFC_02_GTIOC2B	P18_2 / GPTn / GTIOC2B.
IOPORT_PIN_P182_PFC_03_GTIOC3B	P18_2 / GPTn / GTIOC3B.
IOPORT_PIN_P182_PFC_05_XSPI1_CS0	P18_2 / XSPIn / XSPI1_CS0.
IOPORT_PIN_P182_PFC_06_ETH1_COL	P18_2 / ETHER_ETHn / ETH1_COL.
IOPORT_PIN_P182_PFC_07_BS	P18_2 / BSC / BS.
IOPORT_PIN_P182_PFC_08_SCK0	P18_2 / SCIn / SCK0.
IOPORT_PIN_P182_PFC_09_IIC_SDA2	P18_2 / IICn / IIC_SDA2.
IOPORT_PIN_P183_PFC_00_IRQ0	P18_3 / IRQ / IRQ0.
IOPORT_PIN_P183_PFC_01_MTIOC4D	P18_3 / MTU3n / MTIOC4D.
IOPORT_PIN_P183_PFC_02_MTIOC4B	P18_3 / MTU3n / MTIOC4B.
IOPORT_PIN_P183_PFC_03_GTIOC3B	P18_3 / GPTn / GTIOC3B.
IOPORT_PIN_P183_PFC_04_GTIOC2B	P18_3 / GPTn / GTIOC2B.
IOPORT_PIN_P183_PFC_05_CMTW1_TIC1	P18_3 / CMTWn / CMTW1_TIC1.
IOPORT_PIN_P183_PFC_06_CANRXDP1	P18_3 / CANFDn / CANRXDP1.
IOPORT_PIN_P183_PFC_08_XSPI1_IO4	P18_3 / XSPIn / XSPI1_IO4.
IOPORT_PIN_P183_PFC_09_ETH2_CRS	P18_3 / ETHER_ETHn / ETH2_CRS.
IOPORT_PIN_P183_PFC_0A_CKE	P18_3 / BSC / CKE.
IOPORT_PIN_P184_PFC_00_IRQ1	P18_4 / IRQ / IRQ1.
IOPORT_PIN_P184_PFC_01_MTIC5U	P18_4 / MTU3n / MTIC5U.
IOPORT_PIN_P184_PFC_02_TXD4_SDA4_MOSI4	P18_4 / SCIn / TXD4_SDA4_MOSI4.
IOPORT_PIN_P184_PFC_03_SPI_RSPCK2	P18_4 / SPIn / SPI_RSPCK2.
IOPORT_PIN_P184_PFC_05_XSPI1_IO5	P18_4 / XSPIn / XSPI1_IO5.
IOPORT_PIN_P184_PFC_06_ETH1_CRS	P18_4 / ETHER_ETHn / ETH1_CRS.
IOPORT_PIN_P184_PFC_07_CAS	P18_4 / BSC / CAS.
IOPORT_PIN_P184_PFC_08_CANTX0	P18_4 / CANFDn / CANTX0.
IOPORT_PIN_P185_PFC_00_TRACECTL	P18_5 / TRACE / TRACECTL.
IOPORT_PIN_P185_PFC_01_MTIC5V	P18_5 / MTU3n / MTIC5V.
IOPORT_PIN_P185_PFC_02_RXD4_SCL4_MISO4	P18_5 / SCIn / RXD4_SCL4_MISO4.
IOPORT_PIN_P185_PFC_03_SPI_MOSI2	P18_5 / SPIn / SPI_MOSI2.
IOPORT_PIN_P185_PFC_05_XSPI1_IO6	P18_5 / XSPIn / XSPI1_IO6.
IOPORT_PIN_P185_PFC_06_ETH2_COL	P18_5 / ETHER_ETHn / ETH2_COL.
IOPORT_PIN_P185_PFC_07_RAS	P18_5 / BSC / RAS.
IOPORT_PIN_P185_PFC_08_CANRX0	P18_5 / CANFDn / CANRX0.
IOPORT_PIN_P186_PFC_00_IRQ11	P18_6 / IRQ / IRQ11.
IOPORT_PIN_P186_PFC_01_TRACECLK	P18_6 / TRACE / TRACECLK.
IOPORT_PIN_P186_PFC_02_MTIC5W	P18_6 / MTU3n / MTIC5W.
IOPORT_PIN_P186_PFC_03_ADTRG0	P18_6 / ADCn / ADTRG0.
IOPORT_PIN_P186_PFC_04_SCK4	P18_6 / SCIn / SCK4.
IOPORT_PIN_P186_PFC_05_SPI_MISO2	P18_6 / SPIn / SPI_MISO2.
IOPORT_PIN_P186_PFC_06_IIC_SCL2	P18_6 / IICn / IIC_SCL2.
IOPORT_PIN_P186_PFC_08_XSPI1_IO7	P18_6 / XSPIn / XSPI1_IO7.
IOPORT_PIN_P186_PFC_09_ETH1_COL	P18_6 / ETHER_ETHn / ETH1_COL.
IOPORT_PIN_P186_PFC_0A_DE4	P18_6 / SCIn / DE4.
IOPORT_PIN_P190_PFC_00_USB_VBUSEN	P19_0 / USB_HS / USB_VBUSEN.
IOPORT_PIN_P201_PFC_00_ETHSW_TDMAOUT0	P20_1 / ETHER_ETHSW / ETHSW_TDMAOUT0.
IOPORT_PIN_P201_PFC_01_ESC_LINKACT0	P20_1 / ETHER_ESC / ESC_LINKACT0.
IOPORT_PIN_P201_PFC_02_ETHSW_PTPOUT3	P20_1 / ETHER_ETHSW / ETHSW_PTPOUT3.
IOPORT_PIN_P202_PFC_00_ETHSW_TDMAOUT1	P20_2 / ETHER_ETHSW / ETHSW_TDMAOUT1.
IOPORT_PIN_P202_PFC_01_ESC_LEDRUN	P20_2 / ETHER_ESC / ESC_LEDRUN.
IOPORT_PIN_P202_PFC_02_ESC_LEDSTER	P20_2 / ETHER_ESC / ESC_LEDSTER.
IOPORT_PIN_P202_PFC_03_DE3	P20_2 / SCIn / DE3.
IOPORT_PIN_P202_PFC_04_ETHSW_PTPOUT2	P20_2 / ETHER_ETHSW / ETHSW_PTPOUT2.
IOPORT_PIN_P203_PFC_00_ETHSW_TDMAOUT2	P20_3 / ETHER_ETHSW / ETHSW_TDMAOUT2.
IOPORT_PIN_P203_PFC_01_ESC_LEDERR	P20_3 / ETHER_ESC / ESC_LEDERR.
IOPORT_PIN_P203_PFC_02_ETHSW_PTPOUT1	P20_3 / ETHER_ETHSW / ETHSW_PTPOUT1.
IOPORT_PIN_P204_PFC_00_ETHSW_TDMAOUT3	P20_4 / ETHER_ETHSW / ETHSW_TDMAOUT3.
IOPORT_PIN_P204_PFC_01_ESC_LINKACT1	P20_4 / ETHER_ESC / ESC_LINKACT1.
IOPORT_PIN_P204_PFC_02_ETHSW_PTPOUT0	P20_4 / ETHER_ETHSW / ETHSW_PTPOUT0.
IOPORT_PIN_P211_PFC_00_TRACEDATA0	P21_1 / TRACE / TRACEDATA0.
IOPORT_PIN_P211_PFC_01_D0	P21_1 / BSC / D0.
IOPORT_PIN_P211_PFC_02_MTIOC6A	P21_1 / MTU3n / MTIOC6A.
IOPORT_PIN_P211_PFC_03_GTIOC14A	P21_1 / GPTn / GTIOC14A.
IOPORT_PIN_P211_PFC_04_CMTW0_TIC0	P21_1 / CMTWn / CMTW0_TIC0.
IOPORT_PIN_P211_PFC_05_SCK5	P21_1 / SCIn / SCK5.
IOPORT_PIN_P211_PFC_06_SPI_SSL20	P21_1 / SPIn / SPI_SSL20.
IOPORT_PIN_P211_PFC_07_IIC_SCL1	P21_1 / IICn / IIC_SCL1.
IOPORT_PIN_P211_PFC_08_MCLK0	P21_1 / DSMIFn / MCLK0.
IOPORT_PIN_P211_PFC_0A_ESC_SYNC0	P21_1 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P211_PFC_0B_ESC_SYNC1	P21_1 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P211_PFC_0C_HSPI_INT	P21_1 / SHOSTIF / HSPI_INT.
IOPORT_PIN_P211_PFC_0D_HD0	P21_1 / PHOSTIF / HD0.
IOPORT_PIN_P212_PFC_00_TRACEDATA1	P21_2 / TRACE / TRACEDATA1.
IOPORT_PIN_P212_PFC_01_D1	P21_2 / BSC / D1.
IOPORT_PIN_P212_PFC_02_MTIOC6B	P21_2 / MTU3n / MTIOC6B.
IOPORT_PIN_P212_PFC_03_GTIOC14B	P21_2 / GPTn / GTIOC14B.
IOPORT_PIN_P212_PFC_04_CMTW0_TIC1	P21_2 / CMTWn / CMTW0_TIC1.
IOPORT_PIN_P212_PFC_05_RXD5_SCL5_MISO5	P21_2 / SCIn / RXD5_SCL5_MISO5.
IOPORT_PIN_P212_PFC_06_SPI_MISO2	P21_2 / SPIn / SPI_MISO2.
IOPORT_PIN_P212_PFC_07_IIC_SDA1	P21_2 / IICn / IIC_SDA1.
IOPORT_PIN_P212_PFC_08_MDAT0	P21_2 / DSMIFn / MDAT0.
IOPORT_PIN_P212_PFC_0A_ESC_SYNC0	P21_2 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P212_PFC_0B_ESC_SYNC1	P21_2 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P212_PFC_0C_HD1	P21_2 / PHOSTIF / HD1.
IOPORT_PIN_P213_PFC_00_TRACEDATA2	P21_3 / TRACE / TRACEDATA2.
IOPORT_PIN_P213_PFC_01_D2	P21_3 / BSC / D2.
IOPORT_PIN_P213_PFC_02_MTIOC6C	P21_3 / MTU3n / MTIOC6C.
IOPORT_PIN_P213_PFC_03_GTIOC15A	P21_3 / GPTn / GTIOC15A.
IOPORT_PIN_P213_PFC_04_TXD5_SDA5_MOSI5	P21_3 / SCIn / TXD5_SDA5_MOSI5.
IOPORT_PIN_P213_PFC_05_SPI_SSL33	P21_3 / SPIn / SPI_SSL33.
IOPORT_PIN_P213_PFC_06_MCLK1	P21_3 / DSMIFn / MCLK1.
IOPORT_PIN_P213_PFC_08_NMI	P21_3 / IRQ / NMI.
IOPORT_PIN_P213_PFC_09_HD2	P21_3 / PHOSTIF / HD2.
IOPORT_PIN_P214_PFC_00_TRACEDATA3	P21_4 / TRACE / TRACEDATA3.
IOPORT_PIN_P214_PFC_01_D3	P21_4 / BSC / D3.
IOPORT_PIN_P214_PFC_02_MTIOC6D	P21_4 / MTU3n / MTIOC6D.
IOPORT_PIN_P214_PFC_03_GTIOC15B	P21_4 / GPTn / GTIOC15B.
IOPORT_PIN_P214_PFC_04_SS5_CTS5_RTS5	P21_4 / SCIn / SS5_CTS5_RTS5.
IOPORT_PIN_P214_PFC_05_SPI_SSL02	P21_4 / SPIn / SPI_SSL02.
IOPORT_PIN_P214_PFC_06_MDAT1	P21_4 / DSMIFn / MDAT1.
IOPORT_PIN_P214_PFC_08_ETHSW_PTPOUT1	P21_4 / ETHER_ETHSW / ETHSW_PTPOUT1.
IOPORT_PIN_P214_PFC_09_ESC_SYNC0	P21_4 / ETHER_ESC / ESC_SYNC0.
IOPORT_PIN_P214_PFC_0A_ESC_SYNC1	P21_4 / ETHER_ESC / ESC_SYNC1.
IOPORT_PIN_P214_PFC_0B_HD3	P21_4 / PHOSTIF / HD3.
IOPORT_PIN_P214_PFC_0C_MBX_HINT	P21_4 / MBXSEM / MBX_HINT.
IOPORT_PIN_P215_PFC_00_IRQ6	P21_5 / IRQ / IRQ6.
IOPORT_PIN_P215_PFC_01_TRACEDATA4	P21_5 / TRACE / TRACEDATA4.
IOPORT_PIN_P215_PFC_02_D4	P21_5 / BSC / D4.
IOPORT_PIN_P215_PFC_03_MTIOC7A	P21_5 / MTU3n / MTIOC7A.
IOPORT_PIN_P215_PFC_04_GTIOC16A	P21_5 / GPTn / GTIOC16A.
IOPORT_PIN_P215_PFC_05_CMTW1_TOC1	P21_5 / CMTWn / CMTW1_TOC1.
IOPORT_PIN_P215_PFC_06_ADTRG1	P21_5 / ADCn / ADTRG1.
IOPORT_PIN_P215_PFC_07_CTS5	P21_5 / SCIn / CTS5.
IOPORT_PIN_P215_PFC_08_SPI_MISO0	P21_5 / SPIn / SPI_MISO0.
IOPORT_PIN_P215_PFC_09_MCLK2	P21_5 / DSMIFn / MCLK2.
IOPORT_PIN_P215_PFC_0B_HD4	P21_5 / PHOSTIF / HD4.
IOPORT_PIN_P216_PFC_00_IRQ9	P21_6 / IRQ / IRQ9.
IOPORT_PIN_P216_PFC_01_TRACEDATA5	P21_6 / TRACE / TRACEDATA5.
IOPORT_PIN_P216_PFC_02_D5	P21_6 / BSC / D5.
IOPORT_PIN_P216_PFC_03_MTIOC7B	P21_6 / MTU3n / MTIOC7B.
IOPORT_PIN_P216_PFC_04_GTIOC16B	P21_6 / GPTn / GTIOC16B.
IOPORT_PIN_P216_PFC_05_CTS0	P21_6 / SCIn / CTS0.
IOPORT_PIN_P216_PFC_06_TEND	P21_6 / DMAC / TEND.
IOPORT_PIN_P216_PFC_07_MDAT2	P21_6 / DSMIFn / MDAT2.
IOPORT_PIN_P216_PFC_08_HD5	P21_6 / PHOSTIF / HD5.
IOPORT_PIN_P217_PFC_00_IRQ10	P21_7 / IRQ / IRQ10.
IOPORT_PIN_P217_PFC_01_TRACEDATA6	P21_7 / TRACE / TRACEDATA6.
IOPORT_PIN_P217_PFC_02_D6	P21_7 / BSC / D6.
IOPORT_PIN_P217_PFC_03_MTIOC7C	P21_7 / MTU3n / MTIOC7C.
IOPORT_PIN_P217_PFC_04_GTIOC17A	P21_7 / GPTn / GTIOC17A.
IOPORT_PIN_P217_PFC_05_DE0	P21_7 / SCIn / DE0.
IOPORT_PIN_P217_PFC_06_DREQ	P21_7 / DMAC / DREQ.
IOPORT_PIN_P217_PFC_07_MCLK3	P21_7 / DSMIFn / MCLK3.
IOPORT_PIN_P217_PFC_08_HD6	P21_7 / PHOSTIF / HD6.
IOPORT_PIN_P220_PFC_00_IRQ15	P22_0 / IRQ / IRQ15.
IOPORT_PIN_P220_PFC_01_TRACEDATA7	P22_0 / TRACE / TRACEDATA7.
IOPORT_PIN_P220_PFC_02_D7	P22_0 / BSC / D7.
IOPORT_PIN_P220_PFC_03_MTIOC7D	P22_0 / MTU3n / MTIOC7D.
IOPORT_PIN_P220_PFC_04_GTIOC17B	P22_0 / GPTn / GTIOC17B.
IOPORT_PIN_P220_PFC_05_DE5	P22_0 / SCIn / DE5.
IOPORT_PIN_P220_PFC_06_MDAT3	P22_0 / DSMIFn / MDAT3.
IOPORT_PIN_P220_PFC_07_HD7	P22_0 / PHOSTIF / HD7.
IOPORT_PIN_P221_PFC_00_TRACECTL	P22_1 / TRACE / TRACECTL.
IOPORT_PIN_P221_PFC_01_D8	P22_1 / BSC / D8.
IOPORT_PIN_P221_PFC_02_ESC_LINKACT2	P22_1 / ETHER_ESC / ESC_LINKACT2.
IOPORT_PIN_P221_PFC_03_POE4	P22_1 / MTU_POE3 / POE4.
IOPORT_PIN_P221_PFC_04_SS4_CTS4_RTS4	P22_1 / SCIn / SS4_CTS4_RTS4.
IOPORT_PIN_P221_PFC_05_HD8	P22_1 / PHOSTIF / HD8.
IOPORT_PIN_P221_PFC_06_GTETRGB	P22_1 / GPT_POEG / GTETRGB.
IOPORT_PIN_P222_PFC_00_IRQ4	P22_2 / IRQ / IRQ4.
IOPORT_PIN_P222_PFC_01_TRACECLK	P22_2 / TRACE / TRACECLK.
IOPORT_PIN_P222_PFC_02_D9	P22_2 / BSC / D9.
IOPORT_PIN_P222_PFC_03_MTIOC8C	P22_2 / MTU3n / MTIOC8C.
IOPORT_PIN_P222_PFC_04_GTETRGSA	P22_2 / GPT_POEG / GTETRGSA.
IOPORT_PIN_P222_PFC_05_SPI_SSL12	P22_2 / SPIn / SPI_SSL12.
IOPORT_PIN_P222_PFC_07_HD9	P22_2 / PHOSTIF / HD9.
IOPORT_PIN_P222_PFC_08_MCLK1	P22_2 / DSMIFn / MCLK1.
IOPORT_PIN_P223_PFC_00_D10	P22_3 / BSC / D10.
IOPORT_PIN_P223_PFC_01_MTIOC8D	P22_3 / MTU3n / MTIOC8D.
IOPORT_PIN_P223_PFC_02_GTETRGSB	P22_3 / GPT_POEG / GTETRGSB.
IOPORT_PIN_P223_PFC_04_RXD5_SCL5_MISO5	P22_3 / SCIn / RXD5_SCL5_MISO5.
IOPORT_PIN_P223_PFC_05_HD10	P22_3 / PHOSTIF / HD10.
IOPORT_PIN_P237_PFC_00_ETH2_RXD0	P23_7 / ETHER_ETHn / ETH2_RXD0.
IOPORT_PIN_P237_PFC_02_D11	P23_7 / BSC / D11.
IOPORT_PIN_P237_PFC_03_BS	P23_7 / BSC / BS.
IOPORT_PIN_P237_PFC_04_MTIOC0A	P23_7 / MTU3n / MTIOC0A.
IOPORT_PIN_P237_PFC_05_GTETRGA	P23_7 / GPT_POEG / GTETRGA.
IOPORT_PIN_P237_PFC_06_SCK1	P23_7 / SCIn / SCK1.
IOPORT_PIN_P237_PFC_07_MCLK4	P23_7 / DSMIFn / MCLK4.
IOPORT_PIN_P237_PFC_09_HD11	P23_7 / PHOSTIF / HD11.
IOPORT_PIN_P240_PFC_00_ETH2_RXD1	P24_0 / ETHER_ETHn / ETH2_RXD1.
IOPORT_PIN_P240_PFC_02_D12	P24_0 / BSC / D12.
IOPORT_PIN_P240_PFC_03_CKE	P24_0 / BSC / CKE.
IOPORT_PIN_P240_PFC_04_MTIOC0B	P24_0 / MTU3n / MTIOC0B.
IOPORT_PIN_P240_PFC_05_GTETRGB	P24_0 / GPT_POEG / GTETRGB.
IOPORT_PIN_P240_PFC_06_RXD1_SCL1_MISO1	P24_0 / SCIn / RXD1_SCL1_MISO1.
IOPORT_PIN_P240_PFC_07_DREQ	P24_0 / DMAC / DREQ.
IOPORT_PIN_P240_PFC_08_MDAT4	P24_0 / DSMIFn / MDAT4.
IOPORT_PIN_P240_PFC_0A_HD12	P24_0 / PHOSTIF / HD12.
IOPORT_PIN_P241_PFC_00_ETH2_RXCLK	P24_1 / ETHER_ETHn / ETH2_RXCLK.
IOPORT_PIN_P241_PFC_02_D13	P24_1 / BSC / D13.
IOPORT_PIN_P241_PFC_03_CAS	P24_1 / BSC / CAS.
IOPORT_PIN_P241_PFC_04_MTIOC0C	P24_1 / MTU3n / MTIOC0C.
IOPORT_PIN_P241_PFC_05_GTETRGC	P24_1 / GPT_POEG / GTETRGC.
IOPORT_PIN_P241_PFC_06_POE8	P24_1 / MTU_POE3 / POE8.
IOPORT_PIN_P241_PFC_07_MCLK5	P24_1 / DSMIFn / MCLK5.
IOPORT_PIN_P241_PFC_09_HD13	P24_1 / PHOSTIF / HD13.
IOPORT_PIN_P242_PFC_00_ETH2_RXD2	P24_2 / ETHER_ETHn / ETH2_RXD2.
IOPORT_PIN_P242_PFC_02_D14	P24_2 / BSC / D14.
IOPORT_PIN_P242_PFC_03_RAS	P24_2 / BSC / RAS.
IOPORT_PIN_P242_PFC_04_MTIOC0D	P24_2 / MTU3n / MTIOC0D.
IOPORT_PIN_P242_PFC_05_GTETRGD	P24_2 / GPT_POEG / GTETRGD.
IOPORT_PIN_P242_PFC_06_TXD1_SDA1_MOSI1	P24_2 / SCIn / TXD1_SDA1_MOSI1.
IOPORT_PIN_P242_PFC_07_MDAT5	P24_2 / DSMIFn / MDAT5.
IOPORT_PIN_P242_PFC_09_HD14	P24_2 / PHOSTIF / HD14.
IOPORT_PERIPHERAL_END	Marks end of enum - used by parameter checking

ioport_cfg_options_t [2/2]

enum ioport_cfg_options_t

Options to configure pin functions

Enumerator
IOPORT_CFG_PORT_DIRECTION_HIZ	Sets the pin direction to Hi-Z.
IOPORT_CFG_PORT_DIRECTION_INPUT	Sets the pin direction to input (default)
IOPORT_CFG_PORT_DIRECTION_OUTPUT	Sets the pin direction to output.
IOPORT_CFG_PORT_DIRECTION_OUTPUT_INPUT	Sets the pin direction to output (data is input to input buffer)
IOPORT_CFG_PORT_OUTPUT_LOW	Sets the pin level to low.
IOPORT_CFG_PORT_OUTPUT_HIGH	Sets the pin level to high.
IOPORT_CFG_PORT_GPIO	Enables pin to operate as an GPIO pin.
IOPORT_CFG_PORT_PERI	Enables pin to operate as a peripheral pin.
IOPORT_CFG_DRIVE_LOW	Sets pin drive output to low.
IOPORT_CFG_DRIVE_MID	Sets pin drive output to medium.
IOPORT_CFG_DRIVE_HIGH	Sets pin drive output to high.
IOPORT_CFG_DRIVE_UHIGH	Sets pin drive output to ultra high.
IOPORT_CFG_PULLUP_DOWN_DISABLE	Disables the pin's pull-up / pull-down.
IOPORT_CFG_PULLUP_ENABLE	Enables the pin's internal pull-up.
IOPORT_CFG_PULLDOWN_ENABLE	Enables the pin's pull-down.
IOPORT_CFG_SCHMITT_TRIGGER_DISABLE	Disables schmitt trigger input.
IOPORT_CFG_SCHMITT_TRIGGER_ENABLE	Enables schmitt trigger input.
IOPORT_CFG_SLEW_RATE_SLOW	Sets the slew rate to slow.
IOPORT_CFG_SLEW_RATE_FAST	Sets the slew rate to fast.
IOPORT_CFG_REGION_SAFETY	Selects safety region.
IOPORT_CFG_REGION_NSAFETY	Selects non safety region.
IOPORT_CFG_PIM_TTL	This macro has been unsupported.
IOPORT_CFG_NMOS_ENABLE	This macro has been unsupported.
IOPORT_CFG_PMOS_ENABLE	This macro has been unsupported.
IOPORT_CFG_DRIVE_HS_HIGH	This macro has been unsupported.
IOPORT_CFG_DRIVE_MID_IIC	This macro has been unsupported.
IOPORT_CFG_EVENT_RISING_EDGE	This macro has been unsupported.
IOPORT_CFG_EVENT_FALLING_EDGE	This macro has been unsupported.
IOPORT_CFG_EVENT_BOTH_EDGES	This macro has been unsupported.
IOPORT_CFG_IRQ_ENABLE	This macro has been unsupported.
IOPORT_CFG_ANALOG_ENABLE	This macro has been unsupported.
IOPORT_CFG_PERIPHERAL_PIN	This macro has been unsupported.
IOPORT_CFG_PORT_DIRECTION_HIZ	Sets the pin direction to Hi-Z.
IOPORT_CFG_PORT_DIRECTION_INPUT	Sets the pin direction to input (default)
IOPORT_CFG_PORT_DIRECTION_OUTPUT	Sets the pin direction to output.
IOPORT_CFG_PORT_DIRECTION_OUTPUT_INPUT	Sets the pin direction to output (data is input to input buffer)
IOPORT_CFG_PORT_OUTPUT_LOW	Sets the pin level to low.
IOPORT_CFG_PORT_OUTPUT_HIGH	Sets the pin level to high.
IOPORT_CFG_PORT_GPIO	Enables pin to operate as an GPIO pin.
IOPORT_CFG_PORT_PERI	Enables pin to operate as a peripheral pin.
IOPORT_CFG_DRIVE_LOW	Sets pin drive output to low.
IOPORT_CFG_DRIVE_MID	Sets pin drive output to medium.
IOPORT_CFG_DRIVE_HIGH	Sets pin drive output to high.
IOPORT_CFG_DRIVE_UHIGH	Sets pin drive output to ultra high.
IOPORT_CFG_PULLUP_DOWN_DISABLE	Disables the pin's pull-up / pull-down.
IOPORT_CFG_PULLUP_ENABLE	Enables the pin's internal pull-up.
IOPORT_CFG_PULLDOWN_ENABLE	Enables the pin's pull-down.
IOPORT_CFG_SCHMITT_TRIGGER_DISABLE	Disables schmitt trigger input.
IOPORT_CFG_SCHMITT_TRIGGER_ENABLE	Enables schmitt trigger input.
IOPORT_CFG_SLEW_RATE_SLOW	Sets the slew rate to slow.
IOPORT_CFG_SLEW_RATE_FAST	Sets the slew rate to fast.
IOPORT_CFG_REGION_SAFETY	Selects safety region.
IOPORT_CFG_REGION_NSAFETY	Selects non safety region.
IOPORT_CFG_PIM_TTL	This macro has been unsupported.
IOPORT_CFG_NMOS_ENABLE	This macro has been unsupported.
IOPORT_CFG_PMOS_ENABLE	This macro has been unsupported.
IOPORT_CFG_DRIVE_HS_HIGH	This macro has been unsupported.
IOPORT_CFG_DRIVE_MID_IIC	This macro has been unsupported.
IOPORT_CFG_EVENT_RISING_EDGE	This macro has been unsupported.
IOPORT_CFG_EVENT_FALLING_EDGE	This macro has been unsupported.
IOPORT_CFG_EVENT_BOTH_EDGES	This macro has been unsupported.
IOPORT_CFG_IRQ_ENABLE	This macro has been unsupported.
IOPORT_CFG_ANALOG_ENABLE	This macro has been unsupported.
IOPORT_CFG_PERIPHERAL_PIN	This macro has been unsupported.

poe3_state_t [2/2]

enum poe3_state_t

POE3 states.

Enumerator
POE3_STATE_NO_DISABLE_REQUEST	Timer output is not disabled by POE3.
POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE0# pin.
POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE4# pin.
POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE8# pin.
POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE10# pin.
POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE11# pin.
POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST	Timer output disabled due to poe3_api_t::outputDisable()
POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST	Timer output disabled due to main oscillator stop.
POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST	Timer output disabled due to output short circuit 1.
POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST	Timer output disabled due to output short circuit 2.
POE3_STATE_NO_DISABLE_REQUEST	Timer output is not disabled by POE3.
POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE0# pin.
POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE4# pin.
POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE8# pin.
POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE10# pin.
POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE11# pin.
POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST	Timer output disabled due to poe3_api_t::outputDisable()
POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST	Timer output disabled due to main oscillator stop.
POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST	Timer output disabled due to output short circuit 1.
POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST	Timer output disabled due to output short circuit 2.
POE3_STATE_DSMIF0_ERROR_REQUEST	Timer output disabled due to DSMIF0 Error0. Timer output disabled due to DSMIF0 error.
POE3_STATE_DSMIF1_ERROR_REQUEST	Timer output disabled due to DSMIF1 Error0. Timer output disabled due to DSMIF1 error.
POE3_STATE_DSMIF2_ERROR_REQUEST	Timer output disabled due to DSMIF2 Error0.
POE3_STATE_DSMIF3_ERROR_REQUEST	Timer output disabled due to DSMIF3 Error0.
POE3_STATE_DSMIF4_ERROR_REQUEST	Timer output disabled due to DSMIF4 Error0.
POE3_STATE_DSMIF5_ERROR_REQUEST	Timer output disabled due to DSMIF5 Error0.
POE3_STATE_DSMIF7_ERROR_REQUEST	Timer output disabled due to DSMIF7 Error0.
POE3_STATE_DSMIF8_ERROR_REQUEST	Timer output disabled due to DSMIF8 Error0.
POE3_STATE_DSMIF0_1_ERROR_REQUEST	Timer output disabled due to DSMIF0 Error1.
POE3_STATE_DSMIF1_1_ERROR_REQUEST	Timer output disabled due to DSMIF1 Error1.
POE3_STATE_DSMIF2_1_ERROR_REQUEST	Timer output disabled due to DSMIF2 Error1.
POE3_STATE_DSMIF3_1_ERROR_REQUEST	Timer output disabled due to DSMIF3 Error1.
POE3_STATE_DSMIF4_1_ERROR_REQUEST	Timer output disabled due to DSMIF4 Error1.
POE3_STATE_DSMIF5_1_ERROR_REQUEST	Timer output disabled due to DSMIF5 Error1.
POE3_STATE_DSMIF7_1_ERROR_REQUEST	Timer output disabled due to DSMIF7 Error1.
POE3_STATE_DSMIF8_1_ERROR_REQUEST	Timer output disabled due to DSMIF8 Error1.
POE3_STATE_NO_DISABLE_REQUEST	Timer output is not disabled by POE3.
POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE0# pin.
POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE4# pin.
POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE8# pin.
POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE10# pin.
POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST	Timer output disabled due to POE11# pin.
POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST	Timer output disabled due to poe3_api_t::outputDisable()
POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST	Timer output disabled due to main oscillator stop.
POE3_STATE_DSMIF0_ERROR_REQUEST	Timer output disabled due to DSMIF0 Error0. Timer output disabled due to DSMIF0 error.
POE3_STATE_DSMIF1_ERROR_REQUEST	Timer output disabled due to DSMIF1 Error0. Timer output disabled due to DSMIF1 error.
POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST	Timer output disabled due to output short circuit 1.
POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST	Timer output disabled due to output short circuit 2.

poe3_active_level_t [2/2]

enum poe3_active_level_t

POE3 active level for short circuit detection.

Enumerator
POE3_ACTIVE_LEVEL_HIGH	High level is set as the active level to detect a short circuit.
POE3_ACTIVE_LEVEL_LOW	Low level is set as the active level to detect a short circuit.
POE3_ACTIVE_LEVEL_SETTING_NONE	The active level of the pin is set by the timer peripheral side, not by POE3.
POE3_ACTIVE_LEVEL_HIGH	High level is set as the active level to detect a short circuit.
POE3_ACTIVE_LEVEL_LOW	Low level is set as the active level to detect a short circuit.
POE3_ACTIVE_LEVEL_SETTING_NONE	The active level of the pin is set by the timer peripheral side, not by POE3.
POE3_ACTIVE_LEVEL_HIGH	High level is set as the active level to detect a short circuit.
POE3_ACTIVE_LEVEL_LOW	Low level is set as the active level to detect a short circuit.
POE3_ACTIVE_LEVEL_SETTING_NONE	The active level of the pin is set by the timer peripheral side, not by POE3.

poeg_state_t [2/2]

enum poeg_state_t

POEG states.

Enumerator
POEG_STATE_NO_DISABLE_REQUEST	GPT output is not disabled by POEG.
POEG_STATE_PIN_DISABLE_REQUEST	GPT output disabled due to GTETRG pin level.
POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST	GPT output disabled due to high speed analog comparator or GPT.
POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST	GPT output disabled due to main oscillator stop.
POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST	GPT output disabled due to poeg_api_t::outputDisable()
POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE	GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input.
POEG_STATE_NO_DISABLE_REQUEST	GPT output is not disabled by POEG.
POEG_STATE_PIN_DISABLE_REQUEST	GPT output disabled due to GTETRG pin level.
POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST	GPT output disabled due to high speed analog comparator or GPT.
POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST	GPT output disabled due to main oscillator stop.
POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST	GPT output disabled due to poeg_api_t::outputDisable()
POEG_STATE_DSMIF0_DISABLE_REQUEST	GPT output disabled due to DSMIF0 error 0.
POEG_STATE_DSMIF1_DISABLE_REQUEST	GPT output disabled due to DSMIF1 error 0.
POEG_STATE_DSMIF2_DISABLE_REQUEST	GPT output disabled due to DSMIF2 error 0.
POEG_STATE_DSMIF3_DISABLE_REQUEST	GPT output disabled due to DSMIF3 error 0.
POEG_STATE_DSMIF4_DISABLE_REQUEST	GPT output disabled due to DSMIF4 error 0.
POEG_STATE_DSMIF5_DISABLE_REQUEST	GPT output disabled due to DSMIF5 error 0.
POEG_STATE_DSMIF7_DISABLE_REQUEST	GPT output disabled due to DSMIF7 error 0.
POEG_STATE_DSMIF8_DISABLE_REQUEST	GPT output disabled due to DSMIF8 error 0.
POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE	GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input.
POEG_STATE_DSMIF0_1_DISABLE_REQUEST	GPT output disabled due to DSMIF0 error 1.
POEG_STATE_DSMIF1_1_DISABLE_REQUEST	GPT output disabled due to DSMIF1 error 1.
POEG_STATE_DSMIF2_1_DISABLE_REQUEST	GPT output disabled due to DSMIF2 error 1.
POEG_STATE_DSMIF3_1_DISABLE_REQUEST	GPT output disabled due to DSMIF3 error 1.
POEG_STATE_DSMIF4_1_DISABLE_REQUEST	GPT output disabled due to DSMIF4 error 1.
POEG_STATE_DSMIF5_1_DISABLE_REQUEST	GPT output disabled due to DSMIF5 error 1.
POEG_STATE_DSMIF7_1_DISABLE_REQUEST	GPT output disabled due to DSMIF7 error 1.
POEG_STATE_DSMIF8_1_DISABLE_REQUEST	GPT output disabled due to DSMIF8 error 1.
POEG_STATE_NO_DISABLE_REQUEST	GPT output is not disabled by POEG.
POEG_STATE_PIN_DISABLE_REQUEST	GPT output disabled due to GTETRG pin level.
POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST	GPT output disabled due to high speed analog comparator or GPT.
POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST	GPT output disabled due to main oscillator stop.
POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST	GPT output disabled due to poeg_api_t::outputDisable()
POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE	GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input.
POEG_STATE_DSMIF0_DISABLE_REQUEST	GPT output disabled due to DSMIF0 error 0.
POEG_STATE_DSMIF1_DISABLE_REQUEST	GPT output disabled due to DSMIF1 error 0.

poeg_trigger_t [2/2]

enum poeg_trigger_t

Triggers that will disable GPT output pins.

Enumerator
POEG_TRIGGER_SOFTWARE	Software disable is always supported with POEG. Select this option if no other triggers are used.
POEG_TRIGGER_PIN	Disable GPT output based on GTETRG input level. Disable GPT output based on GTETRG input level(PIDE)
POEG_TRIGGER_GPT_OUTPUT_LEVEL	Disable GPT output based on GPT output pin levels. Disable GPT output based on GPT output pin levels(IOCE)
POEG_TRIGGER_OSCILLATION_STOP	Disable GPT output based on main oscillator stop. Disable GPT output based on main oscillator stop(OSPTE)
POEG_TRIGGER_ACMPHS0	Disable GPT output based on ACMPHS0 comparator result.
POEG_TRIGGER_ACMPHS1	Disable GPT output based on ACMPHS1 comparator result.
POEG_TRIGGER_ACMPHS2	Disable GPT output based on ACMPHS2 comparator result.
POEG_TRIGGER_ACMPHS3	Disable GPT output based on ACMPHS3 comparator result.
POEG_TRIGGER_ACMPHS4	Disable GPT output based on ACMPHS4 comparator result.
POEG_TRIGGER_ACMPHS5	Disable GPT output based on ACMPHS5 comparator result.
POEG_TRIGGER_SOFTWARE	Software disable is always supported with POEG. Select this option if no other triggers are used.
POEG_TRIGGER_PIN	Disable GPT output based on GTETRG input level. Disable GPT output based on GTETRG input level(PIDE)
POEG_TRIGGER_GPT_OUTPUT_LEVEL	Disable GPT output based on GPT output pin levels. Disable GPT output based on GPT output pin levels(IOCE)
POEG_TRIGGER_OSCILLATION_STOP	Disable GPT output based on main oscillator stop. Disable GPT output based on main oscillator stop(OSPTE)
POEG_TRIGGER_ACMPHS0	Disable GPT output based on ACMPHS0 comparator result.
POEG_TRIGGER_ACMPHS1	Disable GPT output based on ACMPHS1 comparator result.
POEG_TRIGGER_ACMPHS2	Disable GPT output based on ACMPHS2 comparator result.
POEG_TRIGGER_ACMPHS3	Disable GPT output based on ACMPHS3 comparator result.
POEG_TRIGGER_ACMPHS4	Disable GPT output based on ACMPHS4 comparator result.
POEG_TRIGGER_ACMPHS5	Disable GPT output based on ACMPHS5 comparator result.
POEG_TRIGGER_D0ERR0E	Permit output disabled by DSMIF0 error detection. The GPT output pins can be disabled when DSMIF error occurs (LLPP only).
POEG_TRIGGER_D1ERR0E	Permit output disabled by DSMIF1 error detection.
POEG_TRIGGER_D2ERR0E	Permit output disabled by DSMIF2 error detection.
POEG_TRIGGER_D3ERR0E	Permit output disabled by DSMIF3 error detection.
POEG_TRIGGER_D4ERR0E	Permit output disabled by DSMIF4 error detection.
POEG_TRIGGER_D5ERR0E	Permit output disabled by DSMIF5 error detection.
POEG_TRIGGER_D7ERR0E	Permit output disabled by DSMIF7 error detection.
POEG_TRIGGER_D8ERR0E	Permit output disabled by DSMIF8 error detection.
POEG_TRIGGER_D0ERR1E	Permit output disabled by DSMIF0 error 1 detection.
POEG_TRIGGER_D1ERR1E	Permit output disabled by DSMIF1 error 1 detection.
POEG_TRIGGER_D2ERR1E	Permit output disabled by DSMIF2 error 1 detection.
POEG_TRIGGER_D3ERR1E	Permit output disabled by DSMIF3 error 1 detection.
POEG_TRIGGER_D4ERR1E	Permit output disabled by DSMIF4 error 1 detection.
POEG_TRIGGER_D5ERR1E	Permit output disabled by DSMIF5 error 1 detection.
POEG_TRIGGER_D7ERR1E	Permit output disabled by DSMIF7 error 1 detection.
POEG_TRIGGER_D8ERR1E	Permit output disabled by DSMIF8 error 1 detection.
POEG_TRIGGER_SOFTWARE	Software disable is always supported with POEG. Select this option if no other triggers are used.
POEG_TRIGGER_PIN	Disable GPT output based on GTETRG input level. Disable GPT output based on GTETRG input level(PIDE)
POEG_TRIGGER_GPT_OUTPUT_LEVEL	Disable GPT output based on GPT output pin levels. Disable GPT output based on GPT output pin levels(IOCE)
POEG_TRIGGER_OSCILLATION_STOP	Disable GPT output based on main oscillator stop. Disable GPT output based on main oscillator stop(OSPTE)
POEG_TRIGGER_ACMPHS0	Disable GPT output based on ACMPHS0 comparator result.
POEG_TRIGGER_ACMPHS1	Disable GPT output based on ACMPHS1 comparator result.
POEG_TRIGGER_ACMPHS2	Disable GPT output based on ACMPHS2 comparator result.
POEG_TRIGGER_ACMPHS3	Disable GPT output based on ACMPHS3 comparator result.
POEG_TRIGGER_ACMPHS4	Disable GPT output based on ACMPHS4 comparator result.
POEG_TRIGGER_ACMPHS5	Disable GPT output based on ACMPHS5 comparator result.
POEG_TRIGGER_DERR0E	Permit output disabled by DSMIF0 error detection. The GPT output pins can be disabled when DSMIF error occurs (LLPP only).
POEG_TRIGGER_DERR1E	Permit output disabled by DSMIF1 error detection.

transfer_event_t [2/2]

enum transfer_event_t

Events that can trigger a callback function.

Enumerator
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.

transfer_mode_t [2/2]

enum transfer_mode_t

Transfer mode describes what will happen when a transfer request occurs.

Enumerator
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_REPEAT	Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the repeat area and the transfer length will be reset to their initial values. If DMAC is used, the transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is used, the transfer repeats continuously (no limit to the number of repeat transfers).
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_REPEAT_BLOCK	In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets within a block (to split blocks into arrays of their first data, second data, etc.)
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.

transfer_size_t [2/2]

enum transfer_size_t

Transfer size specifies the size of each individual transfer.

Enumerator
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.

transfer_addr_mode_t [2/2]

enum transfer_addr_mode_t

Address mode specifies whether to modify (increment or decrement) pointer after each transfer.

Enumerator
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_OFFSET	Offset is added to the address pointer after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZN::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_DECREMENTED	Address pointer is decremented by associated transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZN::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZN::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.

Function Documentation

SystemCoreClockUpdate()

void RZN::SystemCoreClockUpdate

(

void

)

Update SystemCoreClock variable based on current clock settings.

bsp_prv_clock_set()

void RZN::bsp_prv_clock_set	(	uint32_t	sckcr,
		uint32_t	sckcr2,
		uint32_t	sckcr3,
		uint32_t	sckcr4
	)

Applies system core clock source and divider changes. The MPU is expected to be in high speed mode during this configuration and the CGC registers are expected to be unlocked in PRCR.

Parameters

[in]	sckcr	Value to set in SCKCR register
[in]	sckcr2	Value to set in SCKCR2 register
[in]	sckcr3	Value to set in SCKCR3 register
[in]	sckcr4	Value to set in SCKCR4 register

bsp_clock_init()

void RZN::bsp_clock_init

(

void

)

Initializes system clocks. Makes no assumptions about current register settings.

bsp_irq_cfg()

void RZN::bsp_irq_cfg

(

void

)

Initialize interrupt controller.

Return values

None	In this device, this function does nothing. This function is written to share code with other devices.

Using the vector table information section that has been built by the linker and placed into ROM in the .vector_info. section, this function will initialize the ICU so that configured ELC events will trigger interrupts in the NVIC.

bsp_irq_core_cfg()

void RZN::bsp_irq_core_cfg

(

void

)

Initialize interrupt controller.

Using the vector table information section that has been built by the linker and placed into ROM in the .vector_info. section, this function will initialize the ICU so that configured ELC events will trigger interrupts in the NVIC.

bsp_common_interrupt_handler()

void RZN::bsp_common_interrupt_handler

(

uint32_t

id

)

This function is called first when an interrupt is generated and branches to each interrupt isr function.

Parameters

[in]

id

GIC INTID used to identify the interrupt.