![]() |
RZ Flexible Software Package Documentation
Release v4.0.0
|
|
Default initialization function. More...
Functions | |
| fsp_err_t | R_FSP_VersionGet (fsp_pack_version_t *const p_version) |
| fsp_err_t | R_ADC_Open (adc_ctrl_t *p_ctrl, adc_cfg_t const *const p_cfg) |
| fsp_err_t | R_ADC_ScanCfg (adc_ctrl_t *p_ctrl, void const *const p_channel_cfg) |
| fsp_err_t | R_ADC_CallbackSet (adc_ctrl_t *const p_ctrl, void(*p_callback)(adc_callback_args_t *), void *const p_context, adc_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_ADC_ScanStart (adc_ctrl_t *p_ctrl) |
| fsp_err_t | R_ADC_ScanGroupStart (adc_ctrl_t *p_ctrl, adc_group_mask_t group_mask) |
| fsp_err_t | R_ADC_ScanStop (adc_ctrl_t *p_ctrl) |
| fsp_err_t | R_ADC_StatusGet (adc_ctrl_t *p_ctrl, adc_status_t *p_status) |
| fsp_err_t | R_ADC_Read (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint16_t *const p_data) |
| fsp_err_t | R_ADC_Read32 (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint32_t *const p_data) |
| fsp_err_t | R_ADC_SampleStateCountSet (adc_ctrl_t *p_ctrl, adc_sample_state_t *p_sample) |
| fsp_err_t | R_ADC_InfoGet (adc_ctrl_t *p_ctrl, adc_info_t *p_adc_info) |
| fsp_err_t | R_ADC_Close (adc_ctrl_t *p_ctrl) |
| fsp_err_t | R_ADC_Calibrate (adc_ctrl_t *const p_ctrl, void const *p_extend) |
| fsp_err_t | R_ADC_OffsetSet (adc_ctrl_t *const p_ctrl, adc_channel_t const reg_id, int32_t offset) |
| fsp_err_t | R_BSC_Open (external_bus_ctrl_t *p_ctrl, external_bus_cfg_t const *const p_cfg) |
| fsp_err_t | R_BSC_Close (external_bus_ctrl_t *p_ctrl) |
| fsp_err_t | R_BSC_CallbackSet (external_bus_ctrl_t *p_ctrl, void(*p_callback)(bsc_callback_args_t *), void *const p_context, bsc_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_BSC_NOR_Open (nor_flash_ctrl_t *p_ctrl, nor_flash_cfg_t const *const p_cfg) |
| fsp_err_t | R_BSC_NOR_Write (nor_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint8_t *const p_dest, uint32_t byte_count) |
| fsp_err_t | R_BSC_NOR_Erase (nor_flash_ctrl_t *p_ctrl, uint8_t *const p_device_address, uint32_t byte_count) |
| fsp_err_t | R_BSC_NOR_StatusGet (nor_flash_ctrl_t *p_ctrl, uint8_t *const p_device_address, nor_flash_status_t *const p_status) |
| fsp_err_t | R_BSC_NOR_Close (nor_flash_ctrl_t *p_ctrl) |
| fsp_err_t | R_BSC_SDRAM_Open (sdram_ctrl_t *p_ctrl, sdram_cfg_t const *const p_cfg) |
| fsp_err_t | R_BSC_SDRAM_SelfRefreshEnter (sdram_ctrl_t *p_ctrl) |
| fsp_err_t | R_BSC_SDRAM_SelfRefreshExit (sdram_ctrl_t *p_ctrl) |
| fsp_err_t | R_BSC_SDRAM_PowerDownEnter (sdram_ctrl_t *p_ctrl) |
| fsp_err_t | R_BSC_SDRAM_PowerDownExit (sdram_ctrl_t *p_ctrl) |
| fsp_err_t | R_BSC_SDRAM_Close (sdram_ctrl_t *p_ctrl) |
| fsp_err_t | R_CANFD_Open (can_ctrl_t *const p_ctrl, can_cfg_t const *const p_cfg) |
| fsp_err_t | R_CANFD_Close (can_ctrl_t *const p_ctrl) |
| fsp_err_t | R_CANFD_Write (can_ctrl_t *const p_ctrl, uint32_t const buffer, can_frame_t *const p_frame) |
| fsp_err_t | R_CANFD_Read (can_ctrl_t *const p_ctrl, uint32_t const buffer, can_frame_t *const p_frame) |
| fsp_err_t | R_CANFD_ModeTransition (can_ctrl_t *const p_ctrl, can_operation_mode_t operation_mode, can_test_mode_t test_mode) |
| fsp_err_t | R_CANFD_InfoGet (can_ctrl_t *const p_ctrl, can_info_t *const p_info) |
| fsp_err_t | R_CANFD_CallbackSet (can_ctrl_t *const p_ctrl, void(*p_callback)(can_callback_args_t *), void *const p_context, can_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_CGC_Open (cgc_ctrl_t *const p_ctrl, cgc_cfg_t const *const p_cfg) |
| fsp_err_t | R_CGC_ClocksCfg (cgc_ctrl_t *const p_ctrl, cgc_clocks_cfg_t const *const p_clock_cfg) |
| fsp_err_t | R_CGC_ClockStart (cgc_ctrl_t *const p_ctrl, cgc_clock_t clock_source, cgc_pll_cfg_t const *const p_pll_cfg) |
| fsp_err_t | R_CGC_ClockStop (cgc_ctrl_t *const p_ctrl, cgc_clock_t clock_source) |
| fsp_err_t | R_CGC_ClockCheck (cgc_ctrl_t *const p_ctrl, cgc_clock_t clock_source) |
| fsp_err_t | R_CGC_SystemClockSet (cgc_ctrl_t *const p_ctrl, cgc_clock_t clock_source, cgc_divider_cfg_t const *const p_divider_cfg) |
| fsp_err_t | R_CGC_SystemClockGet (cgc_ctrl_t *const p_ctrl, cgc_clock_t *const p_clock_source, cgc_divider_cfg_t *const p_divider_cfg) |
| fsp_err_t | R_CGC_OscStopDetectEnable (cgc_ctrl_t *const p_ctrl) |
| fsp_err_t | R_CGC_OscStopDetectDisable (cgc_ctrl_t *const p_ctrl) |
| fsp_err_t | R_CGC_OscStopStatusClear (cgc_ctrl_t *const p_ctrl) |
| fsp_err_t | R_CGC_CallbackSet (cgc_ctrl_t *const p_ctrl, void(*p_callback)(cgc_callback_args_t *), void *const p_context, cgc_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_CGC_Close (cgc_ctrl_t *const p_ctrl) |
| fsp_err_t | R_CMT_Open (timer_ctrl_t *const p_ctrl, timer_cfg_t const *const p_cfg) |
| fsp_err_t | R_CMT_Stop (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_CMT_Start (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_CMT_Reset (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_CMT_Enable (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_CMT_Disable (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_CMT_PeriodSet (timer_ctrl_t *const p_ctrl, uint32_t const period_counts) |
| fsp_err_t | R_CMT_DutyCycleSet (timer_ctrl_t *const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin) |
| fsp_err_t | R_CMT_InfoGet (timer_ctrl_t *const p_ctrl, timer_info_t *const p_info) |
| fsp_err_t | R_CMT_StatusGet (timer_ctrl_t *const p_ctrl, timer_status_t *const p_status) |
| fsp_err_t | R_CMT_CounterSet (timer_ctrl_t *const p_ctrl, uint32_t counter) |
| fsp_err_t | R_CMT_CallbackSet (timer_ctrl_t *const p_ctrl, void(*p_callback)(timer_callback_args_t *), void *const p_context, timer_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_CMT_CompareMatchSet (timer_ctrl_t *const p_ctrl, uint32_t const compare_match_value, timer_compare_match_t const match_channel) |
| fsp_err_t | R_CMT_Close (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_CMTW_Close (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_CMTW_PeriodSet (timer_ctrl_t *const p_ctrl, uint32_t const period_counts) |
| fsp_err_t | R_CMTW_DutyCycleSet (timer_ctrl_t *const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin) |
| fsp_err_t | R_CMTW_Reset (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_CMTW_Start (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_CMTW_Enable (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_CMTW_Disable (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_CMTW_InfoGet (timer_ctrl_t *const p_ctrl, timer_info_t *const p_info) |
| fsp_err_t | R_CMTW_StatusGet (timer_ctrl_t *const p_ctrl, timer_status_t *const p_status) |
| fsp_err_t | R_CMTW_Stop (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_CMTW_Open (timer_ctrl_t *const p_ctrl, timer_cfg_t const *const p_cfg) |
| fsp_err_t | R_CMTW_OutputEnable (timer_ctrl_t *const p_ctrl, cmtw_io_pin_t pin) |
| fsp_err_t | R_CMTW_OutputDisable (timer_ctrl_t *const p_ctrl, cmtw_io_pin_t pin) |
| fsp_err_t | R_CMTW_CallbackSet (timer_ctrl_t *const p_ctrl, void(*p_callback)(timer_callback_args_t *), void *const p_context, timer_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_CMTW_CompareMatchSet (timer_ctrl_t *const p_ctrl, uint32_t const compare_match_value, timer_compare_match_t const match_channel) |
| fsp_err_t | R_CRC_Open (crc_ctrl_t *const p_ctrl, crc_cfg_t const *const p_cfg) |
| fsp_err_t | R_CRC_Close (crc_ctrl_t *const p_ctrl) |
| fsp_err_t | R_CRC_Calculate (crc_ctrl_t *const p_ctrl, crc_input_t *const p_crc_input, uint32_t *calculatedValue) |
| fsp_err_t | R_CRC_CalculatedValueGet (crc_ctrl_t *const p_ctrl, uint32_t *calculatedValue) |
| fsp_err_t | R_CRC_SnoopEnable (crc_ctrl_t *const p_ctrl, uint32_t crc_seed) |
| fsp_err_t | R_CRC_SnoopDisable (crc_ctrl_t *const p_ctrl) |
| fsp_err_t | R_DMAC_Open (transfer_ctrl_t *const p_ctrl, transfer_cfg_t const *const p_cfg) |
| fsp_err_t | R_DMAC_Reconfigure (transfer_ctrl_t *const p_ctrl, transfer_info_t *p_info) |
| fsp_err_t | R_DMAC_Reset (transfer_ctrl_t *const p_ctrl, void const *volatile p_src, void *volatile p_dest, uint16_t const num_transfers) |
| fsp_err_t | R_DMAC_SoftwareStart (transfer_ctrl_t *const p_ctrl, transfer_start_mode_t mode) |
| fsp_err_t | R_DMAC_SoftwareStop (transfer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_DMAC_Enable (transfer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_DMAC_Disable (transfer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_DMAC_InfoGet (transfer_ctrl_t *const p_ctrl, transfer_properties_t *const p_info) |
| fsp_err_t | R_DMAC_Close (transfer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_DMAC_Reload (transfer_ctrl_t *const p_ctrl, void const *p_src, void *p_dest, uint32_t const num_transfers) |
| fsp_err_t | R_DMAC_CallbackSet (transfer_ctrl_t *const p_ctrl, void(*p_callback)(transfer_callback_args_t *), void *const p_context, transfer_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_DMAC_LinkDescriptorSet (transfer_ctrl_t *const p_ctrl, dmac_link_cfg_t *p_descriptor) |
| fsp_err_t | R_DSMIF_Open (adc_ctrl_t *p_ctrl, adc_cfg_t const *const p_cfg) |
| fsp_err_t | R_DSMIF_ScanStart (adc_ctrl_t *p_ctrl) |
| fsp_err_t | R_DSMIF_ScanStop (adc_ctrl_t *p_ctrl) |
| fsp_err_t | R_DSMIF_CfgSet (adc_ctrl_t *p_ctrl, adc_cfg_t const *const p_cfg) |
| fsp_err_t | R_DSMIF_StatusGet (adc_ctrl_t *p_ctrl, adc_status_t *p_status) |
| fsp_err_t | R_DSMIF_ErrorStatusGet (adc_ctrl_t *p_ctrl, dsmif_error_status_t *p_error_status) |
| fsp_err_t | R_DSMIF_Read (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint32_t *const p_data) |
| fsp_err_t | R_DSMIF_Close (adc_ctrl_t *p_ctrl) |
| fsp_err_t | R_DSMIF_CallbackSet (adc_ctrl_t *const p_ctrl, void(*p_callback)(adc_callback_args_t *), void *const p_context, adc_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_ELC_Open (elc_ctrl_t *const p_ctrl, elc_cfg_t const *const p_cfg) |
| fsp_err_t | R_ELC_Close (elc_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ELC_SoftwareEventGenerate (elc_ctrl_t *const p_ctrl, elc_software_event_t event_number) |
| fsp_err_t | R_ELC_LinkSet (elc_ctrl_t *const p_ctrl, elc_peripheral_t peripheral, elc_event_t signal) |
| fsp_err_t | R_ELC_LinkBreak (elc_ctrl_t *const p_ctrl, elc_peripheral_t peripheral) |
| fsp_err_t | R_ELC_Enable (elc_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ELC_Disable (elc_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ETHER_PHY_Open (ether_phy_ctrl_t *const p_ctrl, ether_phy_cfg_t const *const p_cfg) |
| fsp_err_t | R_ETHER_PHY_Close (ether_phy_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ETHER_PHY_ChipInit (ether_phy_ctrl_t *const p_ctrl, ether_phy_cfg_t const *const p_cfg) |
| Initialize Ethernet PHY device. Implements ether_phy_api_t::chipInit. More... | |
| fsp_err_t | R_ETHER_PHY_Read (ether_phy_ctrl_t *const p_ctrl, uint32_t reg_addr, uint32_t *const p_data) |
| Read data from register of PHY-LSI . Implements ether_phy_api_t::read. More... | |
| fsp_err_t | R_ETHER_PHY_Write (ether_phy_ctrl_t *const p_ctrl, uint32_t reg_addr, uint32_t data) |
| Write data to register of PHY-LSI . Implements ether_phy_api_t::write. More... | |
| fsp_err_t | R_ETHER_PHY_StartAutoNegotiate (ether_phy_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ETHER_PHY_LinkPartnerAbilityGet (ether_phy_ctrl_t *const p_ctrl, uint32_t *const p_line_speed_duplex, uint32_t *const p_local_pause, uint32_t *const p_partner_pause) |
| fsp_err_t | R_ETHER_PHY_LinkStatusGet (ether_phy_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ETHER_SELECTOR_Open (ether_selector_ctrl_t *const p_ctrl, ether_selector_cfg_t const *const p_cfg) |
| fsp_err_t | R_ETHER_SELECTOR_Close (ether_selector_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ETHER_SELECTOR_ConverterSet (ether_selector_ctrl_t *const p_ctrl, ether_selector_speed_t speed, ether_selector_duplex_t duplex) |
| fsp_err_t | R_ETHSW_Open (ether_switch_ctrl_t *const p_ctrl, ether_switch_cfg_t const *const p_cfg) |
| fsp_err_t | R_ETHSW_Close (ether_switch_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ETHSW_SpeedCfg (ether_switch_ctrl_t *const p_ctrl, uint32_t const port, ethsw_link_speed_t const speed) |
| fsp_err_t | R_ETHSW_MacTableSet (ether_switch_ctrl_t *const p_ctrl, ethsw_mac_table_entry_addr_t *p_mac_entry_addr, ethsw_mac_table_entry_info_t *p_mac_entry_info) |
| fsp_err_t | R_ETHSW_MacTableGet (ether_switch_ctrl_t *const p_ctrl, ethsw_mac_table_entry_addr_t *p_mac_entry_addr, ethsw_mac_table_entry_info_t *p_mac_entry_info) |
| fsp_err_t | R_ETHSW_MacTableConfigSet (ether_switch_ctrl_t *const p_ctrl, ethsw_mac_table_config_t *p_mac_table_config) |
| fsp_err_t | R_ETHSW_MacTableClear (ether_switch_ctrl_t *const p_ctrl, ethsw_mac_table_clear_mode_t *p_mac_table_clear) |
| fsp_err_t | R_ETHSW_LearningSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool enable) |
| fsp_err_t | R_ETHSW_PortForwardAdd (ether_switch_ctrl_t *const p_ctrl, uint32_t port) |
| fsp_err_t | R_ETHSW_PortForwardDel (ether_switch_ctrl_t *const p_ctrl, uint32_t port) |
| fsp_err_t | R_ETHSW_FloodUnknownSet (ether_switch_ctrl_t *const p_ctrl, ethsw_flood_unknown_config_t *p_flood_config) |
| fsp_err_t | R_ETHSW_LinkStateGet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_link_status_t *p_state_link) |
| fsp_err_t | R_ETHSW_FrameSizeMaxSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, uint32_t frame_size_max) |
| fsp_err_t | R_ETHSW_DlrInitSet (ether_switch_ctrl_t *const p_ctrl, ethsw_dlr_init_t *p_dlr_init) |
| fsp_err_t | R_ETHSW_DlrUninitSet (ether_switch_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ETHSW_DlrEnableSet (ether_switch_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ETHSW_DlrDisableSet (ether_switch_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ETHSW_DlrBeaconStateGet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_dlr_beacon_state_t *p_beacon_state) |
| fsp_err_t | R_ETHSW_DlrNodeStateGet (ether_switch_ctrl_t *const p_ctrl, ethsw_dlr_node_state_t *p_node_state) |
| fsp_err_t | R_ETHSW_DlrSvIpGet (ether_switch_ctrl_t *const p_ctrl, uint32_t *p_ip_addr) |
| fsp_err_t | R_ETHSW_DlrSvPriorityGet (ether_switch_ctrl_t *const p_ctrl, uint8_t *p_priority) |
| fsp_err_t | R_ETHSW_DlrVlanGet (ether_switch_ctrl_t *const p_ctrl, uint16_t *p_vlan_info) |
| fsp_err_t | R_ETHSW_DlrSvMacGet (ether_switch_ctrl_t *const p_ctrl, ethsw_mac_addr_t *p_addr_mac) |
| fsp_err_t | R_ETHSW_RxPatternMatcherSet (ether_switch_ctrl_t *const p_ctrl, ethsw_rx_pattern_matcher_t *p_rx_pattern_matcher) |
| fsp_err_t | R_ETHSW_RxPatternMatcherCallback (ether_switch_ctrl_t *const p_ctrl, void(*p_rx_pattern_callback_func)(ethsw_rx_pattern_event_t event, ethsw_rx_pattern_event_data_t *p_data)) |
| fsp_err_t | R_ETHSW_PreemptQueueSet (ether_switch_ctrl_t *const p_ctrl, ethsw_preempt_queue_t *p_preempt_queue) |
| fsp_err_t | R_ETHSW_PreemptPortControlConfigSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_preempt_port_ctrl_config_t *p_preempt_port_ctrl) |
| fsp_err_t | R_ETHSW_PreemptPortControlEnableSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool frame_preempt_enable) |
| fsp_err_t | R_ETHSW_PreemptHoldReqForceSet (ether_switch_ctrl_t *const p_ctrl, ethsw_port_mask_t holdreq_request_port_mask) |
| fsp_err_t | R_ETHSW_PreemptHoldReqReleaseSet (ether_switch_ctrl_t *const p_ctrl, ethsw_port_mask_t holdreq_release_port_mask) |
| fsp_err_t | R_ETHSW_PreemptStatusGet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_preempt_status_t *p_preempt_status) |
| fsp_err_t | R_ETHSW_MmctlQgateSet (ether_switch_ctrl_t *const p_ctrl, ethsw_mmclt_qgate_t *p_mmctl_qgate) |
| fsp_err_t | R_ETHSW_MmctlPoolSizeSet (ether_switch_ctrl_t *const p_ctrl, ethsw_mmctl_pool_size_t *p_pool_size) |
| fsp_err_t | R_ETHSW_MmctlQueueAssignSet (ether_switch_ctrl_t *const p_ctrl, ethsw_mmctl_queue_assign_t *p_queue_assign) |
| fsp_err_t | R_ETHSW_MmctlYellowLengthSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_yellow_length_t *p_yellow_length) |
| fsp_err_t | R_ETHSW_QueueFlushEventSet (ether_switch_ctrl_t *const p_ctrl, ethsw_queue_flush_event_t *p_queue_flush_event) |
| fsp_err_t | R_ETHSW_MmctlQueueClosedNonemptyStatusGet (ether_switch_ctrl_t *const p_ctrl, ethsw_mmctl_qclosed_nonempty_t *p_qclosed_nonempty) |
| fsp_err_t | R_ETHSW_StatisticsSwitchGet (ether_switch_ctrl_t *const p_ctrl, bool clear, ethsw_statistics_switch_base_t *p_statistics_switch) |
| fsp_err_t | R_ETHSW_StatisticsMacGet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_statistics_mac_t *p_statistics_mac) |
| fsp_err_t | R_ETHSW_StatisticsMacClear (ether_switch_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ETHSW_Statistics8023brGet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool clear, ethsw_statistics_8023br_t *p_statistics_8023br) |
| fsp_err_t | R_ETHSW_StatisticsDlrGet (ether_switch_ctrl_t *const p_ctrl, ethsw_statistics_dlr_t *p_statistics_dlr) |
| fsp_err_t | R_ETHSW_CqfEnableSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_cqf_enable_t *p_cqf_enable) |
| fsp_err_t | R_ETHSW_SnoopParserSet (ether_switch_ctrl_t *const p_ctrl, ethsw_snoop_parser_config_t *p_parser_cnf) |
| fsp_err_t | R_ETHSW_SnoopArithSet (ether_switch_ctrl_t *const p_ctrl, ethsw_snoop_arith_config_t *p_arith_cnf) |
| fsp_err_t | R_ETHSW_EeeSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_eee_t *p_cnf_eee) |
| fsp_err_t | R_ETHSW_StormTimeSet (ether_switch_ctrl_t *const p_ctrl, uint16_t storm_time) |
| fsp_err_t | R_ETHSW_BcastLimitSet (ether_switch_ctrl_t *const p_ctrl, uint16_t storm_frames) |
| fsp_err_t | R_ETHSW_McastLimitSet (ether_switch_ctrl_t *const p_ctrl, uint16_t storm_frames) |
| fsp_err_t | R_ETHSW_TxRateSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, float rate) |
| fsp_err_t | R_ETHSW_QosModeSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_qos_mode_t *p_qos_mode) |
| fsp_err_t | R_ETHSW_QosPrioValnSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_qos_prio_vlan_t *p_qos_prio_vlan) |
| fsp_err_t | R_ETHSW_QosPrioIpSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_qos_prio_ip_t *p_qos_prio_ip) |
| fsp_err_t | R_ETHSW_QosPrioTypeSet (ether_switch_ctrl_t *const p_ctrl, ethsw_qos_prio_type_t *p_qos_prio_ethtype) |
| fsp_err_t | R_ETHSW_MirrorSet (ether_switch_ctrl_t *const p_ctrl, ethsw_mirror_conf_t *p_mirror_conf) |
| fsp_err_t | R_ETHSW_CtEnableSet (ether_switch_ctrl_t *const p_ctrl, ethsw_port_mask_t port_mask) |
| fsp_err_t | R_ETHSW_CtDelaySet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, uint32_t ct_delay) |
| fsp_err_t | R_ETHSW_PulseGeneratorInit (ether_switch_ctrl_t *const p_ctrl, uint32_t time_num) |
| fsp_err_t | R_ETHSW_PulseGeneratorSet (ether_switch_ctrl_t *const p_ctrl, ethsw_ts_pulse_generator_t *p_pulse) |
| fsp_err_t | R_ETHSW_PortAuthSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool auth_state) |
| fsp_err_t | R_ETHSW_PortCtrlDirSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool dir_state) |
| fsp_err_t | R_ETHSW_PortEapolSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool eapol_state) |
| fsp_err_t | R_ETHSW_BpduSet (ether_switch_ctrl_t *const p_ctrl, bool bpdu_state) |
| fsp_err_t | R_ETHSW_VlanDefaultSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, uint16_t vlan_id) |
| fsp_err_t | R_ETHSW_VlanPortAdd (ether_switch_ctrl_t *const p_ctrl, uint32_t port, uint16_t vlan_id) |
| fsp_err_t | R_ETHSW_VlanPortRemove (ether_switch_ctrl_t *const p_ctrl, uint32_t port, uint16_t vlan_id) |
| fsp_err_t | R_ETHSW_VlanInModeSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_vlan_in_mode_t vlan_in_mode) |
| fsp_err_t | R_ETHSW_VlanOutModeSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_vlan_out_mode_t vlan_out_mode) |
| fsp_err_t | R_ETHSW_VlanVerifySet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool enable) |
| fsp_err_t | R_ETHSW_VlanDiscardUnknownSet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, bool enable) |
| fsp_err_t | R_ETHSW_TdmaEnableSet (ether_switch_ctrl_t *const p_ctrl, ethsw_tdma_enable_t *p_tdma_enable) |
| fsp_err_t | R_ETHSW_TdmaScheduleSet (ether_switch_ctrl_t *const p_ctrl, ethsw_tdma_schedule_entry_t *p_tdma_schedule_entry, uint16_t tdma_schedule_entry_count) |
| fsp_err_t | R_ETHSW_TdmaGpioModeSet (ether_switch_ctrl_t *const p_ctrl, uint8_t gpio_num, ethsw_tdma_gpio_mode_t gpio_mode) |
| fsp_err_t | R_ETHSW_TdmaCounter0Set (ether_switch_ctrl_t *const p_ctrl, uint32_t tdma_counter0) |
| fsp_err_t | R_ETHSW_TdmaCounter0Get (ether_switch_ctrl_t *const p_ctrl, uint32_t *p_tdma_counter0) |
| fsp_err_t | R_ETHSW_TdmaCounter1Set (ether_switch_ctrl_t *const p_ctrl, ethsw_tdma_counter1_t *p_tdma_counter1) |
| fsp_err_t | R_ETHSW_TdmaCounter1Get (ether_switch_ctrl_t *const p_ctrl, ethsw_tdma_counter1_t *p_tdma_counter1) |
| fsp_err_t | R_ETHSW_TdmaHoldReqClear (ether_switch_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ETHSW_TimeEnableSet (ether_switch_ctrl_t *const p_ctrl, ethsw_time_enable_t *p_time_enable) |
| fsp_err_t | R_ETHSW_TimeTransmitTimestampSet (ether_switch_ctrl_t *const p_ctrl, ethsw_time_transmit_t *p_time_transmit) |
| fsp_err_t | R_ETHSW_TimeValueSet (ether_switch_ctrl_t *const p_ctrl, ethsw_timestamp_t *p_timestamp) |
| fsp_err_t | R_ETHSW_TimeValueGet (ether_switch_ctrl_t *const p_ctrl, ethsw_timestamp_t *p_timestamp) |
| fsp_err_t | R_ETHSW_TimeValueGetAll (ether_switch_ctrl_t *const p_ctrl, ethsw_timestamp_t *p_timer0, ethsw_timestamp_t *p_timer1) |
| fsp_err_t | R_ETHSW_TimePeerDelaySet (ether_switch_ctrl_t *const p_ctrl, uint32_t port, ethsw_time_peerdelay_t *p_peerdelay) |
| fsp_err_t | R_ETHSW_TimeOffsetSet (ether_switch_ctrl_t *const p_ctrl, ethsw_time_offset_correction_t *p_offset) |
| fsp_err_t | R_ETHSW_TimeRateSet (ether_switch_ctrl_t *const p_ctrl, ethsw_time_rate_correction_t *p_rate) |
| fsp_err_t | R_ETHSW_TimeDomainSet (ether_switch_ctrl_t *const p_ctrl, ethsw_time_domain_t *p_domain) |
| fsp_err_t | R_GMAC_Open (ether_ctrl_t *const p_ctrl, ether_cfg_t const *const p_cfg) |
| fsp_err_t | R_GMAC_Close (ether_ctrl_t *const p_ctrl) |
| fsp_err_t | R_GMAC_Read (ether_ctrl_t *const p_ctrl, void *const p_buffer, uint32_t *const length_bytes) |
| fsp_err_t | R_GMAC_BufferRelease (ether_ctrl_t *const p_ctrl) |
| fsp_err_t | R_GMAC_RxBufferUpdate (ether_ctrl_t *const p_ctrl, void *const p_buffer) |
| fsp_err_t | R_GMAC_Write (ether_ctrl_t *const p_ctrl, void *const p_buffer, uint32_t const frame_length) |
| fsp_err_t | R_GMAC_LinkProcess (ether_ctrl_t *const p_ctrl) |
| fsp_err_t | R_GMAC_GetLinkStatus (ether_ctrl_t *const p_ctrl, uint8_t port, gmac_link_status_t *p_status) |
| fsp_err_t | R_GMAC_WakeOnLANEnable (ether_ctrl_t *const p_ctrl) |
| fsp_err_t | R_GMAC_TxStatusGet (ether_ctrl_t *const p_ctrl, void *const p_buffer_address) |
| fsp_err_t | R_GMAC_CallbackSet (ether_ctrl_t *const p_ctrl, void(*p_callback)(ether_callback_args_t *), void *const p_context, ether_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_GMAC_B_Open (ether_ctrl_t *const p_ctrl, ether_cfg_t const *const p_cfg) |
| fsp_err_t | R_GMAC_B_Close (ether_ctrl_t *const p_ctrl) |
| fsp_err_t | R_GMAC_B_Read (ether_ctrl_t *const p_ctrl, void *const p_buffer, uint32_t *const length_bytes) |
| fsp_err_t | R_GMAC_B_BufferRelease (ether_ctrl_t *const p_ctrl) |
| fsp_err_t | R_GMAC_B_RxBufferUpdate (ether_ctrl_t *const p_ctrl, void *const p_buffer) |
| fsp_err_t | R_GMAC_B_Write (ether_ctrl_t *const p_ctrl, void *const p_buffer, uint32_t const frame_length) |
| fsp_err_t | R_GMAC_B_LinkProcess (ether_ctrl_t *const p_ctrl) |
| fsp_err_t | R_GMAC_B_GetLinkStatus (ether_ctrl_t *const p_ctrl, uint8_t port, gmac_b_link_status_t *p_status) |
| fsp_err_t | R_GMAC_B_WakeOnLANEnable (ether_ctrl_t *const p_ctrl) |
| fsp_err_t | R_GMAC_B_TxStatusGet (ether_ctrl_t *const p_ctrl, void *const p_buffer_address) |
| fsp_err_t | R_GMAC_B_CallbackSet (ether_ctrl_t *const p_ctrl, void(*p_callback)(ether_callback_args_t *), void *const p_context, ether_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_GPT_Open (timer_ctrl_t *const p_ctrl, timer_cfg_t const *const p_cfg) |
| fsp_err_t | R_GPT_Stop (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_GPT_Start (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_GPT_Reset (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_GPT_Enable (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_GPT_Disable (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_GPT_PeriodSet (timer_ctrl_t *const p_ctrl, uint32_t const period_counts) |
| fsp_err_t | R_GPT_DutyCycleSet (timer_ctrl_t *const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin) |
| fsp_err_t | R_GPT_CompareMatchSet (timer_ctrl_t *const p_ctrl, uint32_t const compare_match_value, timer_compare_match_t const match_channel) |
| fsp_err_t | R_GPT_InfoGet (timer_ctrl_t *const p_ctrl, timer_info_t *const p_info) |
| fsp_err_t | R_GPT_StatusGet (timer_ctrl_t *const p_ctrl, timer_status_t *const p_status) |
| fsp_err_t | R_GPT_CounterSet (timer_ctrl_t *const p_ctrl, uint32_t counter) |
| fsp_err_t | R_GPT_OutputEnable (timer_ctrl_t *const p_ctrl, gpt_io_pin_t pin) |
| fsp_err_t | R_GPT_OutputDisable (timer_ctrl_t *const p_ctrl, gpt_io_pin_t pin) |
| fsp_err_t | R_GPT_AdcTriggerSet (timer_ctrl_t *const p_ctrl, gpt_adc_compare_match_t which_compare_match, uint32_t compare_match_value) |
| fsp_err_t | R_GPT_CallbackSet (timer_ctrl_t *const p_ctrl, void(*p_callback)(timer_callback_args_t *), void *const p_context, timer_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_GPT_Close (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_GPT_THREE_PHASE_Open (three_phase_ctrl_t *const p_ctrl, three_phase_cfg_t const *const p_cfg) |
| fsp_err_t | R_GPT_THREE_PHASE_Stop (three_phase_ctrl_t *const p_ctrl) |
| fsp_err_t | R_GPT_THREE_PHASE_Start (three_phase_ctrl_t *const p_ctrl) |
| fsp_err_t | R_GPT_THREE_PHASE_Reset (three_phase_ctrl_t *const p_ctrl) |
| fsp_err_t | R_GPT_THREE_PHASE_DutyCycleSet (three_phase_ctrl_t *const p_ctrl, three_phase_duty_cycle_t *const p_duty_cycle) |
| fsp_err_t | R_GPT_THREE_PHASE_CallbackSet (three_phase_ctrl_t *const p_ctrl, void(*p_callback)(timer_callback_args_t *), void *const p_context, timer_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_GPT_THREE_PHASE_Close (three_phase_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ICU_ExternalIrqOpen (external_irq_ctrl_t *const p_ctrl, external_irq_cfg_t const *const p_cfg) |
| fsp_err_t | R_ICU_ExternalIrqEnable (external_irq_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ICU_ExternalIrqDisable (external_irq_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ICU_ExternalIrqCallbackSet (external_irq_ctrl_t *const p_ctrl, void(*p_callback)(external_irq_callback_args_t *), void *const p_context, external_irq_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_ICU_ExternalIrqClose (external_irq_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ICU_INTER_CPU_IRQ_Open (icu_inter_cpu_irq_ctrl_t *const p_ctrl, icu_inter_cpu_irq_cfg_t const *const p_cfg) |
| fsp_err_t | R_ICU_INTER_CPU_IRQ_Generate (icu_inter_cpu_irq_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ICU_INTER_CPU_IRQ_CallbackSet (icu_inter_cpu_irq_ctrl_t *const p_ctrl, void(*p_callback)(icu_inter_cpu_irq_callback_args_t *), void *const p_context, icu_inter_cpu_irq_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_ICU_INTER_CPU_IRQ_Close (icu_inter_cpu_irq_ctrl_t *const p_ctrl) |
| fsp_err_t | R_IIC_MASTER_Open (i2c_master_ctrl_t *const p_ctrl, i2c_master_cfg_t const *const p_cfg) |
| fsp_err_t | R_IIC_MASTER_Read (i2c_master_ctrl_t *const p_ctrl, uint8_t *const p_dest, uint32_t const bytes, bool const restart) |
| fsp_err_t | R_IIC_MASTER_Write (i2c_master_ctrl_t *const p_ctrl, uint8_t *const p_src, uint32_t const bytes, bool const restart) |
| fsp_err_t | R_IIC_MASTER_Abort (i2c_master_ctrl_t *const p_ctrl) |
| fsp_err_t | R_IIC_MASTER_SlaveAddressSet (i2c_master_ctrl_t *const p_ctrl, uint32_t const slave, i2c_master_addr_mode_t const addr_mode) |
| fsp_err_t | R_IIC_MASTER_Close (i2c_master_ctrl_t *const p_ctrl) |
| fsp_err_t | R_IIC_MASTER_CallbackSet (i2c_master_ctrl_t *const p_ctrl, void(*p_callback)(i2c_master_callback_args_t *), void *const p_context, i2c_master_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_IIC_MASTER_StatusGet (i2c_master_ctrl_t *const p_ctrl, i2c_master_status_t *p_status) |
| fsp_err_t | R_IIC_SLAVE_Open (i2c_slave_ctrl_t *const p_ctrl, i2c_slave_cfg_t const *const p_cfg) |
| fsp_err_t | R_IIC_SLAVE_Read (i2c_slave_ctrl_t *const p_ctrl, uint8_t *const p_dest, uint32_t const bytes) |
| fsp_err_t | R_IIC_SLAVE_Write (i2c_slave_ctrl_t *const p_ctrl, uint8_t *const p_src, uint32_t const bytes) |
| fsp_err_t | R_IIC_SLAVE_Close (i2c_slave_ctrl_t *const p_ctrl) |
| fsp_err_t | R_IIC_SLAVE_CallbackSet (i2c_slave_ctrl_t *const p_ctrl, void(*p_callback)(i2c_slave_callback_args_t *), void *const p_context, i2c_slave_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_IOPORT_Open (ioport_ctrl_t *const p_ctrl, const ioport_cfg_t *p_cfg) |
| fsp_err_t | R_IOPORT_Close (ioport_ctrl_t *const p_ctrl) |
| fsp_err_t | R_IOPORT_PinsCfg (ioport_ctrl_t *const p_ctrl, const ioport_cfg_t *p_cfg) |
| fsp_err_t | R_IOPORT_PinCfg (ioport_ctrl_t *const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg) |
| fsp_err_t | R_IOPORT_PinEventInputRead (ioport_ctrl_t *const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t *p_pin_event) |
| fsp_err_t | R_IOPORT_PinEventOutputWrite (ioport_ctrl_t *const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value) |
| fsp_err_t | R_IOPORT_PinRead (ioport_ctrl_t *const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t *p_pin_value) |
| fsp_err_t | R_IOPORT_PinWrite (ioport_ctrl_t *const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level) |
| fsp_err_t | R_IOPORT_PortDirectionSet (ioport_ctrl_t *const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, ioport_size_t mask) |
| fsp_err_t | R_IOPORT_PortEventInputRead (ioport_ctrl_t *const p_ctrl, bsp_io_port_t port, ioport_size_t *p_event_data) |
| fsp_err_t | R_IOPORT_PortEventOutputWrite (ioport_ctrl_t *const p_ctrl, bsp_io_port_t port, ioport_size_t event_data, ioport_size_t mask_value) |
| fsp_err_t | R_IOPORT_PortRead (ioport_ctrl_t *const p_ctrl, bsp_io_port_t port, ioport_size_t *p_port_value) |
| fsp_err_t | R_IOPORT_PortWrite (ioport_ctrl_t *const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask) |
| fsp_err_t | R_LCDC_Open (display_ctrl_t *const p_api_ctrl, display_cfg_t const *const p_cfg) |
| fsp_err_t | R_LCDC_Close (display_ctrl_t *const p_api_ctrl) |
| fsp_err_t | R_LCDC_Start (display_ctrl_t *const p_api_ctrl) |
| fsp_err_t | R_LCDC_Stop (display_ctrl_t *const p_api_ctrl) |
| fsp_err_t | R_LCDC_LayerChange (display_ctrl_t const *const p_api_ctrl, display_runtime_cfg_t const *const p_cfg, display_frame_layer_t layer) |
| fsp_err_t | R_LCDC_BufferChange (display_ctrl_t const *const p_api_ctrl, uint8_t *const framebuffer, display_frame_layer_t layer) |
| fsp_err_t | R_LCDC_ColorCorrection (display_ctrl_t const *const p_api_ctrl, display_correction_t const *const p_correction) |
| fsp_err_t | R_LCDC_ClutUpdate (display_ctrl_t const *const p_api_ctrl, display_clut_cfg_t const *const p_clut_cfg, display_frame_layer_t layer) |
| fsp_err_t | R_LCDC_ClutEdit (display_ctrl_t const *const p_api_ctrl, display_frame_layer_t layer, uint8_t index, uint32_t color) |
| fsp_err_t | R_LCDC_ColorKeySet (display_ctrl_t const *const p_api_ctrl, display_colorkeying_layer_t ck_cfg, display_frame_layer_t layer) |
| fsp_err_t | R_LCDC_StatusGet (display_ctrl_t const *const p_api_ctrl, display_status_t *const p_status) |
| fsp_err_t | R_MTU3_Open (timer_ctrl_t *const p_ctrl, timer_cfg_t const *const p_cfg) |
| fsp_err_t | R_MTU3_Stop (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_MTU3_Start (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_MTU3_Reset (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_MTU3_PeriodSet (timer_ctrl_t *const p_ctrl, uint32_t const period_counts) |
| fsp_err_t | R_MTU3_DutyCycleSet (timer_ctrl_t *const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin) |
| fsp_err_t | R_MTU3_CompareMatchSet (timer_ctrl_t *const p_ctrl, uint32_t const compare_match_value, timer_compare_match_t const match_channel) |
| fsp_err_t | R_MTU3_InfoGet (timer_ctrl_t *const p_ctrl, timer_info_t *const p_info) |
| fsp_err_t | R_MTU3_StatusGet (timer_ctrl_t *const p_ctrl, timer_status_t *const p_status) |
| fsp_err_t | R_MTU3_CounterSet (timer_ctrl_t *const p_ctrl, uint32_t counter) |
| fsp_err_t | R_MTU3_OutputEnable (timer_ctrl_t *const p_ctrl, mtu3_output_pin_t pin_level) |
| fsp_err_t | R_MTU3_OutputDisable (timer_ctrl_t *const p_ctrl, mtu3_io_pin_t pin) |
| fsp_err_t | R_MTU3_Enable (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_MTU3_Disable (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_MTU3_AdcTriggerSet (timer_ctrl_t *const p_ctrl, mtu3_adc_compare_match_t which_compare_match, uint16_t compare_match_value) |
| fsp_err_t | R_MTU3_CallbackSet (timer_ctrl_t *const p_ctrl, void(*p_callback)(timer_callback_args_t *), void *const p_context, timer_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_MTU3_Close (timer_ctrl_t *const p_ctrl) |
| fsp_err_t | R_MTU3_THREE_PHASE_Open (three_phase_ctrl_t *const p_ctrl, three_phase_cfg_t const *const p_cfg) |
| fsp_err_t | R_MTU3_THREE_PHASE_Stop (three_phase_ctrl_t *const p_ctrl) |
| fsp_err_t | R_MTU3_THREE_PHASE_Start (three_phase_ctrl_t *const p_ctrl) |
| fsp_err_t | R_MTU3_THREE_PHASE_Reset (three_phase_ctrl_t *const p_ctrl) |
| fsp_err_t | R_MTU3_THREE_PHASE_DutyCycleSet (three_phase_ctrl_t *const p_ctrl, three_phase_duty_cycle_t *const p_duty_cycle) |
| fsp_err_t | R_MTU3_THREE_PHASE_CallbackSet (three_phase_ctrl_t *const p_ctrl, void(*p_callback)(timer_callback_args_t *), void *const p_context, timer_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_MTU3_THREE_PHASE_Close (three_phase_ctrl_t *const p_ctrl) |
| fsp_err_t | R_PCIE_EP_Open (pci_ctrl_t *const p_ctrl, pci_cfg_t const *const p_cfg) |
| fsp_err_t | R_PCIE_EP_ConfigurationRegisterWrite (pci_ctrl_t *const p_ctrl, pci_configuration_write_type_t transaction_type, pci_configuration_register_transfer_t *const p_transfer) |
| fsp_err_t | R_PCIE_EP_ConfigurationRegisterRead (pci_ctrl_t *const p_ctrl, pci_configuration_read_type_t transaction_type, pci_configuration_register_transfer_t *const p_transfer) |
| fsp_err_t | R_PCIE_EP_SelfConfigurationRegisterGet (pci_ctrl_t *const p_ctrl, uint32_t register_number, uint32_t *p_data) |
| fsp_err_t | R_PCIE_EP_SelfConfigurationRegisterSet (pci_ctrl_t *const p_ctrl, uint32_t register_number, uint32_t data) |
| fsp_err_t | R_PCIE_EP_IORegisterWrite (pci_ctrl_t *const p_ctrl, pci_io_register_transfer_t *const p_transfer) |
| fsp_err_t | R_PCIE_EP_IORegisterRead (pci_ctrl_t *const p_ctrl, pci_io_register_transfer_t *const p_transfer) |
| fsp_err_t | R_PCIE_EP_MessageWrite (pci_ctrl_t *const p_ctrl, pci_message_transfer_t *const p_transfer, bool with_data) |
| fsp_err_t | R_PCIE_EP_MessageRead (pci_ctrl_t *const p_ctrl, pci_message_transfer_t *const p_transfer) |
| fsp_err_t | R_PCIE_EP_IntxAssert (pci_ctrl_t *const p_ctrl) |
| fsp_err_t | R_PCIE_EP_IntxDeassert (pci_ctrl_t *const p_ctrl) |
| fsp_err_t | R_PCIE_EP_LinkStatusGet (pci_ctrl_t *const p_ctrl, pci_status_t *const p_status) |
| fsp_err_t | R_PCIE_EP_LinkWidthChange (pci_ctrl_t *const p_ctrl, uint32_t link_width, uint32_t option) |
| fsp_err_t | R_PCIE_EP_LinkSpeedChange (pci_ctrl_t *const p_ctrl, pci_link_speed_t link_speed, uint32_t option) |
| fsp_err_t | R_PCIE_EP_LinkEqualizationRequest (pci_ctrl_t *const p_ctrl) |
| fsp_err_t | R_PCIE_EP_CallbackSet (pci_ctrl_t *const p_ctrl, void(*p_callback)(pci_callback_args_t *), void *const p_context, pci_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_PCIE_EP_Close (pci_ctrl_t *const p_ctrl) |
| fsp_err_t | R_PCIE_RC_Open (pci_ctrl_t *const p_ctrl, pci_cfg_t const *const p_cfg) |
| fsp_err_t | R_PCIE_RC_SelfConfigurationRegisterGet (pci_ctrl_t *const p_ctrl, uint32_t register_number, uint32_t *p_data) |
| fsp_err_t | R_PCIE_RC_SelfConfigurationRegisterSet (pci_ctrl_t *const p_ctrl, uint32_t register_number, uint32_t data) |
| fsp_err_t | R_PCIE_RC_MessageWrite (pci_ctrl_t *const p_ctrl, pci_message_transfer_t *const p_transfer, bool with_data) |
| fsp_err_t | R_PCIE_RC_MessageRead (pci_ctrl_t *const p_ctrl, pci_message_transfer_t *const p_transfer) |
| fsp_err_t | R_PCIE_RC_ConfigurationRegisterWrite (pci_ctrl_t *const p_ctrl, pci_configuration_write_type_t transaction_type, pci_configuration_register_transfer_t *const p_transfer) |
| fsp_err_t | R_PCIE_RC_ConfigurationRegisterRead (pci_ctrl_t *const p_ctrl, pci_configuration_read_type_t transaction_type, pci_configuration_register_transfer_t *const p_transfer) |
| fsp_err_t | R_PCIE_RC_IORegisterWrite (pci_ctrl_t *const p_ctrl, pci_io_register_transfer_t *const p_transfer) |
| fsp_err_t | R_PCIE_RC_IORegisterRead (pci_ctrl_t *const p_ctrl, pci_io_register_transfer_t *const p_transfer) |
| fsp_err_t | R_PCIE_RC_LinkStatusGet (pci_ctrl_t *const p_ctrl, pci_status_t *const p_status) |
| fsp_err_t | R_PCIE_RC_IntxAssert (pci_ctrl_t *const p_ctrl) |
| fsp_err_t | R_PCIE_RC_IntxDeassert (pci_ctrl_t *const p_ctrl) |
| fsp_err_t | R_PCIE_RC_LinkWidthChange (pci_ctrl_t *const p_ctrl, uint32_t link_width, uint32_t option) |
| fsp_err_t | R_PCIE_RC_LinkSpeedChange (pci_ctrl_t *const p_ctrl, pci_link_speed_t link_speed, uint32_t option) |
| fsp_err_t | R_PCIE_RC_LinkEqualizationRequest (pci_ctrl_t *const p_ctrl) |
| fsp_err_t | R_PCIE_RC_CallbackSet (pci_ctrl_t *const p_ctrl, void(*p_callback)(pci_callback_args_t *), void *const p_context, pci_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_PCIE_RC_Close (pci_ctrl_t *const p_ctrl) |
| fsp_err_t | R_POE3_Open (poe3_ctrl_t *const p_ctrl, poe3_cfg_t const *const p_cfg) |
| fsp_err_t | R_POE3_OutputDisable (poe3_ctrl_t *const p_ctrl) |
| fsp_err_t | R_POE3_Reset (poe3_ctrl_t *const p_ctrl) |
| fsp_err_t | R_POE3_StatusGet (poe3_ctrl_t *const p_ctrl, poe3_status_t *const p_status) |
| fsp_err_t | R_POE3_Close (poe3_ctrl_t *const p_ctrl) |
| fsp_err_t | R_POE3_CallbackSet (poe3_ctrl_t *const p_ctrl, void(*p_callback)(poe3_callback_args_t *), void *const p_context, poe3_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_POEG_Open (poeg_ctrl_t *const p_ctrl, poeg_cfg_t const *const p_cfg) |
| fsp_err_t | R_POEG_OutputDisable (poeg_ctrl_t *const p_ctrl) |
| fsp_err_t | R_POEG_Reset (poeg_ctrl_t *const p_ctrl) |
| fsp_err_t | R_POEG_StatusGet (poeg_ctrl_t *const p_ctrl, poeg_status_t *const p_status) |
| fsp_err_t | R_POEG_CallbackSet (poeg_ctrl_t *const p_ctrl, void(*p_callback)(poeg_callback_args_t *), void *const p_context, poeg_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_POEG_Close (poeg_ctrl_t *const p_ctrl) |
| fsp_err_t | R_RTC_Open (rtc_ctrl_t *const p_ctrl, rtc_cfg_t const *const p_cfg) |
| fsp_err_t | R_RTC_Close (rtc_ctrl_t *const p_ctrl) |
| fsp_err_t | R_RTC_ClockSourceSet (rtc_ctrl_t *const p_ctrl) |
| fsp_err_t | R_RTC_CalendarTimeSet (rtc_ctrl_t *const p_ctrl, rtc_time_t *const p_time) |
| fsp_err_t | R_RTC_CalendarTimeGet (rtc_ctrl_t *const p_ctrl, rtc_time_t *const p_time) |
| fsp_err_t | R_RTC_CalendarAlarmSet (rtc_ctrl_t *const p_ctrl, rtc_alarm_time_t *const p_alarm) |
| fsp_err_t | R_RTC_CalendarAlarmGet (rtc_ctrl_t *const p_ctrl, rtc_alarm_time_t *const p_alarm) |
| fsp_err_t | R_RTC_PeriodicIrqRateSet (rtc_ctrl_t *const p_ctrl, rtc_periodic_irq_select_t const rate) |
| fsp_err_t | R_RTC_ErrorAdjustmentSet (rtc_ctrl_t *const p_ctrl, rtc_error_adjustment_cfg_t const *const err_adj_cfg) |
| fsp_err_t | R_RTC_InfoGet (rtc_ctrl_t *const p_ctrl, rtc_info_t *const p_rtc_info) |
| fsp_err_t | R_RTC_CallbackSet (rtc_ctrl_t *const p_ctrl, void(*p_callback)(rtc_callback_args_t *), void *const p_context, rtc_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_RTC_TimeCaptureSet (rtc_ctrl_t *const p_ctrl, rtc_time_capture_t *const p_time_capture) |
| fsp_err_t | R_RTC_TimeCaptureGet (rtc_ctrl_t *const p_ctrl, rtc_time_capture_t *const p_time_capture) |
| fsp_err_t | R_SCI_I2C_Open (i2c_master_ctrl_t *const p_ctrl, i2c_master_cfg_t const *const p_cfg) |
| fsp_err_t | R_SCI_I2C_Close (i2c_master_ctrl_t *const p_ctrl) |
| fsp_err_t | R_SCI_I2C_Read (i2c_master_ctrl_t *const p_ctrl, uint8_t *const p_dest, uint32_t const bytes, bool const restart) |
| fsp_err_t | R_SCI_I2C_Write (i2c_master_ctrl_t *const p_ctrl, uint8_t *const p_src, uint32_t const bytes, bool const restart) |
| fsp_err_t | R_SCI_I2C_Abort (i2c_master_ctrl_t *const p_ctrl) |
| fsp_err_t | R_SCI_I2C_SlaveAddressSet (i2c_master_ctrl_t *const p_ctrl, uint32_t const slave, i2c_master_addr_mode_t const addr_mode) |
| fsp_err_t | R_SCI_I2C_CallbackSet (i2c_master_ctrl_t *const p_ctrl, void(*p_callback)(i2c_master_callback_args_t *), void *const p_context, i2c_master_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_SCI_I2C_StatusGet (i2c_master_ctrl_t *const p_ctrl, i2c_master_status_t *p_status) |
| fsp_err_t | R_SCI_SMCI_Open (smci_ctrl_t *const p_ctrl, smci_cfg_t const *const p_cfg) |
| fsp_err_t | R_SCI_SMCI_Write (smci_ctrl_t *const p_ctrl, uint8_t const *const p_src, uint32_t const bytes) |
| fsp_err_t | R_SCI_SMCI_Read (smci_ctrl_t *const p_ctrl, uint8_t *const p_dest, uint32_t const bytes) |
| fsp_err_t | R_SCI_SMCI_TransferModeSet (smci_ctrl_t *const p_ctrl, smci_transfer_mode_t const *const p_transfer_mode_params) |
| fsp_err_t | R_SCI_SMCI_BaudCalculate (smci_speed_params_t const *const p_speed_params, uint32_t baud_rate_error_x_1000, sci_smci_clock_source_t clock_source, void *const p_baud_setting) |
| fsp_err_t | R_SCI_SMCI_BaudSet (smci_ctrl_t *const p_ctrl, void const *const p_baud_setting) |
| fsp_err_t | R_SCI_SMCI_StatusGet (smci_ctrl_t *const p_ctrl, smci_status_t *const p_status) |
| fsp_err_t | R_SCI_SMCI_ClockControl (smci_ctrl_t *const p_ctrl, bool clock_enable) |
| fsp_err_t | R_SCI_SMCI_CallbackSet (smci_ctrl_t *const p_ctrl, void(*p_callback)(smci_callback_args_t *), void *const p_context, smci_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_SCI_SMCI_Close (smci_ctrl_t *const p_ctrl) |
| fsp_err_t | R_SCI_SPI_Open (spi_ctrl_t *p_ctrl, spi_cfg_t const *const p_cfg) |
| fsp_err_t | R_SCI_SPI_Read (spi_ctrl_t *const p_ctrl, void *p_dest, uint32_t const length, spi_bit_width_t const bit_width) |
| fsp_err_t | R_SCI_SPI_Write (spi_ctrl_t *const p_ctrl, void const *p_src, uint32_t const length, spi_bit_width_t const bit_width) |
| fsp_err_t | R_SCI_SPI_WriteRead (spi_ctrl_t *const p_ctrl, void const *p_src, void *p_dest, uint32_t const length, spi_bit_width_t const bit_width) |
| fsp_err_t | R_SCI_SPI_Close (spi_ctrl_t *const p_ctrl) |
| fsp_err_t | R_SCI_SPI_CalculateBitrate (uint32_t bitrate, sci_spi_clock_source_t clock_source, sci_spi_div_setting_t *sclk_div) |
| fsp_err_t | R_SCI_SPI_CallbackSet (spi_ctrl_t *const p_ctrl, void(*p_callback)(spi_callback_args_t *), void *const p_context, spi_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_SCI_UART_Open (uart_ctrl_t *const p_ctrl, uart_cfg_t const *const p_cfg) |
| fsp_err_t | R_SCI_UART_Read (uart_ctrl_t *const p_ctrl, uint8_t *const p_dest, uint32_t const bytes) |
| fsp_err_t | R_SCI_UART_Write (uart_ctrl_t *const p_ctrl, uint8_t const *const p_src, uint32_t const bytes) |
| fsp_err_t | R_SCI_UART_BaudSet (uart_ctrl_t *const p_ctrl, void const *const p_baud_setting) |
| fsp_err_t | R_SCI_UART_InfoGet (uart_ctrl_t *const p_ctrl, uart_info_t *const p_info) |
| fsp_err_t | R_SCI_UART_Close (uart_ctrl_t *const p_ctrl) |
| fsp_err_t | R_SCI_UART_Abort (uart_ctrl_t *const p_ctrl, uart_dir_t communication_to_abort) |
| fsp_err_t | R_SCI_UART_BaudCalculate (sci_uart_baud_calculation_t const *const p_baud_target, sci_uart_clock_source_t clock_source, sci_baud_setting_t *const p_baud_setting) |
| fsp_err_t | R_SCI_UART_CallbackSet (uart_ctrl_t *const p_ctrl, void(*p_callback)(uart_callback_args_t *), void *const p_context, uart_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_SCI_UART_ReadStop (uart_ctrl_t *const p_ctrl, uint32_t *remaining_bytes) |
| fsp_err_t | R_SCI_UART_ReceiveSuspend (uart_ctrl_t *const p_api_ctrl) |
| fsp_err_t | R_SCI_UART_ReceiveResume (uart_ctrl_t *const p_api_ctrl) |
| fsp_err_t | R_SDHI_Open (sdmmc_ctrl_t *const p_api_ctrl, sdmmc_cfg_t const *const p_cfg) |
| fsp_err_t | R_SDHI_MediaInit (sdmmc_ctrl_t *const p_api_ctrl, sdmmc_device_t *const p_device) |
| fsp_err_t | R_SDHI_Read (sdmmc_ctrl_t *const p_api_ctrl, uint8_t *const p_dest, uint32_t const start_sector, uint32_t const sector_count) |
| fsp_err_t | R_SDHI_Write (sdmmc_ctrl_t *const p_api_ctrl, uint8_t const *const p_source, uint32_t const start_sector, uint32_t const sector_count) |
| fsp_err_t | R_SDHI_ReadIo (sdmmc_ctrl_t *const p_api_ctrl, uint8_t *const p_data, uint32_t const function, uint32_t const address) |
| fsp_err_t | R_SDHI_WriteIo (sdmmc_ctrl_t *const p_api_ctrl, uint8_t *const p_data, uint32_t const function, uint32_t const address, sdmmc_io_write_mode_t const read_after_write) |
| fsp_err_t | R_SDHI_ReadIoExt (sdmmc_ctrl_t *const p_api_ctrl, uint8_t *const p_dest, uint32_t const function, uint32_t const address, uint32_t *const count, sdmmc_io_transfer_mode_t transfer_mode, sdmmc_io_address_mode_t address_mode) |
| fsp_err_t | R_SDHI_WriteIoExt (sdmmc_ctrl_t *const p_api_ctrl, uint8_t const *const p_source, uint32_t const function, uint32_t const address, uint32_t const count, sdmmc_io_transfer_mode_t transfer_mode, sdmmc_io_address_mode_t address_mode) |
| fsp_err_t | R_SDHI_IoIntEnable (sdmmc_ctrl_t *const p_api_ctrl, bool enable) |
| fsp_err_t | R_SDHI_StatusGet (sdmmc_ctrl_t *const p_api_ctrl, sdmmc_status_t *const p_status) |
| fsp_err_t | R_SDHI_Erase (sdmmc_ctrl_t *const p_api_ctrl, uint32_t const start_sector, uint32_t const sector_count) |
| fsp_err_t | R_SDHI_CallbackSet (sdmmc_ctrl_t *const p_api_ctrl, void(*p_callback)(sdmmc_callback_args_t *), void *const p_context, sdmmc_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_SDHI_Close (sdmmc_ctrl_t *const p_api_ctrl) |
| fsp_err_t | R_SHARED_MEMORY_Open (shared_memory_ctrl_t *const p_ctrl, shared_memory_cfg_t const *const p_cfg) |
| fsp_err_t | R_SHARED_MEMORY_Read (shared_memory_ctrl_t *const p_ctrl, uint8_t *const p_dest, uint32_t const offset, uint32_t const bytes) |
| fsp_err_t | R_SHARED_MEMORY_Write (shared_memory_ctrl_t *const p_ctrl, uint8_t *const p_src, uint32_t const offset, uint32_t const bytes) |
| fsp_err_t | R_SHARED_MEMORY_StatusGet (shared_memory_ctrl_t *const p_ctrl, shared_memory_status_t *p_status) |
| fsp_err_t | R_SHARED_MEMORY_CallbackSet (shared_memory_ctrl_t *const p_ctrl, void(*p_callback)(shared_memory_callback_args_t *), void *const p_context, shared_memory_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_SHARED_MEMORY_Close (shared_memory_ctrl_t *const p_ctrl) |
| fsp_err_t | R_SPI_Open (spi_ctrl_t *p_ctrl, spi_cfg_t const *const p_cfg) |
| fsp_err_t | R_SPI_Read (spi_ctrl_t *const p_ctrl, void *p_dest, uint32_t const length, spi_bit_width_t const bit_width) |
| fsp_err_t | R_SPI_Write (spi_ctrl_t *const p_ctrl, void const *p_src, uint32_t const length, spi_bit_width_t const bit_width) |
| fsp_err_t | R_SPI_WriteRead (spi_ctrl_t *const p_ctrl, void const *p_src, void *p_dest, uint32_t const length, spi_bit_width_t const bit_width) |
| fsp_err_t | R_SPI_Close (spi_ctrl_t *const p_ctrl) |
| fsp_err_t | R_SPI_CalculateBitrate (uint32_t bitrate, spi_clock_source_t clock_source, rspck_div_setting_t *spck_div) |
| fsp_err_t | R_SPI_CallbackSet (spi_ctrl_t *const p_ctrl, void(*p_callback)(spi_callback_args_t *), void *const p_context, spi_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_TSU_Open (adc_ctrl_t *p_ctrl, adc_cfg_t const *const p_cfg) |
| fsp_err_t | R_TSU_ScanCfg (adc_ctrl_t *p_ctrl, void const *const p_extend) |
| fsp_err_t | R_TSU_ScanStart (adc_ctrl_t *p_ctrl) |
| fsp_err_t | R_TSU_ScanGroupStart (adc_ctrl_t *p_ctrl, adc_group_mask_t group_mask) |
| fsp_err_t | R_TSU_ScanStop (adc_ctrl_t *p_ctrl) |
| fsp_err_t | R_TSU_StatusGet (adc_ctrl_t *p_ctrl, adc_status_t *p_status) |
| fsp_err_t | R_TSU_Read (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint16_t *const p_data) |
| fsp_err_t | R_TSU_Read32 (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint32_t *const p_data) |
| fsp_err_t | R_TSU_Close (adc_ctrl_t *p_ctrl) |
| fsp_err_t | R_TSU_InfoGet (adc_ctrl_t *p_ctrl, adc_info_t *p_adc_info) |
| fsp_err_t | R_TSU_Calibrate (adc_ctrl_t *const p_ctrl, void const *p_extend) |
| fsp_err_t | R_TSU_OffsetSet (adc_ctrl_t *const p_ctrl, adc_channel_t const reg_id, int32_t offset) |
| fsp_err_t | R_TSU_CallbackSet (adc_ctrl_t *const p_ctrl, void(*p_callback)(adc_callback_args_t *), void *const p_context, adc_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_TSU_B_Open (adc_ctrl_t *p_ctrl, adc_cfg_t const *const p_cfg) |
| fsp_err_t | R_TSU_B_ScanCfg (adc_ctrl_t *p_ctrl, void const *const p_channel_cfg) |
| fsp_err_t | R_TSU_B_ScanStart (adc_ctrl_t *p_ctrl) |
| fsp_err_t | R_TSU_B_ScanGroupStart (adc_ctrl_t *p_ctrl, adc_group_mask_t group_id) |
| fsp_err_t | R_TSU_B_ScanStop (adc_ctrl_t *p_ctrl) |
| fsp_err_t | R_TSU_B_StatusGet (adc_ctrl_t *p_ctrl, adc_status_t *p_status) |
| fsp_err_t | R_TSU_B_Read (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint16_t *const p_data) |
| fsp_err_t | R_TSU_B_Read32 (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint32_t *const p_data) |
| fsp_err_t | R_TSU_B_Close (adc_ctrl_t *p_ctrl) |
| fsp_err_t | R_TSU_B_InfoGet (adc_ctrl_t *p_ctrl, adc_info_t *p_adc_info) |
| fsp_err_t | R_TSU_B_Calibrate (adc_ctrl_t *const p_ctrl, void const *p_extend) |
| fsp_err_t | R_TSU_B_OffsetSet (adc_ctrl_t *const p_ctrl, adc_channel_t const reg_id, int32_t offset) |
| fsp_err_t | R_TSU_B_CallbackSet (adc_ctrl_t *const p_api_ctrl, void(*p_callback)(adc_callback_args_t *), void *const p_context, adc_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_TSU_B_CalculateTemperature (adc_ctrl_t *p_ctrl, uint16_t temperature_code, float *const p_temperature) |
| fsp_err_t | R_USB_Open (usb_ctrl_t *const p_ctrl, usb_cfg_t const *const p_cfg) |
| Applies power to the USB module specified in the argument (p_ctrl). More... | |
| fsp_err_t | R_USB_Close (usb_ctrl_t *const p_ctrl) |
| Terminates power to the USB module specified in argument (p_ctrl). USB0 module stops when USB_IP0 is specified to the member (module), USB1 module stops when USB_IP1 is specified to the member (module). More... | |
| fsp_err_t | R_USB_Read (usb_ctrl_t *const p_ctrl, uint8_t *p_buf, uint32_t size, uint8_t destination) |
| Bulk/interrupt data transfer and control data transfer. More... | |
| fsp_err_t | R_USB_Write (usb_ctrl_t *const p_ctrl, uint8_t const *const p_buf, uint32_t size, uint8_t destination) |
| Bulk/Interrupt data transfer and control data transfer. More... | |
| fsp_err_t | R_USB_Stop (usb_ctrl_t *const p_ctrl, usb_transfer_t direction, uint8_t destination) |
| Requests a data read/write transfer be terminated when a data read/write transfer is being performed. More... | |
| fsp_err_t | R_USB_Suspend (usb_ctrl_t *const p_ctrl) |
| Sends a SUSPEND signal from the USB module assigned to the member (module) of the usb_crtl_t structure. More... | |
| fsp_err_t | R_USB_Resume (usb_ctrl_t *const p_ctrl) |
| Sends a RESUME signal from the USB module assigned to the member (module) of the usb_ctrl_tstructure. More... | |
| fsp_err_t | R_USB_VbusSet (usb_ctrl_t *const p_ctrl, uint16_t state) |
| Specifies starting or stopping the VBUS supply. More... | |
| fsp_err_t | R_USB_InfoGet (usb_ctrl_t *const p_ctrl, usb_info_t *p_info, uint8_t destination) |
| Obtains completed USB-related events. More... | |
| fsp_err_t | R_USB_PipeRead (usb_ctrl_t *const p_ctrl, uint8_t *p_buf, uint32_t size, uint8_t pipe_number) |
| Requests a data read (bulk/interrupt transfer) via the pipe specified in the argument. More... | |
| fsp_err_t | R_USB_PipeWrite (usb_ctrl_t *const p_ctrl, uint8_t *p_buf, uint32_t size, uint8_t pipe_number) |
| Requests a data write (bulk/interrupt transfer). More... | |
| fsp_err_t | R_USB_PipeStop (usb_ctrl_t *const p_ctrl, uint8_t pipe_number) |
| Terminates a data read/write operation. More... | |
| fsp_err_t | R_USB_UsedPipesGet (usb_ctrl_t *const p_ctrl, uint16_t *p_pipe, uint8_t destination) |
| Gets the selected pipe number (number of the pipe that has completed initalization) via bit map information. More... | |
| fsp_err_t | R_USB_PipeInfoGet (usb_ctrl_t *const p_ctrl, usb_pipe_t *p_info, uint8_t pipe_number) |
| Gets the following pipe information regarding the pipe specified in the argument (p_ctrl) member (pipe): endpoint number, transfer type, transfer direction and maximum packet size. More... | |
| fsp_err_t | R_USB_EventGet (usb_ctrl_t *const p_ctrl, usb_status_t *event) |
| Obtains completed USB related events. (OS-less Only) More... | |
| fsp_err_t | R_USB_Callback (usb_callback_t *p_callback) |
| Register a callback function to be called upon completion of a USB related event. (RTOS only) More... | |
| fsp_err_t | R_USB_PullUp (usb_ctrl_t *const p_ctrl, uint8_t state) |
| This API enables or disables pull-up of D+/D- line. More... | |
| fsp_err_t | R_USB_HostControlTransfer (usb_ctrl_t *const p_ctrl, usb_setup_t *p_setup, uint8_t *p_buf, uint8_t device_address) |
| Performs settings and transmission processing when transmitting a setup packet. More... | |
| fsp_err_t | R_USB_PeriControlDataGet (usb_ctrl_t *const p_ctrl, uint8_t *p_buf, uint32_t size) |
| Receives data sent by control transfer. More... | |
| fsp_err_t | R_USB_PeriControlDataSet (usb_ctrl_t *const p_ctrl, uint8_t *p_buf, uint32_t size) |
| Performs transfer processing for control transfer. More... | |
| fsp_err_t | R_USB_PeriControlStatusSet (usb_ctrl_t *const p_ctrl, usb_setup_status_t status) |
| Set the response to the setup packet. More... | |
| fsp_err_t | R_USB_RemoteWakeup (usb_ctrl_t *const p_ctrl) |
| Sends a remote wake-up signal to the connected Host. More... | |
| fsp_err_t | R_USB_DriverActivate (usb_ctrl_t *const p_api_ctrl) |
| Activate USB Driver for USB Peripheral BareMetal. More... | |
| fsp_err_t | R_USB_CallbackMemorySet (usb_ctrl_t *const p_api_ctrl, usb_callback_args_t *p_callback_memory) |
| Set callback memory to USB Driver for USB Peripheral BareMetal. More... | |
| fsp_err_t | R_USB_ModuleNumberGet (usb_ctrl_t *const p_ctrl, uint8_t *module_number) |
| This API gets the module number. More... | |
| fsp_err_t | R_USB_ClassTypeGet (usb_ctrl_t *const p_ctrl, usb_class_t *class_type) |
| This API gets the class type. More... | |
| fsp_err_t | R_USB_DeviceAddressGet (usb_ctrl_t *const p_ctrl, uint8_t *device_address) |
| This API gets the device address. More... | |
| fsp_err_t | R_USB_PipeNumberGet (usb_ctrl_t *const p_ctrl, uint8_t *pipe_number) |
| This API gets the pipe number. More... | |
| fsp_err_t | R_USB_DeviceStateGet (usb_ctrl_t *const p_ctrl, uint16_t *state) |
| This API gets the state of the device. More... | |
| fsp_err_t | R_USB_DataSizeGet (usb_ctrl_t *const p_ctrl, uint32_t *data_size) |
| This API gets the data size. More... | |
| fsp_err_t | R_USB_SetupGet (usb_ctrl_t *const p_ctrl, usb_setup_t *setup) |
| This API gets the setup type. More... | |
| fsp_err_t | R_USB_OtgCallbackSet (usb_ctrl_t *const p_api_ctrl, usb_otg_callback_t *p_callback) |
| Set callback function to be called when the OTG role swap was completed on Azure RTOS. More... | |
| fsp_err_t | R_USB_OtgSRP (usb_ctrl_t *const p_api_ctrl) |
| Start the SRP processing for OTG on Azure RTOS. More... | |
| fsp_err_t | R_USB_HMSC_StorageCommand (usb_ctrl_t *const p_api_ctrl, uint8_t *buf, uint8_t command, uint8_t destination) |
| Processing for MassStorage(ATAPI) command. More... | |
| fsp_err_t | R_USB_HMSC_DriveNumberGet (usb_ctrl_t *const p_api_ctrl, uint8_t *p_drive, uint8_t destination) |
| Get number of Storage drive. More... | |
| fsp_err_t | R_USB_HMSC_StorageReadSector (uint16_t drive_number, uint8_t *const buff, uint32_t sector_number, uint16_t sector_count) |
| Read sector information. More... | |
| fsp_err_t | R_USB_HMSC_StorageWriteSector (uint16_t drive_number, uint8_t const *const buff, uint32_t sector_number, uint16_t sector_count) |
| Write sector information. More... | |
| fsp_err_t | R_USB_HMSC_SemaphoreGet (void) |
| Get a semaphore. (RTOS only) More... | |
| fsp_err_t | R_USB_HMSC_SemaphoreRelease (void) |
| Release a semaphore. (RTOS only) More... | |
| fsp_err_t | R_WDT_Refresh (wdt_ctrl_t *const p_ctrl) |
| fsp_err_t | R_WDT_Open (wdt_ctrl_t *const p_ctrl, wdt_cfg_t const *const p_cfg) |
| fsp_err_t | R_WDT_StatusClear (wdt_ctrl_t *const p_ctrl, const wdt_status_t status) |
| fsp_err_t | R_WDT_StatusGet (wdt_ctrl_t *const p_ctrl, wdt_status_t *const p_status) |
| fsp_err_t | R_WDT_CounterGet (wdt_ctrl_t *const p_ctrl, uint32_t *const p_count) |
| fsp_err_t | R_WDT_TimeoutGet (wdt_ctrl_t *const p_ctrl, wdt_timeout_values_t *const p_timeout) |
| fsp_err_t | R_WDT_CallbackSet (wdt_ctrl_t *const p_ctrl, void(*p_callback)(wdt_callback_args_t *), void *const p_context, wdt_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_XSPI_HYPER_Open (hyperbus_ctrl_t *p_ctrl, hyperbus_cfg_t const *const p_cfg) |
| fsp_err_t | R_XSPI_HYPER_Close (hyperbus_ctrl_t *p_ctrl) |
| fsp_err_t | R_XSPI_HYPER_BurstTypeSet (hyperbus_ctrl_t *p_ctrl, hyperbus_burst_type_t burst_type) |
| fsp_err_t | R_XSPI_HYPER_AccessSpaceSet (hyperbus_ctrl_t *p_ctrl, hyperbus_space_select_t access_space) |
| fsp_err_t | R_XSPI_HYPER_DirectTransfer (hyperbus_ctrl_t *const p_ctrl, hyperbus_direct_transfer_t *const p_transfer) |
| fsp_err_t | R_XSPI_HYPER_Write (hyperbus_ctrl_t *p_ctrl, uint8_t const *const p_src, uint8_t *const p_dest, uint32_t byte_count) |
| fsp_err_t | R_XSPI_HYPER_Erase (hyperbus_ctrl_t *p_ctrl, uint8_t *const p_device_address, uint32_t byte_count) |
| fsp_err_t | R_XSPI_HYPER_StatusGet (hyperbus_ctrl_t *p_ctrl, hyperbus_status_t *const p_status) |
| fsp_err_t | R_XSPI_HYPER_AutoCalibrate (hyperbus_ctrl_t *p_ctrl) |
| fsp_err_t | R_XSPI_OSPI_Open (spi_flash_ctrl_t *p_ctrl, spi_flash_cfg_t const *const p_cfg) |
| fsp_err_t | R_XSPI_OSPI_Close (spi_flash_ctrl_t *p_ctrl) |
| fsp_err_t | R_XSPI_OSPI_DirectWrite (spi_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint32_t const bytes, bool const read_after_write) |
| fsp_err_t | R_XSPI_OSPI_DirectRead (spi_flash_ctrl_t *p_ctrl, uint8_t *const p_dest, uint32_t const bytes) |
| fsp_err_t | R_XSPI_OSPI_SpiProtocolSet (spi_flash_ctrl_t *p_ctrl, spi_flash_protocol_t spi_protocol) |
| fsp_err_t | R_XSPI_OSPI_XipEnter (spi_flash_ctrl_t *p_ctrl) |
| fsp_err_t | R_XSPI_OSPI_XipExit (spi_flash_ctrl_t *p_ctrl) |
| fsp_err_t | R_XSPI_OSPI_Write (spi_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint8_t *const p_dest, uint32_t byte_count) |
| fsp_err_t | R_XSPI_OSPI_Erase (spi_flash_ctrl_t *p_ctrl, uint8_t *const p_device_address, uint32_t byte_count) |
| fsp_err_t | R_XSPI_OSPI_StatusGet (spi_flash_ctrl_t *p_ctrl, spi_flash_status_t *const p_status) |
| fsp_err_t | R_XSPI_OSPI_BankSet (spi_flash_ctrl_t *p_ctrl, uint32_t bank) |
| fsp_err_t | R_XSPI_OSPI_DirectTransfer (spi_flash_ctrl_t *p_ctrl, spi_flash_direct_transfer_t *const p_transfer, spi_flash_direct_transfer_dir_t direction) |
| fsp_err_t | R_XSPI_OSPI_AutoCalibrate (spi_flash_ctrl_t *p_ctrl) |
| fsp_err_t | R_XSPI_QSPI_Open (spi_flash_ctrl_t *p_ctrl, spi_flash_cfg_t const *const p_cfg) |
| fsp_err_t | R_XSPI_QSPI_Close (spi_flash_ctrl_t *p_ctrl) |
| fsp_err_t | R_XSPI_QSPI_DirectWrite (spi_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint32_t const bytes, bool const read_after_write) |
| fsp_err_t | R_XSPI_QSPI_DirectRead (spi_flash_ctrl_t *p_ctrl, uint8_t *const p_dest, uint32_t const bytes) |
| fsp_err_t | R_XSPI_QSPI_SpiProtocolSet (spi_flash_ctrl_t *p_ctrl, spi_flash_protocol_t spi_protocol) |
| fsp_err_t | R_XSPI_QSPI_XipEnter (spi_flash_ctrl_t *p_ctrl) |
| fsp_err_t | R_XSPI_QSPI_XipExit (spi_flash_ctrl_t *p_ctrl) |
| fsp_err_t | R_XSPI_QSPI_Write (spi_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint8_t *const p_dest, uint32_t byte_count) |
| fsp_err_t | R_XSPI_QSPI_Erase (spi_flash_ctrl_t *p_ctrl, uint8_t *const p_device_address, uint32_t byte_count) |
| fsp_err_t | R_XSPI_QSPI_StatusGet (spi_flash_ctrl_t *p_ctrl, spi_flash_status_t *const p_status) |
| fsp_err_t | R_XSPI_QSPI_BankSet (spi_flash_ctrl_t *p_ctrl, uint32_t bank) |
| fsp_err_t | R_XSPI_QSPI_DirectTransfer (spi_flash_ctrl_t *p_ctrl, spi_flash_direct_transfer_t *const p_transfer, spi_flash_direct_transfer_dir_t direction) |
| fsp_err_t | R_XSPI_QSPI_AutoCalibrate (spi_flash_ctrl_t *p_ctrl) |
| fsp_err_t | RM_BLOCK_MEDIA_SDMMC_Open (rm_block_media_ctrl_t *const p_ctrl, rm_block_media_cfg_t const *const p_cfg) |
| fsp_err_t | RM_BLOCK_MEDIA_SDMMC_MediaInit (rm_block_media_ctrl_t *const p_ctrl) |
| fsp_err_t | RM_BLOCK_MEDIA_SDMMC_Read (rm_block_media_ctrl_t *const p_ctrl, uint8_t *const p_dest_address, uint32_t const block_address, uint32_t const num_blocks) |
| fsp_err_t | RM_BLOCK_MEDIA_SDMMC_Write (rm_block_media_ctrl_t *const p_ctrl, uint8_t const *const p_src_address, uint32_t const block_address, uint32_t const num_blocks) |
| fsp_err_t | RM_BLOCK_MEDIA_SDMMC_Erase (rm_block_media_ctrl_t *const p_ctrl, uint32_t const block_address, uint32_t const num_blocks) |
| fsp_err_t | RM_BLOCK_MEDIA_SDMMC_CallbackSet (rm_block_media_ctrl_t *const p_ctrl, void(*p_callback)(rm_block_media_callback_args_t *), void *const p_context, rm_block_media_callback_args_t *const p_callback_memory) |
| fsp_err_t | RM_BLOCK_MEDIA_SDMMC_StatusGet (rm_block_media_ctrl_t *const p_api_ctrl, rm_block_media_status_t *const p_status) |
| fsp_err_t | RM_BLOCK_MEDIA_SDMMC_InfoGet (rm_block_media_ctrl_t *const p_ctrl, rm_block_media_info_t *const p_info) |
| fsp_err_t | RM_BLOCK_MEDIA_SDMMC_Close (rm_block_media_ctrl_t *const p_ctrl) |
| fsp_err_t | RM_BLOCK_MEDIA_USB_Open (rm_block_media_ctrl_t *const p_ctrl, rm_block_media_cfg_t const *const p_cfg) |
| fsp_err_t | RM_BLOCK_MEDIA_USB_MediaInit (rm_block_media_ctrl_t *const p_ctrl) |
| fsp_err_t | RM_BLOCK_MEDIA_USB_Read (rm_block_media_ctrl_t *const p_ctrl, uint8_t *const p_dest_address, uint32_t const block_address, uint32_t const num_blocks) |
| fsp_err_t | RM_BLOCK_MEDIA_USB_Write (rm_block_media_ctrl_t *const p_ctrl, uint8_t const *const p_src_address, uint32_t const block_address, uint32_t const num_blocks) |
| fsp_err_t | RM_BLOCK_MEDIA_USB_Erase (rm_block_media_ctrl_t *const p_ctrl, uint32_t const block_address, uint32_t const num_blocks) |
| fsp_err_t | RM_BLOCK_MEDIA_USB_CallbackSet (rm_block_media_ctrl_t *const p_ctrl, void(*p_callback)(rm_block_media_callback_args_t *), void *const p_context, rm_block_media_callback_args_t *const p_callback_memory) |
| fsp_err_t | RM_BLOCK_MEDIA_USB_StatusGet (rm_block_media_ctrl_t *const p_api_ctrl, rm_block_media_status_t *const p_status) |
| fsp_err_t | RM_BLOCK_MEDIA_USB_InfoGet (rm_block_media_ctrl_t *const p_ctrl, rm_block_media_info_t *const p_info) |
| fsp_err_t | RM_BLOCK_MEDIA_USB_Close (rm_block_media_ctrl_t *const p_ctrl) |
| fsp_err_t | RM_ETHERCAT_SSC_PORT_Open (ethercat_ssc_port_ctrl_t *const p_ctrl, ethercat_ssc_port_cfg_t const *const p_cfg) |
| EtherCAT Slave Controller is initialized with this function. This function includes PHY initialization and ESC EEPROM loading. Afterwards, EtherCAT communication begins. Also EtherCAT interrupts are permitted if the interrupts are used. In order to receive the EtherCAT, EtherCAT Sync0, EtherCAT Sync1 interrupt event, it's necessary to register a callback function. Implements ethercat_ssc_port_api_t::open. More... | |
| fsp_err_t | RM_ETHERCAT_SSC_PORT_Close (ethercat_ssc_port_ctrl_t *const p_ctrl) |
| fsp_err_t | RM_FREERTOS_PLUS_FAT_Open (rm_freertos_plus_fat_ctrl_t *const p_ctrl, rm_freertos_plus_fat_cfg_t const *const p_cfg) |
| fsp_err_t | RM_FREERTOS_PLUS_FAT_MediaInit (rm_freertos_plus_fat_ctrl_t *const p_ctrl, rm_freertos_plus_fat_device_t *const p_device) |
| fsp_err_t | RM_FREERTOS_PLUS_FAT_DiskInit (rm_freertos_plus_fat_ctrl_t *const p_ctrl, rm_freertos_plus_fat_disk_cfg_t const *const p_disk_cfg, FF_Disk_t *const p_disk) |
| fsp_err_t | RM_FREERTOS_PLUS_FAT_DiskDeinit (rm_freertos_plus_fat_ctrl_t *const p_ctrl, FF_Disk_t *const p_disk) |
| fsp_err_t | RM_FREERTOS_PLUS_FAT_InfoGet (rm_freertos_plus_fat_ctrl_t *const p_ctrl, FF_Disk_t *const p_disk, rm_freertos_plus_fat_info_t *const p_info) |
| fsp_err_t | RM_FREERTOS_PLUS_FAT_Close (rm_freertos_plus_fat_ctrl_t *const p_ctrl) |
| void | Default_Handler (void) |
| BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void | system_init (void) |
| BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void | bsp_register_initialization (void) |
| void | SystemInit (void) |
| void | R_BSP_WarmStart (bsp_warm_start_event_t event) |
| BSP_ATTRIBUTE_STACKLESS void | R_BSP_WarmStart_StackLess (void) |
| void | R_BSP_CacheEnableInst (void) |
| void | R_BSP_CacheEnableData (void) |
| void | R_BSP_CacheEnableMemoryProtect (void) |
| void | R_BSP_CacheDisableInst (void) |
| void | R_BSP_CacheDisableData (void) |
| void | R_BSP_CacheDisableMemoryProtect (void) |
| void | R_BSP_CacheCleanAll (void) |
| void | R_BSP_CacheInvalidateAll (void) |
| void | R_BSP_CacheCleanInvalidateAll (void) |
| void | R_BSP_CacheCleanRange (uintptr_t base_address, uintptr_t length) |
| void | R_BSP_CacheInvalidateRange (uintptr_t base_address, uintptr_t length) |
| void | R_BSP_CacheCleanInvalidateRange (uintptr_t base_address, uintptr_t length) |
| void | R_BSP_CacheL3PowerCtrl (void) |
| void | SystemCoreClockUpdate (void) |
| void | bsp_prv_clock_set (uint32_t sckcr, uint32_t sckcr2, uint32_t sckcr3, uint32_t sckcr4) |
| void | bsp_clock_init (void) |
| __WEAK void | R_BSP_FspAssert (void) |
| __STATIC_INLINE IRQn_Type | R_FSP_CurrentIrqGet (void) |
| __STATIC_INLINE uint32_t | R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) |
| void | R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units) |
| void | R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect) |
| void | R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect) |
| __STATIC_INLINE void | R_BSP_PinSet (bsp_io_region_t region, bsp_io_port_pin_t pin) |
| __STATIC_INLINE void | R_BSP_PinClear (bsp_io_region_t region, bsp_io_port_pin_t pin) |
| __STATIC_INLINE void | R_BSP_PinToggle (bsp_io_region_t region, bsp_io_port_pin_t pin) |
| __STATIC_INLINE uint32_t | R_BSP_FastPinRead (bsp_io_region_t region, bsp_io_port_pin_t pin) |
| __STATIC_INLINE void | R_BSP_PortWrite (bsp_io_region_t region, bsp_io_port_t port, uint8_t set_value) |
| __STATIC_INLINE uint32_t | R_BSP_PortRead (bsp_io_region_t region, bsp_io_port_t port) |
| __STATIC_INLINE void | R_BSP_PinAccessEnable (void) |
| __STATIC_INLINE void | R_BSP_PinAccessDisable (void) |
| __STATIC_INLINE bsp_io_region_t | R_BSP_IoRegionGet (bsp_io_port_pin_t pin) |
| __STATIC_INLINE void | R_FSP_IsrContextSet (IRQn_Type const irq, void *p_context) |
| Sets the ISR context associated with the requested IRQ. More... | |
| __STATIC_INLINE void | R_BSP_IrqClearPending (IRQn_Type irq) |
| __STATIC_INLINE uint32_t | R_BSP_IrqPendingGet (IRQn_Type irq) |
| __STATIC_INLINE void | R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void *p_context) |
| __STATIC_INLINE void | R_BSP_IrqEnableNoClear (IRQn_Type const irq) |
| __STATIC_INLINE void | R_BSP_IrqEnable (IRQn_Type const irq) |
| __STATIC_INLINE void | R_BSP_IrqDisable (IRQn_Type const irq) |
| __STATIC_INLINE void | R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void *p_context) |
| __STATIC_INLINE void * | R_FSP_IsrContextGet (IRQn_Type const irq) |
| Finds the ISR context associated with the requested IRQ. More... | |
| __STATIC_INLINE void | R_BSP_IrqDetectTypeSet (IRQn_Type const irq, uint32_t detect_type) |
| __STATIC_INLINE void | R_BSP_IrqGroupSet (IRQn_Type const irq, uint32_t interrupt_group) |
| __STATIC_INLINE void | R_BSP_IrqMaskLevelSet (uint32_t mask_level) |
| __STATIC_INLINE uint32_t | R_BSP_IrqMaskLevelGet (void) |
| void | bsp_irq_cfg (void) |
| void | R_BSP_SystemReset (void) |
| void | R_BSP_CpuReset (bsp_reset_t cpu) |
| void | R_BSP_CpuResetAutoRelease (bsp_reset_t cpu) |
| void | R_BSP_CpuResetRelease (bsp_reset_t cpu) |
| void | R_BSP_ModuleResetEnable (bsp_module_reset_t module_to_enable) |
| void | R_BSP_ModuleResetDisable (bsp_module_reset_t module_to_disable) |
| BSP_TFU_INLINE float | __sinf (float angle) |
| BSP_TFU_INLINE float | __cosf (float angle) |
| BSP_TFU_INLINE void | __sincosf (float angle, float *sin, float *cos) |
| BSP_TFU_INLINE float | __atan2f (float y_cord, float x_cord) |
| BSP_TFU_INLINE float | __hypotf (float x_cord, float y_cord) |
| BSP_TFU_INLINE void | __atan2hypotf (float y_cord, float x_cord, float *atan2, float *hypot) |
| BSP_TFU_INLINE uint32_t | __sinfx (uint32_t angle) |
| BSP_TFU_INLINE uint32_t | __cosfx (uint32_t angle) |
| BSP_TFU_INLINE void | __sincosfx (uint32_t angle, uint32_t *sin, uint32_t *cos) |
| BSP_TFU_INLINE uint32_t | __atan2fx (uint32_t y_cord, uint32_t x_cord) |
| BSP_TFU_INLINE int32_t | __hypotfx (uint32_t x_cord, uint32_t y_cord) |
| BSP_TFU_INLINE void | __atan2hypotfx (uint32_t y_cord, uint32_t x_cord, uint32_t *atan2, int32_t *hypot) |
| BSP_ATTRIBUTE_STACKLESS void | r_bsp_software_delay_loop (__attribute__((unused)) uint32_t loop_cnt) |
| fsp_err_t | R_BSP_GroupIrqWrite (bsp_grp_irq_t irq, void(*p_callback)(bsp_grp_irq_t irq)) |
| void | R_BSP_GICD_SetCtlr (bsp_gicd_ctlr_bit_t bit) |
| uint32_t | R_BSP_GICD_GetCtlr (void) |
| void | R_BSP_GICD_Enable (bsp_gicd_ctlr_bit_t bit) |
| void | R_BSP_GICD_Disable (bsp_gicd_ctlr_bit_t bit) |
| void | R_BSP_GICD_AffinityRouteEnable (bsp_gicd_ctlr_bit_t bit) |
| void | R_BSP_GICD_SpiEnable (IRQn_Type irq) |
| void | R_BSP_GICD_SpiDisable (IRQn_Type irq) |
| void | R_BSP_GICD_SetSpiPriority (IRQn_Type irq, uint32_t priority) |
| uint32_t | R_BSP_GICD_GetSpiPriority (IRQn_Type irq) |
| void | R_BSP_GICD_SetSpiRoute (IRQn_Type id, uint64_t route, bsp_gicd_irouter_route_t mode) |
| uint64_t | R_BSP_GICD_GetSpiRoute (IRQn_Type id) |
| void | R_BSP_GICD_SetSpiSense (IRQn_Type irq, bsp_gicd_icfgr_sense_t sense) |
| uint32_t | R_BSP_GICD_GetSpiSense (IRQn_Type irq) |
| void | R_BSP_GICD_SetSpiPending (IRQn_Type irq) |
| uint32_t | R_BSP_GICD_GetSpiPending (IRQn_Type irq) |
| void | R_BSP_GICD_SetSpiClearPending (IRQn_Type irq) |
| uint32_t | R_BSP_GICD_GetSpiClearPending (IRQn_Type irq) |
| void | R_BSP_GICD_SetSpiSecurity (IRQn_Type irq, bsp_gic_igroupr_secure_t group) |
| void | R_BSP_GICD_SetSpiSecurityLine (uint32_t line, bsp_gic_igroupr_secure_t group) |
| void | R_BSP_GICD_SetSpiSecurityAll (bsp_gic_igroupr_secure_t group) |
| void | R_BSP_GICD_SetSpiClass (IRQn_Type id, bsp_gicd_iclar_class_t class_group) |
| void | R_BSP_GICR_Enable (void) |
| void | R_BSP_GICR_SgiPpiEnable (IRQn_Type irq) |
| void | R_BSP_GICR_SgiPpiDisable (IRQn_Type irq) |
| void | R_BSP_GICR_SetSgiPpiPriority (IRQn_Type irq, uint32_t priority) |
| uint32_t | R_BSP_GICR_GetSgiPpiPriority (IRQn_Type irq) |
| void | R_BSP_GICR_SetSgiPpiSense (IRQn_Type irq, bsp_gicd_icfgr_sense_t sense) |
| uint32_t | R_BSP_GICR_GetSgiPpiSense (IRQn_Type irq) |
| void | R_BSP_GICR_SetSgiPpiPending (IRQn_Type irq) |
| uint32_t | R_BSP_GICR_GetSgiPpiPending (IRQn_Type irq) |
| void | R_BSP_GICR_SetSgiPpiClearPending (IRQn_Type irq) |
| uint32_t | R_BSP_GICR_GetSgiPpiClearPending (IRQn_Type irq) |
| void | R_BSP_GICR_SetSgiPpiSecurity (IRQn_Type irq, bsp_gic_igroupr_secure_t group) |
| void | R_BSP_GICR_SetSgiPpiSecurityLine (bsp_gic_igroupr_secure_t group) |
| void | R_BSP_GICR_SetClass (bsp_gicd_iclar_class_t class_group) |
| uint32_t | R_BSP_GICR_GetRoute (void) |
| void | R_BSP_GICC_SetMaskLevel (uint64_t mask_level) |
| uint64_t | R_BSP_GICC_GetMaskLevel (void) |
| void | R_BSP_GICC_SetEoiGrp0 (IRQn_Type irq) |
| void | R_BSP_GICC_SetEoiGrp1 (IRQn_Type irq) |
| uint32_t | R_BSP_GICC_Get_IntIdGrp0 (void) |
| uint32_t | R_BSP_GICC_Get_IntIdGrp1 (void) |
| fsp_err_t | R_BSP_MmuVatoPa (uint64_t vaddress, uint64_t *p_paddress) |
| fsp_err_t | R_BSP_MmuPatoVa (uint64_t paddress, uint64_t *p_vaddress, bsp_mmu_conversion_flag_t cache_flag) |
| fsp_err_t | R_BSP_MemoryMap (r_mmu_pgtbl_cfg_t *p_memory_map_cfg) |
| fsp_err_t | R_BSP_MemoryUnMap (void) |
| void | bsp_irq_core_cfg (void) |
| void | bsp_common_interrupt_handler (uint32_t id) |
| fsp_err_t | R_BSP_MpuRegionDynamicConfig (bsp_mpu_dynamic_cfg_t *p_dynamic_region_cfg) |
| fsp_err_t | R_BSP_MpuRegionRestoreConfig (void) |
| fsp_err_t | R_DOC_Open (doc_ctrl_t *const p_ctrl, doc_cfg_t const *const p_cfg) |
| fsp_err_t | R_DOC_Close (doc_ctrl_t *const p_ctrl) |
| fsp_err_t | R_DOC_Read (doc_ctrl_t *const p_ctrl, uint32_t *p_result) |
| fsp_err_t | R_DOC_Write (doc_ctrl_t *const p_ctrl, uint32_t data) |
| fsp_err_t | R_DOC_CallbackSet (doc_ctrl_t *const p_ctrl, void(*p_callback)(doc_callback_args_t *), void *const p_context, doc_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_ICU_ERROR_Open (error_ctrl_t *const p_ctrl, error_cfg_t const *const p_cfg) |
| fsp_err_t | R_ICU_ERROR_Close (error_ctrl_t *const p_ctrl) |
| fsp_err_t | R_ICU_ERROR_StatusGet (error_ctrl_t *const p_ctrl, uint32_t source, uint32_t *const p_status) |
| fsp_err_t | R_ICU_ERROR_StatusClear (error_ctrl_t *const p_ctrl, uint32_t source, uint32_t const event) |
| fsp_err_t | R_ICU_ERROR_CallbackSet (error_ctrl_t *const p_ctrl, void(*p_callback)(error_callback_args_t *), void *const p_context, error_callback_args_t *const p_callback_memory) |
| fsp_err_t | R_RSIP_Open (rsip_ctrl_t *const p_ctrl, rsip_cfg_t const *const p_cfg) |
| fsp_err_t | R_RSIP_Close (rsip_ctrl_t *const p_ctrl) |
| fsp_err_t | R_RSIP_RandomNumberGenerate (rsip_ctrl_t *const p_ctrl, uint8_t *const p_random) |
| fsp_err_t | R_RSIP_KeyGenerate (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t *const p_wrapped_key) |
| fsp_err_t | R_RSIP_KeyPairGenerate (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t *const p_wrapped_public_key, rsip_wrapped_key_t *const p_wrapped_private_key) |
| fsp_err_t | R_RSIP_EncryptedKeyWrap (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_key_update_key, void const *const p_initial_vector, void const *const p_encrypted_key, rsip_wrapped_key_t *const p_wrapped_key) |
| fsp_err_t | R_RSIP_RFC3394_KeyWrap (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_kek, rsip_wrapped_key_t const *const p_wrapped_target_key, uint8_t *const p_rfc3394_wrapped_target_key) |
| fsp_err_t | R_RSIP_RFC3394_KeyUnwrap (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_kek, uint8_t const *const p_rfc3394_wrapped_target_key, rsip_wrapped_key_t *const p_wrapped_target_key) |
| fsp_err_t | R_RSIP_PublicKeyExport (rsip_wrapped_key_t const *const p_wrapped_public_key, uint8_t *const p_raw_public_key) |
| fsp_err_t | R_RSIP_AES_Cipher_Init (rsip_ctrl_t *const p_ctrl, rsip_aes_cipher_mode_t const mode, rsip_wrapped_key_t const *const p_wrapped_key, uint8_t const *const p_initial_vector) |
| fsp_err_t | R_RSIP_AES_Cipher_Update (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_input, uint8_t *const p_output, uint32_t const length) |
| fsp_err_t | R_RSIP_AES_Cipher_Finish (rsip_ctrl_t *const p_ctrl) |
| fsp_err_t | R_RSIP_AES_AEAD_Init (rsip_ctrl_t *const p_ctrl, rsip_aes_aead_mode_t mode, rsip_wrapped_key_t const *const p_wrapped_key, uint8_t const *const p_nonce, uint32_t const nonce_length) |
| fsp_err_t | R_RSIP_AES_AEAD_LengthsSet (rsip_ctrl_t *const p_ctrl, uint32_t const total_aad_length, uint32_t const total_text_length, uint32_t const tag_length) |
| fsp_err_t | R_RSIP_AES_AEAD_AADUpdate (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_aad, uint32_t const aad_length) |
| fsp_err_t | R_RSIP_AES_AEAD_Update (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_input, uint32_t const input_length, uint8_t *const p_output, uint32_t *const p_output_length) |
| fsp_err_t | R_RSIP_AES_AEAD_Finish (rsip_ctrl_t *const p_ctrl, uint8_t *const p_output, uint32_t *const p_output_length, uint8_t *const p_tag) |
| fsp_err_t | R_RSIP_AES_AEAD_Verify (rsip_ctrl_t *const p_ctrl, uint8_t *const p_output, uint32_t *const p_output_length, uint8_t const *const p_tag, uint32_t const tag_length) |
| fsp_err_t | R_RSIP_AES_MAC_Init (rsip_ctrl_t *const p_ctrl, rsip_aes_mac_mode_t const mode, rsip_wrapped_key_t const *const p_wrapped_key) |
| fsp_err_t | R_RSIP_AES_MAC_Update (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_message, uint32_t const message_length) |
| fsp_err_t | R_RSIP_AES_MAC_SignFinish (rsip_ctrl_t *const p_ctrl, uint8_t *const p_mac) |
| fsp_err_t | R_RSIP_AES_MAC_VerifyFinish (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_mac, uint32_t const mac_length) |
| fsp_err_t | R_RSIP_ChaCha20_Init (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_key, uint8_t const *const p_nonce, uint32_t const counter) |
| fsp_err_t | R_RSIP_ChaCha20_Update (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_input, uint32_t const input_length, uint8_t *const p_output, uint32_t *const p_output_length) |
| fsp_err_t | R_RSIP_ChaCha20_Finish (rsip_ctrl_t *const p_ctrl, uint8_t *const p_output, uint32_t *const p_output_length) |
| fsp_err_t | R_RSIP_ChaCha20_Poly1305_Init (rsip_ctrl_t *const p_ctrl, rsip_chacha_poly_mode_t const mode, rsip_wrapped_key_t const *const p_wrapped_key, uint8_t const *const p_nonce, uint32_t const nonce_length) |
| fsp_err_t | R_RSIP_ChaCha20_Poly1305_AADUpdate (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_aad, uint32_t const aad_length) |
| fsp_err_t | R_RSIP_ChaCha20_Poly1305_Update (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_input, uint32_t const input_length, uint8_t *const p_output, uint32_t *const p_output_length) |
| fsp_err_t | R_RSIP_ChaCha20_Poly1305_Finish (rsip_ctrl_t *const p_ctrl, uint8_t *const p_output, uint32_t *const p_output_length, uint8_t *const p_tag) |
| fsp_err_t | R_RSIP_ChaCha20_Poly1305_Verify (rsip_ctrl_t *const p_ctrl, uint8_t *const p_output, uint32_t *const p_output_length, uint8_t const *const p_tag, uint32_t const tag_length) |
| fsp_err_t | R_RSIP_ECDSA_Sign (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, uint8_t const *const p_hash, uint8_t *const p_signature) |
| fsp_err_t | R_RSIP_ECDSA_Verify (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, uint8_t const *const p_hash, uint8_t const *const p_signature) |
| fsp_err_t | R_RSIP_PKI_ECDSA_CertVerify (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, uint8_t const *const p_hash, uint8_t const *const p_signature) |
| fsp_err_t | R_RSIP_PureEdDSA_Sign (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, rsip_wrapped_key_t const *const p_wrapped_public_key, uint8_t const *const p_message, uint64_t const message_length, uint8_t *const p_signature) |
| fsp_err_t | R_RSIP_PureEdDSA_Verify (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, uint8_t const *const p_message, uint64_t const message_length, uint8_t const *const p_signature) |
| fsp_err_t | R_RSIP_ECDH_KeyAgree (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, rsip_wrapped_key_t const *const p_wrapped_public_key, rsip_wrapped_secret_t *const p_wrapped_secret) |
| fsp_err_t | R_RSIP_ECDH_PlainKeyAgree (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, uint8_t const *const p_plain_public_key, rsip_wrapped_secret_t *const p_wrapped_secret) |
| fsp_err_t | R_RSIP_KDF_SHA_Init (rsip_ctrl_t *const p_ctrl, rsip_hash_type_t const hash_type) |
| fsp_err_t | R_RSIP_KDF_SHA_ECDHSecretUpdate (rsip_ctrl_t *const p_ctrl, rsip_wrapped_secret_t const *const p_wrapped_secret) |
| fsp_err_t | R_RSIP_KDF_SHA_Update (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_message, uint32_t const message_length) |
| fsp_err_t | R_RSIP_KDF_SHA_Finish (rsip_ctrl_t *const p_ctrl, rsip_wrapped_dkm_t *const p_wrapped_dkm) |
| fsp_err_t | R_RSIP_KDF_SHA_Suspend (rsip_ctrl_t *const p_ctrl, rsip_kdf_sha_handle_t *const p_handle) |
| fsp_err_t | R_RSIP_KDF_SHA_Resume (rsip_ctrl_t *const p_ctrl, rsip_kdf_sha_handle_t const *const p_handle) |
| fsp_err_t | R_RSIP_KDF_HMAC_DKMKeyImport (rsip_ctrl_t *const p_ctrl, rsip_wrapped_dkm_t const *const p_wrapped_dkm, uint32_t const key_length, rsip_wrapped_key_t *const p_wrapped_key) |
| fsp_err_t | R_RSIP_KDF_HMAC_ECDHSecretKeyImport (rsip_ctrl_t *const p_ctrl, rsip_wrapped_secret_t const *const p_wrapped_secret, rsip_wrapped_key_t *const p_wrapped_key) |
| fsp_err_t | R_RSIP_KDF_HMAC_Init (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_key) |
| fsp_err_t | R_RSIP_KDF_HMAC_DKMUpdate (rsip_ctrl_t *const p_ctrl, rsip_wrapped_dkm_t const *const p_wrapped_dkm) |
| fsp_err_t | R_RSIP_KDF_HMAC_ECDHSecretUpdate (rsip_ctrl_t *const p_ctrl, rsip_wrapped_secret_t const *const p_wrapped_secret) |
| fsp_err_t | R_RSIP_KDF_HMAC_Update (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_message, uint32_t const message_length) |
| fsp_err_t | R_RSIP_KDF_HMAC_SignFinish (rsip_ctrl_t *const p_ctrl, rsip_wrapped_dkm_t *const p_wrapped_dkm) |
| fsp_err_t | R_RSIP_KDF_HMAC_Suspend (rsip_ctrl_t *const p_ctrl, rsip_kdf_hmac_handle_t *const p_handle) |
| fsp_err_t | R_RSIP_KDF_HMAC_Resume (rsip_ctrl_t *const p_ctrl, rsip_kdf_hmac_handle_t const *const p_handle) |
| fsp_err_t | R_RSIP_KDF_DKMConcatenate (rsip_wrapped_dkm_t *const p_wrapped_dkm1, rsip_wrapped_dkm_t const *const p_wrapped_dkm2, uint32_t const wrapped_dkm1_buffer_length) |
| fsp_err_t | R_RSIP_KDF_DerivedKeyImport (rsip_ctrl_t *const p_ctrl, rsip_wrapped_dkm_t const *const p_wrapped_dkm, uint32_t const position, rsip_wrapped_key_t *const p_wrapped_key) |
| fsp_err_t | R_RSIP_KDF_DerivedIVWrap (rsip_ctrl_t *const p_ctrl, rsip_wrapped_dkm_t const *const p_wrapped_dkm, rsip_initial_vector_type_t const initial_vector_type, uint32_t const position, uint8_t const *const p_tls_sequence_num, uint8_t *const p_wrapped_initial_vector) |
| fsp_err_t | R_RSIP_OTF_Init (rsip_ctrl_t *const p_ctrl, rsip_otf_channel_t const channel, rsip_wrapped_key_t *const p_wrapped_key, uint8_t const *const p_seed) |
| fsp_err_t | R_RSIP_PKI_VerifiedCertInfoExport (rsip_ctrl_t *const p_ctrl, rsip_verified_cert_info_t *const p_verified_cert_info) |
| fsp_err_t | R_RSIP_PKI_VerifiedCertInfoImport (rsip_ctrl_t *const p_ctrl, rsip_verified_cert_info_t const *const p_verified_cert_info) |
| fsp_err_t | R_RSIP_PKI_CertKeyImport (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_cert, uint32_t const cert_length, uint8_t const *const p_key_param1, uint32_t const key_param1_length, uint8_t const *const p_key_param2, uint32_t const key_param2_length, rsip_hash_type_t const hash_function, rsip_wrapped_key_t *const p_wrapped_public_key) |
| fsp_err_t | R_RSIP_RSA_Encrypt (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, uint8_t const *const p_plain, uint8_t *const p_cipher) |
| fsp_err_t | R_RSIP_RSA_Decrypt (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, uint8_t const *const p_cipher, uint8_t *const p_plain) |
| fsp_err_t | R_RSIP_RSAES_PKCS1_V1_5_Encrypt (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, uint8_t const *const p_plain, uint32_t const plain_length, uint8_t *const p_cipher) |
| fsp_err_t | R_RSIP_RSAES_PKCS1_V1_5_Decrypt (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, uint8_t const *const p_cipher, uint8_t *const p_plain, uint32_t *const p_plain_length, uint32_t const plain_buffer_length) |
| fsp_err_t | R_RSIP_RSAES_OAEP_Encrypt (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, rsip_hash_type_t const hash_function, rsip_mgf_type_t const mask_generation_function, uint8_t const *const p_label, uint32_t const label_length, uint8_t const *const p_plain, uint32_t const plain_length, uint8_t *const p_cipher) |
| fsp_err_t | R_RSIP_RSAES_OAEP_Decrypt (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, rsip_hash_type_t const hash_function, rsip_mgf_type_t const mask_generation_function, uint8_t const *const p_label, uint32_t const label_length, uint8_t const *const p_cipher, uint8_t *const p_plain, uint32_t *const p_plain_length, uint32_t const plain_buffer_length) |
| fsp_err_t | R_RSIP_RSASSA_PKCS1_V1_5_Sign (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, rsip_hash_type_t const hash_function, uint8_t const *const p_hash, uint8_t *const p_signature) |
| fsp_err_t | R_RSIP_RSASSA_PKCS1_V1_5_Verify (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, rsip_hash_type_t const hash_function, uint8_t const *const p_hash, uint8_t const *const p_signature) |
| fsp_err_t | R_RSIP_RSASSA_PSS_Sign (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, rsip_hash_type_t const hash_function, rsip_mgf_type_t const mask_generation_function, uint32_t const salt_length, uint8_t const *const p_hash, uint8_t *const p_signature) |
| fsp_err_t | R_RSIP_RSASSA_PSS_Verify (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, rsip_hash_type_t const hash_function, rsip_mgf_type_t const mask_generation_function, uint32_t const salt_length, uint8_t const *const p_hash, uint8_t const *const p_signature) |
| fsp_err_t | R_RSIP_PKI_RSASSA_PKCS1_V1_5_CertVerify (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, rsip_hash_type_t const hash_function, uint8_t const *const p_hash, uint8_t const *const p_signature) |
| fsp_err_t | R_RSIP_PKI_RSASSA_PSS_CertVerify (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, rsip_hash_type_t const hash_function, rsip_mgf_type_t const mask_generation_function, uint32_t const salt_length, uint8_t const *const p_hash, uint8_t const *const p_signature) |
| fsp_err_t | R_RSIP_SHA_Compute (rsip_ctrl_t *const p_ctrl, rsip_hash_type_t const hash_type, uint8_t const *const p_message, uint32_t const message_length, uint8_t *const p_digest) |
| fsp_err_t | R_RSIP_SHA_Init (rsip_ctrl_t *const p_ctrl, rsip_hash_type_t const hash_type) |
| fsp_err_t | R_RSIP_SHA_Update (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_message, uint32_t const message_length) |
| fsp_err_t | R_RSIP_SHA_Finish (rsip_ctrl_t *const p_ctrl, uint8_t *const p_digest) |
| fsp_err_t | R_RSIP_SHA_Suspend (rsip_ctrl_t *const p_ctrl, rsip_sha_handle_t *const p_handle) |
| fsp_err_t | R_RSIP_SHA_Resume (rsip_ctrl_t *const p_ctrl, rsip_sha_handle_t const *const p_handle) |
| fsp_err_t | R_RSIP_HMAC_Compute (rsip_ctrl_t *const p_ctrl, const rsip_wrapped_key_t *p_wrapped_key, uint8_t const *const p_message, uint32_t const message_length, uint8_t *const p_mac) |
| fsp_err_t | R_RSIP_HMAC_Verify (rsip_ctrl_t *const p_ctrl, const rsip_wrapped_key_t *p_wrapped_key, uint8_t const *const p_message, uint32_t const message_length, uint8_t const *const p_mac, uint32_t const mac_length) |
| fsp_err_t | R_RSIP_HMAC_Init (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_key) |
| fsp_err_t | R_RSIP_HMAC_Update (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_message, uint32_t const message_length) |
| fsp_err_t | R_RSIP_HMAC_SignFinish (rsip_ctrl_t *const p_ctrl, uint8_t *const p_mac) |
| fsp_err_t | R_RSIP_HMAC_VerifyFinish (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_mac, uint32_t const mac_length) |
| fsp_err_t | R_RSIP_HMAC_Suspend (rsip_ctrl_t *const p_ctrl, rsip_hmac_handle_t *const p_handle) |
| fsp_err_t | R_RSIP_HMAC_Resume (rsip_ctrl_t *const p_ctrl, rsip_hmac_handle_t const *const p_handle) |
| fsp_err_t | R_RSIP_InitialKeyWrap (rsip_ctrl_t *const p_ctrl, void const *const p_wrapped_user_factory_programming_key, void const *const p_initial_vector, void const *const p_encrypted_key, rsip_wrapped_key_t *const p_wrapped_key) |
| fsp_err_t | R_RSIP_SB_InitialCommonKeyWrap (rsip_ctrl_t *const p_ctrl, void const *const p_wrapped_user_factory_programming_key, void const *const p_initial_vector, void const *const p_encrypted_key, rsip_sb_common_key_t *const p_injected_key) |
| fsp_err_t | R_RSIP_AuthPasswordHashCompute (rsip_ctrl_t *const p_ctrl, void const *const p_wrapped_user_factory_programming_key, void const *const p_initial_vector, rsip_auth_type_t const authentication_type, void const *const p_encrypted_password, rsip_hashed_auth_password_t *const p_hashed_password) |
| fsp_err_t | R_RSIP_PKI_InitialRootCertWrap (rsip_ctrl_t *const p_ctrl, void const *const p_wrapped_user_factory_programming_key, void const *const p_initial_vector, void const *const p_encrypted_cert, uint32_t const cert_length, uint8_t *const p_cert, rsip_root_cert_mac_t *const p_cert_mac) |
| fsp_err_t | R_RSIP_PKI_RootCertKeyImport (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_cert, rsip_root_cert_mac_t const *const p_cert_mac, uint8_t const *const p_key_param1, uint32_t const key_param1_length, uint8_t const *const p_key_param2, uint32_t const key_param2_length, rsip_wrapped_key_t *const p_wrapped_public_key) |
| fsp_err_t | R_RSIP_KDF_TLS12PRFVerifyDataCompute (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_key, rsip_tls12_prf_label_t const label, uint8_t const *const p_hash, uint8_t *const p_verify_data) |
| fsp_err_t | R_RSIP_TLS12_RSAPremasterSecretGenerate (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t *const p_wrapped_premaster_secret) |
| fsp_err_t | R_RSIP_TLS12_RSAPremasterSecretEncrypt (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_public_key, rsip_wrapped_key_t const *const p_wrapped_premaster_secret, uint8_t *const p_encrypted_premaster_secret) |
| fsp_err_t | R_RSIP_TLS12_RSAPremasterSecretDecrypt (rsip_ctrl_t *const p_ctrl, rsip_wrapped_key_t const *const p_wrapped_private_key, uint8_t const *const p_encrypted_premaster_secret, rsip_wrapped_key_t *const p_wrapped_premaster_secret) |
| fsp_err_t | R_RSIP_SB_ManifestVerify (rsip_ctrl_t *const p_ctrl, uint8_t const *const p_key_cert, uint32_t const key_cert_max_length, uint8_t const *const p_code_cert, uint32_t const code_cert_max_length) |
| void | spi_rxi_isr (void) |
| void | spi_rx_dmac_callback (spi_instance_ctrl_t *p_instance_ctrl) |
| void | spi_txi_isr (void) |
| void | spi_tx_dmac_callback (spi_instance_ctrl_t *p_instance_ctrl) |
| void | spi_tei_isr (void) |
| void | spi_eri_isr (void) |
| fsp_err_t | R_USB_HCDC_ControlDataRead (usb_ctrl_t *const p_api_ctrl, uint8_t *p_buf, uint32_t size, uint8_t device_address) |
| Read Control Data.(CDC Interrupt IN data) More... | |
| fsp_err_t | R_USB_HCDC_SpecificDeviceRegister (usb_ctrl_t *const p_api_ctrl, uint16_t vendor_id, uint16_t product_id) |
| Register the specified vendor class device in the device table. More... | |
| fsp_err_t | R_USB_HCDC_DeviceInfoGet (usb_ctrl_t *const p_api_ctrl, usb_hcdc_device_info_t *p_info, uint8_t device_address) |
| Get the VID, PID and subclass code of the connected device. More... | |
| fsp_err_t | R_USB_HHID_TypeGet (usb_ctrl_t *const p_api_ctrl, uint8_t *p_type, uint8_t device_address) |
| Get HID protocol.(USB Mouse/USB Keyboard/Other Type.) More... | |
| fsp_err_t | R_USB_HHID_MaxPacketSizeGet (usb_ctrl_t *const p_api_ctrl, uint16_t *p_size, uint8_t direction, uint8_t device_address) |
| Obtains max packet size for the connected HID device. The max packet size is set to the area. Set the direction (USB_HID_IN/USB_HID_OUT). More... | |
Variables | |
| uint32_t | SystemCoreClock |
Default initialization function.
Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file.
Array of GICD_ICFGR initialization value.
| enum adc_channel_t |
ADC channels
Divider values of clock provided to xSPI
Divider values of base clock generated for xSPI
Clock output divider values
CANFD clock divider values
| enum cgc_phy_clock_t |
PHY clock source identifiers
SPI asynchronous serial clock frequency
SCI asynchronous serial clock frequency
| enum cgc_lcdc_div_t |
LCDC clock divider values
SCIE asynchronous serial clock frequency
| enum cgc_encout_clock_t |
| enum cgc_cpu_clock_div_t |
CPU clock divider values
| enum cgc_clock_t |
System clock source identifiers
| enum cgc_clock_change_t |
Clock options
| enum display_in_format_t |
| enum elc_peripheral_t |
Possible peripherals to be linked to event signals (not all available on all MPUs)
| enum error_event_t |
Error event source.
| enum ioport_pin_pfc_t |
Superset of all peripheral functions.
| enum ioport_cfg_options_t |
Options to configure pin functions
| enum ether_event_t |
Event code of callback function
| enum ether_switch_event_t |
Ether Switch Event code of callback function
| enum ether_phy_lsi_type_t |
Phy LSI
| enum poe3_state_t |
POE3 states.
| Enumerator | |
|---|---|
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| POE3_STATE_DSMIF0_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error0. Timer output disabled due to DSMIF0 error. |
| POE3_STATE_DSMIF1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error0. Timer output disabled due to DSMIF1 error. |
| POE3_STATE_DSMIF2_ERROR_REQUEST | Timer output disabled due to DSMIF2 Error0. |
| POE3_STATE_DSMIF3_ERROR_REQUEST | Timer output disabled due to DSMIF3 Error0. |
| POE3_STATE_DSMIF4_ERROR_REQUEST | Timer output disabled due to DSMIF4 Error0. |
| POE3_STATE_DSMIF5_ERROR_REQUEST | Timer output disabled due to DSMIF5 Error0. |
| POE3_STATE_DSMIF6_ERROR_REQUEST | Timer output disabled due to DSMIF6 Error0. |
| POE3_STATE_DSMIF7_ERROR_REQUEST | Timer output disabled due to DSMIF7 Error0. |
| POE3_STATE_DSMIF8_ERROR_REQUEST | Timer output disabled due to DSMIF8 Error0. |
| POE3_STATE_DSMIF9_ERROR_REQUEST | Timer output disabled due to DSMIF9 Error0. |
| POE3_STATE_DSMIF0_1_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error1. |
| POE3_STATE_DSMIF1_1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error1. |
| POE3_STATE_DSMIF2_1_ERROR_REQUEST | Timer output disabled due to DSMIF2 Error1. |
| POE3_STATE_DSMIF3_1_ERROR_REQUEST | Timer output disabled due to DSMIF3 Error1. |
| POE3_STATE_DSMIF4_1_ERROR_REQUEST | Timer output disabled due to DSMIF4 Error1. |
| POE3_STATE_DSMIF5_1_ERROR_REQUEST | Timer output disabled due to DSMIF5 Error1. |
| POE3_STATE_DSMIF6_1_ERROR_REQUEST | Timer output disabled due to DSMIF6 Error1. |
| POE3_STATE_DSMIF7_1_ERROR_REQUEST | Timer output disabled due to DSMIF7 Error1. |
| POE3_STATE_DSMIF8_1_ERROR_REQUEST | Timer output disabled due to DSMIF8 Error1. |
| POE3_STATE_DSMIF9_1_ERROR_REQUEST | Timer output disabled due to DSMIF9 Error1. |
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_DSMIF0_0_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error0. |
| POE3_STATE_DSMIF1_0_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error0. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| POE3_STATE_DSMIF0_1_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error1. |
| POE3_STATE_DSMIF1_1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error1. |
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_DSMIF0_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error0. Timer output disabled due to DSMIF0 error. |
| POE3_STATE_DSMIF1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error0. Timer output disabled due to DSMIF1 error. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_DSMIF0_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error0. Timer output disabled due to DSMIF0 error. |
| POE3_STATE_DSMIF1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error0. Timer output disabled due to DSMIF1 error. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| enum poe3_active_level_t |
POE3 active level for short circuit detection.
| enum poeg_state_t |
POEG states.
| Enumerator | |
|---|---|
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_DSMIF0_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 0. |
| POEG_STATE_DSMIF1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 0. |
| POEG_STATE_DSMIF2_DISABLE_REQUEST | GPT output disabled due to DSMIF2 error 0. |
| POEG_STATE_DSMIF3_DISABLE_REQUEST | GPT output disabled due to DSMIF3 error 0. |
| POEG_STATE_DSMIF4_DISABLE_REQUEST | GPT output disabled due to DSMIF4 error 0. |
| POEG_STATE_DSMIF5_DISABLE_REQUEST | GPT output disabled due to DSMIF5 error 0. |
| POEG_STATE_DSMIF6_DISABLE_REQUEST | GPT output disabled due to DSMIF6 error 0. |
| POEG_STATE_DSMIF7_DISABLE_REQUEST | GPT output disabled due to DSMIF7 error 0. |
| POEG_STATE_DSMIF8_DISABLE_REQUEST | GPT output disabled due to DSMIF8 error 0. |
| POEG_STATE_DSMIF9_DISABLE_REQUEST | GPT output disabled due to DSMIF9 error 0. |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_DSMIF0_1_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 1. |
| POEG_STATE_DSMIF1_1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 1. |
| POEG_STATE_DSMIF2_1_DISABLE_REQUEST | GPT output disabled due to DSMIF2 error 1. |
| POEG_STATE_DSMIF3_1_DISABLE_REQUEST | GPT output disabled due to DSMIF3 error 1. |
| POEG_STATE_DSMIF4_1_DISABLE_REQUEST | GPT output disabled due to DSMIF4 error 1. |
| POEG_STATE_DSMIF5_1_DISABLE_REQUEST | GPT output disabled due to DSMIF5 error 1. |
| POEG_STATE_DSMIF6_1_DISABLE_REQUEST | GPT output disabled due to DSMIF6 error 1. |
| POEG_STATE_DSMIF7_1_DISABLE_REQUEST | GPT output disabled due to DSMIF7 error 1. |
| POEG_STATE_DSMIF8_1_DISABLE_REQUEST | GPT output disabled due to DSMIF8 error 1. |
| POEG_STATE_DSMIF9_1_DISABLE_REQUEST | GPT output disabled due to DSMIF9 error 1. |
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_DSMIF0_1_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 1. |
| POEG_STATE_DSMIF1_1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 1. |
| POEG_STATE_DSMIF0_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 0. |
| POEG_STATE_DSMIF1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 0. |
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_DSMIF0_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 0. |
| POEG_STATE_DSMIF1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 0. |
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_DSMIF0_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 0. |
| POEG_STATE_DSMIF1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 0. |
| enum poeg_trigger_t |
Triggers that will disable GPT output pins.
| enum transfer_event_t |
Events that can trigger a callback function.
| enum transfer_mode_t |
Transfer mode describes what will happen when a transfer request occurs.
| Enumerator | |
|---|---|
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_REPEAT | Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the repeat area and the transfer length will be reset to their initial values. If DMAC is used, the transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is used, the transfer repeats continuously (no limit to the number of repeat transfers). |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| TRANSFER_MODE_REPEAT_BLOCK | In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets within a block (to split blocks into arrays of their first data, second data, etc.) |
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| enum transfer_size_t |
Transfer size specifies the size of each individual transfer.
| enum transfer_addr_mode_t |
Address mode specifies whether to modify (increment or decrement) pointer after each transfer.
| Enumerator | |
|---|---|
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| TRANSFER_ADDR_MODE_OFFSET | Offset is added to the address pointer after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_DECREMENTED | Address pointer is decremented by associated transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| enum adc_channel_t |
ADC channels
Divider values of clock provided to xSPI
Divider values of base clock generated for xSPI
Clock output divider values
CANFD clock divider values
| enum cgc_phy_clock_t |
PHY clock source identifiers
SPI asynchronous serial clock frequency
SCI asynchronous serial clock frequency
| enum cgc_cpu_clock_div_t |
CPU clock divider values
| enum cgc_baseclock_div_t |
Base clock divider values
| enum cgc_clock_t |
System clock source identifiers
| enum cgc_clock_change_t |
Clock options
| enum elc_peripheral_t |
Possible peripherals to be linked to event signals (not all available on all MPUs)
| enum error_event_t |
Error event source.
| enum ether_event_t |
Event code of callback function
| enum ether_phy_lsi_type_t |
Phy LSI
| enum ioport_pin_pfc_t |
Superset of all peripheral functions.
| enum ioport_cfg_options_t |
Options to configure pin functions
| enum poe3_state_t |
POE3 states.
| Enumerator | |
|---|---|
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| POE3_STATE_DSMIF0_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error0. Timer output disabled due to DSMIF0 error. |
| POE3_STATE_DSMIF1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error0. Timer output disabled due to DSMIF1 error. |
| POE3_STATE_DSMIF2_ERROR_REQUEST | Timer output disabled due to DSMIF2 Error0. |
| POE3_STATE_DSMIF3_ERROR_REQUEST | Timer output disabled due to DSMIF3 Error0. |
| POE3_STATE_DSMIF4_ERROR_REQUEST | Timer output disabled due to DSMIF4 Error0. |
| POE3_STATE_DSMIF5_ERROR_REQUEST | Timer output disabled due to DSMIF5 Error0. |
| POE3_STATE_DSMIF6_ERROR_REQUEST | Timer output disabled due to DSMIF6 Error0. |
| POE3_STATE_DSMIF7_ERROR_REQUEST | Timer output disabled due to DSMIF7 Error0. |
| POE3_STATE_DSMIF8_ERROR_REQUEST | Timer output disabled due to DSMIF8 Error0. |
| POE3_STATE_DSMIF9_ERROR_REQUEST | Timer output disabled due to DSMIF9 Error0. |
| POE3_STATE_DSMIF0_1_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error1. |
| POE3_STATE_DSMIF1_1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error1. |
| POE3_STATE_DSMIF2_1_ERROR_REQUEST | Timer output disabled due to DSMIF2 Error1. |
| POE3_STATE_DSMIF3_1_ERROR_REQUEST | Timer output disabled due to DSMIF3 Error1. |
| POE3_STATE_DSMIF4_1_ERROR_REQUEST | Timer output disabled due to DSMIF4 Error1. |
| POE3_STATE_DSMIF5_1_ERROR_REQUEST | Timer output disabled due to DSMIF5 Error1. |
| POE3_STATE_DSMIF6_1_ERROR_REQUEST | Timer output disabled due to DSMIF6 Error1. |
| POE3_STATE_DSMIF7_1_ERROR_REQUEST | Timer output disabled due to DSMIF7 Error1. |
| POE3_STATE_DSMIF8_1_ERROR_REQUEST | Timer output disabled due to DSMIF8 Error1. |
| POE3_STATE_DSMIF9_1_ERROR_REQUEST | Timer output disabled due to DSMIF9 Error1. |
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_DSMIF0_0_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error0. |
| POE3_STATE_DSMIF1_0_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error0. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| POE3_STATE_DSMIF0_1_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error1. |
| POE3_STATE_DSMIF1_1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error1. |
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_DSMIF0_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error0. Timer output disabled due to DSMIF0 error. |
| POE3_STATE_DSMIF1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error0. Timer output disabled due to DSMIF1 error. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_DSMIF0_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error0. Timer output disabled due to DSMIF0 error. |
| POE3_STATE_DSMIF1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error0. Timer output disabled due to DSMIF1 error. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| enum poe3_active_level_t |
POE3 active level for short circuit detection.
| enum poeg_state_t |
POEG states.
| Enumerator | |
|---|---|
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_DSMIF0_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 0. |
| POEG_STATE_DSMIF1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 0. |
| POEG_STATE_DSMIF2_DISABLE_REQUEST | GPT output disabled due to DSMIF2 error 0. |
| POEG_STATE_DSMIF3_DISABLE_REQUEST | GPT output disabled due to DSMIF3 error 0. |
| POEG_STATE_DSMIF4_DISABLE_REQUEST | GPT output disabled due to DSMIF4 error 0. |
| POEG_STATE_DSMIF5_DISABLE_REQUEST | GPT output disabled due to DSMIF5 error 0. |
| POEG_STATE_DSMIF6_DISABLE_REQUEST | GPT output disabled due to DSMIF6 error 0. |
| POEG_STATE_DSMIF7_DISABLE_REQUEST | GPT output disabled due to DSMIF7 error 0. |
| POEG_STATE_DSMIF8_DISABLE_REQUEST | GPT output disabled due to DSMIF8 error 0. |
| POEG_STATE_DSMIF9_DISABLE_REQUEST | GPT output disabled due to DSMIF9 error 0. |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_DSMIF0_1_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 1. |
| POEG_STATE_DSMIF1_1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 1. |
| POEG_STATE_DSMIF2_1_DISABLE_REQUEST | GPT output disabled due to DSMIF2 error 1. |
| POEG_STATE_DSMIF3_1_DISABLE_REQUEST | GPT output disabled due to DSMIF3 error 1. |
| POEG_STATE_DSMIF4_1_DISABLE_REQUEST | GPT output disabled due to DSMIF4 error 1. |
| POEG_STATE_DSMIF5_1_DISABLE_REQUEST | GPT output disabled due to DSMIF5 error 1. |
| POEG_STATE_DSMIF6_1_DISABLE_REQUEST | GPT output disabled due to DSMIF6 error 1. |
| POEG_STATE_DSMIF7_1_DISABLE_REQUEST | GPT output disabled due to DSMIF7 error 1. |
| POEG_STATE_DSMIF8_1_DISABLE_REQUEST | GPT output disabled due to DSMIF8 error 1. |
| POEG_STATE_DSMIF9_1_DISABLE_REQUEST | GPT output disabled due to DSMIF9 error 1. |
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_DSMIF0_1_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 1. |
| POEG_STATE_DSMIF1_1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 1. |
| POEG_STATE_DSMIF0_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 0. |
| POEG_STATE_DSMIF1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 0. |
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_DSMIF0_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 0. |
| POEG_STATE_DSMIF1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 0. |
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_DSMIF0_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 0. |
| POEG_STATE_DSMIF1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 0. |
| enum poeg_trigger_t |
Triggers that will disable GPT output pins.
| enum transfer_event_t |
Events that can trigger a callback function.
| enum transfer_mode_t |
Transfer mode describes what will happen when a transfer request occurs.
| Enumerator | |
|---|---|
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_REPEAT | Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the repeat area and the transfer length will be reset to their initial values. If DMAC is used, the transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is used, the transfer repeats continuously (no limit to the number of repeat transfers). |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| TRANSFER_MODE_REPEAT_BLOCK | In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets within a block (to split blocks into arrays of their first data, second data, etc.) |
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| enum transfer_size_t |
Transfer size specifies the size of each individual transfer.
| enum transfer_addr_mode_t |
Address mode specifies whether to modify (increment or decrement) pointer after each transfer.
| Enumerator | |
|---|---|
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| TRANSFER_ADDR_MODE_OFFSET | Offset is added to the address pointer after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_DECREMENTED | Address pointer is decremented by associated transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| enum adc_channel_t |
ADC channels
Divider values of clock provided to xSPI
Divider values of base clock generated for xSPI
Clock output divider values
CANFD clock divider values
| enum cgc_phy_clock_t |
PHY clock source identifiers
SPI asynchronous serial clock frequency
SCI asynchronous serial clock frequency
| enum cgc_cpu_clock_div_t |
CPU clock divider values
| enum cgc_baseclock_div_t |
Base clock divider values
| enum cgc_clock_t |
System clock source identifiers
| enum cgc_clock_change_t |
Clock options
| enum elc_peripheral_t |
Possible peripherals to be linked to event signals (not all available on all MPUs)
| enum ether_event_t |
Event code of callback function
| enum ether_phy_lsi_type_t |
Phy LSI
| enum ether_switch_event_t |
Ether Switch Event code of callback function
| enum ioport_pin_pfc_t |
Superset of all peripheral functions.
| enum ioport_cfg_options_t |
Options to configure pin functions
| enum poe3_state_t |
POE3 states.
| Enumerator | |
|---|---|
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| POE3_STATE_DSMIF0_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error0. Timer output disabled due to DSMIF0 error. |
| POE3_STATE_DSMIF1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error0. Timer output disabled due to DSMIF1 error. |
| POE3_STATE_DSMIF2_ERROR_REQUEST | Timer output disabled due to DSMIF2 Error0. |
| POE3_STATE_DSMIF3_ERROR_REQUEST | Timer output disabled due to DSMIF3 Error0. |
| POE3_STATE_DSMIF4_ERROR_REQUEST | Timer output disabled due to DSMIF4 Error0. |
| POE3_STATE_DSMIF5_ERROR_REQUEST | Timer output disabled due to DSMIF5 Error0. |
| POE3_STATE_DSMIF6_ERROR_REQUEST | Timer output disabled due to DSMIF6 Error0. |
| POE3_STATE_DSMIF7_ERROR_REQUEST | Timer output disabled due to DSMIF7 Error0. |
| POE3_STATE_DSMIF8_ERROR_REQUEST | Timer output disabled due to DSMIF8 Error0. |
| POE3_STATE_DSMIF9_ERROR_REQUEST | Timer output disabled due to DSMIF9 Error0. |
| POE3_STATE_DSMIF0_1_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error1. |
| POE3_STATE_DSMIF1_1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error1. |
| POE3_STATE_DSMIF2_1_ERROR_REQUEST | Timer output disabled due to DSMIF2 Error1. |
| POE3_STATE_DSMIF3_1_ERROR_REQUEST | Timer output disabled due to DSMIF3 Error1. |
| POE3_STATE_DSMIF4_1_ERROR_REQUEST | Timer output disabled due to DSMIF4 Error1. |
| POE3_STATE_DSMIF5_1_ERROR_REQUEST | Timer output disabled due to DSMIF5 Error1. |
| POE3_STATE_DSMIF6_1_ERROR_REQUEST | Timer output disabled due to DSMIF6 Error1. |
| POE3_STATE_DSMIF7_1_ERROR_REQUEST | Timer output disabled due to DSMIF7 Error1. |
| POE3_STATE_DSMIF8_1_ERROR_REQUEST | Timer output disabled due to DSMIF8 Error1. |
| POE3_STATE_DSMIF9_1_ERROR_REQUEST | Timer output disabled due to DSMIF9 Error1. |
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_DSMIF0_0_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error0. |
| POE3_STATE_DSMIF1_0_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error0. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| POE3_STATE_DSMIF0_1_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error1. |
| POE3_STATE_DSMIF1_1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error1. |
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_DSMIF0_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error0. Timer output disabled due to DSMIF0 error. |
| POE3_STATE_DSMIF1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error0. Timer output disabled due to DSMIF1 error. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_DSMIF0_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error0. Timer output disabled due to DSMIF0 error. |
| POE3_STATE_DSMIF1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error0. Timer output disabled due to DSMIF1 error. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| enum poe3_active_level_t |
POE3 active level for short circuit detection.
| enum poeg_state_t |
POEG states.
| Enumerator | |
|---|---|
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_DSMIF0_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 0. |
| POEG_STATE_DSMIF1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 0. |
| POEG_STATE_DSMIF2_DISABLE_REQUEST | GPT output disabled due to DSMIF2 error 0. |
| POEG_STATE_DSMIF3_DISABLE_REQUEST | GPT output disabled due to DSMIF3 error 0. |
| POEG_STATE_DSMIF4_DISABLE_REQUEST | GPT output disabled due to DSMIF4 error 0. |
| POEG_STATE_DSMIF5_DISABLE_REQUEST | GPT output disabled due to DSMIF5 error 0. |
| POEG_STATE_DSMIF6_DISABLE_REQUEST | GPT output disabled due to DSMIF6 error 0. |
| POEG_STATE_DSMIF7_DISABLE_REQUEST | GPT output disabled due to DSMIF7 error 0. |
| POEG_STATE_DSMIF8_DISABLE_REQUEST | GPT output disabled due to DSMIF8 error 0. |
| POEG_STATE_DSMIF9_DISABLE_REQUEST | GPT output disabled due to DSMIF9 error 0. |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_DSMIF0_1_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 1. |
| POEG_STATE_DSMIF1_1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 1. |
| POEG_STATE_DSMIF2_1_DISABLE_REQUEST | GPT output disabled due to DSMIF2 error 1. |
| POEG_STATE_DSMIF3_1_DISABLE_REQUEST | GPT output disabled due to DSMIF3 error 1. |
| POEG_STATE_DSMIF4_1_DISABLE_REQUEST | GPT output disabled due to DSMIF4 error 1. |
| POEG_STATE_DSMIF5_1_DISABLE_REQUEST | GPT output disabled due to DSMIF5 error 1. |
| POEG_STATE_DSMIF6_1_DISABLE_REQUEST | GPT output disabled due to DSMIF6 error 1. |
| POEG_STATE_DSMIF7_1_DISABLE_REQUEST | GPT output disabled due to DSMIF7 error 1. |
| POEG_STATE_DSMIF8_1_DISABLE_REQUEST | GPT output disabled due to DSMIF8 error 1. |
| POEG_STATE_DSMIF9_1_DISABLE_REQUEST | GPT output disabled due to DSMIF9 error 1. |
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_DSMIF0_1_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 1. |
| POEG_STATE_DSMIF1_1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 1. |
| POEG_STATE_DSMIF0_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 0. |
| POEG_STATE_DSMIF1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 0. |
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_DSMIF0_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 0. |
| POEG_STATE_DSMIF1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 0. |
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_DSMIF0_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 0. |
| POEG_STATE_DSMIF1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 0. |
| enum poeg_trigger_t |
Triggers that will disable GPT output pins.
| enum transfer_event_t |
Events that can trigger a callback function.
| enum transfer_mode_t |
Transfer mode describes what will happen when a transfer request occurs.
| Enumerator | |
|---|---|
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_REPEAT | Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the repeat area and the transfer length will be reset to their initial values. If DMAC is used, the transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is used, the transfer repeats continuously (no limit to the number of repeat transfers). |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| TRANSFER_MODE_REPEAT_BLOCK | In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets within a block (to split blocks into arrays of their first data, second data, etc.) |
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| enum transfer_size_t |
Transfer size specifies the size of each individual transfer.
| enum transfer_addr_mode_t |
Address mode specifies whether to modify (increment or decrement) pointer after each transfer.
| Enumerator | |
|---|---|
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| TRANSFER_ADDR_MODE_OFFSET | Offset is added to the address pointer after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_DECREMENTED | Address pointer is decremented by associated transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| enum adc_channel_t |
ADC channels
Divider values of clock provided to xSPI
Divider values of base clock generated for xSPI
Clock output divider values
CANFD clock divider values
| enum cgc_phy_clock_t |
PHY clock source identifiers
SPI asynchronous serial clock frequency
SCI asynchronous serial clock frequency
| enum cgc_cpu_clock_div_t |
CPU clock divider values
| enum cgc_baseclock_div_t |
Base clock divider values
| enum cgc_clock_t |
System clock source identifiers
| enum cgc_clock_change_t |
Clock options
| enum elc_peripheral_t |
Possible peripherals to be linked to event signals (not all available on all MPUs)
| enum ether_event_t |
Event code of callback function
| enum ether_phy_lsi_type_t |
Phy LSI
| enum ether_switch_event_t |
Ether Switch Event code of callback function
| enum ioport_pin_pfc_t |
Superset of all peripheral functions.
| enum ioport_cfg_options_t |
Options to configure pin functions
| enum poe3_state_t |
POE3 states.
| Enumerator | |
|---|---|
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| POE3_STATE_DSMIF0_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error0. Timer output disabled due to DSMIF0 error. |
| POE3_STATE_DSMIF1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error0. Timer output disabled due to DSMIF1 error. |
| POE3_STATE_DSMIF2_ERROR_REQUEST | Timer output disabled due to DSMIF2 Error0. |
| POE3_STATE_DSMIF3_ERROR_REQUEST | Timer output disabled due to DSMIF3 Error0. |
| POE3_STATE_DSMIF4_ERROR_REQUEST | Timer output disabled due to DSMIF4 Error0. |
| POE3_STATE_DSMIF5_ERROR_REQUEST | Timer output disabled due to DSMIF5 Error0. |
| POE3_STATE_DSMIF6_ERROR_REQUEST | Timer output disabled due to DSMIF6 Error0. |
| POE3_STATE_DSMIF7_ERROR_REQUEST | Timer output disabled due to DSMIF7 Error0. |
| POE3_STATE_DSMIF8_ERROR_REQUEST | Timer output disabled due to DSMIF8 Error0. |
| POE3_STATE_DSMIF9_ERROR_REQUEST | Timer output disabled due to DSMIF9 Error0. |
| POE3_STATE_DSMIF0_1_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error1. |
| POE3_STATE_DSMIF1_1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error1. |
| POE3_STATE_DSMIF2_1_ERROR_REQUEST | Timer output disabled due to DSMIF2 Error1. |
| POE3_STATE_DSMIF3_1_ERROR_REQUEST | Timer output disabled due to DSMIF3 Error1. |
| POE3_STATE_DSMIF4_1_ERROR_REQUEST | Timer output disabled due to DSMIF4 Error1. |
| POE3_STATE_DSMIF5_1_ERROR_REQUEST | Timer output disabled due to DSMIF5 Error1. |
| POE3_STATE_DSMIF6_1_ERROR_REQUEST | Timer output disabled due to DSMIF6 Error1. |
| POE3_STATE_DSMIF7_1_ERROR_REQUEST | Timer output disabled due to DSMIF7 Error1. |
| POE3_STATE_DSMIF8_1_ERROR_REQUEST | Timer output disabled due to DSMIF8 Error1. |
| POE3_STATE_DSMIF9_1_ERROR_REQUEST | Timer output disabled due to DSMIF9 Error1. |
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_DSMIF0_0_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error0. |
| POE3_STATE_DSMIF1_0_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error0. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| POE3_STATE_DSMIF0_1_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error1. |
| POE3_STATE_DSMIF1_1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error1. |
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_DSMIF0_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error0. Timer output disabled due to DSMIF0 error. |
| POE3_STATE_DSMIF1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error0. Timer output disabled due to DSMIF1 error. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| POE3_STATE_NO_DISABLE_REQUEST | Timer output is not disabled by POE3. |
| POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE0# pin. |
| POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE4# pin. |
| POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE8# pin. |
| POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE10# pin. |
| POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST | Timer output disabled due to POE11# pin. |
| POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST | Timer output disabled due to poe3_api_t::outputDisable() |
| POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST | Timer output disabled due to main oscillator stop. |
| POE3_STATE_DSMIF0_ERROR_REQUEST | Timer output disabled due to DSMIF0 Error0. Timer output disabled due to DSMIF0 error. |
| POE3_STATE_DSMIF1_ERROR_REQUEST | Timer output disabled due to DSMIF1 Error0. Timer output disabled due to DSMIF1 error. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST | Timer output disabled due to output short circuit 1. |
| POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST | Timer output disabled due to output short circuit 2. |
| enum poe3_active_level_t |
POE3 active level for short circuit detection.
| enum poeg_state_t |
POEG states.
| Enumerator | |
|---|---|
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_DSMIF0_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 0. |
| POEG_STATE_DSMIF1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 0. |
| POEG_STATE_DSMIF2_DISABLE_REQUEST | GPT output disabled due to DSMIF2 error 0. |
| POEG_STATE_DSMIF3_DISABLE_REQUEST | GPT output disabled due to DSMIF3 error 0. |
| POEG_STATE_DSMIF4_DISABLE_REQUEST | GPT output disabled due to DSMIF4 error 0. |
| POEG_STATE_DSMIF5_DISABLE_REQUEST | GPT output disabled due to DSMIF5 error 0. |
| POEG_STATE_DSMIF6_DISABLE_REQUEST | GPT output disabled due to DSMIF6 error 0. |
| POEG_STATE_DSMIF7_DISABLE_REQUEST | GPT output disabled due to DSMIF7 error 0. |
| POEG_STATE_DSMIF8_DISABLE_REQUEST | GPT output disabled due to DSMIF8 error 0. |
| POEG_STATE_DSMIF9_DISABLE_REQUEST | GPT output disabled due to DSMIF9 error 0. |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_DSMIF0_1_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 1. |
| POEG_STATE_DSMIF1_1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 1. |
| POEG_STATE_DSMIF2_1_DISABLE_REQUEST | GPT output disabled due to DSMIF2 error 1. |
| POEG_STATE_DSMIF3_1_DISABLE_REQUEST | GPT output disabled due to DSMIF3 error 1. |
| POEG_STATE_DSMIF4_1_DISABLE_REQUEST | GPT output disabled due to DSMIF4 error 1. |
| POEG_STATE_DSMIF5_1_DISABLE_REQUEST | GPT output disabled due to DSMIF5 error 1. |
| POEG_STATE_DSMIF6_1_DISABLE_REQUEST | GPT output disabled due to DSMIF6 error 1. |
| POEG_STATE_DSMIF7_1_DISABLE_REQUEST | GPT output disabled due to DSMIF7 error 1. |
| POEG_STATE_DSMIF8_1_DISABLE_REQUEST | GPT output disabled due to DSMIF8 error 1. |
| POEG_STATE_DSMIF9_1_DISABLE_REQUEST | GPT output disabled due to DSMIF9 error 1. |
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_DSMIF0_1_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 1. |
| POEG_STATE_DSMIF1_1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 1. |
| POEG_STATE_DSMIF0_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 0. |
| POEG_STATE_DSMIF1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 0. |
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_DSMIF0_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 0. |
| POEG_STATE_DSMIF1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 0. |
| POEG_STATE_NO_DISABLE_REQUEST | GPT output is not disabled by POEG. |
| POEG_STATE_PIN_DISABLE_REQUEST | GPT output disabled due to GTETRG pin level. |
| POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST | GPT output disabled due to high speed analog comparator or GPT. |
| POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST | GPT output disabled due to main oscillator stop. |
| POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST | GPT output disabled due to poeg_api_t::outputDisable() |
| POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE | GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of the filtered input. |
| POEG_STATE_DSMIF0_DISABLE_REQUEST | GPT output disabled due to DSMIF0 error 0. |
| POEG_STATE_DSMIF1_DISABLE_REQUEST | GPT output disabled due to DSMIF1 error 0. |
| enum poeg_trigger_t |
Triggers that will disable GPT output pins.
| enum transfer_event_t |
Events that can trigger a callback function.
| enum transfer_mode_t |
Transfer mode describes what will happen when a transfer request occurs.
| Enumerator | |
|---|---|
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_REPEAT | Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the repeat area and the transfer length will be reset to their initial values. If DMAC is used, the transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is used, the transfer repeats continuously (no limit to the number of repeat transfers). |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| TRANSFER_MODE_REPEAT_BLOCK | In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets within a block (to split blocks into arrays of their first data, second data, etc.) |
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| TRANSFER_MODE_NORMAL | In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode. |
| TRANSFER_MODE_BLOCK | In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode. |
| enum transfer_size_t |
Transfer size specifies the size of each individual transfer.
| enum transfer_addr_mode_t |
Address mode specifies whether to modify (increment or decrement) pointer after each transfer.
| Enumerator | |
|---|---|
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| TRANSFER_ADDR_MODE_OFFSET | Offset is added to the address pointer after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_DECREMENTED | Address pointer is decremented by associated transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| TRANSFER_ADDR_MODE_INCREMENTED | Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZT::transfer_size_t after each transfer. |
| TRANSFER_ADDR_MODE_FIXED | Address pointer remains fixed after each transfer. |
| void RZT::SystemCoreClockUpdate | ( | void | ) |
Update SystemCoreClock variable based on current clock settings.
| void RZT::bsp_prv_clock_set | ( | uint32_t | sckcr, |
| uint32_t | sckcr2, | ||
| uint32_t | sckcr3, | ||
| uint32_t | sckcr4 | ||
| ) |
Applies system core clock source and divider changes. The MPU is expected to be in high speed mode during this configuration and the CGC registers are expected to be unlocked in PRCR.
| [in] | sckcr | Value to set in SCKCR register |
| [in] | sckcr2 | Value to set in SCKCR2 register |
| [in] | sckcr3 | Value to set in SCKCR3 register |
| [in] | sckcr4 | Value to set in SCKCR4 register |
| void RZT::bsp_clock_init | ( | void | ) |
Initializes system clocks. Makes no assumptions about current register settings.
| void RZT::bsp_irq_cfg | ( | void | ) |
Initialize interrupt controller.
| None | In this device, this function does nothing. This function is written to share code with other devices. |
Using the vector table information section that has been built by the linker and placed into ROM in the .vector_info. section, this function will initialize the ICU so that configured ELC events will trigger interrupts in the NVIC.
| void RZT::bsp_irq_core_cfg | ( | void | ) |
Initialize interrupt controller.
Using the vector table information section that has been built by the linker and placed into ROM in the .vector_info. section, this function will initialize the ICU so that configured ELC events will trigger interrupts in the NVIC.
| void RZT::bsp_common_interrupt_handler | ( | uint32_t | id | ) |
This function is called first when an interrupt is generated and branches to each interrupt isr function.
| [in] | id | GIC INTID used to identify the interrupt. |
| void RZT::spi_rxi_isr | ( | void | ) |
ISR called when data is loaded into SPI data register from the shift register. This function calls spi_rxi_common().
| void RZT::spi_rx_dmac_callback | ( | spi_instance_ctrl_t * | p_instance_ctrl | ) |
Callback that must be called after a RX DMAC transfer completes.
| [in] | p_instance_ctrl | Pointer to SPI instance control block |
| void RZT::spi_txi_isr | ( | void | ) |
ISR called when data is copied from the SPI data register into the SPI shift register. This function calls spi_txi_common().
| void RZT::spi_tx_dmac_callback | ( | spi_instance_ctrl_t * | p_instance_ctrl | ) |
Callback that must be called after a TX DMAC transfer completes.
| [in] | p_instance_ctrl | Pointer to SPI instance control block |
| void RZT::spi_tei_isr | ( | void | ) |
ISR called when the SPI peripheral transitions from the transferring state to the IDLE state.
| void RZT::spi_eri_isr | ( | void | ) |
ISR called in the event that an error occurs (Ex: RX_OVERFLOW).