Multi-Function Timer Pulse Unit 3 (r_mtu3)

Functions
fsp_err_t	R_MTU3_Open (timer_ctrl_t *const p_ctrl, timer_cfg_t const *const p_cfg)
fsp_err_t	R_MTU3_Stop (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_Start (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_Reset (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_PeriodSet (timer_ctrl_t *const p_ctrl, uint32_t const period_counts)
fsp_err_t	R_MTU3_DutyCycleSet (timer_ctrl_t *const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin)
fsp_err_t	R_MTU3_CompareMatchSet (timer_ctrl_t *const p_ctrl, uint32_t const compare_match_value, timer_compare_match_t const match_channel)
fsp_err_t	R_MTU3_InfoGet (timer_ctrl_t *const p_ctrl, timer_info_t *const p_info)
fsp_err_t	R_MTU3_StatusGet (timer_ctrl_t *const p_ctrl, timer_status_t *const p_status)
fsp_err_t	R_MTU3_CounterSet (timer_ctrl_t *const p_ctrl, uint32_t counter)
fsp_err_t	R_MTU3_OutputEnable (timer_ctrl_t *const p_ctrl, mtu3_output_pin_t pin_level)
fsp_err_t	R_MTU3_OutputDisable (timer_ctrl_t *const p_ctrl, mtu3_io_pin_t pin)
fsp_err_t	R_MTU3_Enable (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_Disable (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_AdcTriggerSet (timer_ctrl_t *const p_ctrl, mtu3_adc_compare_match_t which_compare_match, uint16_t compare_match_value)
fsp_err_t	R_MTU3_CallbackSet (timer_ctrl_t *const p_api_ctrl, void(*p_callback)(timer_callback_args_t *), void const *const p_context, timer_callback_args_t *const p_callback_memory)
fsp_err_t	R_MTU3_Close (timer_ctrl_t *const p_ctrl)

Detailed Description

Driver for the MTU3 peripherals on RZ microprocessor. This module implements the Timer Interface.

Overview

The MTU3 module can be used to measure external input signals, generate a periodic interrupt, or output a periodic or PWM signal to a MTIOC pin.

This module supports the MTU3 peripherals are 16-bit timers. The 16-bit timers are all treated the same in this module from the API perspective.

Features

The MTU3 module has the following features:

• Supports normal mode and PWM mode 1.
• Supports count source of PCLK, MTCLK pins, MTIOC pins.
• Supports noise filter on MTCLK pins, MTIOC pins.
• Signal can be output to a pin.
• Configurable period (counts per timer cycle).
• Configurable duty cycle in PWM mode.
• Supports runtime reconfiguration of period.
• Supports runtime reconfiguration of duty cycle in PWM mode.
• Supports runtime reconfiguration of compare match value.
• APIs are provided to start, stop, and reset the counter.
• APIs are provided to get the current period, source clock frequency, and count direction.
• APIs are provided to get the current timer status and counter value.
• Supports PWM waveform generation.
• Supports setting the counter value while the timer is stopped.
• Supports enabling and disabling output pins.
• Supports skipping overflow / comparison match interrupts for specific channels
• Supports buffer operation.
• Supports start an ADC scan at a compare match value and updating the compare match value.
  • A/D Converter Activation by TGRA Input Capture/Compare Match
  • A/D Converter Activation by A/D Converter Start Request Delaying Function

The following functions are not supported in RZ/A3UL.

• Phase counting mode.
• Cascade connection operation.
• Reset-synchronized PWM mode.
• Complementary PWM mode.
• Synchronous operation.
• Operation as a dead-time compensation counter.
• PWM mode 2.
• A/D Converter Activation by Compare Match between MTU0.TCNT and MTU0.TGRE.
• Three Phase Function (MTU5).

Selecting a Timer

RZ MPUs have two timer peripherals: the Multi-Function Timer Pulse Unit 3 (MTU3) and the General Timer (GTM). When selecting between them, consider these factors:

	MTU3	GTM
Available Channels	The number of MTU3 channels is device specific. All currently supported MPUs have at least 8 MTU3 channels.	All MPUs have 3 GTM channels.
Timer Resolution	All MPUs have at least one 16-bit MTU3 timer.	The GTM timers are 32-bit timers.
Clock Source	The MTU3 runs off P0 clock with a configurable divider up to 1024.	The GTM runs off P0 clock.

Configuration

Build Time Configurations for r_mtu3

The following build time configurations are defined in fsp_cfg/r_mtu3_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Pin Output Support	Disabled Enabled	Disabled	If selected code for outputting a waveform to a pin is included in the build.

Configurations for Timers > Timer Driver on r_mtu3

This module can be added to the Stacks tab via New Stack > Timers > Timer Driver on r_mtu3.

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_timer0	Module name.
General > Channel	Channel number must exist on this MPU	0	Specify the hardware channel.
General > Mode	Periodic PWM	Periodic	Mode selection. Periodic: Generates periodic interrupts or square waves. One-shot: Generate a single interrupt or a pulse wave. Note: One-shot mode is implemented in software. ISRs must be enabled for one-shot even if callback is unused. PWM: Generates basic PWM waveforms. Triangle-Wave Symmetric PWM: Generates symmetric PWM waveforms with duty cycle determined by compare match set during a crest interrupt and updated at the next trough. Triangle-Wave Asymmetric PWM: Generates asymmetric PWM waveforms with duty cycle determined by compare match set during a crest/trough interrupt and updated at the next trough/crest.
General > TGRA(Output Compare or Input Capture Value)	Value must be an integer between 1 and 65536 (0x10000).	0x10000	Capture/Compare match A value.
General > TGRB(Output Compare or Input Capture Value)	Value must be an integer between 1 and 65536 (0x10000).	0x10000	Capture/Compare match B value.
General > TGRC(Output Compare or Input Capture Value)	Value must be an integer between 1 and 65536 (0x10000).	0x10000	Capture/Compare match C value.
General > TGRD(Output Compare or Input Capture Value)	Value must be an integer between 1 and 65536 (0x10000).	0x10000	Capture/Compare match D value.
General > Time Prescaler	Refer to the RZA Configuration tool for available options.	P0CLK divided by 1 (common ch)	Select time prescaler.
General > Clock Edge	Rising Falling Both	Rising	Select clock edge.
General > Counter Clear Source	Disabled TGRA TGRB	Disabled	Select counter clear source.
Noise Filter > External Clock > Enable	MTCLKA Enabled MTCLKB Enabled MTCLKC Enabled MTCLKD Enabled		Sets the noise filter for the external clock. Since it is a setting common to all channels, it may be overwritten by other Stacks settings.
Noise Filter > External Clock > Clock Select	P0CLK divided by 1 P0CLK divided by 2 P0CLK divided by 8 P0CLK divided by 32	P0CLK divided by 1	Select noise filter clock.
Noise Filter > Input Capture > Enable	MTIOCA Enabled MTIOCB Enabled		Select whether to enable extra features on this channel.
Noise Filter > Input Capture > Clock Select	P0CLK divided by 1 P0CLK divided by 8 P0CLK divided by 32 External Clock	P0CLK divided by 1	Select noise filter clock.
I/O Control > MTIOCnA Pin Function	No Output Low Output at Low compare match Low Output at High compare match Low Output at Toggle compare match High Output at Low compare match High Output at High compare match High Output at Toggle compare match Input capture at rising edge Input capture at falling edge Input capture at both edges	No Output	Select TGRA initial output.
I/O Control > MTIOCnB Pin Function	No Output Low Output at Low compare match Low Output at High compare match Low Output at Toggle compare match High Output at Low compare match High Output at High compare match High Output at Toggle compare match Input capture at rising edge Input capture at falling edge Input capture at both edges	No Output	Select TGRB initial output.
Interrupts > Callback	Name must be a valid C symbol	NULL	A user callback function can be specified here. If this callback function is provided, it will be called from the interrupt service routine (ISR) each time the timer period elapses
Interrupts > Overflow/Crest Interrupt Enable	MCU Specific Options		Enable the overflow interrupt.
Interrupts > Overflow/Crest Interrupt Priority	Value must be an integer between 0 and 31	24	Select the overflow interrupt priority. This is the crest interrupt for triangle-wave PWM.
Interrupts > Capture/Compare Match A Interrupt Enable	MCU Specific Options		Enable the capture/compare match A interrupt.
Interrupts > Capture/Compare Match A Interrupt Priority	Value must be an integer between 0 and 31	24	Select the interrupt priority for capture/compare match A.
Interrupts > Capture/Compare Match B Interrupt Enable	MCU Specific Options		Enable the capture/compare match B interrupt.
Interrupts > Capture/Compare Match B Interrupt Priority	Value must be an integer between 0 and 31	24	Select the interrupt priority for capture/compare match B.
Extra Features > ADC Trigger > Start request cycle A (Start Request Delaying Function)	Must be a valid non-negative integer with a maximum configurable value of 65535 (0xffff).	0	Timer A/D Converter start request cycle A (MTU4 or MTU7).
Extra Features > ADC Trigger > Start request cycle B (Start Request Delaying Function)	Must be a valid non-negative integer with a maximum configurable value of 65535 (0xffff).	0	Timer A/D Converter start request cycle B (MTU4 or MTU7).
Extra Features > ADC Trigger > A/D Converter Activation by TGRA Input Capture/Compare Match Enable	Disabled Enabled	Disabled	Select whether to enable A/D Converter Activation by TGRA Input Capture/Compare Match.
Extra Features > Interrupt Skipping > Group A > Mode	Mode 1 Mode 2	Mode 1	Selects interrupt skipping function 1 or 2(TIMTRA).
Extra Features > Interrupt Skipping > Group A > TCIV4 Interrupt Skip Count	Not skip 1 2 3 4 5 6 7	Not skip	Select the number of TCIV4 interrupts to skip.
Extra Features > Interrupt Skipping > Group A > TCIV3 Interrupt Skip Count	Not skip 1 2 3 4 5 6 7	Not skip	Select the number of TCIV3 interrupts to skip.
Extra Features > Interrupt Skipping > Group A > TRG4AN/TRG4BN Interrupt Skip Count	Not skip 1 2 3 4 5 6 7	Not skip	Select the number of TRG4AN/TRG4BN interrupts to skip.
Extra Features > Interrupt Skipping > Group B > Mode	Mode 1 Mode 2	Mode 1	Selects interrupt skipping function 1 or 2(TIMTRB).
Extra Features > Interrupt Skipping > Group B > TCIV7 Interrupt Skip Count	Not skip 1 2 3 4 5 6 7	Not skip	Select the number of TCIV7 interrupts to skip.
Extra Features > Interrupt Skipping > Group B > TGIA6 Interrupt Skip Count	Not skip 1 2 3 4 5 6 7	Not skip	Select the number of TGIA6 interrupts to skip.
Extra Features > Interrupt Skipping > Group B > TRG7AN/TRG7BN Interrupt Skip Count	Not skip 1 2 3 4 5 6 7	Not skip	Select the number of TRG7AN/TRG7BN interrupts to skip.
Extra Features > Extra Features Enable	Enabled Disabled	Disabled	Select whether to enable extra features on this channel.

Clock Configuration

The MTU3 clock is based on the P0 clock frequency. You can set the P0 clock frequency using the Clocks tab of the Configuration editor.

Pin Configuration

This module can use MTIOCA and MTIOCB pins as output pins for periodic or PWM signals.

This module can use MTIOCA and MTIOCB as input pins to measure input signals.

Usage Notes

Updating Period and Duty Cycle

The period is updated after the next counter compare match after calling R_MTU3_PeriodSet().

The duty cycle is updated after the next counter compare match after calling R_MTU3_DutyCycleSet().

Periodic Output

The MTIOC pin toggles twice each time the timer expires in periodic mode. This is achieved by defining a PWM wave at a 50 percent duty cycle so that the period of the resulting square wave (from rising edge to rising edge) matches the period of the MTU3 timer. Since the periodic output is actually a PWM output, the time at the stop level is one cycle shorter than the time opposite the stop level for odd period values.

PWM Output

For the PWM output signal, the signal level at the start of the cycle and at the end of the cycle can be selected arbitrarily.

Interrupt Skipping

When an interrupt skipping source is selected a hardware counter will increment each time the selected event occurs. Each interrupt past the first (up to the specified skip count) will be suppressed.

Examples

MTU3 Basic Example

This is a basic example of minimal use of the MTU3 in an application.

void mtu3_basic_example (void)
{
    fsp_err_t err = FSP_SUCCESS;


    /* Initializes the module. */
    err = R_MTU3_Open(&g_timer0_ctrl, &g_timer0_cfg);


    /* Handle any errors. This function should be defined by the user. */
    handle_error(err);


    /* Start the timer. */
    (void) R_MTU3_Start(&g_timer0_ctrl);

}

MTU3 Callback Example

This is an example of a timer callback.

/* Example callback called when timer expires. */
void timer_callback (timer_callback_args_t * p_args)
{
    if (TIMER_EVENT_CYCLE_END == p_args->event)
    {
        /* Add application code to be called periodically here. */
    }
}

MTU3 Free Running Counter Example

To use the MTU3 as a free running counter, select periodic mode and set the the Period to 0xFFFF for a 16-bit timer.

void mtu3_counter_example (void)
{
    fsp_err_t err = FSP_SUCCESS;

    /* Initializes the module. */
    err = R_MTU3_Open(&g_timer0_ctrl, &g_timer0_cfg);

    /* Handle any errors. This function should be defined by the user. */
    handle_error(err);

    /* Start the timer. */
    (void) R_MTU3_Start(&g_timer0_ctrl);


    /* (Optional) Stop the timer. */
    (void) R_MTU3_Stop(&g_timer0_ctrl);



    /* Read the current counter value. Counter value is in status.counter. */
    timer_status_t status;
    (void) R_MTU3_StatusGet(&g_timer0_ctrl, &status);

}

MTU3 Period Update Example

This an example of updating the period.

#define MTU3_EXAMPLE_MICROSEC_PER_SEC           (1000000)
#define MTU3_EXAMPLE_DESIRED_PERIOD_MICROSEC    (200)

/* This example shows how to calculate a new period value at runtime. */
void mtu3_period_calculation_example (void)
{
    fsp_err_t err = FSP_SUCCESS;

    /* Initializes the module. */
    err = R_MTU3_Open(&g_timer0_ctrl, &g_timer0_cfg);

    /* Handle any errors. This function should be defined by the user. */
    handle_error(err);

    /* Start the timer. */
    (void) R_MTU3_Start(&g_timer0_ctrl);


    /* Get the source clock frequency (in Hz). There are 3 ways to do this in FSP:
     *  - If P0 clock  is chosen in agt_extended_cfg_t::clock_source and the P0 clock frequency has not changed since reset,
     *      - The source clock frequency is BSP_STARTUP_P0CLK_HZ >> timer_cfg_t::source_div
     *  - Use the R_MTU3_InfoGet function (it accounts for the divider).
     *  - Calculate the current P0 clock frequency using R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_P0CLK) and right shift
     *    by mtu3_extended_cfg_t::mtu3_clk_div.
     *
     * This example uses the 3rd option (R_FSP_SystemClockHzGet).
     */
    uint32_t p0clk_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_P0CLK) >> g_timer0_cfg.source_div;

    /* Calculate the desired period based on the current clock. Note that this calculation could overflow if the
     * desired period is larger than UINT16_MAX / p0clk_freq_hz. A cast to uint64_t is used to prevent this. */
    uint32_t period_counts =
        (uint32_t) (((uint64_t) p0clk_freq_hz * MTU3_EXAMPLE_DESIRED_PERIOD_MICROSEC) / MTU3_EXAMPLE_MICROSEC_PER_SEC);

    /* Set the calculated period. */
    err = R_MTU3_PeriodSet(&g_timer0_ctrl, period_counts);
    handle_error(err);

}

MTU3 Duty Cycle Update Example

This an example of updating the duty cycle.

#define MTU3_EXAMPLE_DESIRED_DUTY_CYCLE_PERCENT    (25)
#define MTU3_EXAMPLE_MAX_PERCENT                   (100)

/* This example shows how to calculate a new duty cycle value at runtime. */
void mtu3_duty_cycle_calculation_example (void)
{
    fsp_err_t err = FSP_SUCCESS;

    /* Initializes the module. */
    err = R_MTU3_Open(&g_timer0_ctrl, &g_timer0_cfg);

    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);

    /* Start the timer. */
    (void) R_MTU3_Start(&g_timer0_ctrl);


    /* Get the current period setting. */
    timer_info_t info;
    (void) R_MTU3_InfoGet(&g_timer0_ctrl, &info);
    uint32_t current_period_counts = info.period_counts;

    /* Calculate the desired duty cycle based on the current period. */
    uint32_t duty_cycle_counts = (current_period_counts * MTU3_EXAMPLE_DESIRED_DUTY_CYCLE_PERCENT) /
                                 MTU3_EXAMPLE_MAX_PERCENT;

    /* Set the calculated duty cycle. */
    err = R_MTU3_DutyCycleSet(&g_timer0_ctrl, duty_cycle_counts, 0);
    assert(FSP_SUCCESS == err);

}

MTU3 Compare Match Set Example

This example demonstrates the configuration and use of compare match with MTU3 timer.

/* Example callback called when compare match occurs. */
void mtu3_compare_match_callback (timer_callback_args_t * p_args)
{
    if (TIMER_EVENT_COMPARE_A == p_args->event)
    {
        /* Add application code to be called periodically here. */
    }
}

#define MTU3_COMPARE_MATCH_EXAMPLE_VALUE    (0x2000U)

void mtu3_compare_match_set_example (void)
{
    fsp_err_t err = FSP_SUCCESS;

    /* Initializes the module. */
    err = R_MTU3_Open(&g_timer0_ctrl, &g_timer0_cfg);

    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);


    /* Set the compare match value (MTU3_COMPARE_MATCH_EXAMPLE_VALUE). This value must be less than or equal to period value. */
    err = R_MTU3_CompareMatchSet(&g_timer0_ctrl, MTU3_COMPARE_MATCH_EXAMPLE_VALUE, TIMER_COMPARE_MATCH_A);
    assert(FSP_SUCCESS == err);


    /* Start the timer. */
    (void) R_MTU3_Start(&g_timer0_ctrl);

    /* (Optional) Stop the timer. */
    (void) R_MTU3_Stop(&g_timer0_ctrl);
}

Data Structures
struct	mtu3_output_pin_t
struct	mtu3_instance_ctrl_t
struct	mtu3_extended_pwm_cfg_t
struct	mtu3_extended_cfg_t

Enumerations
enum	mtu3_io_pin_level_t
enum	mtu3_clock_edge_t
enum	mtu3_clock_div_t
enum	mtu3_tcnt_clear_t
enum	mtu3_io_pin_t
enum	mtu3_noise_filter_t
enum	mtu3_noise_filter_mtclk_t
enum	mtu3_noise_filter_clock_t
enum	mtu3_noise_filter_external_clock_t
enum	mtu3_interrupt_skip_mode_t
enum	mtu3_interrupt_skip_count_t
enum	mtu3_adc_compare_match_t
enum	mtu3_adc_activation_tgra_compare_match_t

---

Data Structure Documentation

mtu3_output_pin_t

struct mtu3_output_pin_t

Configurations for output pins.

Data Fields
mtu3_io_pin_level_t	output_pin_level_a	I/O Control A.
mtu3_io_pin_level_t	output_pin_level_b	I/O Control B.

mtu3_instance_ctrl_t

struct mtu3_instance_ctrl_t

Channel control block. DO NOT INITIALIZE. Initialization occurs when timer_api_t::open is called.

Data Fields
uint32_t	open
	Whether or not channel is open.
const timer_cfg_t *	p_cfg
	Pointer to initial configurations.
void *	p_reg
	Base register for this channel.
R_MTU_Type *	p_reg_com
	Base register for this channel(common ch)
void *	p_reg_nf
	Base register for this channel(noise fileter)
uint32_t	channel_mask
	Channel bitmask.
void(*	p_callback )(timer_callback_args_t *)
	Pointer to callback.
timer_callback_args_t *	p_callback_memory
	Pointer to optional callback argument memory.
void const *	p_context
	Pointer to context to be passed into callback function.

mtu3_extended_pwm_cfg_t

struct mtu3_extended_pwm_cfg_t

MTU3 extension for advanced PWM features.

Data Fields
mtu3_interrupt_skip_mode_t	interrupt_skip_mode_a	Selects interrupt skipping function 1 or 2(TIMTRA)
mtu3_interrupt_skip_mode_t	interrupt_skip_mode_b	Selects interrupt skipping function 1 or 2(TIMTRB)
uint16_t	adc_a_compare_match	Timer A/D Converter Start Request Cycle A (MTU4 or MTU7)
uint16_t	adc_b_compare_match	Timer A/D Converter Start Request Cycle B (MTU4 or MTU7)
mtu3_interrupt_skip_count_t	interrupt_skip_count_tciv4	TCIV4 Interrupt Skipping Count Setting(TITCR1A)
mtu3_interrupt_skip_count_t	interrupt_skip_count_tgia3	TGIA3 Interrupt Skipping Count Setting(TITCR1A)
mtu3_interrupt_skip_count_t	interrupt_skip_count_tciv7	TCIV7 Interrupt Skipping Count Setting(TITCR1B)
mtu3_interrupt_skip_count_t	interrupt_skip_count_tgia6	TGIA6 Interrupt Skipping Count Setting(TITCR1B)
mtu3_interrupt_skip_count_t	interrupt_skip_count_tgr4an_bn	TRG4AN/TRG4BN Interrupt Skipping Count Setting(TITCR2A)
mtu3_interrupt_skip_count_t	interrupt_skip_count_tgr7an_bn	TRG7AN/TRG7BN Interrupt Skipping Count Setting(TITCR2B)

mtu3_extended_cfg_t

struct mtu3_extended_cfg_t

The MTU3 extension constitutes a unique feature of MTU3.

Data Fields
uint32_t	tgra_val	Capture/Compare match A register.
uint32_t	tgrb_val	Capture/Compare match B register.
uint32_t	tgrc_val	Capture/Compare match C register (Does not exist in MTU ch1-2)
uint32_t	tgrd_val	Capture/Compare match D register (Does not exist in MTU ch1-2)
mtu3_clock_div_t	mtu3_clk_div	Time Prescaler Select.
mtu3_clock_edge_t	clk_edge	Clock Edge Select.
mtu3_tcnt_clear_t	mtu3_clear	Counter Clear Source Select.
mtu3_output_pin_t	mtioc_ctrl_setting	I/O Control A, B.
mtu3_noise_filter_t	noise_filter_mtioc_setting
mtu3_noise_filter_clock_t	noise_filter_mtioc_clk
mtu3_noise_filter_mtclk_t	noise_filter_mtclk_setting
mtu3_noise_filter_external_clock_t	noise_filter_mtclk_clk
mtu3_adc_activation_tgra_compare_match_t	adc_activation_setting
uint8_t	capture_a_ipl	Capture/Compare match A interrupt priority.
uint8_t	capture_b_ipl	Capture/Compare match B interrupt priority.
IRQn_Type	capture_a_irq	Capture/Compare match A interrupt.
IRQn_Type	capture_b_irq	Capture/Compare match B interrupt.
mtu3_extended_pwm_cfg_t const *	p_pwm_cfg	Advanced PWM features, optional.

Enumeration Type Documentation

mtu3_io_pin_level_t

enum mtu3_io_pin_level_t

I/O Level Select

Enumerator
MTU3_IO_PIN_LEVEL_NO_OUTPUT	Output prohibited.
MTU3_IO_PIN_LEVEL_INITIAL_LOW_COMPARE_LOW	Initial output is low. Low output at compare match.
MTU3_IO_PIN_LEVEL_INITIAL_LOW_COMPARE_HIGH	Initial output is low. High output at compare match.
MTU3_IO_PIN_LEVEL_INITIAL_LOW_COMPARE_TOGGLE	Initial output is low. Toggle output at compare match.
MTU3_IO_PIN_LEVEL_INITIAL_HIGH_COMPARE_LOW	Initial output is high. Low output at compare match.
MTU3_IO_PIN_LEVEL_INITIAL_HIGH_COMPARE_HIGH	Initial output is high. High output at compare match.
MTU3_IO_PIN_LEVEL_INITIAL_HIGH_COMPARE_TOGGLE	Initial output is high. Toggle output at compare match.
MTU3_IO_PIN_LEVEL_INPUT_RISING_EDGE	Input capture at rising edge.
MTU3_IO_PIN_LEVEL_INPUT_FALLING_EDGE	Input capture at falling edge.
MTU3_IO_PIN_LEVEL_INPUT_BOTH_EDGE	Input capture at both edges.

mtu3_clock_edge_t

enum mtu3_clock_edge_t

Clock Edge Select

Enumerator
MTU3_CLOCK_EDGE_RISING	Count at rising edge.
MTU3_CLOCK_EDGE_FALLING	Count at falling edge.
MTU3_CLOCK_EDGE_BOTH	Count at both edges.

mtu3_clock_div_t

enum mtu3_clock_div_t

Time Prescaler Select

Enumerator
MTU3_CLOCK_DIV_1	CLOCK divided by 1 (common ch)
MTU3_CLOCK_DIV_4	CLOCK divided by 4 (common ch)
MTU3_CLOCK_DIV_16	CLOCK divided by 16 (common ch)
MTU3_CLOCK_DIV_64	CLOCK divided by 64 (common ch)
MTU3_CLOCK_DIV_2	CLOCK divided by 2 (common ch)
MTU3_CLOCK_DIV_8	CLOCK divided by 8 (common ch)
MTU3_CLOCK_DIV_32	CLOCK divided by 32 (common ch)
MTU3_CLOCK_DIV_MTCLKA_CH_0	External clock: counts on MTCLKA pin input (ch0)
MTU3_CLOCK_DIV_MTCLKB_CH_0	External clock: counts on MTCLKB pin input (ch0)
MTU3_CLOCK_DIV_MTCLKC_CH_0	External clock: counts on MTCLKC pin input (ch0)
MTU3_CLOCK_DIV_MTCLKD_CH_0	External clock: counts on MTCLKD pin input (ch0)
MTU3_CLOCK_DIV_256_CH_0	CLOCK divided by 256 (ch0)
MTU3_CLOCK_DIV_1024_CH_0	CLOCK divided by 1024 (ch0)
MTU3_CLOCK_DIV_MTIOC1A_CH_0	External clock: counts on MTIOC1A pin input (ch0)
MTU3_CLOCK_DIV_MTCLKA_CH_1	External clock: counts on MTCLKA pin input (ch1)
MTU3_CLOCK_DIV_MTCLKB_CH_1	External clock: counts on MTCLKB pin input (ch1)
MTU3_CLOCK_DIV_256_CH_1	CLOCK divided by 256 (ch1)
MTU3_CLOCK_DIV_TCNT_CH1	Overflow/underflow of MTU2.TCNT.
MTU3_CLOCK_DIV_1024_CH_1	CLOCK divided by 1024 (ch1)
MTU3_CLOCK_DIV_MTCLKA_CH_2	External clock: counts on MTCLKA pin input (ch2)
MTU3_CLOCK_DIV_MTCLKB_CH_2	External clock: counts on MTCLKB pin input (ch2)
MTU3_CLOCK_DIV_MTCLKC_CH_2	External clock: counts on MTCLKC pin input (ch2)
MTU3_CLOCK_DIV_1024_CH_2	CLOCK divided by 1024 (ch2)
MTU3_CLOCK_DIV_256_CH_2	CLOCK divided by 256 (ch2)
MTU3_CLOCK_DIV_256_CH_3_4_6_7_8	CLOCK divided by 256 (ch3-4, 6-8)
MTU3_CLOCK_DIV_1024_CH_3_4_6_7_8	CLOCK divided by 1024 (ch3-4, 6-8)
MTU3_CLOCK_DIV_MTCLKA_CH_3_4_6_7_8	External clock: counts on MTCLKA pin input (ch3-4, 6-8)
MTU3_CLOCK_DIV_MTCLKB_CH_3_4_6_7_8	External clock: counts on MTCLKB pin input (ch3-4, 6-8)

mtu3_tcnt_clear_t

enum mtu3_tcnt_clear_t

Counter Clear Source Select

Enumerator
MTU3_TCNT_CLEAR_DISABLE	TCNT clearing disabled.
MTU3_TCNT_CLEAR_TGRA	TCNT cleared by TGRA compare match/input capture.
MTU3_TCNT_CLEAR_TGRB	TCNT cleared by TGRB compare match/input capture.

mtu3_io_pin_t

enum mtu3_io_pin_t

Level of MTU3 pin

Enumerator
MTU3_IO_PIN_MTIOCA	MTIOCA.
MTU3_IO_PIN_MTIOCB	MTIOCB.
MTU3_IO_PIN_MTIOCA_AND_MTIOCB	MTIOCA and MTIOCB.

mtu3_noise_filter_t

enum mtu3_noise_filter_t

Disables or enables the noise filter for input from the MTIOCnA pin

Enumerator
MTU3_NOISE_FILTER_DISABLE	The noise filter for the MTIOC pin is disabled.
MTU3_NOISE_FILTER_A_ENABLE	The noise filter for the MTIOCA pin is enabled.
MTU3_NOISE_FILTER_B_ENABLE	The noise filter for the MTIOCB pin is enabled.

mtu3_noise_filter_mtclk_t

enum mtu3_noise_filter_mtclk_t

Disables or enables the noise filter for the external clock input pins of the MTU

Enumerator
MTU3_NOISE_FILTER_MTCLK_DISABLE	The noise filter for the MTCLK pin is disabled.
MTU3_NOISE_FILTER_MTCLK_A_ENABLE	The noise filter for the MTCLKA pin is enabled.
MTU3_NOISE_FILTER_MTCLK_B_ENABLE	The noise filter for the MTCLKB pin is enabled.
MTU3_NOISE_FILTER_MTCLK_C_ENABLE	The noise filter for the MTCLKC pin is enabled.
MTU3_NOISE_FILTER_MTCLK_D_ENABLE	The noise filter for the MTCLKD pin is enabled.

mtu3_noise_filter_clock_t

enum mtu3_noise_filter_clock_t

Enumerator
MTU3_NOISE_FILTER_CLOCK_DIV_1	CLK/1 - fast sampling.
MTU3_NOISE_FILTER_CLOCK_DIV_8	CLK/8.
MTU3_NOISE_FILTER_CLOCK_DIV_32	CLK/32 - slow sampling.
MTU3_NOISE_FILTER_CLOCK_SOURCE	Clock source for counting.

mtu3_noise_filter_external_clock_t

enum mtu3_noise_filter_external_clock_t

Enumerator
MTU3_NOISE_FILTER_EXTERNAL_CLOCK_DIV_1	CLK/1 - fast sampling.
MTU3_NOISE_FILTER_EXTERNAL_CLOCK_DIV_2	CLK/2.
MTU3_NOISE_FILTER_EXTERNAL_CLOCK_DIV_8	CLK/8.
MTU3_NOISE_FILTER_EXTERNAL_CLOCK_DIV_32	CLK/32 - slow sampling.

mtu3_interrupt_skip_mode_t

enum mtu3_interrupt_skip_mode_t

Interrupt Skipping Function Select

Enumerator
MTU3_INTERRUPT_SKIP_MODE_1	Setting the TITCR1A or TITCR1B register enables.
MTU3_INTERRUPT_SKIP_MODE_2	Setting the TITCR2A or TITCR2B register enables.

mtu3_interrupt_skip_count_t

enum mtu3_interrupt_skip_count_t

Number of interrupts to skip between events

Enumerator
MTU3_INTERRUPT_SKIP_COUNT_0	Do not skip interrupts.
MTU3_INTERRUPT_SKIP_COUNT_1	Skip one interrupt.
MTU3_INTERRUPT_SKIP_COUNT_2	Skip two interrupts.
MTU3_INTERRUPT_SKIP_COUNT_3	Skip three interrupts.
MTU3_INTERRUPT_SKIP_COUNT_4	Skip four interrupts.
MTU3_INTERRUPT_SKIP_COUNT_5	Skip five interrupts.
MTU3_INTERRUPT_SKIP_COUNT_6	Skip six interrupts.
MTU3_INTERRUPT_SKIP_COUNT_7	Skip seven interrupts.

mtu3_adc_compare_match_t

enum mtu3_adc_compare_match_t

Trigger options to start A/D conversion.

Enumerator
MTU3_ADC_COMPARE_MATCH_ADC_A	Set A/D conversion start request value for MTU3 A/D converter start request A.
MTU3_ADC_COMPARE_MATCH_ADC_B	Set A/D conversion start request value for MTU3 A/D converter start request B.

mtu3_adc_activation_tgra_compare_match_t

enum mtu3_adc_activation_tgra_compare_match_t

Enumerator
MTU3_ADC_TGRA_COMPARE_MATCH_DISABLE	A/D Converter Activation by TGRA Input Capture/Compare Match Disable.
MTU3_ADC_TGRA_COMPARE_MATCH_ENABLE	A/D Converter Activation by TGRA Input Capture/Compare Match Enable.

Function Documentation

R_MTU3_Open()

fsp_err_t R_MTU3_Open	(	timer_ctrl_t *const	p_ctrl,
		timer_cfg_t const *const	p_cfg
	)

Initializes the timer module and applies configurations. Implements timer_api_t::open.

The MTU3 implementation of the general timer can accept a mtu3_extended_cfg_t extension parameter.

Example:

    /* Initializes the module. */
    err = R_MTU3_Open(&g_timer0_ctrl, &g_timer0_cfg);

Return values

FSP_SUCCESS	Initialization was successful and timer has started.
FSP_ERR_ASSERTION	A required input pointer is NULL.
FSP_ERR_ALREADY_OPEN	Module is already open.
FSP_ERR_INVALID_MODE	Only PERIODIC and PWM are supported.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	The channel requested in the p_cfg parameter is not available on this device.

R_MTU3_Stop()

fsp_err_t R_MTU3_Stop

(

timer_ctrl_t *const

p_ctrl

)

Stops timer. Implements timer_api_t::stop.

Example:

    /* (Optional) Stop the timer. */
    (void) R_MTU3_Stop(&g_timer0_ctrl);

Return values

FSP_SUCCESS	Timer successfully stopped.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_Start()

fsp_err_t R_MTU3_Start

(

timer_ctrl_t *const

p_ctrl

)

Starts timer. Implements timer_api_t::start.

Example:

    /* Start the timer. */
    (void) R_MTU3_Start(&g_timer0_ctrl);

Return values

FSP_SUCCESS	Timer successfully started.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_Reset()

fsp_err_t R_MTU3_Reset

(

timer_ctrl_t *const

p_ctrl

)

Resets the counter value to 0. Implements timer_api_t::reset.

Note

This function also updates to the new period if no counter overflow has occurred since the last call to R_MTU3_PeriodSet().

Return values

FSP_SUCCESS	Counter value written successfully.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_PeriodSet()

fsp_err_t R_MTU3_PeriodSet	(	timer_ctrl_t *const	p_ctrl,
		uint32_t const	period_counts
	)

Sets period value provided. If the timer is running, the period will be updated after the next compare match. If the timer is stopped, this function resets the counter and updates the period. Implements timer_api_t::periodSet.

Example:

    /* Get the source clock frequency (in Hz). There are 3 ways to do this in FSP:
     *  - If P0 clock  is chosen in agt_extended_cfg_t::clock_source and the P0 clock frequency has not changed since reset,
     *      - The source clock frequency is BSP_STARTUP_P0CLK_HZ >> timer_cfg_t::source_div
     *  - Use the R_MTU3_InfoGet function (it accounts for the divider).
     *  - Calculate the current P0 clock frequency using R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_P0CLK) and right shift
     *    by mtu3_extended_cfg_t::mtu3_clk_div.
     *
     * This example uses the 3rd option (R_FSP_SystemClockHzGet).
     */
    uint32_t p0clk_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_P0CLK) >> g_timer0_cfg.source_div;

    /* Calculate the desired period based on the current clock. Note that this calculation could overflow if the
     * desired period is larger than UINT16_MAX / p0clk_freq_hz. A cast to uint64_t is used to prevent this. */
    uint32_t period_counts =
        (uint32_t) (((uint64_t) p0clk_freq_hz * MTU3_EXAMPLE_DESIRED_PERIOD_MICROSEC) / MTU3_EXAMPLE_MICROSEC_PER_SEC);

    /* Set the calculated period. */
    err = R_MTU3_PeriodSet(&g_timer0_ctrl, period_counts);
    handle_error(err);

Return values

FSP_SUCCESS	Period value written successfully.
FSP_ERR_ASSERTION	A required pointer was NULL, or the period was not in the valid range of 1 to 0xFFFF.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_DutyCycleSet()

fsp_err_t R_MTU3_DutyCycleSet	(	timer_ctrl_t *const	p_ctrl,
		uint32_t const	duty_cycle_counts,
		uint32_t const	pin
	)

Sets duty cycle. Implements timer_api_t::dutyCycleSet.

Duty cycle is updated in the TGRx register.

Parameters

[in]	p_ctrl	Pointer to instance control block.
[in]	duty_cycle_counts	Duty cycle to set in counts. When the initial output setting of the period register is LOW, entering a value greater than the period register will result in a 0% duty cycle.
[in]	pin	Not Used.

Return values

FSP_SUCCESS	Duty cycle updated successfully.
FSP_ERR_ASSERTION	A required pointer was NULL, or the period was not in the valid range of 1 to 0xFFFF.
FSP_ERR_NOT_OPEN	The instance is not opened.
FSP_ERR_UNSUPPORTED	MTU3_CFG_OUTPUT_SUPPORT_ENABLE is 0.

R_MTU3_CompareMatchSet()

fsp_err_t R_MTU3_CompareMatchSet	(	timer_ctrl_t *const	p_ctrl,
		uint32_t const	compare_match_value,
		timer_compare_match_t const	match_channel
	)

Set value for compare match feature. Implements timer_api_t::compareMatchSet.

Note

This API should be used when timer is stop counting. And shall not be used along with PWM operation.

Example:

    /* Set the compare match value (MTU3_COMPARE_MATCH_EXAMPLE_VALUE). This value must be less than or equal to period value. */
    err = R_MTU3_CompareMatchSet(&g_timer0_ctrl, MTU3_COMPARE_MATCH_EXAMPLE_VALUE, TIMER_COMPARE_MATCH_A);
    assert(FSP_SUCCESS == err);

Return values

FSP_SUCCESS	Set the compare match value successfully.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_InfoGet()

fsp_err_t R_MTU3_InfoGet	(	timer_ctrl_t *const	p_ctrl,
		timer_info_t *const	p_info
	)

Get timer information and store it in provided pointer p_info. Implements timer_api_t::infoGet.

Return values

FSP_SUCCESS	TGRx, count direction, frequency, structure successfully.
FSP_ERR_ASSERTION	p_ctrl or p_info was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_StatusGet()

fsp_err_t R_MTU3_StatusGet	(	timer_ctrl_t *const	p_ctrl,
		timer_status_t *const	p_status
	)

Get current timer status and store it in provided pointer p_status. Implements timer_api_t::statusGet.

Example:

    /* Read the current counter value. Counter value is in status.counter. */
    timer_status_t status;
    (void) R_MTU3_StatusGet(&g_timer0_ctrl, &status);

Return values

FSP_SUCCESS	Current timer state and counter value set successfully.
FSP_ERR_ASSERTION	p_ctrl or p_status was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_CounterSet()

fsp_err_t R_MTU3_CounterSet	(	timer_ctrl_t *const	p_ctrl,
		uint32_t	counter
	)

Set counter value.

Note

Do not call this API while the counter is counting. The counter value can only be updated while the counter is stopped.

Return values

FSP_SUCCESS	Counter value updated.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.
FSP_ERR_IN_USE	The timer is running. Stop the timer before calling this function.

R_MTU3_OutputEnable()

fsp_err_t R_MTU3_OutputEnable	(	timer_ctrl_t *const	p_ctrl,
		mtu3_output_pin_t	pin_level
	)

Enable output for MTIOCA and/or MTIOCB.

Return values

FSP_SUCCESS	Output is enabled.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_OutputDisable()

fsp_err_t R_MTU3_OutputDisable	(	timer_ctrl_t *const	p_ctrl,
		mtu3_io_pin_t	pin
	)

Disable output for MTIOCA and/or MTIOCB.

Return values

FSP_SUCCESS	Output is disabled.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_Enable()

fsp_err_t R_MTU3_Enable

(

timer_ctrl_t *const

p_ctrl

)

timer_api_t::enable is not supported.

Return values

FSP_ERR_UNSUPPORTED

Enable not supported on this MPU.

R_MTU3_Disable()

fsp_err_t R_MTU3_Disable

(

timer_ctrl_t *const

p_ctrl

)

timer_api_t::disable is not supported.

Return values

FSP_ERR_UNSUPPORTED

Disable not supported on this MPU.

R_MTU3_AdcTriggerSet()

fsp_err_t R_MTU3_AdcTriggerSet	(	timer_ctrl_t *const	p_ctrl,
		mtu3_adc_compare_match_t	which_compare_match,
		uint16_t	compare_match_value
	)

Set A/D converter start request compare match value.

Note

MTU ch4, ch7 only

Return values

FSP_SUCCESS	Counter value updated.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_CallbackSet()

fsp_err_t R_MTU3_CallbackSet	(	timer_ctrl_t *const	p_api_ctrl,
		void(*)(timer_callback_args_t *)	p_callback,
		void const *const	p_context,
		timer_callback_args_t *const	p_callback_memory
	)

Updates the user callback with the option to provide memory for the callback argument structure. Implements timer_api_t::callbackSet.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

R_MTU3_Close()

fsp_err_t R_MTU3_Close

(

timer_ctrl_t *const

p_ctrl

)

Stops counter, disables output pins, and clears internal driver data. Implements timer_api_t::close.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.