Functions
fsp_err_t	R_SCIF_UART_Open (uart_ctrl_t const p_api_ctrl, uart_cfg_t const const p_cfg)

fsp_err_t	R_SCIF_UART_Read (uart_ctrl_t const p_api_ctrl, uint8_t const p_dest, uint32_t const bytes)

fsp_err_t	R_SCIF_UART_Write (uart_ctrl_t const p_api_ctrl, uint8_t const const p_src, uint32_t const bytes)

fsp_err_t	R_SCIF_UART_BaudSet (uart_ctrl_t const p_api_ctrl, void const const p_baud_setting)

fsp_err_t	R_SCIF_UART_InfoGet (uart_ctrl_t const p_api_ctrl, uart_info_t const p_info)

fsp_err_t	R_SCIF_UART_Close (uart_ctrl_t *const p_api_ctrl)

fsp_err_t	R_SCIF_UART_Abort (uart_ctrl_t *const p_api_ctrl, uart_dir_t communication_to_abort)

fsp_err_t	R_SCIF_UART_BaudCalculate (uart_ctrl_t const p_api_ctrl, uint32_t baudrate, bool bitrate_modulation, uint32_t baud_rate_error_x_1000, scif_baud_setting_t const p_baud_setting)

fsp_err_t	R_SCIF_UART_ReadStop (uart_ctrl_t const p_api_ctrl, uint32_t remaining_bytes)

fsp_err_t	R_SCIF_UART_CallbackSet (uart_ctrl_t const p_api_ctrl, void(p_callback)(uart_callback_args_t ), void const const p_context, uart_callback_args_t *const p_callback_memory)

Detailed Description

Driver for the SCIF peripheral on RZ MPUs. This module implements the UART Interface.

Overview

Features

The SCIF UART module supports the following features:

Full-duplex UART communication
Interrupt-driven data transmission and reception
Invoking the user-callback function with an event code (RX/TX complete, TX data empty, RX char, error, etc)
Baud-rate change at run-time
Bit rate modulation and noise cancellation
- RS232 CTS/RTS hardware flow control (with an associated pin)
- RS485 Half/Full Duplex flow control
Abort in-progress read/write operations
FIFO support on supported channels

Configuration

Build Time Configurations for r_scif_uart

The following build time configurations are defined in fsp_cfg/r_scif_uart_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
DMAC Support	Enable Disable	Disable	Enable DMAC support for the SCIF_UART module.
RS485 Flow (Driver Enable) Control Support	Enable Disable	Disable	Enable RS485 flow (driver enable) control support using a user provided pin.

Configurations for Connectivity > UART Driver on r_scif_uart

This module can be added to the Stacks tab via New Stack > Connectivity > UART Driver on r_scif_uart.

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_uart0	Module name.
General > Channel	Channel number does not exist	0	Select the SCIF channel.
General > Data Bits	8bits 7bits	8bits	Select the number of bits per word.
General > Parity	None Odd Even	None	Select the parity mode.
General > Stop Bits	1bit 2bits	1bit	Select the number of stop bits.
Baud > Baud Rate	Value must be an integer greater than 0	115200	Enter the desired baud rate.
Baud > Baud Rate Modulation	Disabled Enabled	Disabled	Enabling baud rate modulation reduces the percent error of the actual baud rate with respect to the requested baud rate. It does this by modulating the number of cycles per clock, so some bits are slightly longer than others.
Baud > Max Error (%)	Must be a valid non negative integer with a maximum configurable value of 100	5	Maximum percent error allowed during baud calculation. This is used by the algorithm to determine whether or not to consider using less accurate alternative register settings. NOTE: The baud calculation does not show an error in the tool if this percent error was not achieved. The calculated percent error is recorded in a comment in the generated baud_setting_t structure.
Flow Control > UART Communication Mode	RS232 RS485 Half Duplex RS485 Full Duplex	RS232	Select the UART communication mode as either RS232 or RS485.
Flow Control > RS485 Driver Enable Pin Polarity	Active Low Active High	Active High	Enabling baud rate modulation reduces the percent error of the actual baud rate with respect to the requested baud rate. It does this by modulating the number of cycles per clock, so some bits are slightly longer than others.
Flow Control > RS485 Driver Enable Port	Refer to the RZA Configuration tool for available options.	Disabled	Specify the flow control pin port for the MPU.
Flow Control > RS485 Driver Enable Pin	Disabled 00 01 02 03 04	Disabled	Specify the flow control pin for the MPU.
Flow Control > RS232C Automatic Flow Control	Enabled Disabled	Disabled	Enable RS232C automatic flow control.
Extra > Clock Source	Internal Clock Internal Clock With Output on SCK External Clock 8x baud rate External Clock 16x baud rate	Internal Clock	Selection of the clock source to be used in the baud-rate clock generator. When internal clock is used the baud rate can be output on the SCK pin.
Extra > Noise Filter	Enable Disable	Disable	Enable the digital noise filter on RXDn pin. The digital noise filter block in SCIF consists of two-stage flipflop circuits.
Extra > Receive FIFO Trigger Level	Refer to the RZA Configuration tool for available options.	Max	Set to One to get a callback immediately when each byte is received. Set to Max to get a callback when FIFO is full or after 15 bit times with no data (fewer interrupts).
Extra > Receive FIFO RTS Trigger Level	1 4 6 8 10 12 14 15	14	Trigger level for negative the RTS
Interrupts > Callback	Name must be a valid C symbol	NULL	A user callback function can be provided. If this callback function is provided, it will be called from the interrupt service routine (ISR).
Interrupts > Error Interrupt (ERI) Priority	Value must be an integer between 0 and 31	24	Select the error interrupt (eri) priority(0-31). Note: If you specify the lowest priority (i.e.,31), no interrupt will occur.
Interrupts > Error Interrupt (BRI) Priority	Value must be an integer between 0 and 31	24	Select the break detection interrupt (bri) and overrun error interrupt (orer) priority(0-31). Note: If you specify the lowest priority (i.e.,31), no interrupt will occur.
Interrupts > Receive Interrupt Priority	Value must be an integer between 0 and 31	24	Select the receive interrupt priority(0-31). Note: If you specify the lowest priority (i.e.,31), no interrupt will occur.
Interrupts > Transmit Data Empty Interrupt Priority	Value must be an integer between 0 and 31	24	Select the transmit interrupt priority(0-31). Note: If you specify the lowest priority (i.e.,31), no interrupt will occur.

Clock Configuration

The clock for this module is derived from the following peripheral clock for each MCU group:

MCU Group	Peripheral Clock
RZA3UL	P0CLK

The clock source for the baud-rate clock generator can be selected from the internal clock, the external clock times 8 or the external clock times 16. The external clock is supplied to the SCK pin.

Pin Configuration

This module uses TXD and RXD to communicate to external devices. CTS or RTS can be controlled by the hardware. If both are desired a GPIO pin can be used for RTS. When the internal clock is the source for the baud-rate generator the SCK pin can be used to output a clock with the same frequency as the bit rate.

Usage Notes

Limitations

Transfer size must be less than or equal to 64K bytes if DMAC interface is used for transfer. uart_api_t::infoGet API can be used to get the max transfer size allowed.
Reception is still enabled after uart_api_t::communicationAbort API is called. Any characters received after abort and before the next call to read will arrive via the callback function with event UART_EVENT_RX_CHAR.
When using 9-bit reception with DMAC, clear the upper 7 bits of data before processing the read data. The upper 7 bits contain status flags that are part of the register used to read data in 9-bit mode.

Examples

SCIF UART Example

uint8_t  g_dest[TRANSFER_LENGTH];
uint8_t  g_src[TRANSFER_LENGTH];
uint8_t  g_out_of_band_received[TRANSFER_LENGTH];
uint32_t g_transfer_complete = 0;
uint32_t g_receive_complete  = 0;
uint32_t g_out_of_band_index = 0;
void r_scif_uart_basic_example (void)
{
    /* Initialize p_src to known data */
    for (uint32_t i = 0; i < TRANSFER_LENGTH; i++)
    {
        g_src[i] = (uint8_t) ('A' + (i % 26));
    }
    /* Open the transfer instance with initial configuration. */
    fsp_err_t err = R_SCIF_UART_Open(&g_uart0_ctrl, &g_uart0_cfg);
    assert(FSP_SUCCESS == err);
    err = R_SCIF_UART_Read(&g_uart0_ctrl, g_dest, TRANSFER_LENGTH);
    assert(FSP_SUCCESS == err);
    err = R_SCIF_UART_Write(&g_uart0_ctrl, g_src, TRANSFER_LENGTH);
    assert(FSP_SUCCESS == err);
    while (!g_transfer_complete)
    {
    }
    while (!g_receive_complete)
    {
    }
}
void example_callback (uart_callback_args_t * p_args)
{
    /* Handle the UART event */
    switch (p_args->event)
    {
        /* Received a character */
        case UART_EVENT_RX_CHAR:
        {
            /* Only put the next character in the receive buffer if there is space for it */
            if (sizeof(g_out_of_band_received) > g_out_of_band_index)
            {
                /* Write either the next one or two bytes depending on the receive data size */
                if (UART_DATA_BITS_8 >= g_uart0_cfg.data_bits)
                {
                    g_out_of_band_received[g_out_of_band_index++] = (uint8_t) p_args->data;
                }
                else
                {
                    uint16_t * p_dest = (uint16_t *) &g_out_of_band_received[g_out_of_band_index];
                    *p_dest              = (uint16_t) p_args->data;
                    g_out_of_band_index += 2;
                }
            }
            break;
        }
        /* Receive complete */
        case UART_EVENT_RX_COMPLETE:
        {
            g_receive_complete = 1;
            break;
        }
        /* Transmit complete */
        case UART_EVENT_TX_COMPLETE:
        {
            g_transfer_complete = 1;
            break;
        }
        default:
        {
        }
    }
}

SCIF UART Baud Set Example

#define SCIF_UART_BAUDRATE_19200              (19200)
#define SCIF_UART_BAUDRATE_ERROR_PERCENT_5    (5000)
void r_scif_uart_baud_example (void)
{
    scif_baud_setting_t scif_baud_setting;
    uint32_t            baud_rate                 = SCIF_UART_BAUDRATE_19200;
    bool                enable_bitrate_modulation = false;
    uint32_t            error_rate_x_1000         = SCIF_UART_BAUDRATE_ERROR_PERCENT_5;
    fsp_err_t err = R_SCIF_UART_BaudCalculate(&g_uart0_ctrl,
                                              baud_rate,
                                              enable_bitrate_modulation,
                                              error_rate_x_1000,
                                              &scif_baud_setting);
    assert(FSP_SUCCESS == err);
    err = R_SCIF_UART_BaudSet(&g_uart0_ctrl, (void *) &scif_baud_setting);
    assert(FSP_SUCCESS == err);
}

Data Structures
struct	scif_uart_instance_ctrl_t

struct	scif_baud_setting_t

struct	scif_uart_rs485_setting_t

struct	scif_uart_extended_cfg_t

Enumerations
enum	scif_clk_src_t

enum	scif_uart_mode_t

enum	scif_uart_flow_control_t

enum	scif_uart_noise_cancellation_t

enum	scif_uart_rs485_enable_t

enum	scif_uart_rs485_de_polarity_t

enum	scif_uart_rx_fifo_trigger_t

enum	scif_uart_rts_trigger_t

Data Structure Documentation

◆ scif_uart_instance_ctrl_t

struct scif_uart_instance_ctrl_t

UART instance control block.

◆ scif_baud_setting_t

struct scif_baud_setting_t

Register settings to achieve a desired baud rate and modulation duty.

Data Fields
struct scif_baud_setting_t	semr_baudrate_bits_b
uint8_t	brr	Bit Rate Register setting.
uint8_t	mddr	Modulation Duty Register setting.

◆ scif_uart_rs485_setting_t

struct scif_uart_rs485_setting_t

Configuration settings for controlling the DE signal for RS-485.

Data Fields
scif_uart_rs485_enable_t	enable	Enable the DE signal.
scif_uart_rs485_de_polarity_t	polarity	DE signal polarity.
bsp_io_port_pin_t	de_control_pin	UART Driver Enable pin.

◆ scif_uart_extended_cfg_t

struct scif_uart_extended_cfg_t

UART on SCIF device Configuration

Data Fields
uint8_t	bri_ipl	Break interrupt priority.
IRQn_Type	bri_irq	Break interrupt IRQ number.
scif_clk_src_t	clock	The source clock for the baud-rate generator.
scif_uart_noise_cancellation_t	noise_cancel	Noise cancellation setting.
scif_baud_setting_t *	p_baud_setting	Register settings for a desired baud rate.
scif_uart_rx_fifo_trigger_t	rx_fifo_trigger	Receive FIFO trigger level.
scif_uart_rts_trigger_t	rts_fifo_trigger	RTS trigger level.
scif_uart_mode_t	uart_mode	UART communication mode selection.
scif_uart_flow_control_t	flow_control	CTS/RTS function.
scif_uart_rs485_setting_t	rs485_setting	RS-485 settings.

Enumeration Type Documentation

◆ scif_clk_src_t

enum scif_clk_src_t

Enumeration for SCIF clock source

Enumerator
SCIF_UART_CLOCK_INT	Use internal clock for baud generation.
SCIF_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT	Use internal clock for baud generation and output on SCK.
SCIF_UART_CLOCK_EXT8X	Use external clock 8x baud rate.
SCIF_UART_CLOCK_EXT16X	Use external clock 16x baud rate.

◆ scif_uart_mode_t

enum scif_uart_mode_t

UART communication mode definition

Enumerator
SCIF_UART_MODE_RS232	Enables RS232 communication mode.
SCIF_UART_MODE_RS485_HD	Enables RS485 half duplex communication mode.
SCIF_UART_MODE_RS485_FD	Enables RS485 full duplex communication mode.

◆ scif_uart_flow_control_t

enum scif_uart_flow_control_t

UART automatic flow control definition

Enumerator
SCIF_UART_FLOW_CONTROL_NONE	Disables flow control.
SCIF_UART_FLOW_CONTROL_AUTO	Enables automatic RTS/CTS flow control.

◆ scif_uart_noise_cancellation_t

enum scif_uart_noise_cancellation_t

Noise cancellation configuration.

Enumerator
SCIF_UART_NOISE_CANCELLATION_DISABLE	Disable noise cancellation.
SCIF_UART_NOISE_CANCELLATION_ENABLE	Enable noise cancellation.

◆ scif_uart_rs485_enable_t

enum scif_uart_rs485_enable_t

RS-485 Enable/Disable.

Enumerator
SCIF_UART_RS485_DISABLE	RS-485 disabled.
SCIF_UART_RS485_ENABLE	RS-485 enabled.

◆ scif_uart_rs485_de_polarity_t

enum scif_uart_rs485_de_polarity_t

The polarity of the RS-485 DE signal.

Enumerator
SCIF_UART_RS485_DE_POLARITY_HIGH	The DE signal is high when a write transfer is in progress.
SCIF_UART_RS485_DE_POLARITY_LOW	The DE signal is low when a write transfer is in progress.

◆ scif_uart_rx_fifo_trigger_t

enum scif_uart_rx_fifo_trigger_t

Receive FIFO trigger configuration.

Enumerator
SCIF_UART_RX_FIFO_TRIGGER_ONE	Interrupt at least one byte is in FIFO.
SCIF_UART_RX_FIFO_TRIGGER_QUARTER	Interrupt at least quarter of FIFO or 15ETU past from last receive.
SCIF_UART_RX_FIFO_TRIGGER_HALF	Interrupt at least half of FIFO or 15ETU past from last receive.
SCIF_UART_RX_FIFO_TRIGGER_MAX	Interrupt at almost full in FIFO or 15ETU past from last receive.
SCIF_UART_RX_FIFO_TRIGGER_1	Interrupt at least 1 byte is in FIFO or 15ETU past from last receive.
SCIF_UART_RX_FIFO_TRIGGER_2	Interrupt at least 2 bytes is in FIFO or 15ETU past from last receive.
SCIF_UART_RX_FIFO_TRIGGER_3	Interrupt at least 3 bytes is in FIFO or 15ETU past from last receive.
SCIF_UART_RX_FIFO_TRIGGER_4	Interrupt at least 4 bytes is in FIFO or 15ETU past from last receive.
SCIF_UART_RX_FIFO_TRIGGER_5	Interrupt at least 5 bytes is in FIFO or 15ETU past from last receive.
SCIF_UART_RX_FIFO_TRIGGER_6	Interrupt at least 6 bytes is in FIFO or 15ETU past from last receive.
SCIF_UART_RX_FIFO_TRIGGER_7	Interrupt at least 7 bytes is in FIFO or 15ETU past from last receive.
SCIF_UART_RX_FIFO_TRIGGER_8	Interrupt at least 8 bytes is in FIFO or 15ETU past from last receive.
SCIF_UART_RX_FIFO_TRIGGER_9	Interrupt at least 9 bytes is in FIFO or 15ETU past from last receive.
SCIF_UART_RX_FIFO_TRIGGER_10	Interrupt at least 10 bytes is in FIFO or 15ETU past from last receive.
SCIF_UART_RX_FIFO_TRIGGER_11	Interrupt at least 11 bytes is in FIFO or 15ETU past from last receive.
SCIF_UART_RX_FIFO_TRIGGER_12	Interrupt at least 12 bytes is in FIFO or 15ETU past from last receive.
SCIF_UART_RX_FIFO_TRIGGER_13	Interrupt at least 13 bytes is in FIFO or 15ETU past from last receive.
SCIF_UART_RX_FIFO_TRIGGER_14	Interrupt at least 14 bytes is in FIFO or 15ETU past from last receive.
SCIF_UART_RX_FIFO_TRIGGER_15	Interrupt at least 15 bytes is in FIFO or 15ETU past from last receive.

◆ scif_uart_rts_trigger_t

enum scif_uart_rts_trigger_t

RTS trigger level.

Enumerator
SCIF_UART_RTS_TRIGGER_1	RTS trigger level = 1.
SCIF_UART_RTS_TRIGGER_4	RTS trigger level = 4.
SCIF_UART_RTS_TRIGGER_6	RTS trigger level = 6.
SCIF_UART_RTS_TRIGGER_8	RTS trigger level = 8.
SCIF_UART_RTS_TRIGGER_10	RTS trigger level = 10.
SCIF_UART_RTS_TRIGGER_12	RTS trigger level = 12.
SCIF_UART_RTS_TRIGGER_14	RTS trigger level = 14.
SCIF_UART_RTS_TRIGGER_15	RTS trigger level = 15.

Function Documentation

◆ R_SCIF_UART_Open()

fsp_err_t R_SCIF_UART_Open	(	uart_ctrl_t *const	p_api_ctrl,
		uart_cfg_t const *const	p_cfg
	)

Configures the UART driver based on the input configurations. If reception is enabled at compile time, reception is enabled at the end of this function. Implements uart_api_t::open

Return values

FSP_SUCCESS	Channel opened successfully.
FSP_ERR_ASSERTION	Pointer to UART control block or configuration structure is NULL.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	The requested channel does not exist on this MPU.
FSP_ERR_ALREADY_OPEN	Control block has already been opened or channel is being used by another instance. Call close() then open() to reconfigure.
FSP_ERR_INVALID_ARGUMENT	Setting for RS485 DE Control pin is invalid

Returns: See Common Error Codes

◆ R_SCIF_UART_Read()

fsp_err_t R_SCIF_UART_Read	(	uart_ctrl_t *const	p_api_ctrl,
		uint8_t *const	p_dest,
		uint32_t const	bytes
	)

Receives user specified number of bytes into destination buffer pointer. Implements uart_api_t::read

Return values

FSP_SUCCESS	Data reception successfully ends.
FSP_ERR_ASSERTION	Pointer to UART control block is NULL. Number of transfers outside the max or min boundary when transfer instance used
FSP_ERR_NOT_OPEN	The control block has not been opened
FSP_ERR_IN_USE	A previous read operation is still in progress.
FSP_ERR_UNSUPPORTED	SCIF_UART_CFG_RX_ENABLE is set to 0

Returns: See Common Error Codes

◆ R_SCIF_UART_Write()

fsp_err_t R_SCIF_UART_Write	(	uart_ctrl_t *const	p_api_ctrl,
		uint8_t const *const	p_src,
		uint32_t const	bytes
	)

Transmits user specified number of bytes from the source buffer pointer. Implements uart_api_t::write

Return values

FSP_SUCCESS	Data transmission finished successfully.
FSP_ERR_ASSERTION	Pointer to UART control block is NULL. Number of transfers outside the max or min boundary when transfer instance used
FSP_ERR_NOT_OPEN	The control block has not been opened
FSP_ERR_IN_USE	A UART transmission is in progress
FSP_ERR_UNSUPPORTED	SCIF_UART_CFG_TX_ENABLE is set to 0

Returns: See Common Error Codes

◆ R_SCIF_UART_BaudSet()

fsp_err_t R_SCIF_UART_BaudSet	(	uart_ctrl_t *const	p_api_ctrl,
		void const *const	p_baud_setting
	)

Updates the baud rate using the clock selected in Open. p_baud_setting is a pointer to a scif_baud_setting_t structure. Implements uart_api_t::baudSet

Warning: This terminates any in-progress transmission.

Return values

FSP_SUCCESS	Baud rate was successfully changed.
FSP_ERR_ASSERTION	Pointer to UART control block is NULL or the UART is not configured to use the internal clock.
FSP_ERR_NOT_OPEN	The control block has not been opened

◆ R_SCIF_UART_InfoGet()

fsp_err_t R_SCIF_UART_InfoGet	(	uart_ctrl_t *const	p_api_ctrl,
		uart_info_t *const	p_info
	)

Provides the driver information, including the maximum number of bytes that can be received or transmitted at a time. Implements uart_api_t::infoGet

Return values

FSP_SUCCESS	Information stored in provided p_info.
FSP_ERR_ASSERTION	Pointer to UART control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened

◆ R_SCIF_UART_Close()

fsp_err_t R_SCIF_UART_Close ( uart_ctrl_t *const p_api_ctrl )

Aborts any in progress transfers. Disables interrupts, receiver, and transmitter. Closes lower level transfer drivers if used. Removes power. Implements uart_api_t::close

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	Pointer to UART control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened

◆ R_SCIF_UART_Abort()

fsp_err_t R_SCIF_UART_Abort	(	uart_ctrl_t *const	p_api_ctrl,
		uart_dir_t	communication_to_abort
	)

Provides API to abort ongoing transfer. Transmission is aborted after the current character is transmitted. Reception is still enabled after abort(). Any characters received after abort() and before the transfer is reset in the next call to read(), will arrive via the callback function with event UART_EVENT_RX_CHAR. Implements uart_api_t::communicationAbort

Return values

FSP_SUCCESS	UART transaction aborted successfully.
FSP_ERR_ASSERTION	Pointer to UART control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_UNSUPPORTED	The requested Abort direction is unsupported.

Returns: See Common Error Codes or functions called by this function for other possible return codes.

◆ R_SCIF_UART_BaudCalculate()

fsp_err_t R_SCIF_UART_BaudCalculate	(	uart_ctrl_t *const	p_api_ctrl,
		uint32_t	baudrate,
		bool	bitrate_modulation,
		uint32_t	baud_rate_error_x_1000,
		scif_baud_setting_t *const	p_baud_setting
	)

Calculates baud rate register settings. Evaluates and determines the best possible settings set to the baud rate related registers.

Parameters

[in]	p_api_ctrl	Pointer to the UART control block.
[in]	baudrate	Baud rate [bps]. For example, 19200, 57600, 115200, etc.
[in]	bitrate_modulation	Enable bitrate modulation
[in]	baud_rate_error_x_1000	<baud_rate_percent_error> x 1000 required for module to function. Absolute max baud_rate_error is 15000 (15%).
[out]	p_baud_setting	Baud setting information stored here if successful

Return values

FSP_SUCCESS	Baud rate is set successfully
FSP_ERR_ASSERTION	Null pointer
FSP_ERR_INVALID_ARGUMENT	Baud rate is '0', source clock frequency could not be read, or error in calculated baud rate is larger than 10%.

◆ R_SCIF_UART_ReadStop()

fsp_err_t R_SCIF_UART_ReadStop	(	uart_ctrl_t *const	p_api_ctrl,
		uint32_t *	remaining_bytes
	)

Provides API to abort ongoing read. Reception is still enabled after abort(). Any characters received after abort() and before the transfer is reset in the next call to read(), will arrive via the callback function with event UART_EVENT_RX_CHAR. Implements uart_api_t::readStop

Return values

FSP_SUCCESS	UART transaction aborted successfully.
FSP_ERR_ASSERTION	Pointer to UART control block is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_UNSUPPORTED	The requested Abort direction is unsupported.

Returns: See Common Error Codes or functions called by this function for other possible return codes.

◆ R_SCIF_UART_CallbackSet()

fsp_err_t R_SCIF_UART_CallbackSet	(	uart_ctrl_t *const	p_api_ctrl,
		void()(uart_callback_args_t )	p_callback,
		void const *const	p_context,
		uart_callback_args_t *const	p_callback_memory
	)

Updates the user callback and has option of providing memory for callback structure. Implements uart_api_t::callbackSet

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.
FSP_ERR_NO_CALLBACK_MEMORY	p_callback is non-secure and p_callback_memory is either secure or NULL.

Functions

Detailed Description

Overview

Features

Configuration

Build Time Configurations for r_scif_uart

Configurations for Connectivity > UART Driver on r_scif_uart

Clock Configuration

Pin Configuration

Usage Notes

Limitations

Examples

SCIF UART Example

SCIF UART Baud Set Example

Data Structures

Enumerations

Data Structure Documentation

◆ scif_uart_instance_ctrl_t

◆ scif_baud_setting_t

◆ scif_uart_rs485_setting_t

◆ scif_uart_extended_cfg_t

Enumeration Type Documentation

◆ scif_clk_src_t

◆ scif_uart_mode_t

◆ scif_uart_flow_control_t

◆ scif_uart_noise_cancellation_t

◆ scif_uart_rs485_enable_t

◆ scif_uart_rs485_de_polarity_t

◆ scif_uart_rx_fifo_trigger_t

◆ scif_uart_rts_trigger_t

Function Documentation

◆ R_SCIF_UART_Open()

◆ R_SCIF_UART_Read()

◆ R_SCIF_UART_Write()

◆ R_SCIF_UART_BaudSet()

◆ R_SCIF_UART_InfoGet()

◆ R_SCIF_UART_Close()

◆ R_SCIF_UART_Abort()

◆ R_SCIF_UART_BaudCalculate()

◆ R_SCIF_UART_ReadStop()

◆ R_SCIF_UART_CallbackSet()