Quad Serial Peripheral Interface Flash (r_spibsc)

Functions
fsp_err_t	R_SPIBSC_Open (spi_flash_ctrl_t *p_api_ctrl, spi_flash_cfg_t const *const p_cfg)
fsp_err_t	R_SPIBSC_Close (spi_flash_ctrl_t *p_api_ctrl)
fsp_err_t	R_SPIBSC_DirectWrite (spi_flash_ctrl_t *p_api_ctrl, uint8_t const *const p_src, uint32_t const bytes, bool const read_after_write)
fsp_err_t	R_SPIBSC_DirectRead (spi_flash_ctrl_t *p_api_ctrl, uint8_t *const p_dest, uint32_t const bytes)
fsp_err_t	R_SPIBSC_SpiProtocolSet (spi_flash_ctrl_t *p_api_ctrl, spi_flash_protocol_t spi_protocol)
fsp_err_t	R_SPIBSC_XipEnter (spi_flash_ctrl_t *p_api_ctrl)
fsp_err_t	R_SPIBSC_XipExit (spi_flash_ctrl_t *p_api_ctrl)
fsp_err_t	R_SPIBSC_Write (spi_flash_ctrl_t *p_api_ctrl, uint8_t const *const p_src, uint8_t *const p_dest, uint32_t byte_count)
fsp_err_t	R_SPIBSC_Erase (spi_flash_ctrl_t *p_api_ctrl, uint8_t *const p_device_address, uint32_t byte_count)
fsp_err_t	R_SPIBSC_StatusGet (spi_flash_ctrl_t *p_api_ctrl, spi_flash_status_t *const p_status)
fsp_err_t	R_SPIBSC_BankSet (spi_flash_ctrl_t *p_api_ctrl, uint32_t bank)
fsp_err_t	R_SPIBSC_DirectTransfer (spi_flash_ctrl_t *p_api_ctrl, spi_flash_direct_transfer_t *const p_transfer, spi_flash_direct_transfer_dir_t direction)
fsp_err_t	R_SPIBSC_AutoCalibrate (spi_flash_ctrl_t *p_api_ctrl)

Detailed Description

Driver for the SPIBSC peripheral on RZ MPUs. This module implements the SPI Flash Interface.

Overview

Features

The SPIBSC driver has the following key features:

• Initialization of memory mapped read access to QSPI flash device (Disabled by default. The Initial Program Loader already enables it before running application)
• Programming QSPI flash device
• Erasing QSPI flash device
• Sending device specific commands and reading back responses
• Entering and exiting XIP mode
• 3 or 4 byte addressing
• Obtaining write status by de-facto standard instructions

Configuration

Build Time Configurations for r_spibsc

The following build time configurations are defined in driver/r_spibsc_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
SPIBSC initialization	Disable Enable	Disable	Whether or not to enable initialization of SPIBSC or not.

Configurations for Storage > SPIBSC (r_spibsc)

This module can be added to the Stacks tab via New Stack > Storage > SPIBSC (r_spibsc).

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_spi_flash0	Module name.
General > SPI Protocol	Extended SPI	Extended SPI	Select the initial SPI protocol.
General > Address Bytes	3 4 4 with 4-byte read code	3	Select the number of address bytes. Selecting '4 with 4-byte read code' converts the default read code determined in Read Mode to the 4-byte version. If 4-byte mode is selected without using 4-byte commands, the application must issue the EN4B command using R_SPIBSC_Direct().
General > Read Mode	Standard Read Fast Read Fast Read Quad Output Fast Read Quad I/O	Fast Read Quad I/O	Select the read mode for memory mapped access.
General > Dummy Clocks for Fast Read	Refer to the RZA Configuration tool for available options.	Default	Select the number of dummy clocks for fast read operations. Default is 6 clocks for Fast Read Quad I/O, and 8 clocks for other fast read instructions including Fast Read Quad Output, and Fast Read
General > Page Size Bytes	Must be an integer greater than 0	256	The maximum number of bytes allowed for a single write.
Command Definitions > Read Command	Must be an 8-bit Read Command under Command Definitions	0x00	The Read command. Set Read Command to 0 if selected by Read Mode and Address Bytes.
Command Definitions > Page Program Command	Must be an 8-bit Page Program Command under Command Definitions	0x33	The command to program a page.
Command Definitions > Page Program Address Lines	1 4	4	Select the number of lines to use for the address bytes during write operations. This can be determined by referencing the datasheet for the flash memory device.
Command Definitions > Write Enable Command	Must be an 8-bit Write Enable Command under Command Definitions	0x06	The command to enable write.
Command Definitions > Read Status Command	Must be an 8-bit Read Status Command under Command Definitions	0x05	The command to query the status of a write or erase command.
Command Definitions > Write Status Bit	Must be an integer between 0 and 7	0	Which bit contains the write in progress status returned from the Read Status Command.
Command Definitions > Erase Command #1	Must be an 8-bit Erase Command under Command Definitions	0x20	The command to erase #1. Set Erase Size #1 to 0 if unused.
Command Definitions > Erase Size #1	Must be an integer greater than or equal to 0	4096	The erase size #1. Set Erase Size #1 to 0 if Erase #1 is not supported.
Command Definitions > Erase Command #2	Must be an 8-bit Erase Command under Command Definitions	0x52	The command to erase #2. Set Erase Size #2 to 0 if unused.
Command Definitions > Erase Size #2	Must be an integer greater than or equal to 0	32768	The erase size #2. Set Erase Size #2 to 0 if Erase #2 is not supported.
Command Definitions > Erase Command #3	Must be an 8-bit Erase Command under Command Definitions	0xD8	The command to erase #3. Set Erase Size #3 to 0 if unused.
Command Definitions > Erase Size #3	Must be an integer greater than or equal to 0	65536	The erase size #3. Set Erase Size #3 to 0 if Erase #3 is not supported.
Command Definitions > Chip Erase Command	Must be an 8-bit Chip Erase Command under Command Definitions	0xC7	The command to erase the entire chip. Set Chip Erase Command to 0 if unused.
Command Definitions > XIP Enter M7-M0	Must be an 8-bit XIP Enter M7-M0 command under Command Definitions	0xa5	How to set M7-M0 to enter XIP mode.
Command Definitions > XIP Exit M7-M0	Must be an 8-bit XIP Exit M7-M0 command under Command Definitions	0x00	How to set M7-M0 exit XIP mode.
Bus Parameter > IO2 Fix Enable	Enable Disable	Disable	Enable or not the IO2 level will fix during idle state.
Bus Parameter > IO2 Fix Value	1 (High) 0 (Low)	1 (High)	Value for IO2 level fix state.
Bus Parameter > IO3 Fix Enable	Enable Disable	Enable	Enable or not the IO3 level will fix during idle state.
Bus Parameter > IO3 Fix Value	1 (High) 0 (Low)	1 (High)	Value for IO3 level fix state.
Bus Timing > Select to Clock Delay Cycles	1.5 cycle 2.5 cycle 3.5 cycle 4.5 cycle 5.5 cycle 6.5 cycle 7.5 cycle 8.5 cycle	1.5 cycle	Define the cycles that begin the SCLK from SSL start.
Bus Timing > Clock Low to De-select Delay Cycles	1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle	1 cycle	Define the cycles that stop the SSL from last SCLK is out.
Bus Timing > De-select to Select Delay Cycles	1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle	5 cycle	Define the cycles that starts the new SSL from previous SSL finished.

Clock Configuration

The QSPI clock is derived from SPI1φ.

Note

This implementation does not change the SPI1φ settings. Do call R_FSP_SystemClockHzSet(FSP_PRIV_CLOCK_SPI1CLK, 2nd, 3rd) separately if needed.

Desired SPI frequency	2nd parameter	3rd parameter
66.625MHz	0	1
50MHz	1	1
33.3125MHz	0	2
25MHz	1	2
16.65625MHz	0	3
12.5MHz	1	3
4.1640625MHz	0	4
3.125MHz	1	4

Pin Configuration

RZ MPUs provide these pins as dedicated.

Usage Notes

QSPI Memory Mapped Access

The IPL already enables as memory-mapped access. By the default, R_SPIBSC_Open() does nothing to configure and only prepare to erase/write.

Limitations

Developers should be aware of the following limitations when using the SPIBSC driver:

• While write/erase operation is in progress, do not access flash contents via the memory-mapped area.
  • To use the erase, write, or the bankSet function, both the caller's and the callee's codes and datas must not store in the affected flash memory.
  • It also includes indirect access by interrupt handlers, etc.

Examples

Basic Example (R_SPIBSC_Open, R_SPIBSC_Close, R_SPIBSC_Erase, R_SPIBSC_Write, R_SPIBSC_StatusGet)

This is a basic write example in an application.

#define SPIBSC_EXAMPLE_ERASE_LENGTH    (4096)
#define SPIBSC_EXAMPLE_DATA_LENGTH     (256)
#define EXAMPLE_TARGET_ADDRESS         ((uint8_t *) 0x20fff000)
#define ERASE_TEST_VALUE               (0xffffffffffffffffULL)
#define ERASE_TEST_VALUE_U8            (0xffU)

static uint8_t s_src[SPIBSC_EXAMPLE_DATA_LENGTH] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ";

/* Place code in the FASTCODE(On-chip RAM) section. */
static void r_spibsc_example_wait(void) BSP_PLACE_IN_SECTION("FASTCODE");

static void r_spibsc_example_wait (void)
{
    spi_flash_status_t status;
    fsp_err_t          err;

    while (1)
    {

        /* Obtaining status */
        err = R_SPIBSC_StatusGet(&g_spi_flash0_ctrl, &status);

        assert(FSP_SUCCESS == err);

        /* Check it and break if not in progress */
        if (status.write_in_progress == false)
        {
            break;
        }
    }
}

static bool check_erased(void * buf, size_t size) BSP_PLACE_IN_SECTION("FASTCODE");

static bool check_erased (void * buf, size_t size)
{
    uintptr_t       current = (uintptr_t) buf;
    const uint8_t * u8test;
    if (current & 7)
    {
        u8test = (const uint8_t *) current;
        uintptr_t remain = current & 7;
        while (size && remain)
        {
            if (*u8test != ERASE_TEST_VALUE_U8)
            {
                return false;
            }

            size--;
            remain--;
            u8test++;
        }

        current = (uintptr_t) u8test;
    }
    else
    {
        const uint64_t * u64test = (const uint64_t *) current;
        while (size >= 8)
        {
            if (*u64test != ERASE_TEST_VALUE)
            {
                return false;
            }

            size -= 8;
            u64test++;
        }

        current = (uintptr_t) u64test;
    }

    u8test = (const uint8_t *) current;
    while (size)
    {
        if (*u8test != ERASE_TEST_VALUE_U8)
        {
            return false;
        }

        size--;
        u8test++;
    }

    return true;
}

fsp_err_t r_spibsc_basic_example(void) BSP_PLACE_IN_SECTION("FASTCODE");

fsp_err_t r_spibsc_basic_example (void)
{
    fsp_err_t err;


    /* Open SPIBSC instance. */
    err = R_SPIBSC_Open(&g_spi_flash0_ctrl, &g_spi_flash0_cfg);

    FSP_ERROR_RETURN(err == FSP_SUCCESS, err);


    /* Erase 4KB sector from 0xfff000 via erase API. */
    err = R_SPIBSC_Erase(&g_spi_flash0_ctrl, EXAMPLE_TARGET_ADDRESS, SPIBSC_EXAMPLE_ERASE_LENGTH);

    FSP_ERROR_RETURN(err == FSP_SUCCESS, err);

    /* Wait for erase complete */
    r_spibsc_example_wait();

    /* Invalidating SPIBSC cache before invalidating cache */
    R_SPIBSC->DRCR_b.RCF = 1;

    /* After the write/erase is completed, invalidating its cached data is required because the contents are useless. */
    R_BSP_CACHE_InvalidateRange((uint64_t) EXAMPLE_TARGET_ADDRESS, SPIBSC_EXAMPLE_ERASE_LENGTH);

    /* Validating erase */
    FSP_ERROR_RETURN(check_erased(EXAMPLE_TARGET_ADDRESS, SPIBSC_EXAMPLE_ERASE_LENGTH), FSP_ERR_ERASE_FAILED);


    /* Write 256-byte page from 0xfff000 via write API. */
    err = R_SPIBSC_Write(&g_spi_flash0_ctrl, &s_src[0], EXAMPLE_TARGET_ADDRESS, SPIBSC_EXAMPLE_DATA_LENGTH);

    FSP_ERROR_RETURN(err == FSP_SUCCESS, err);

    /* Wait for erase complete */
    r_spibsc_example_wait();

    /* Invalidating SPIBSC cache before invalidating cache */
    R_SPIBSC->DRCR_b.RCF = 1;

    /* After the write/erase is completed, invalidating its cached data is required because the contents are useless. */
    R_BSP_CACHE_InvalidateRange((uint64_t) EXAMPLE_TARGET_ADDRESS, SPIBSC_EXAMPLE_DATA_LENGTH);

    /* Verifying wrote data */
    if (memcmp(s_src, EXAMPLE_TARGET_ADDRESS, SPIBSC_EXAMPLE_DATA_LENGTH) == 0)
    {
        /* Verify succeed */
    }
    else
    {
        /* Verify failed */
    }


    /* Close SPIBSC instance. */
    err = R_SPIBSC_Close(&g_spi_flash0_ctrl);


    return err;
}

Reading Flag Status Register Example (R_SPIBSC_DirectTransfer)

Some flash memories may be polled alternated ways for the "write in progress" status. In this case, developers implement their StatusGet function. There is an example of implementing the StatusGet function using R_SPIBSC_DirectTransfer API.

#define SPIBSC_COMMAND_READ_FLAG_STATUS_REGISTER    (0x70U)

fsp_err_t r_spibsc_own_statusget_example (bool * p_write_in_progress)
{
    /* Read a flag status register. */
    spi_flash_direct_transfer_t transfer =
    {
        .address        = 0,
        .data           = 0,
        .command        = SPIBSC_COMMAND_READ_FLAG_STATUS_REGISTER,
        .dummy_cycles   = 0,
        .command_length = 1,
        .address_length = 0,
        .data_length    = 1
    };

    fsp_err_t err;

    /* Execute direct transaction */
    err = R_SPIBSC_DirectTransfer(&g_spi_flash0_ctrl, &transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    assert(FSP_SUCCESS == err);

    /* Status register contents are available in lower-byte of 'transfer.data'. */
    /* Check b7 of returned data */
    if (transfer.data & (1U << 7))
    {
        *p_write_in_progress = false;
    }
    else
    {
        *p_write_in_progress = true;
    }

    return err;
}

Querying Device Size Example (R_SPIBSC_DirectTransfer)

This is an example of using R_SPIBSC_DirectTransfer to query the device size.

#define SPIBSC_EXAMPLE_COMMAND_READ_ID      (0x9F)
#define SPIBSC_EXAMPLE_COMMAND_READ_SFDP    (0x5A)
#define MAKEUINT32(p1, p2, p3,                                                                                         \
                   p4)    ((uint32_t) ((uint32_t) (p1) * 0x1000000UL + (uint32_t) (p2) * 0x10000UL + (uint32_t) (p3) * \
                                       0x100UL +                                                                       \
                                       (uint32_t) (p4)))

void r_spibsc_size_example (void)
{
    /* Many QSPI devices support more than one way to query the device size. Consult the datasheet for your
     * flash device to determine which of these methods are supported (if any). */
    uint32_t  device_size_bytes;
    fsp_err_t err;
    uint8_t   buffer[16];

#ifdef SPIBSC_EXAMPLE_COMMAND_READ_ID

    /* This example shows how to get the device size by reading the manufacturer ID. */
    spi_flash_direct_transfer_t transfer =
    {
        .address        = 0,
        .data           = 0,
        .command        = SPIBSC_EXAMPLE_COMMAND_READ_ID,
        .dummy_cycles   = 0,
        .command_length = 1,
        .address_length = 0,
        .data_length    = 3
    };

    /* Execute direct transaction */
    err = R_SPIBSC_DirectTransfer(&g_spi_flash0_ctrl, &transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    assert(FSP_SUCCESS == err);

    /* The third byte often represents the size of the flash device, where the size of the QSPI = 2 ^ N. */
    memcpy(&buffer[0], &transfer.data, 3);
    device_size_bytes = 1U << buffer[2];
    FSP_PARAMETER_NOT_USED(device_size_bytes);
#endif

#ifdef SPIBSC_EXAMPLE_COMMAND_READ_SFDP

    /* Read the JEDEC SFDP header to locate the JEDEC flash parameters table. Reference JESD216 "Serial Flash
     * Discoverable Parameters (SFDP)". */
    spi_flash_direct_transfer_t read_sfdp =
    {
        .address        = 0,
        .data           = 0,
        .command        = SPIBSC_EXAMPLE_COMMAND_READ_SFDP,
        .dummy_cycles   = 8,
        .command_length = 1,
        .address_length = 3,
        .data_length    = 4
    };

    /* Send the standard 0x5A command (SFDP header is at address 0). */
    /* Read out 16-byte (call R_SPIBSC_DirectTransfer 4-times). */
    err = R_SPIBSC_DirectTransfer(&g_spi_flash0_ctrl, &read_sfdp, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    assert(FSP_SUCCESS == err);
    memcpy(&buffer[0], &read_sfdp.data, 4);
    read_sfdp.address = 4;
    err               = R_SPIBSC_DirectTransfer(&g_spi_flash0_ctrl, &read_sfdp, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    assert(FSP_SUCCESS == err);
    memcpy(&buffer[4], &read_sfdp.data, 4);
    read_sfdp.address = 8;
    err               = R_SPIBSC_DirectTransfer(&g_spi_flash0_ctrl, &read_sfdp, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    assert(FSP_SUCCESS == err);
    memcpy(&buffer[8], &read_sfdp.data, 4);
    read_sfdp.address = 12;
    err               = R_SPIBSC_DirectTransfer(&g_spi_flash0_ctrl, &read_sfdp, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    assert(FSP_SUCCESS == err);
    memcpy(&buffer[12], &read_sfdp.data, 4);

    /* Send the standard 0x5A command (address located at offset 0xC-0xE). */
    /* Read out 8-byte (call R_SPIBSC_DirectTransfer 2-times). */
    read_sfdp.address = MAKEUINT32(0, buffer[0xe], buffer[0xd], buffer[0xc]);
    err               = R_SPIBSC_DirectTransfer(&g_spi_flash0_ctrl, &read_sfdp, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    assert(FSP_SUCCESS == err);
    memcpy(&buffer[0], &read_sfdp.data, 4);
    read_sfdp.address += 4;
    err                = R_SPIBSC_DirectTransfer(&g_spi_flash0_ctrl, &read_sfdp, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    assert(FSP_SUCCESS == err);
    memcpy(&buffer[4], &read_sfdp.data, 4);

    /* Read the memory density (located in big endian order at offset 0x4-0x7). */
    uint32_t memory_density = MAKEUINT32(buffer[7], buffer[6], buffer[5], buffer[4]);
    if ((1U << 31) & memory_density)
    {
        /* For densities 4 gigabits and above, bit-31 is set to 1b.  The field 30:0 defines ‘N’ where the density is
         * computed as 2^N bits (N must be >= 32). This code subtracts 3 from N to divide by 8 to get the size in
         * bytes instead of bits. */
        device_size_bytes = 1U << ((memory_density & ~(1U << 31)) - 3U);
    }
    else
    {
        /* For densities 2 gigabits or less, bit-31 is set to 0b.  The field 30:0 defines the size in bits. This
         * code divides the memory density by 8 to get the size in bytes instead of bits. */
        device_size_bytes = (memory_density / 8) + 1;
    }
    FSP_PARAMETER_NOT_USED(device_size_bytes);
#endif
}

Data Structures
struct	spibsc_instance_ctrl_t

---

Data Structure Documentation

spibsc_instance_ctrl_t

struct spibsc_instance_ctrl_t

Instance control block. DO NOT INITIALIZE. Initialization occurs when spi_flash_api_t::open is called

Function Documentation

R_SPIBSC_Open()

fsp_err_t R_SPIBSC_Open	(	spi_flash_ctrl_t *	p_api_ctrl,
		spi_flash_cfg_t const *const	p_cfg
	)

Open the SPIBSC driver module.

Implements spi_flash_api_t::open.

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	The parameter p_api_ctrl or p_cfg is NULL.
FSP_ERR_UNSUPPORTED	One or more parameters in p_cfg are not supported by this implementation.
FSP_ERR_OUT_OF_MEMORY	Memory allocation error.
FSP_ERR_INVALID_SIZE	Page size is not specified.
FSP_ERR_INVALID_POINTER	Pointer points to invalid memory location.
FSP_ERR_INVALID_MODE	This function can't be called when XIP mode is enabled.
FSP_ERR_ALREADY_OPEN	Driver has already been opened with the same p_api_ctrl.

R_SPIBSC_Close()

fsp_err_t R_SPIBSC_Close

(

spi_flash_ctrl_t *

p_api_ctrl

)

Close the SPIBSC driver module.

Implements spi_flash_api_t::close.

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	p_api_ctrl is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_SPIBSC_DirectWrite()

fsp_err_t R_SPIBSC_DirectWrite	(	spi_flash_ctrl_t *	p_api_ctrl,
		uint8_t const *const	p_src,
		uint32_t const	bytes,
		bool const	read_after_write
	)

DEPRECATED: Writes raw data directly to the flash device.

Implements spi_flash_api_t::directWrite.

Note

After sending operations that change its contents, it may be inconsistent with cached contents.

Warning

Its behavior is not guaranteed if the caller and/or the callee are stored in the same device you are trying to change its contents.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_UNSUPPORTED	Read-after-write is not supported by this implementation.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_MODE	This function can't be called when XIP mode is enabled.

R_SPIBSC_DirectRead()

fsp_err_t R_SPIBSC_DirectRead	(	spi_flash_ctrl_t *	p_api_ctrl,
		uint8_t *const	p_dest,
		uint32_t const	bytes
	)

Reads raw data directly from the flash device. Unsupported by SPIBSC.

Implements spi_flash_api_t::directRead.

Return values

FSP_ERR_UNSUPPORTED

API not supported by SPIBSC.

R_SPIBSC_SpiProtocolSet()

fsp_err_t R_SPIBSC_SpiProtocolSet	(	spi_flash_ctrl_t *	p_api_ctrl,
		spi_flash_protocol_t	spi_protocol
	)

Sets the SPI protocol.

Implements spi_flash_api_t::spiProtocolSet.

Return values

FSP_ERR_UNSUPPORTED

API not supported by SPIBSC

R_SPIBSC_XipEnter()

fsp_err_t R_SPIBSC_XipEnter

(

spi_flash_ctrl_t *

p_api_ctrl

)

Enters XIP (execute in place) mode.

Implements spi_flash_api_t::xipEnter.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_INVALID_MODE	This function can't be called when already enabled or not 4-bit transfer.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_SPIBSC_XipExit()

fsp_err_t R_SPIBSC_XipExit

(

spi_flash_ctrl_t *

p_api_ctrl

)

Exits XIP (execute in place) mode.

Implements spi_flash_api_t::xipExit.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_INVALID_MODE	This function can't be called when XIP mode is enabled.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_SPIBSC_Write()

fsp_err_t R_SPIBSC_Write	(	spi_flash_ctrl_t *	p_api_ctrl,
		uint8_t const *const	p_src,
		uint8_t *const	p_dest,
		uint32_t	byte_count
	)

Program a page of data to the flash.

Implements spi_flash_api_t::write.

Note

After writing, it may be inconsistent with cached contents.

Warning

Its behavior is not guaranteed if the caller and/or the callee are stored in the same device you are writing.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	p_api_ctrl, p_dest or p_src is NULL, or byte_count crosses a page boundary.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_MODE	This function can't be called when XIP mode is enabled.

R_SPIBSC_Erase()

fsp_err_t R_SPIBSC_Erase	(	spi_flash_ctrl_t *	p_api_ctrl,
		uint8_t *const	p_device_address,
		uint32_t	byte_count
	)

Erase a block or sector of flash. The byte_count must exactly match one of the erase sizes defined in spi_flash_cfg_t. For chip erase, byte_count must be SPI_FLASH_ERASE_SIZE_CHIP_ERASE.

Implements spi_flash_api_t::erase.

Note

After erasing, it may be inconsistent with cached contents.

Warning

Its behavior is not guaranteed if the caller and/or the callee are stored in the same device you are erasing.

Return values

FSP_SUCCESS	The command to erase the flash was executed successfully.
FSP_ERR_ASSERTION	p_api_ctrl or p_device_address is NULL, or byte_count doesn't match an erase size defined in spi_flash_cfg_t, or device is in XIP mode.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_MODE	This function can't be called when XIP mode is enabled.

R_SPIBSC_StatusGet()

fsp_err_t R_SPIBSC_StatusGet	(	spi_flash_ctrl_t *	p_api_ctrl,
		spi_flash_status_t *const	p_status
	)

Gets the write or erase status of the flash.

Implements spi_flash_api_t::statusGet.

Return values

FSP_SUCCESS	The write status is in p_status.
FSP_ERR_ASSERTION	p_api_ctrl or p_status is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_MODE	This function can't be called when XIP mode is enabled.

R_SPIBSC_BankSet()

fsp_err_t R_SPIBSC_BankSet	(	spi_flash_ctrl_t *	p_api_ctrl,
		uint32_t	bank
	)

Selects the bank to access. A bank is a 256Mega-byte access window into the SPI Multi area. To access device address 0x10000000, select bank 1, then read from address 0x20000000(physical). To access device address 0x20001000, select bank 2, then read from address 0x20001000(physical).

This function is not required for memory devices less than or equal to 256Mega-byte.

Implements spi_flash_api_t::bankSet.

Note

After different bank selections, it becomes inconsistent with cache.

Warning

Its behavior is not guaranteed if the caller and/or the callee are stored in the same device you are trying to select banks. After changing the bank, the contents (code, data, or more) of the previously selected bank will become inaccessible.

Return values

FSP_SUCCESS	Bank successfully selected.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_INVALID_ARGUMENT	"bank" is invalid.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_SPIBSC_DirectTransfer()

fsp_err_t R_SPIBSC_DirectTransfer	(	spi_flash_ctrl_t *	p_api_ctrl,
		spi_flash_direct_transfer_t *const	p_transfer,
		spi_flash_direct_transfer_dir_t	direction
	)

Read/Write raw data directly with the flash device.

Implements spi_flash_api_t::directTransfer.

Note

After sending operations that change its contents, it may be inconsistent with cached contents.

Warning

Its behavior is not guaranteed if the caller and/or the callee are stored in the same device you are trying to change its contents.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_INVALID_MODE	This function can't be called when XIP mode is enabled.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_SPIBSC_AutoCalibrate()

fsp_err_t R_SPIBSC_AutoCalibrate

(

spi_flash_ctrl_t *

p_api_ctrl

)

Auto-calibrate the OctaRAM device using the preamble pattern. Unsupported by SPIBSC.

Implements spi_flash_api_t::autoCalibrate.

Return values

FSP_ERR_UNSUPPORTED

API not supported by SPIBSC