Bus State Controller (BSC) NOR Flash (r_bsc_nor)

Functions
fsp_err_t	R_BSC_NOR_Open (nor_flash_ctrl_t *p_ctrl, nor_flash_cfg_t const *const p_cfg)
fsp_err_t	R_BSC_NOR_Write (nor_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint8_t *const p_dest, uint32_t byte_count)
fsp_err_t	R_BSC_NOR_Erase (nor_flash_ctrl_t *p_ctrl, uint8_t *const p_device_address, uint32_t byte_count)
fsp_err_t	R_BSC_NOR_StatusGet (nor_flash_ctrl_t *p_ctrl, uint8_t *const p_device_address, nor_flash_status_t *const p_status)
fsp_err_t	R_BSC_NOR_Close (nor_flash_ctrl_t *p_ctrl)

Detailed Description

Driver for the BSC peripheral on RZ microprocessor. This module implements the NOR Flash Interface.

Overview

Features

The BSC NOR driver has the following key features:

• Supports the NOR Flash that is compatible with the JEDEC standard command system.
• Memory mapped read access to the NOR Flash
• Access NOR Flash using JEDEC standard command system
  • Programming the NOR Flash using Program command sequence or Write to Buffer Program / Write to Buffer Program confirm sequence
  • Erasing the NOR Flash using Sector Erase sequence or Chip Erase Sequence
  • Checking the NOR Flash status by continuous reading toggle bit
• Issue arbitrary commands (Address / Data set) to the NOR Flash
• Data bus size : 16bit
• Configurable idle cycle, wait state cycle

Note

This driver retrieves flash device block and sector information by CFI query and can handle up to 8 block regions.

Configuration

Build Time Configurations for r_bsc_nor

The following build time configurations are defined in fsp_cfg/r_bsc_nor_cfg.h:

Configuration	Options	Default	Description
Parameter Checking Enable	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.

Configurations for Storage > BSC_NOR (r_bsc_nor)

This module can be added to the Stacks tab via New Stack > Storage > BSC_NOR (r_bsc_nor).

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_nor_flash0	Module name.
General > Chip Select	Chip Select 0 Chip Select 2 Chip Select 3 Chip Select 5	Chip Select 0	Specify the NOR Flash chip select line to use.
General > Data Bus With	16-bit	16-bit	Select the number of NOR Flash data bus width.
Idle Cycles > Read-Read Cycles In The Same CS Space	0 CYCLE 1 CYCLE 2 CYCLES 4 CYCLES 6 CYCLES 8 CYCLES 10 CYCLES 12 CYCLES	4 CYCLES	Idle cycle insertion between Read-Read cycles in the same CS space.
Idle Cycles > Read-Read Cycles In The Different CS Spaces	0 CYCLE 1 CYCLE 2 CYCLES 4 CYCLES 6 CYCLES 8 CYCLES 10 CYCLES 12 CYCLES	4 CYCLES	Idle cycle insertion between Read-Read cycles in different CS space.
Idle Cycles > Read-Write Cycles In The Same CS Spaces	0 CYCLE 1 CYCLE 2 CYCLES 4 CYCLES 6 CYCLES 8 CYCLES 10 CYCLES 12 CYCLES	4 CYCLES	Idle cycle insertion between Read-Write cycles in the same CS space.
Idle Cycles > Read-Write Cycles In The Different CS Spaces	0 CYCLE 1 CYCLE 2 CYCLES 4 CYCLES 6 CYCLES 8 CYCLES 10 CYCLES 12 CYCLES	4 CYCLES	Idle cycle insertion between Read-Write cycles in different CS space.
Idle Cycles > Write-Read Cycles And Write-Write Cycles	0 CYCLE 1 CYCLE 2 CYCLES 4 CYCLES 6 CYCLES 8 CYCLES 10 CYCLES 12 CYCLES	4 CYCLES	Idle cycles between Write-Read cycles and Write-Write cycles.
Chip Select Timing > CS Negate (RD#,WE# to CSn#) Delay Timing (CS0,5 only)	0.5 CYCLES 1.5 CYCLES 2.5 CYCLES 3.5 CYCLES	0.5 CYCLES	Delay States from RD#, WEn# Negation to Address, CSn# Negation.
Chip Select Timing > CS Assert (CSn# to RD#,WE#) Delay Timing (CS0,5 only)	0.5 CYCLES 1.5 CYCLES 2.5 CYCLES 3.5 CYCLES	0.5 CYCLES	Number of Delay Cycles from Address, CSn# Assertion to RD#, WE# Assertion.
Number of Access Wait > Access Wait For Read	Refer to the RZT Configuration tool for available options.	14 WAITS	The number of waits that are necessary for read access.
Number of Access Wait > Access Wait For Write	The Same As Number Of Read Access Wait (Select when use CS0,2,3) 0 WAIT 1 WAIT 2 WAITS 3 WAITS 4 WAITS 5 WAITS 6 WAITS	The Same As Number Of Read Access Wait (Select when use CS0,2,3)	The number of waits that are necessary for write access.

Clock Configuration

The BSC clock is derived from External bus clock (BSC_CLK, CKIO). You can set the clock frequency using the Clocks tab of the FSP Configuration editor or by using the CGC Interface at run-time.

Usage Notes

BSC Memory Mapped Access

After R_BSC_NOR_Open() completes successfully, the connected BSC device contents are mapped to address 0x70000000(External address space) or 0x50000000(Mirror area External address space) and can be read like internal memory.

When not using the cache, access the memory via the mirror area.

Operation

The BSC NOR driver supports flash memory that is compatible with the JEDEC standard command system.

The command set issued by BSC NOR driver is as follows. For 16-bit data bus width connections, issue a 1-bit left-shifted address.

Programming Operation (Single word)

Issue Program command sequence when programming single word as follows:

Command Cycle	Address	Data
1st	0x555	0xAA
2nd	0x2AA	0x55
3rd	0x555	0xA0
4th	Program Address	Program Data

Programming Operation (Multiple words)

Issue Write to Buffer sequence and Program Buffer to Flash (confirm) sequence when programming multiple words as follows:

Command Cycle	Address	Data
1st	0x555	0xAA
2nd	0x2AA	0x55
3rd	Sector Address	0x25
4th	Sector Address	Program Count
5th	Program Address	Program Data
6th	Write Buffer Location	Program Data
Last	Sector Address	0x29

Sector Erase Operation

Issue Sector Erase sequence as follows:

Command Cycle	Address	Data
1st	0x555	0xAA
2nd	0x2AA	0x55
3rd	0x555	0x80
4th	0x555	0xAA
5th	0x2AA	0x55
6th	Sector Address	0x30

Chip Erase Operation

Issue Chip Erase sequence as follows:

Command Cycle	Address	Data
1st	0x555	0xAA
2nd	0x2AA	0x55
3rd	0x555	0x80
4th	0x555	0xAA
5th	0x2AA	0x55
6th	0x555	0x10

Status Check Operation

Status register 6th bit toggle monitors whether the program/erase operation has completed its operations or not.

Examples

Basic Example

This is a basic example of minimal use of the BSC_NOR in an application.

#define BSC_NOR_EXAMPLE_DATA_LENGTH    (1024)

uint8_t g_dest[BSC_NOR_EXAMPLE_DATA_LENGTH];

/* Place data in the .cs0_space section to flash it during programming. */
const uint8_t g_src[BSC_NOR_EXAMPLE_DATA_LENGTH] BSP_PLACE_IN_SECTION(".cs0_space") = "ABCDEFGHIJKLMNOPQRSTUVWXYZ";

/* Place code in the .code_in_cs0 section to flash it during programming. */
void r_bsc_nor_example_function(void) BSP_PLACE_IN_SECTION(".code_in_cs0") __attribute__((noinline));

void r_bsc_nor_example_function (void)
{
    /* Add code here. */
}

void r_bsc_nor_basic_example (void)
{

    /* Open the BSC_NOR instance. */
    fsp_err_t err = R_BSC_NOR_Open(&g_nor_flash_ctrl, &g_nor_flash_cfg);
    handle_error(err);


    /* After R_BSC_NOR_Open() and any required device specific initialization, data can be read directly from the BSC_NOR flash. */
    memcpy(&g_dest[0], &g_src[0], BSC_NOR_EXAMPLE_DATA_LENGTH);

    /* After R_BSC_NOR_Open() and any required device specific initialization, functions in the BSC_NOR flash can be called. */
    r_bsc_nor_example_function();
}

Querying Device Size Example

This is an example of using a CFI query to get the device size.

#define BSC_NOR_EXAMPLE_CFI_QUERY_COMMAND_ADDRESS    (0x55U)
#define BSC_NOR_EXAMPLE_CFI_QUERY_COMMAND_DATA       (0x98U)
#define BSC_NOR_EXAMPLE_DEVICE_SIZE_QUERY_ADDRESS    (0x27U)

void r_bsc_nor_size_example (void)
{
    uint16_t query_size;
    uint32_t device_size_bytes;

    /* CFI Enter Sequence. */
    *((volatile uint16_t *) BSC_NOR_DEVICE_START_ADDRESS +
      BSC_NOR_EXAMPLE_CFI_QUERY_COMMAND_ADDRESS) = BSC_NOR_EXAMPLE_CFI_QUERY_COMMAND_DATA;
    __asm volatile ("dsb");

    /* Query device size. */
    query_size = *((volatile uint16_t *) BSC_NOR_DEVICE_START_ADDRESS + BSC_NOR_EXAMPLE_DEVICE_SIZE_QUERY_ADDRESS);
    __asm volatile ("dsb");

    device_size_bytes = 1U << query_size;
    FSP_PARAMETER_NOT_USED(device_size_bytes);
}

Data Structures
struct	bsc_nor_block_info_t
struct	bsc_nor_extended_cfg_t
struct	bsc_nor_instance_ctrl_t

Enumerations
enum	bsc_nor_idle_cycle_t
enum	bsc_nor_access_wait_cycle_t
enum	bsc_nor_cs_wait_cycle_t

---

Data Structure Documentation

bsc_nor_block_info_t

struct bsc_nor_block_info_t

Store CFI query result of Flash memory sector block information.

bsc_nor_extended_cfg_t

struct bsc_nor_extended_cfg_t

Extended configuration.

Data Fields
bsc_nor_idle_cycle_t	r_r_same_space_idle_cycle	Idle cycle between Read-Read cycles in the same CS space
bsc_nor_idle_cycle_t	r_r_different_space_idle_cycle	Idle cycle between Read-Read cycles in the different CS space
bsc_nor_idle_cycle_t	r_w_same_space_idle_cycle	Idle cycle between Read-Write cycles in the same CS space
bsc_nor_idle_cycle_t	r_w_different_space_idle_cycle	Idle cycle between Read-Write cycles in the different CS space
bsc_nor_idle_cycle_t	w_r_w_w_idle_cycle	Idle cycle between Write-Read cycles and Write-Write cycles
bsc_nor_access_wait_cycle_t	read_access_wait_cycle	Number of read access cycle waits.
bsc_nor_access_wait_cycle_t	write_access_wait_cycle	Number of write access cycle waits.
bsc_nor_cs_wait_cycle_t	cs_pullup_lag	Duration to de-assert CS line after RD#,WE# de-assert.
bsc_nor_cs_wait_cycle_t	cs_pulldown_lead	Duration to assert CS line before RD#,WE# assert.

bsc_nor_instance_ctrl_t

struct bsc_nor_instance_ctrl_t

Instance control block. DO NOT INITIALIZE. Initialization occurs when nor_flash_api_t::open is called

Enumeration Type Documentation

bsc_nor_idle_cycle_t

enum bsc_nor_idle_cycle_t

Number of insertion idle cycle between access cycles

Enumerator
BSC_NOR_IDLE_CYCLE_0	No idle cycle insertion.
BSC_NOR_IDLE_CYCLE_1	1 idle cycle insertion
BSC_NOR_IDLE_CYCLE_2	2 idle cycle insertion
BSC_NOR_IDLE_CYCLE_4	4 idle cycle insertion
BSC_NOR_IDLE_CYCLE_6	6 idle cycle insertion
BSC_NOR_IDLE_CYCLE_8	8 idle cycle insertion
BSC_NOR_IDLE_CYCLE_10	10 idle cycle insertion
BSC_NOR_IDLE_CYCLE_12	12 idle cycle insertion

bsc_nor_access_wait_cycle_t

enum bsc_nor_access_wait_cycle_t

Number of insertion access wait cycle

Enumerator
BSC_NOR_ACCESS_WAIT_CYCLE_0	No wait insertion.
BSC_NOR_ACCESS_WAIT_CYCLE_1	1 access wait cycle insertion
BSC_NOR_ACCESS_WAIT_CYCLE_2	2 access wait cycle insertion
BSC_NOR_ACCESS_WAIT_CYCLE_3	3 access wait cycle insertion
BSC_NOR_ACCESS_WAIT_CYCLE_4	4 access wait cycle insertion
BSC_NOR_ACCESS_WAIT_CYCLE_5	5 access wait cycle insertion
BSC_NOR_ACCESS_WAIT_CYCLE_6	6 access wait cycle insertion
BSC_NOR_ACCESS_WAIT_CYCLE_8	8 access wait cycle insertion
BSC_NOR_ACCESS_WAIT_CYCLE_10	10 access wait cycle insertion
BSC_NOR_ACCESS_WAIT_CYCLE_12	12 access wait cycle insertion
BSC_NOR_ACCESS_WAIT_CYCLE_14	14 access wait cycle insertion
BSC_NOR_ACCESS_WAIT_CYCLE_18	18 access wait cycle insertion
BSC_NOR_ACCESS_WAIT_CYCLE_24	24 access wait cycle insertion
BSC_NOR_ACCESS_WAIT_CYCLE_SAME_AS_READ_ACCESS	Insert the same weight cycle when read access (Used only for Write access wait settings)

bsc_nor_cs_wait_cycle_t

enum bsc_nor_cs_wait_cycle_t

Number of insertion CS wait cycle

Enumerator
BSC_NOR_CS_WAIT_CYCLE_0_5	CS wait 0.5 cycle insertion.
BSC_NOR_CS_WAIT_CYCLE_1_5	CS wait 1.5 cycle insertion.
BSC_NOR_CS_WAIT_CYCLE_2_5	CS wait 2.5 cycle insertion.
BSC_NOR_CS_WAIT_CYCLE_3_5	CS wait 3.5 cycle insertion.

Function Documentation

R_BSC_NOR_Open()

fsp_err_t R_BSC_NOR_Open	(	nor_flash_ctrl_t *	p_ctrl,
		nor_flash_cfg_t const *const	p_cfg
	)

Open the BSC_NOR driver module. After the driver is open, the BSC can be accessed like internal flash memory starting at address 0x70000000 or 0x50000000.

Implements nor_flash_api_t::open.

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	The parameter p_instance_ctrl or p_cfg is NULL. Connected Flash memory device does not support CFI query, or insufficient memory area for storing CFI query.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	Invalid Channel.
FSP_ERR_ALREADY_OPEN	Driver has already been opened with the same p_instance_ctrl.

R_BSC_NOR_Write()

fsp_err_t R_BSC_NOR_Write	(	nor_flash_ctrl_t *	p_ctrl,
		uint8_t const *const	p_src,
		uint8_t *const	p_dest,
		uint32_t	byte_count
	)

Program data to the flash.

Implements nor_flash_api_t::write.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	p_instance_ctrl, p_dest or p_src is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_DEVICE_BUSY	Another Write/Erase transaction is in progress.
FSP_ERR_INVALID_ARGUMENT	p_dest is invalid for connected device.

Note

The size that can be written to the buffer at one time depends on the device. Please refer to the data sheet of the connected device for details.

R_BSC_NOR_Erase()

fsp_err_t R_BSC_NOR_Erase	(	nor_flash_ctrl_t *	p_ctrl,
		uint8_t *const	p_device_address,
		uint32_t	byte_count
	)

Erase a sector or a chip of flash.

Implements nor_flash_api_t::erase.

Return values

FSP_SUCCESS	The command to erase the flash was executed successfully.
FSP_ERR_ASSERTION	p_instance_ctrl or p_device_address is NULL, or byte_count doesn't match the device defined erase size resulting from the CFI query.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_DEVICE_BUSY	The device is busy.

R_BSC_NOR_StatusGet()

fsp_err_t R_BSC_NOR_StatusGet	(	nor_flash_ctrl_t *	p_ctrl,
		uint8_t *const	p_device_address,
		nor_flash_status_t *const	p_status
	)

Gets the write or erase status of the flash.

Implements nor_flash_api_t::statusGet.

Return values

FSP_SUCCESS	The write status is in p_status.
FSP_ERR_ASSERTION	p_instance_ctrl, p_device_address or p_status is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_BSC_NOR_Close()

fsp_err_t R_BSC_NOR_Close

(

nor_flash_ctrl_t *

p_ctrl

)

Close the BSC_NOR driver module.

Implements nor_flash_api_t::close.

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	p_instance_ctrl is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.