Bus State Controller (BSC) SDRAM (r_bsc_sdram)

Functions
fsp_err_t	R_BSC_SDRAM_Open (sdram_ctrl_t *p_ctrl, sdram_cfg_t const *const p_cfg)
fsp_err_t	R_BSC_SDRAM_SelfRefreshEnter (sdram_ctrl_t *p_ctrl)
fsp_err_t	R_BSC_SDRAM_SelfRefreshExit (sdram_ctrl_t *p_ctrl)
fsp_err_t	R_BSC_SDRAM_PowerDownEnter (sdram_ctrl_t *p_ctrl)
fsp_err_t	R_BSC_SDRAM_PowerDownExit (sdram_ctrl_t *p_ctrl)
fsp_err_t	R_BSC_SDRAM_Close (sdram_ctrl_t *p_ctrl)

Detailed Description

Driver for the BSC peripheral on RZ microprocessor. This module implements the SDRAM Interface.

Overview

Features

The BSC SDRAM driver has the following key features:

• Memory mapped write/read access to the SDRAM
• Supports 16bit Data bus size
• Supports CS3 space
• Can be configured with SDRAM device
• Can be configured with SDRAM timing
• Auto-Refresh operation
• Entering and exiting Self-Refresh mode
• Entering and exiting Power-Down mode
• Auto-precharge mode (using READA and WRITA commands) operation or Bank active mode (using READ and WRIT commands) operation

Configuration

Build Time Configurations for r_bsc_sdram

The following build time configurations are defined in fsp_cfg/r_bsc_sdram_cfg.h:

Configuration	Options	Default	Description
Parameter Checking Enable	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Multiplex Interrupt	Enabled Disabled	Disabled	Enable multiplex interrupt for a single driver.

Configurations for Storage > SDRAM (r_bsc_sdram)

This module can be added to the Stacks tab via New Stack > Storage > SDRAM (r_bsc_sdram).

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_sdram0	Module name.
General > Chip Select	Chip Select 3	Chip Select 3	Specify the SDRAM chip select line to use.
General > Data Bus Width	16-bit	16-bit	Select the number of SDRAM data bus width.
Idle Cycles > Read-Read Cycles In The Same CS Space	0 CYCLE 1 CYCLE 2 CYCLES 4 CYCLES 6 CYCLES 8 CYCLES 10 CYCLES 12 CYCLES	4 CYCLES	Idle cycle insertion between Read-Read cycles in the same CS space.
Idle Cycles > Read-Read Cycles In The Different CS Spaces	0 CYCLE 1 CYCLE 2 CYCLES 4 CYCLES 6 CYCLES 8 CYCLES 10 CYCLES 12 CYCLES	4 CYCLES	Idle cycle insertion between Read-Read cycles in different CS space.
Idle Cycles > Read-Write Cycles In The Same CS Spaces	0 CYCLE 1 CYCLE 2 CYCLES 4 CYCLES 6 CYCLES 8 CYCLES 10 CYCLES 12 CYCLES	4 CYCLES	Idle cycle insertion between Read-Write cycles in the same CS space.
Idle Cycles > Read-Write Cycles In The Different CS Spaces	0 CYCLE 1 CYCLE 2 CYCLES 4 CYCLES 6 CYCLES 8 CYCLES 10 CYCLES 12 CYCLES	4 CYCLES	Idle cycle insertion between Read-Write cycles in different CS space.
Idle Cycles > Write-Read Cycles And Write-Write Cycles	0 CYCLE 1 CYCLE 2 CYCLES 4 CYCLES 6 CYCLES 8 CYCLES 10 CYCLES 12 CYCLES	4 CYCLES	Idle cycles between Write-Read cycles and Write-Write cycles.
Address Bit Width > Row Address Bit Width	11-bit 12-bit 13-bit	11-bit	Select the number of SDRAM row address bus width.
Address Bit Width > Column Address Bit Width	8-bit 9-bit 10-bit	8-bit	Select the number of SDRAM column address bus width.
Wait Insertion for SDRAM Timing > RAS# Precharge Cycle (PRECHARGE to ACTIVE)	0 CYCLE 1 CYCLE 2 CYCLES 3 CYCLES	0 CYCLE	Number of Auto-Precharge Completion Wait States (tRP)
Wait Insertion for SDRAM Timing > RAS# To CAS# Delay Cycle (ACTIVE to READ/WRITE)	0 CYCLE 1 CYCLE 2 CYCLES 3 CYCLES	0 CYCLE	Number of Waits between ACTV Command and READ(A)/WRIT(A) Command (tRCD)
Wait Insertion for SDRAM Timing > CAS Latency	1 CYCLE 2 CYCLES 3 CYCLES 4 CYCLES	1 CYCLE	CAS Latency (tCL)
Wait Insertion for SDRAM Timing > Last data in to Active Latency (WRITA to ACTIVE) / Write Recovery Cycle (WRIT to PRECHARGE)	0 CYCLE 1 CYCLE 2 CYCLES 3 CYCLES	0 CYCLE	The state number from the issuance of the WRITA command until the issuance of the ACTV command (tDAL) / The state number from the issuance of the WRIT command until the issuance of the PRE command (tWR)
Wait Insertion for SDRAM Timing > Row Cycle (ACTIVE to ACTIVE)	2 CYCLES 3 CYCLES 5 CYCLES 8 CYCLES	2 CYCLES	Number of Idle States from REF Command/Self-Refresh Release to ACTV/REF/MRS Command (tRC)
Auto Refresh > Refresh Cycle Period (tREF)	Value must be non-negative	64	Refresh Cycle Time (tREF)
Auto Refresh > Refresh Cycle Period Unit	Milliseconds	Milliseconds	Unit of the period specified above
Auto Refresh > The Number of Continuous Refresh Cycles	1 2 4 6 8	1	A refresh request is generated and an auto-refresh is performed for the number of times specified by this configuration.
Extra > MRS Burst Setting	Burst Read / Burst Write Burst Read / Single Write	Burst Read / Burst Write	Write Burst Mode setting of SDRAM mode register
Extra > Command Mode	Auto Precharge Mode (using READA and WRITA commands) Bank Active Mode (using READ and WRIT commands)	Auto Precharge Mode (using READA and WRITA commands)	Select whether to access in auto-precharge mode (using READA and WRITA commands) or in bank active mode (using READ and WRIT commands).
Interrupts > Callback	Name must be a valid C symbol	NULL	A user callback function can be provided. If this callback function is provided, it will be called from the interrupt service routine (ISR).
Interrupts > Refresh Timer Compare Match Interrupt Priority	MCU Specific Options		Select the refresh timer compare match interrupt priority.

Auto-Refresh operation interval configuration

Auto-Refresh operation interval is calculated from "Refresh Cycle Period (tREF)" , "Row Address Bit Width" and "The Number of Continuous Refresh Cycles" user-setting. In the example below, Auto-Refresh operation interval setting target to the BSC peripheral is 7.8125 us. This interval is counted by CKIO clock.

Refresh Cycle Period (tREF) = 64 ms

Row Address Bit Width = 13bit = 8192 row

The Number of Continuous Refresh Cycles = 1

Auto-Refresh operation interval = (64 ms / 8192) * 1 = 7.8125 us

Clock Configuration

The BSC clock is derived from External bus clock (BSC_CLK, CKIO). You can set the clock frequency using the Clocks tab of the FSP Configuration editor or by using the CGC Interface at run-time.

Usage Notes

BSC_SDRAM Memory Mapped Access

After R_BSC_SDRAM_Open() completes successfully, the connected SDRAM device contents are mapped to address 0x78000000(External address space CS3) or 0x58000000(Mirror space of External address space CS3) and can be read like internal memory.

When not using the cache, access the memory via the mirror space.

The address map for the external address space for BSC_SDRAM is as follows:

Address	Space
0x58000000 to 0x5BFFFFFF	CS3 mirror space
0x78000000 to 0x7BFFFFFF	CS3 space

Self-Refresh Operation

After R_BSC_SDRAM_Open() completes successfully, BSC_SDRAM starts Auto-Refresh operation which issues refresh command every configured cycle.

If not using the auto-refresh operation after R_BSC_SDRAM_Open(), self-refresh operation can be started by calling R_BSC_SDRAM_SelfRefreshEnter() after R_BSC_SDRAM_Open().

Examples

Basic Example

This is a basic example of minimal use of the BSC_SDRAM module in an application.

#define CS3_BASE                         (0x58000000)
#define BSC_SDRAM_EXAMPLE_DATA_LENGTH    (256)
uint16_t write_data[BSC_SDRAM_EXAMPLE_DATA_LENGTH];
uint16_t read_data[BSC_SDRAM_EXAMPLE_DATA_LENGTH];

void r_bsc_sdram_basic_example (void)
{
    /* Write some data to the write buffer */
    for (uint16_t i = 0; i < BSC_SDRAM_EXAMPLE_DATA_LENGTH; i++)
    {
        write_data[i] = i;
    }


    /* Open the BSC_SDRAM instance */
    fsp_err_t err = R_BSC_SDRAM_Open(&g_sdram_ctrl, &g_sdram_cfg);
    handle_error(err);


    /* After R_BSC_SDRAM_Open() and any required device specific initialization, data can be write directly
     * to the SDRAM connected to BSC. */
    for (uint16_t i = 0; i < BSC_SDRAM_EXAMPLE_DATA_LENGTH; i++)
    {
        *((volatile uint16_t *) CS3_BASE + 0x0000 + i) = write_data[i];
    }

    /* After R_BSC_SDRAM_Open() and any required device specific initialization, data can be read directly
     * from the SDRAM connected to BSC. */
    for (uint16_t i = 0; i < BSC_SDRAM_EXAMPLE_DATA_LENGTH; i++)
    {
        read_data[i] = *((volatile uint16_t *) CS3_BASE + 0x0000 + i);
    }

    /* Verify the read_data. */
    for (uint16_t i = 0; i < BSC_SDRAM_EXAMPLE_DATA_LENGTH; i++)
    {
        if (read_data[i] != write_data[i])
        {
            /* Verify error. */
            __BKPT(0);
        }
    }

    while (1)
    {
        ;
    }
}

Data Structures
struct	bsc_sdram_callback_args_t
struct	bsc_sdram_extended_cfg_t
struct	bsc_sdram_instance_ctrl_t

Enumerations
enum	bsc_sdram_chip_select_t
enum	bsc_sdram_idle_cycle_t
enum	bsc_sdram_command_t

---

Data Structure Documentation

bsc_sdram_callback_args_t

struct bsc_sdram_callback_args_t

Callback function parameter data.

Data Fields
void const *	p_context	Placeholder for user data.

bsc_sdram_extended_cfg_t

struct bsc_sdram_extended_cfg_t

Extended configuration.

Data Fields
bsc_sdram_chip_select_t	chip_select
	Select which device to use.
bsc_sdram_idle_cycle_t	r_r_same_space_idle_cycle
bsc_sdram_idle_cycle_t	r_r_different_space_idle_cycle
bsc_sdram_idle_cycle_t	r_w_same_space_idle_cycle
bsc_sdram_idle_cycle_t	r_w_different_space_idle_cycle
bsc_sdram_idle_cycle_t	w_r_w_w_idle_cycle
bsc_sdram_command_t	command_mode
uint8_t	cmi_ipl
	SDRAM refresh compare match interrupt.
IRQn_Type	cmi_irq
	SDRAM refresh compare match interrupt priority.
void(*	p_callback )(bsc_sdram_callback_args_t *p_args)
void const *	p_context

Field Documentation

r_r_same_space_idle_cycle

bsc_sdram_idle_cycle_t bsc_sdram_extended_cfg_t::r_r_same_space_idle_cycle

Idle cycle between Read-Read cycles in the same CS space

r_r_different_space_idle_cycle

bsc_sdram_idle_cycle_t bsc_sdram_extended_cfg_t::r_r_different_space_idle_cycle

Idle cycle between Read-Read cycles in the different CS space

r_w_same_space_idle_cycle

bsc_sdram_idle_cycle_t bsc_sdram_extended_cfg_t::r_w_same_space_idle_cycle

Idle cycle between Read-Write cycles in the same CS space

r_w_different_space_idle_cycle

bsc_sdram_idle_cycle_t bsc_sdram_extended_cfg_t::r_w_different_space_idle_cycle

Idle cycle between Read-Write cycles in the different CS space

w_r_w_w_idle_cycle

bsc_sdram_idle_cycle_t bsc_sdram_extended_cfg_t::w_r_w_w_idle_cycle

Idle cycle between Write-Read cycles and Write-Write cycles

command_mode

bsc_sdram_command_t bsc_sdram_extended_cfg_t::command_mode

Auto-precharge mode (using READA/WRITA commands) or Bank active mode (using READ/WRIT commands)

p_callback

void(* bsc_sdram_extended_cfg_t::p_callback) (bsc_sdram_callback_args_t *p_args)

Callback for SDRAM refresh compare match.

p_context

void const* bsc_sdram_extended_cfg_t::p_context

Placeholder for user data. Passed to the user callback in bsc_sdram_callback_args_t.

bsc_sdram_instance_ctrl_t

struct bsc_sdram_instance_ctrl_t

Instance control block. DO NOT INITIALIZE. Initialization occurs when sdram_api_t::open is called

Enumeration Type Documentation

bsc_sdram_chip_select_t

enum bsc_sdram_chip_select_t

SDRAM chip select.

Enumerator
BSC_SDRAM_CHIP_SELECT_3	Device connected to Chip-Select 3.

bsc_sdram_idle_cycle_t

enum bsc_sdram_idle_cycle_t

Number of insertion idle cycle between access cycles

Enumerator
BSC_SDRAM_IDLE_CYCLE_0	No idle cycle insertion.
BSC_SDRAM_IDLE_CYCLE_1	1 idle cycle insertion
BSC_SDRAM_IDLE_CYCLE_2	2 idle cycle insertion
BSC_SDRAM_IDLE_CYCLE_4	4 idle cycle insertion
BSC_SDRAM_IDLE_CYCLE_6	6 idle cycle insertion
BSC_SDRAM_IDLE_CYCLE_8	8 idle cycle insertion
BSC_SDRAM_IDLE_CYCLE_10	10 idle cycle insertion
BSC_SDRAM_IDLE_CYCLE_12	12 idle cycle insertion

bsc_sdram_command_t

enum bsc_sdram_command_t

Specify SDRAM command

Function Documentation

R_BSC_SDRAM_Open()

fsp_err_t R_BSC_SDRAM_Open	(	sdram_ctrl_t *	p_ctrl,
		sdram_cfg_t const *const	p_cfg
	)

Open the BSC_SDRAM driver module. Configure the BSC and operate the SDRAM initialization. (PALL command is firstly issued. REF command is issued 8 times. MRS command is finally issued.)

User can access to the SDRAM like internal memory starting at address 0x78000000 or 0x58000000.

Note

After the driver is open, Auto-Refresh operation is started.

Implements sdram_api_t::open.

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	The parameter p_instance_ctrl or p_cfg is NULL.
FSP_ERR_INVALID_CHANNEL	Invalid Channel.
FSP_ERR_ALREADY_OPEN	Driver has already been opened with the same p_instance_ctrl.
FSP_ERR_INVALID_ARGUMENT	SDRAM parameter is not available.

R_BSC_SDRAM_SelfRefreshEnter()

fsp_err_t R_BSC_SDRAM_SelfRefreshEnter

(

sdram_ctrl_t *

p_ctrl

)

Enters Self-Refresh mode.

Implements sdram_api_t::selfRefreshEnter.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_INVALID_MODE	This function can't be called when SDRAM is in Power-down mode.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_BSC_SDRAM_SelfRefreshExit()

fsp_err_t R_BSC_SDRAM_SelfRefreshExit

(

sdram_ctrl_t *

p_ctrl

)

Exits Self-Refresh mode. Auto-Refresh operation is re-started to the SDRAM.

Implements sdram_api_t::selfRefreshExit.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_BSC_SDRAM_PowerDownEnter()

fsp_err_t R_BSC_SDRAM_PowerDownEnter

(

sdram_ctrl_t *

p_ctrl

)

Enters Power-Down mode.

Implements sdram_api_t::powerDownEnter.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_INVALID_MODE	This function can't be called when SDRAM is in Self-Refresh mode.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_BSC_SDRAM_PowerDownExit()

fsp_err_t R_BSC_SDRAM_PowerDownExit

(

sdram_ctrl_t *

p_ctrl

)

Exits Power-Down mode.

Implements sdram_api_t::powerDownExit.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_BSC_SDRAM_Close()

fsp_err_t R_BSC_SDRAM_Close

(

sdram_ctrl_t *

p_ctrl

)

Close the BSC_SDRAM driver module.

Implements sdram_api_t::close.

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	p_instance_ctrl is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.