Direct Memory Access Controller (r_dmac)

Functions
fsp_err_t	R_DMAC_Open (transfer_ctrl_t *const p_ctrl, transfer_cfg_t const *const p_cfg)
fsp_err_t	R_DMAC_Reconfigure (transfer_ctrl_t *const p_ctrl, transfer_info_t *p_info)
fsp_err_t	R_DMAC_Reset (transfer_ctrl_t *const p_ctrl, void const *volatile p_src, void *volatile p_dest, uint16_t const num_transfers)
fsp_err_t	R_DMAC_SoftwareStart (transfer_ctrl_t *const p_ctrl, transfer_start_mode_t mode)
fsp_err_t	R_DMAC_SoftwareStop (transfer_ctrl_t *const p_ctrl)
fsp_err_t	R_DMAC_Enable (transfer_ctrl_t *const p_ctrl)
fsp_err_t	R_DMAC_Disable (transfer_ctrl_t *const p_ctrl)
fsp_err_t	R_DMAC_InfoGet (transfer_ctrl_t *const p_ctrl, transfer_properties_t *const p_info)
fsp_err_t	R_DMAC_Close (transfer_ctrl_t *const p_ctrl)
fsp_err_t	R_DMAC_Reload (transfer_ctrl_t *const p_ctrl, void const *p_src, void *p_dest, uint32_t const num_transfers)
fsp_err_t	R_DMAC_CallbackSet (transfer_ctrl_t *const p_ctrl, void(*p_callback)(transfer_callback_args_t *), void const *const p_context, transfer_callback_args_t *const p_callback_memory)
fsp_err_t	R_DMAC_LinkDescriptorSet (transfer_ctrl_t *const p_ctrl, dmac_link_cfg_t *p_descriptor)

Detailed Description

Driver for the DMAC peripheral on RZ microprocessor. This module implements the Transfer Interface.

Overview

The Direct Memory Access Controller (DMAC) transfers data from one memory location to another without using the CPU.

Features

• Supports multiple transfer modes
  • Normal transfer
  • Block transfer
• Support Register mode and Link mode
• Supports Next0 Register set and Next1 Register set
• Address increment, fixed
• Triggered by various events
  • Some exceptions apply, see the Event table in the Event Numbers section of the Interrupt Controller Unit chapter of the hardware manual
• Supports 1, 2, 4, 8, 16, 32, 64(DMAC0 only) byte data units
• Configurable DMA transfer activation request source, detection method of DMA request signal and DACK output mode
• Configurable DMA transfer interval
• Configurable DMAC channel priority

Configuration

Build Time Configurations for r_dmac

The following build time configurations are defined in fsp_cfg/r_dmac_cfg.h:

Configuration	Options	Default	Description
Channel Priority Control > Unit 0 > Arbitration method (Channel 0-7)	Fixed Round Robin	Fixed	Select Unit0 Channel 0 - 7 channel priority
Channel Priority Control > Unit 0 > Arbitration method (Channel 8-15)	Fixed Round Robin	Fixed	Select Unit0 Channel 8 - 15 channel priority
Channel Priority Control > Unit 1 > Arbitration method (Channel 0-7)	Fixed Round Robin	Fixed	Select Unit1 Channel 0 - 7 channel priority
Channel Priority Control > Unit 1 > Arbitration method (Channel 8-15)	Fixed Round Robin	Fixed	Select Unit1 Channel 8 - 15 channel priority
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Multiplex Interrupt	Enabled Disabled	Disabled	Enable multiplex interrupt for a single driver.

Note

When DMAC and other modules (e.g. SCI_UART) form a stack, interlocking modules do not generate interrupt which is used as DMAC trigger and instead, a DMAC interrupt occurs when the transfer completes. In this case, it is recommended to match these Multiplex Interrupt settings. Otherwise, multiplex interrupts can be allowed at unintended timings for the user.

Configurations for Transfer > Transfer (r_dmac)

This module can be added to the Stacks tab via New Stack > Transfer > Transfer (r_dmac).

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_transfer0	Module name.
General > Unit	Value must be a non-negative integer	0	Specify the hardware unit.
General > Channel	Must be a valid integer between 0 and 15.	0	Specify the hardware channel.
General > DMA Mode	Register mode Link mode	Register mode	Select the DMA mode.
General > Activation Source	MCU Specific Options		Select the DMAC transfer start event. Don't select same event between defferent CPUs.
Register Mode > Mode	Normal Block	Normal	Select the transfer mode.
Register Mode > Transfer Source Size	1 Byte 2 Bytes 4 Bytes 8 Bytes 16 Bytes 32 Bytes 64 Bytes	2 Bytes	Select the transfer source size.
Register Mode > Transfer Destination Size	1 Byte 2 Bytes 4 Bytes 8 Bytes 16 Bytes 32 Bytes 64 Bytes	2 Bytes	Select the transfer destination size.
Register Mode > Destination Address Mode	Fixed Incremented	Fixed	Select the address mode for the destination.
Register Mode > Source Address Mode	Fixed Incremented	Fixed	Select the address mode for the source.
Register Mode > Destination Pointer	Manual Entry	NULL	Specify the transfer destination pointer.
Register Mode > Source Pointer	Manual Entry	NULL	Specify the transfer source pointer.
Register Mode > Number of Transfers	Value must be a non-negative integer	1	Specify the bytes of transfers.
Register Mode > DMA Activation Request Source Select	Requested by a transfer source module Requested by a transfer destination module	Requested by a transfer source module	Select DMA activation request source.
Register Mode > Low Detection Enable	Enable Disable	Enable	Select low detection enable.
Register Mode > High Detection Enable	Enable Disable	Disable	Select high detection enable.
Register Mode > Level Detection Enable	Edge Level	Edge	Select level detection enable.
Register Mode > DACK Output mode	Level mode Bus cycle mode Mask mode	Level mode	Select DACK output mode.
Register Mode > Next 1 Register Set enable	Disable Enable Enable(Continuous)	Disable	When Next0 Register Set Transfer completes, Next1 Register Set Transfer occurs
Register Mode > Next 1 Register Set Destination Pointer	Manual Entry	NULL	Specify the transfer destination pointer.
Register Mode > Next 1 Register Set Source Pointer	Manual Entry	NULL	Specify the transfer source pointer.
Register Mode > Next 1 Register Set Number of Transfers	Value must be a non-negative integer	1	Specify the bytes of transfers.
Register Mode > Transfer Interval	Value must be a non-negative integer	0	Transfer interval
Link Mode > Descriptor	Name must be a valid C symbol	NULL	DMAC Link mode descriptor symbol name.
Interrupts > Callback	Name must be a valid C symbol	NULL	A user callback that is called at the end of the transfer.
Interrupts > Context	Manual Entry	NULL	Pointer to the context structure passed through the callback argument.
Interrupts > Transfer End Interrupt Detect Type	MCU Specific Options		Select transfer end interrupt detect type.
Interrupts > Transfer End Interrupt Priority	MCU Specific Options		Select the transfer end interrupt priority.

Warning

1. "DMA Activation Request Source Select", "Low Detection Enable", "High Detection Enable", and "DACK output" must be set according to the DMAC transfer source. For details, see 'DMA Transfer Request Detection Operation Setting Table' of RZ microprocessor manual.

2. Do not set the same activation source for multiple channels of the same unit. If the same source is set, the operation cannot be guaranteed.

Clock Configuration

The DMAC peripheral module uses ICLK as the clock source. The ICLK frequency is set by using the Clocks tab of the FSP Configuration editor prior to a build, or by using the CGC module at run-time.

Pin Configuration

The following pins are available by this module.

• DREQ: DMA transfer request
• DACK: Output of DMAC transfer request acceptance
• TEND: Output of transfer completion

Usage Notes

Transfer Modes

The DMAC Module supports two modes of operation.

• Normal Mode - In normal mode, a single data unit is transfered every time the configured event is received by the DMAC channel. A data unit can be 1-byte, 2-bytes, 4-bytes, 8-byte, 16-byte or 32-byte (64-byte can be set only for DMAC0). The source and destination addresses can be fixed or increment. A 32-bit counter decrements after each transfer. When the counter reaches 0, transfers will no longer be triggered by the event and the CPU can be interrupted to signal that all transfers have finished.
• Block Mode - In block mode, the amount of data units transfered by each interrupt. For one DMA request, performs transfers until a DMA transfer completes. When the counter reaches 0, transfers will no longer be triggered by the event and the CPU can be interrupted to signal that all transfers have finished.

Link Mode

In Link mode, a DMA transfer is performed by reading a descriptor placed in the RAM area as the transfer information setting value. The descriptor is configured by dmac_link_cfg_t struct. For more information see 'Link Mode' section in the RZ microprocessor manual.

Note

1. The descriptor must be 4-byte align and cannot be placed in TCM area. The DMAC HAL driver provides a memory section ".dmac_link_mode" on SystemRAM area for the descriptor allocation.

2. To set the transfer source/destination address, use the memory map with the DMAC unit0/1 as the bus master. For more information, see 'Address Space' chapter in the RZ microprocessor manual for details.

3. dmac_link_cfg_t::channel_cfg and dmac_link_cfg_t::channel_extension_cfg have configuration restrictions same as the DMAC CHCFG_n and CHEXT_n registers. For more information see 'CHCFG_n : Channel Configuration Register n' and 'CHEXT_n : Channel Extension Register n' section in the RZ microprocessor manual.

4. Setting the link destination of the last descriptor to the address of the previous descriptor configures the descriptors in a loop. When set the descriptor to a loop, disable Parameter Checking of Build Time Configuration to avoid infinite loop operation.

Error Interrupt

The DMAC outputs an error signal to the ICU when DMA error interrupt occurs. ICU can output PERI_ERRn interrupt (Peripherals error event n) to GIC or cause error reset when ICU accepts error signal from DMAC. To use PERI_ERRn interrupt or reset at DMAC, Interrupt Controller Unit (ICU) ERROR (r_icu_error) need to be configured. When the PERI_ERRn interrupt is configured to use interrupt and triggered, the callback function registered during open is called.

Limitations

Developers should be aware of the following limitations when using the DMAC:

• When operating link mode on the Cortex-A55, the source address, destination address, and next link address set in the descriptor should be set with physical addresses. To set the physical address, use R_BSP_MmuVatoPa function to convert from the virtual address to the physical address. If virtual address is set in the descriptor, proper DMA transfer is not guaranteed.
• When operating on the Cortex-A55, do not set the virtual address value that cannot be translated to physical value by MMU as source address, destination address, or descriptor address. These address values are converted to physical addresses in the driver.

Examples

Basic Example (Register mode operation)

This is a basic example of minimal use of the DMAC register mode operation in an application.

In this case, one or more events have been routed to the DMAC for handling so it only needs to be enabled to start accepting transfers.

void dmac_minimal_example (void)
{

    /* Open the transfer instance with initial configuration. */
    fsp_err_t err = R_DMAC_Open(&g_transfer0_ctrl, &g_transfer0_cfg);

    /* Handle any errors. This function should be defined by the user. */
    handle_error(err);



    /* Enable the DMAC so that it responds to transfer requests. */
    err = R_DMAC_Enable(&g_transfer0_ctrl);
    handle_error(err);

}

CMTW Example (Register mode operation)

In this example, one or more events (include CMTW) have been routed to the DMAC for handling so it only needs to be enabled to start accepting transfers.

volatile bool g_transfer_complete = false;

void user_dmac_callback (transfer_callback_args_t * p_args)
{
    if (p_args->event == TRANSFER_EVENT_TRANSFER_END)
    {
        g_transfer_complete = true;
    }
}

void timer_callback (timer_callback_args_t * p_args)
{
    if (TIMER_EVENT_CYCLE_END == p_args->event)
    {
        /* Add application code to be called periodically here. */
    }
}

void dmac_cmtw_example (void)
{
    /* Initialize p_src0 */
    for (uint32_t i = 0; i < TRANSFER_LENGTH_0; i++)
    {
        p_src0[i] = (uint8_t) ('A' + (i % 26));
    }

    /* Initialize p_src1 */
    for (uint32_t i = 0; i < TRANSFER_LENGTH_1; i++)
    {
        p_src1[i] = (uint8_t) ('0' + (i % 10));
    }

    /* Initialize p_src2 */
    for (uint32_t i = 0; i < TRANSFER_LENGTH_2; i++)
    {
        p_src2[i] = (uint8_t) ('a' + (i % 26));
    }

    /* Open the transfer instance with initial configuration. */
    fsp_err_t err = R_DMAC_Open(&g_transfer0_ctrl, &g_transfer0_cfg);

    /* Handle any errors. This function should be defined by the user. */
    handle_error(err);

    /* Open the CMTW instance. (CMTW timer for DMAC transfer trigger.) */
    err = R_CMTW_Open(&g_timer0_ctrl, &g_timer0_cfg);

    /* Handle any errors. This function should be defined by the user. */
    handle_error(err);


    transfer_info_t transfer_info_0;

    /* Transfer size settings */
    transfer_info_0.src_size  = TRANSFER_SIZE_64_BYTE;
    transfer_info_0.dest_size = TRANSFER_SIZE_64_BYTE;

    /* Next0 register settings. */
    transfer_info_0.p_src  = (void *) (&p_src0[0]);
    transfer_info_0.p_dest = (void *) (&p_dest0[0]);
    transfer_info_0.mode   = TRANSFER_MODE_NORMAL;
    transfer_info_0.length = TRANSFER_LENGTH_0;

    /* Next1 register settings. */
    transfer_info_0.p_next1_src  = (void *) (uint32_t) &p_src1[0];
    transfer_info_0.p_next1_dest = (void *) (uint32_t) &p_dest1[0];
    transfer_info_0.next1_length = TRANSFER_LENGTH_1;

    /* Triggered by CMTW, transfer is performed continuously with Next0 -> Next1 setting. */
    err = R_DMAC_Reconfigure(&g_transfer0_ctrl, &transfer_info_0);
    handle_error(err);


    /* Start the timer for DMAC trigger. */
    (void) R_CMTW_Start(&g_timer0_ctrl);

    while (!g_transfer_complete)
    {
        /* Wait for the 1st(Next0 register set) DMA transfer completion. */
    }

    g_transfer_complete = false;

    while (!g_transfer_complete)
    {
        /* Wait for the 2nd(Next1 register set) DMA transfer completion. */
    }

    g_transfer_complete = false;

    /* Stop the timer for DMAC trigger. Transfer will be triggered by software */
    (void) R_CMTW_Stop(&g_timer0_ctrl);

    /* Set Transfer settings by using reconfigure API. */
    transfer_info_t transfer_info_1 = transfer_info_0;
    transfer_info_1.p_src  = (void *) (&p_src2[0]);
    transfer_info_1.p_dest = (void *) (&p_dest2[0]);
    transfer_info_1.mode   = TRANSFER_MODE_BLOCK;
    transfer_info_1.length = TRANSFER_LENGTH_2;
    err = R_DMAC_Reconfigure(&g_transfer0_ctrl, &transfer_info_1);
    handle_error(err);


    /* SoftwareStart */
    /* Note: When executing SoftwareStart API continuously without calling Reconfigure API, */
    /*       Enable API must be called in advance.                                          */
    /*       (EN bit is automatically cleared after the transfer.                           */
    /*        see RZ microprocessor 'CHSTAT_n : Channel Status Register n' section)         */
    err = R_DMAC_SoftwareStart(&g_transfer0_ctrl, (transfer_start_mode_t) NULL);
    handle_error(err);


    while (!g_transfer_complete)
    {
        /* Wait for transfer complete interrupt */
    }
}

Reload Example (Register mode Next0/1 continuous execution operation)

This is a basic example of minimal use of two Next register sets (Next0/1 register set) to continue DMA transfers in register mode. For more information see 'Next Register Continuous Execution Settings' section in the RZ microprocessor manual.

void dmac_reload_example (void)
{
    for (uint32_t i = 0; i < TRANSFER_LENGTH_0; i++)
    {
        p_src0[i] = (uint8_t) (i % UINT8_MAX);
    }

    for (uint32_t i = 0; i < TRANSFER_LENGTH_1; i++)
    {
        p_src1[i] = (uint8_t) ('A' + (i % 26));
    }

    for (uint32_t i = 0; i < TRANSFER_LENGTH_2; i++)
    {
        p_src2[i] = (uint8_t) ('a' + (i % 26));
    }

    /* Open the transfer instance with initial configuration. */
    R_DMAC_Open(&g_transfer0_ctrl, &g_transfer0_cfg);

    /* Reconfigure for the DMA transfer (1st(Next0 register set) and 2nd(Next1 register set) DMA transfer) information. */
    transfer_info_t transfer_info_0;

    /* Transfer size settings */
    transfer_info_0.src_size  = TRANSFER_SIZE_1_BYTE;
    transfer_info_0.dest_size = TRANSFER_SIZE_1_BYTE;

    /* Address mode settings. */
    transfer_info_0.src_addr_mode  = TRANSFER_ADDR_MODE_INCREMENTED;
    transfer_info_0.dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED;

    /* Next0 register settings. */
    transfer_info_0.p_src  = (void *) (&p_src0[0]);
    transfer_info_0.p_dest = (void *) (&p_dest0[0]);
    transfer_info_0.mode   = TRANSFER_MODE_NORMAL;
    transfer_info_0.length = TRANSFER_LENGTH_0;

    /* Next1 register settings. */
    transfer_info_0.p_next1_src  = (void *) (uint32_t) &p_src1[0];
    transfer_info_0.p_next1_dest = (void *) (uint32_t) &p_dest1[0];
    transfer_info_0.next1_length = TRANSFER_LENGTH_1;

    R_DMAC_Reconfigure(&g_transfer0_ctrl, &transfer_info_0);

    /* Software Start. (Block Transfer) */
    R_DMAC_SoftwareStart(&g_transfer0_ctrl, (transfer_start_mode_t) NULL);

    while (!g_transfer_complete)
    {
        /* Wait for the 1st(Next0 register set) DMA transfer completion. */
    }

    g_transfer_complete = false;

    /* Set for the next DMA transfer (3rd(Next0 register set) DMA transfer) information. */
    /* While performing a DMA transfer of a Next register, set the other Next register. */
    R_DMAC_Reload(&g_transfer0_ctrl, &p_src2[0], &p_dest2[0], TRANSFER_LENGTH_2);

    while (!g_transfer_complete)
    {
        /* Wait for the 2nd(Next1 register set) DMA transfer completion. */
    }

    g_transfer_complete = false;

    while (!g_transfer_complete)
    {
        /* Wait for the 3rd(Next0 register set) DMA transfer completion. */
    }
}

Link Mode Example (Cortex-R52 CPU0 Side)

This is a basic example of minimal use of the DMAC link mode operation in an application. DMAC transfer is triggered by R_DMAC_SoftwareStart().

Note

DMAC accesses to TCMs of Cortex-R52 CPU0 via AXIS interface in Cortex-R52 CPU0. Therefore, when setting a TCM area of Cortex-R52 CPU0 as the transfer source/destination address, CPU0 TCM via AXIS area must be set. For more information, see 'Address Space' chapter in the RZ microprocessor manual for details.

#define TRANSFER_LENGTH                     (128)
uint8_t g_src_cr52_cpu0[TRANSFER_LENGTH];  /* Placed at TCM area of Cortex-R52 CPU0 */
uint8_t g_dest_cr52_cpu0[TRANSFER_LENGTH]; /* Placed at TCM area of Cortex-R52 CPU0 */

#define CPU0_TCM_VIA_AXIS_ADDRESS_OFFSET    (0x20000000)

#define DMAC_CHCFG_SETTING_VALUE            (0x80444220)
#define DMAC_CHEXT_SCA_POS                  (4UL)
#define DMAC_CHEXT_DCA_POS                  (12UL)
#define DMAC_CHEXT_SETTING_VALUE_FOR_TCM    ((0x02U << DMAC_CHEXT_SCA_POS) | (0x02U << DMAC_CHEXT_DCA_POS))

dmac_link_cfg_t transfer0_descriptor_cr52_cpu0 BSP_ALIGN_VARIABLE (4) BSP_PLACE_IN_SECTION(".dmac_link_mode") =
{
    .header.link_valid         = DMAC_LINK_VALID_DESCRIPTOR_ENABLE,
    .header.link_end           = DMAC_LINK_END_ENABLE,
    .header.write_back_disable = DMAC_LINK_WRITE_BACK_DISABLE,
    .header.interrupt_mask     = DMAC_LINK_INTERRUPT_MASK_ENABLE,
    .p_src                 = (void *) ((uint32_t) &g_src_cr52_cpu0[0] + CPU0_TCM_VIA_AXIS_ADDRESS_OFFSET),  /* Source address */
    .p_dest                = (void *) ((uint32_t) &g_dest_cr52_cpu0[0] + CPU0_TCM_VIA_AXIS_ADDRESS_OFFSET), /* Destination address */
    .transaction_byte      = TRANSFER_LENGTH,                                                               /* Transaction byte */
    .channel_cfg           = DMAC_CHCFG_SETTING_VALUE,                                                      /* Channel configuration register setting */
    .channel_interval      = 0,                                                                             /* Channel interval. */
    .channel_extension_cfg = DMAC_CHEXT_SETTING_VALUE_FOR_TCM,                                              /* Channel extension register setting */
    .p_next_link_addr      = NULL,                                                                          /* Next link address */
};

void dmac_link_mode_example_cpu0 (void)
{
    for (uint32_t i = 0; i < TRANSFER_LENGTH; i++)
    {
        g_src_cr52_cpu0[i] = (uint8_t) ('A' + (i % 26));
    }

    /* Open the transfer instance with initial configuration. */
    R_DMAC_Open(&g_transfer0_ctrl, &g_transfer0_cfg);

    /* Reset transfer descriptor. */
    R_DMAC_LinkDescriptorSet(&g_transfer0_ctrl, &transfer0_descriptor_cr52_cpu0);

    /* Trigger the transfer using software. */
    R_DMAC_SoftwareStart(&g_transfer0_ctrl, (transfer_start_mode_t) NULL);

    while (!g_transfer_complete)
    {
        /* Wait for transfer complete interrupt */
    }
}

Link Mode Example (Cortex-R52 CPU1 Side)

This is a basic example of minimal use of the DMAC link mode operation in an application. DMAC transfer is triggered by R_DMAC_SoftwareStart().

In this example, the transfer source/destination address is set to a Non-Cached area of System RAM.

#define TRANSFER_LENGTH             (128)
uint8_t g_src_cr52_cpu1[TRANSFER_LENGTH] BSP_PLACE_IN_SECTION(".noncache_buffer");  /* Placed at System RAM Non-Cache buffer area */
uint8_t g_dest_cr52_cpu1[TRANSFER_LENGTH] BSP_PLACE_IN_SECTION(".noncache_buffer"); /* Placed at System RAM Non-Cache buffer area */

#define DMAC_CHCFG_SETTING_VALUE    (0x80444220)
#define DMAC_CHEXT_SETTING_VALUE    (0x00)

dmac_link_cfg_t transfer0_descriptor_cr52_cpu1 BSP_ALIGN_VARIABLE (4) BSP_PLACE_IN_SECTION(".dmac_link_mode") =
{
    .header.link_valid         = DMAC_LINK_VALID_DESCRIPTOR_ENABLE,
    .header.link_end           = DMAC_LINK_END_ENABLE,
    .header.write_back_disable = DMAC_LINK_WRITE_BACK_DISABLE,
    .header.interrupt_mask     = DMAC_LINK_INTERRUPT_MASK_ENABLE,
    .p_src                 = &g_src_cr52_cpu1[0],      /* Source address */
    .p_dest                = &g_dest_cr52_cpu1[0],     /* Destination address */
    .transaction_byte      = TRANSFER_LENGTH,          /* Transaction byte */
    .channel_cfg           = DMAC_CHCFG_SETTING_VALUE, /* Channel configuration register setting */
    .channel_interval      = 0,                        /* Channel interval. */
    .channel_extension_cfg = DMAC_CHEXT_SETTING_VALUE, /* Channel extension register setting */
    .p_next_link_addr      = NULL,                     /* Next link address */
};

void dmac_link_mode_example_cpu1 (void)
{
    for (uint32_t i = 0; i < TRANSFER_LENGTH; i++)
    {
        g_src_cr52_cpu1[i] = (uint8_t) ('A' + (i % 26));
    }

    /* Open the transfer instance with initial configuration. */
    R_DMAC_Open(&g_transfer0_ctrl, &g_transfer0_cfg);

    /* Reset transfer descriptor. */
    R_DMAC_LinkDescriptorSet(&g_transfer0_ctrl, &transfer0_descriptor_cr52_cpu1);

    /* Trigger the transfer using software. */
    R_DMAC_SoftwareStart(&g_transfer0_ctrl, (transfer_start_mode_t) NULL);

    while (!g_transfer_complete)
    {
        /* Wait for transfer complete interrupt */
    }
}

Link Mode Example (Cortex-A55 Side)

This is a basic example of minimal use of the DMAC link mode operation in an application. DMAC transfer is triggered by R_DMAC_SoftwareStart().

In this example, the transfer source/destination address is set to a Non-Cached area of System RAM.

 #define TRANSFER_LENGTH                         (128)
uint8_t g_src_ca55[TRANSFER_LENGTH] BSP_PLACE_IN_SECTION(".noncache_buffer");  /* Placed at System RAM Non-Cache buffer area */
uint8_t g_dest_ca55[TRANSFER_LENGTH] BSP_PLACE_IN_SECTION(".noncache_buffer"); /* Placed at System RAM Non-Cache buffer area */
 #define DMAC_NEXT_DESCRIPTOR_VIRTUAL_ADDRESS    (0x0)
 #define DMAC_CHCFG_SETTING_VALUE                (0x80444220)
 #define DMAC_CHEXT_SETTING_VALUE                (0x00)

dmac_link_cfg_t transfer0_descriptor_ca55 BSP_ALIGN_VARIABLE (8) BSP_PLACE_IN_SECTION(".dmac_link_mode") =
{
    .header.link_valid         = DMAC_LINK_VALID_DESCRIPTOR_ENABLE,
    .header.link_end           = DMAC_LINK_END_ENABLE,
    .header.write_back_disable = DMAC_LINK_WRITE_BACK_DISABLE,
    .header.interrupt_mask     = DMAC_LINK_INTERRUPT_MASK_ENABLE,
    .src_addr              = 0,                        /* Source address (dummy) */
    .dest_addr             = 0,                        /* Destination address (dummy) */
    .transaction_byte      = TRANSFER_LENGTH,          /* Transaction byte */
    .channel_cfg           = DMAC_CHCFG_SETTING_VALUE, /* Channel configuration register setting */
    .channel_interval      = 0,                        /* Channel interval. */
    .channel_extension_cfg = DMAC_CHEXT_SETTING_VALUE, /* Channel extension register setting */
    .next_link_addr        = 0,                        /* Next link address (dummy) */
};

void dmac_link_mode_example_ca55 (void)
{
    for (uint32_t i = 0; i < TRANSFER_LENGTH; i++)
    {
        g_src_ca55[i] = (uint8_t) ('A' + (i % 26));
    }

    /*  To set the physical address, use R_BSP_MmuVatoPa function to convert from the virtual address to the physical address. */
    uint64_t * p_src_paddress;
    R_BSP_MmuVatoPa((uint64_t) &g_src_ca55[0], p_src_paddress);
    transfer0_descriptor_ca55.src_addr = (uint32_t) *p_src_paddress;

    uint64_t * p_dest_paddress;
    R_BSP_MmuVatoPa((uint64_t) &g_dest_ca55[0], p_dest_paddress);
    transfer0_descriptor_ca55.dest_addr = (uint32_t) *p_dest_paddress;

    uint64_t * p_next_link_paddress;
    R_BSP_MmuVatoPa(DMAC_NEXT_DESCRIPTOR_VIRTUAL_ADDRESS, p_next_link_paddress);
    transfer0_descriptor_ca55.next_link_addr = (uint32_t) *p_next_link_address;

    /* Open the transfer instance with initial configuration. */
    R_DMAC_Open(&g_transfer0_ctrl, &g_transfer0_cfg);

    /* Reset transfer descriptor. */
    R_DMAC_LinkDescriptorSet(&g_transfer0_ctrl, &transfer0_descriptor_ca55);

    /* Trigger the transfer using software. */
    R_DMAC_SoftwareStart(&g_transfer0_ctrl, (transfer_start_mode_t) NULL);

    while (!g_transfer_complete)
    {
        /* Wait for transfer complete interrupt */
    }
}

Data Structures
struct	dmac_link_cfg_t
struct	dmac_instance_ctrl_t
struct	dmac_extended_cfg_t

Macros
#define	DMAC_MAX_NORMAL_TRANSFER_LENGTH
#define	DMAC_MAX_BLOCK_TRANSFER_LENGTH

Enumerations
enum	dmac_link_valid_t
enum	dmac_link_end_t
enum	dmac_link_write_back_t
enum	dmac_link_interrupt_mask_t
enum	dmac_register_select_reverse_t
enum	dmac_ack_mode_t
enum	dmac_detection_t
enum	dmac_request_direction_t
enum	dmac_channel_scheduling_t
enum	dmac_mode_select_t

---

Data Structure Documentation

dmac_link_cfg_t

struct dmac_link_cfg_t

Descriptor structure used in DMAC link mode, and variables of dmac_link_cfg_t must be allocated in the memory area.

Data Fields
union dmac_link_cfg_t	__unnamed__
void const *volatile	p_src	Source address.
void *volatile	p_dest	Destination address.
volatile uint32_t	transaction_byte	Transaction byte.
volatile uint32_t	channel_cfg	Channel configuration (Set value for CHCFG_n register).
volatile uint32_t	channel_interval	Channel interval (Set value for CHITVL register).
volatile uint32_t	channel_extension_cfg	Channel extension configuration (Set value for CHEXT_n register).
void *volatile	p_next_link_addr	Next link address.

dmac_instance_ctrl_t

struct dmac_instance_ctrl_t

Control block used by driver. DO NOT INITIALIZE - this structure will be initialized in transfer_api_t::open.

dmac_extended_cfg_t

struct dmac_extended_cfg_t

DMAC transfer configuration extension. This extension is required.

Data Fields
uint8_t	unit
	Unit number.
uint8_t	channel
	Channel number.
IRQn_Type	dmac_int_irq
	DMAC interrupt number.
uint8_t	dmac_int_ipl
	DMAC interrupt priority.
uint32_t	dmac_int_irq_detect_type
	DMAC interrupt detection type.
elc_event_t	activation_source
dmac_ack_mode_t	ack_mode
	DACK output mode.
dmac_detection_t	detection_mode
	DMAC request detection method.
dmac_request_direction_t	activation_request_source_select
	DMAC activation request source.
dmac_register_select_reverse_t	next_register_operaion
	DEPRECATED - next_register_operaion will be renamed next_register_operation in the major release. Next register operation settings.
dmac_mode_select_t	dmac_mode
	DMAC Mode.
dmac_link_cfg_t const *	p_descriptor
	The address of the descriptor (DMA Link Mode only)
uint16_t	transfer_interval
	DMA transfer interval.
dmac_channel_scheduling_t	channel_scheduling
	DMA channel scheduling.
void(*	p_callback )(transfer_callback_args_t *cb_data)
void const *	p_context

Field Documentation

activation_source

elc_event_t dmac_extended_cfg_t::activation_source

Select which event will trigger the transfer.

p_callback

void(* dmac_extended_cfg_t::p_callback) (transfer_callback_args_t *cb_data)

Callback for transfer end interrupt.

p_context

void const* dmac_extended_cfg_t::p_context

Placeholder for user data. Passed to the user p_callback in transfer_callback_args_t.

Macro Definition Documentation

DMAC_MAX_NORMAL_TRANSFER_LENGTH

#define DMAC_MAX_NORMAL_TRANSFER_LENGTH

Max configurable number of transfers in TRANSFER_MODE_NORMAL.

DMAC_MAX_BLOCK_TRANSFER_LENGTH

#define DMAC_MAX_BLOCK_TRANSFER_LENGTH

Max number of transfers per block in TRANSFER_MODE_BLOCK

Enumeration Type Documentation

dmac_link_valid_t

enum dmac_link_valid_t

Indicates the descriptor is enabled or disabled.

Enumerator
DMAC_LINK_VALID_DESCRIPTOR_DISABLE	The Descriptor is disabled.
DMAC_LINK_VALID_DESCRIPTOR_ENABLE	The Descriptor is enabled.

dmac_link_end_t

enum dmac_link_end_t

Indicates that the link ends during DMA transfer of this descriptor.

Enumerator
DMAC_LINK_END_DISABLE	The link continues.
DMAC_LINK_END_ENABLE	The link ends.

dmac_link_write_back_t

enum dmac_link_write_back_t

Masks write back execution of the dmac_link_cfg_t::link_valid. When disable, DMAC does not perform write-back operation.

Enumerator
DMAC_LINK_WRITE_BACK_ENABLE	Set dmac_link_cfg_t::link_valid to disable after the DMA transfer ends.
DMAC_LINK_WRITE_BACK_DISABLE	Remain dmac_link_cfg_t::link_valid after DMA transfer ends.

dmac_link_interrupt_mask_t

enum dmac_link_interrupt_mask_t

When dmac_link_cfg_t::link_valid is DMAC_LINK_VALID_DESCRIPTOR_DISABLE at loading of header, specifies whether DMA transfer completion interrupt mask or not.

Enumerator
DMAC_LINK_INTERRUPT_MASK_DISABLE	DMA transfer completion interrupt is asserted.
DMAC_LINK_INTERRUPT_MASK_ENABLE	DMA transfer completion interrupt is masked.

dmac_register_select_reverse_t

enum dmac_register_select_reverse_t

Select the Next register set to be executed next.

Enumerator
DMAC_REGISTER_SELECT_REVERSE_DISABLE	Use Next0 register set.
DMAC_REGISTER_SELECT_REVERSE_ENABLE	Use Next1 register set.
DMAC_REGISTER_SELECT_REVERSE_ENABLE_PERFORM_ACCORDINGLY	Use Next1 register set after Next0 register set transfer completed.

dmac_ack_mode_t

enum dmac_ack_mode_t

DACK output mode. See 'DMA Transfer Request Detection Operation Setting Table' of RZ microprocessor manual.

Enumerator
DMAC_ACK_MODE_LEVEL_MODE	Level mode.
DMAC_ACK_MODE_BUS_CYCLE_MODE	Bus cycle mode.
DMAC_ACK_MODE_MASK_DACK_OUTPUT	Output is masked.

dmac_detection_t

enum dmac_detection_t

Detection method of the DMA request signal. See 'DMA Transfer Request Detection Operation Setting Table' of RZ microprocessor manual.

Enumerator
DMAC_DETECTION_FALLING_EDGE	Falling edge detection.
DMAC_DETECTION_RISING_EDGE	Rising edge detection.
DMAC_DETECTION_LOW_LEVEL	Low level detection.
DMAC_DETECTION_HIGH_LEVEL	High level detection.

dmac_request_direction_t

enum dmac_request_direction_t

DMA activation request source select. See 'DMA Transfer Request Detection Operation Setting Table' of RZ microprocessor manual.

Enumerator
DMAC_REQUEST_DIRECTION_SOURCE_MODULE	Requested by a transfer source module.
DMAC_REQUEST_DIRECTION_DESTINATION_MODULE	Requested by a transfer destination module.

dmac_channel_scheduling_t

enum dmac_channel_scheduling_t

DMAC channel scheduling.

Enumerator
DMAC_CHANNEL_SCHEDULING_FIXED	Fixed priority mode.
DMAC_CHANNEL_SCHEDULING_ROUND_ROBIN	Round-robin mode.

dmac_mode_select_t

enum dmac_mode_select_t

DMAC mode setting.

Enumerator
DMAC_MODE_SELECT_REGISTER	Register mode.
DMAC_MODE_SELECT_LINK	Link mode.

Function Documentation

R_DMAC_Open()

fsp_err_t R_DMAC_Open	(	transfer_ctrl_t *const	p_ctrl,
		transfer_cfg_t const *const	p_cfg
	)

Configure a DMAC channel.

Return values

FSP_SUCCESS	Successful open.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	The configured channel is invalid.
FSP_ERR_IRQ_BSP_DISABLED	The IRQ associated with the activation source is not enabled in the BSP.
FSP_ERR_ALREADY_OPEN	The control structure is already opened.

R_DMAC_Reconfigure()

fsp_err_t R_DMAC_Reconfigure	(	transfer_ctrl_t *const	p_ctrl,
		transfer_info_t *	p_info
	)

Reconfigure the transfer with new transfer info.

Return values

FSP_SUCCESS	Transfer is configured and will start when trigger occurs.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_ENABLED	DMAC is not enabled. The current configuration must not be valid.
FSP_ERR_INVALID_MODE	DMA mode is link mode. This function can only be used when the DMA mode is register mode.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.

R_DMAC_Reset()

fsp_err_t R_DMAC_Reset	(	transfer_ctrl_t *const	p_ctrl,
		void const *volatile	p_src,
		void *volatile	p_dest,
		uint16_t const	num_transfers
	)

Reset transfer source, destination, and number of transfers.

Return values

FSP_ERR_UNSUPPORTED

API not supported.

R_DMAC_SoftwareStart()

fsp_err_t R_DMAC_SoftwareStart	(	transfer_ctrl_t *const	p_ctrl,
		transfer_start_mode_t	mode
	)

Set a transfer request by software.

Return values

FSP_SUCCESS	Transfer started written successfully.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.

R_DMAC_SoftwareStop()

fsp_err_t R_DMAC_SoftwareStop

(

transfer_ctrl_t *const

p_ctrl

)

Stop software transfers if they were started with TRANSFER_START_MODE_REPEAT.

Return values

FSP_ERR_UNSUPPORTED

API not supported.

R_DMAC_Enable()

fsp_err_t R_DMAC_Enable

(

transfer_ctrl_t *const

p_ctrl

)

Enable transfers for the configured activation source.

Return values

FSP_SUCCESS	Counter value written successfully.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.

R_DMAC_Disable()

fsp_err_t R_DMAC_Disable

(

transfer_ctrl_t *const

p_ctrl

)

Disable transfers so that they are no longer triggered by the activation source.

Return values

FSP_SUCCESS	Counter value written successfully.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.

R_DMAC_InfoGet()

fsp_err_t R_DMAC_InfoGet	(	transfer_ctrl_t *const	p_ctrl,
		transfer_properties_t *const	p_info
	)

Set driver specific information in provided pointer.

Return values

FSP_SUCCESS	Information has been written to p_info.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.
FSP_ERR_ASSERTION	An input parameter is invalid.

R_DMAC_Close()

fsp_err_t R_DMAC_Close

(

transfer_ctrl_t *const

p_ctrl

)

Disable transfer and clean up internal data. Implements transfer_api_t::close.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.

R_DMAC_Reload()

fsp_err_t R_DMAC_Reload	(	transfer_ctrl_t *const	p_ctrl,
		void const *volatile	p_src,
		void *volatile	p_dest,
		uint32_t const	num_transfers
	)

Make the following transfer settings to continue the transfer.

Return values

FSP_SUCCESS	Successful continuous transfer settings.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.
FSP_ERR_INVALID_MODE	This API cannot be called during link mode operation or setting not to use the Next1 register.
FSP_ERR_INVALID_CALL	Invalid call. The series of transfer processing has finished.

R_DMAC_CallbackSet()

fsp_err_t R_DMAC_CallbackSet	(	transfer_ctrl_t *const	p_ctrl,
		void(*)(transfer_callback_args_t *)	p_callback,
		void const *const	p_context,
		transfer_callback_args_t *const	p_callback_memory
	)

Updates the user callback with the option to provide memory for the callback argument structure. Implements transfer_api_t::callbackSet.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

R_DMAC_LinkDescriptorSet()

fsp_err_t R_DMAC_LinkDescriptorSet	(	transfer_ctrl_t *const	p_ctrl,
		dmac_link_cfg_t *	p_descriptor
	)

Reconfigure the transfer descriptor information with new transfer descriptor.

Return values

FSP_SUCCESS	Transfer is configured and will start when trigger occurs.
FSP_ERR_ASSERTION	An input parameter is invalid.
FSP_ERR_NOT_ENABLED	DMAC is not enabled. The current configuration must not be valid.
FSP_ERR_INVALID_MODE	DMA mode is register mode. This function can only be used when the DMA mode is link mode.
FSP_ERR_NOT_OPEN	Handle is not initialized. Call R_DMAC_Open to initialize the control block.