Delta-Sigma Interface (r_dsmif)

Functions
fsp_err_t	R_DSMIF_Open (adc_ctrl_t *p_ctrl, adc_cfg_t const *const p_cfg)
fsp_err_t	R_DSMIF_ScanStart (adc_ctrl_t *p_ctrl)
fsp_err_t	R_DSMIF_ScanStop (adc_ctrl_t *p_ctrl)
fsp_err_t	R_DSMIF_CfgSet (adc_ctrl_t *p_ctrl, adc_cfg_t const *const p_cfg)
fsp_err_t	R_DSMIF_Read (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint32_t *const p_data)
fsp_err_t	R_DSMIF_StatusGet (adc_ctrl_t *p_ctrl, adc_status_t *p_status)
fsp_err_t	R_DSMIF_Close (adc_ctrl_t *p_ctrl)
fsp_err_t	R_DSMIF_CallbackSet (adc_ctrl_t *const p_ctrl, void(*p_callback)(adc_callback_args_t *), void const *const p_context, adc_callback_args_t *const p_callback_memory)
fsp_err_t	R_DSMIF_ErrorStatusGet (adc_ctrl_t *p_ctrl, dsmif_error_status_t *p_error_status)

Detailed Description

Driver for the DSMIF peripheral on RZ microprocessor. This module implements the ADC Interface.

Overview

Features

The DSMIF module supports the following features:

• Number of units: 2 units (10 units for RZ/T2H)
• Number of channels: 3 channels per unit for a total of 6 channels (30 channels for RZ/T2H)
• Decimation filter characteristics: Filter are selectable as Sinc 1st order, Sinc 2nd order, Sinc 3rd order Can select each channel.
• Over-sampling rate (decimation rate): Selectable from 4 to 256 Can select each channel.
• Interface clock: Support Master mode (MCLK is used as output)/Slave mode (MCLK is used as input) by channel

Master mode supports the following output clock for RZ/T2M, RZ/T2ME and RZ/T2L:

• 25/20/12.5/10/6.25/5 MHz (PCLKH 200 MHz)
• 25/18.75/12.5/9.375/6.25/5 MHz (PCLKH 150 MHz)

Master mode supports the following output clock for RZ/T2H:

• 25/20/12.5/10/6.25/5 MHz (Core clock 400Mhz, Bus Clock 250 Mhz)
• 25/20.8/12.5/10.4/6.25/5 MHz (Core Clock 250 MHz, Bus Clock 250 Mhz)

Filter received clock inversion function.

• Data capture: Crests and troughs can trigger capture, allowing capture of values for current with the same timing.Can select one capture trigger from six triggers for each trigger input by channel.
• Unit synchronization: Not supported.
• Reset function of differential filter clock divider: Support channel by channel. Can select one from three triggers.
• Error source ouput (interrupt): Error signals are output under the following conditions: Abnormal-overcurrent detection Short-circuit detection Total-current error detection
• Low-power consumption function: The module-stop state can be set. (clock gating function is implemented)

Configuration

Build Time Configurations for r_dsmif

The following build time configurations are defined in fsp_cfg/r_dsmif_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Multiplex Interrupt	Enabled Disabled	Disabled	Enable multiplex interrupt for a single driver.

Configurations for Analog > ADC Driver (r_dsmif)

This module can be added to the Stacks tab via New Stack > Analog > ADC Driver (r_dsmif).

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_dsmif0	Module name.
General > Unit	Value must be an integer greater than or equal to 0	0	DSMIF Unit No.
General > [DEPRECATED]Mode	Synchronization Individual	Synchronization	DSMIF operation mode definitions.
Extra > Channel Synchronization > Counter Reset > Division counter initialization trigger	No Trigger Trigger 0 Trigger 1 Trigger 2	No Trigger	Current measurement filter initialization trigger.
Extra > Channel Synchronization > Counter Reset > Edge	Negative Edge Positive Edge	Negative Edge	Current measurement filter initialization trigger for division counter for decimation edge.
Extra > Channel Synchronization > Capture Trigger A	No Trigger Trigger 0 Trigger 1 Trigger 2 Trigger 3 Trigger 4 Trigger 5	No Trigger	Current capture trigger A selection.
Extra > Channel Synchronization > Capture Trigger B	No Trigger Trigger 0 Trigger 1 Trigger 2 Trigger 3 Trigger 4 Trigger 5	No Trigger	Current capture trigger B selection.
Extra > Overcurrent Sum Error > Upper Limit > Detection	Invalid Valid	Invalid	Overcurrent sum error upper limit detection enable.
Extra > Overcurrent Sum Error > Upper Limit > Limit Value	Overcurrent Sum Error Detect High Threshold between 0x00000 and 0x3FFFF	0x00000	Overcurrent Sum Error Detect High Threshold.
Extra > Overcurrent Sum Error > Lower Limit > Detection	Invalid Valid	Invalid	Overcurrent sum error lower limit detection enable.
Extra > Overcurrent Sum Error > Lower Limit > Limit Value	Overcurrent Sum Error Detect Low Threshold between 0x00000 and 0x3FFFF	0x00000	Overcurrent Sum Error Detect Low Threshold.
Extra > Overcurrent Sum Error > Interrupts > Callback	Name must be a valid C symbol	NULL	A user callback function. If this callback function is provided, it is called from the interrupt service routine (ISR) each time the overcurrent sum error.
Extra > Overcurrent Sum Error > Interrupts > Interrupt Priority	MCU Specific Options		Select the overcurrent sum error interrupt priority.
Extra > Overcurrent Sum Error > Interrupts > Upper Limit Interrupt	Disabled Enabled	Disabled	Overcurrent sum error upper limit detection interrupt enable.
Extra > Overcurrent Sum Error > Interrupts > Lower Limit Interrupt	Disabled Enabled	Disabled	Overcurrent sum error lower limit detection interrupt enable.
Extra > Overcurrent Sum Error > Mode	CH0, CH1, CH2 CH0, CH1 CH0 CH1 CH2	CH0, CH1, CH2	Overcurrent sum error detect mode setting.
Extra > Data Format Select	Left justified Right justified	Left justified	Data shift setting when setting the Sinc filter output to the DSCDRCHn register.
ELC > DSMIF CAP_TRG0 event > Trigger Source	MCU Specific Options		ELC_SSEL settings.
ELC > DSMIF CAP_TRG1 event > Trigger Source	MCU Specific Options		ELC_SSEL settings.
ELC > DSMIF CAP_TRG2 event > Trigger Source	MCU Specific Options		ELC_SSEL settings.
ELC > DSMIF CAP_TRG3 event > Trigger Source	MCU Specific Options		ELC_SSEL settings.
ELC > DSMIF CAP_TRG4 event > Trigger Source	MCU Specific Options		ELC_SSEL settings.
ELC > DSMIF CAP_TRG5 event > Trigger Source	MCU Specific Options		ELC_SSEL settings.
ELC > DSMIF CDCNT_INT_TRG0 > Trigger Source	MCU Specific Options		ELC_SSEL settings.
ELC > DSMIF CDCNT_INT_TRG1 > Trigger Source	MCU Specific Options		ELC_SSEL settings.
ELC > DSMIF CDCNT_INT_TRG2 > Trigger Source	MCU Specific Options		ELC_SSEL settings.
Unique No	Numbers only	0	A unique number that manages multiple instances.

Configurations for Analog > DSMIF Channel Configuration (r_dsmif)

Configuration	Options	Default	Description
A/D Convert(Current Measurement) > Clock > Clock Mode	Slave Master	Slave	A/D conversion clock master/slave switching.
A/D Convert(Current Measurement) > Clock > Clock(clock master mode)	MCU Specific Options		This setting needs the PCLKH setting that can be set on the Clocks tab. A/D conversion clock division ratio.
A/D Convert(Current Measurement) > Sinc Filter > Filter Order	Filter Order 3rd Filter Order 1st Filter Order 2nd	Filter Order 3rd	Current measurement filter order setting.
A/D Convert(Current Measurement) > Sinc Filter > Decimation Ratio	MCU Specific Options		Decimation ratio selection for current measurement.
A/D Convert(Current Measurement) > Interrupts > Capture	Disabled Enabled	Disabled	Current data register update interrupt enable.
A/D Convert(Current Measurement) > Capture Edge	Negative Edge Positive Edge	Negative Edge	Sampling edge selection.
Extra > Overcurrent > Sinc Filter > Filter Order	Filter Order 3rd Filter Order 1st Filter Order 2nd	Filter Order 3rd	Overcurrent detection filter order setting.
Extra > Overcurrent > Sinc Filter > Decimation Ratio	MCU Specific Options		Decimation ratio selection for overcurrent detectiont.
Extra > Overcurrent > Detection 0 > Upper Limit > Detection	Disabled Enabled	Disabled	Overcurrent upper limit exceeded detection enable.
Extra > Overcurrent > Detection 0 > Upper Limit > Limit Value	Overcurrent detection upper limit between 0x0 and 0xFFFF	0x0	Overcurrent detection upper limit.
Extra > Overcurrent > Detection 0 > Lower Limit > Detection	Disabled Enabled	Disabled	Overcurrent lower limit detection enable.
Extra > Overcurrent > Detection 0 > Lower Limit > Limit Value	Overcurrent detection lower limit between 0x0 and 0xFFFF	0x0	Overcurrent detection lower limit.
Extra > Overcurrent > Detection 0 > Interrupts > Upper Limit Interrupt	Disabled Enabled	Disabled	Overcurrent upper limit exceeded output interrupt enable.
Extra > Overcurrent > Detection 0 > Interrupts > Lower Limit Interrupt	Disabled Enabled	Disabled	Overcurrent lower limit detection interrupt enable.
Extra > Overcurrent > Detection 1 > Upper Limit > Detection	Disabled Enabled	Disabled	Overcurrent upper limit exceeded detection enable.
Extra > Overcurrent > Detection 1 > Upper Limit > Limit Value	Overcurrent detection upper limit between 0x0 and 0xFFFF	0x0	Overcurrent detection upper limit.
Extra > Overcurrent > Detection 1 > Lower Limit > Detection	Disabled Enabled	Disabled	Overcurrent lower limit detection enable.
Extra > Overcurrent > Detection 1 > Lower Limit > Limit Value	Overcurrent detection lower limit between 0x0 and 0xFFFF	0x0	Overcurrent detection lower limit.
Extra > Overcurrent > Detection 1 > Interrupts > Upper Limit Interrupt	Disabled Enabled	Disabled	Overcurrent upper limit exceeded output interrupt enable.
Extra > Overcurrent > Detection 1 > Interrupts > Lower Limit Interrupt	Disabled Enabled	Disabled	Overcurrent lower limit detection interrupt enable.
Extra > Overcurrent > Detection 2 > Upper Limit > Detection	Disabled Enabled	Disabled	Overcurrent upper limit exceeded detection enable.
Extra > Overcurrent > Detection 2 > Upper Limit > Limit Value	Overcurrent detection upper limit between 0x0 and 0xFFFF	0x0	Overcurrent detection upper limit.
Extra > Overcurrent > Detection 2 > Lower Limit > Detection	Disabled Enabled	Disabled	Overcurrent lower limit detection enable.
Extra > Overcurrent > Detection 2 > Lower Limit > Limit Value	Overcurrent detection lower limit between 0x0 and 0xFFFF	0x0	Overcurrent detection lower limit.
Extra > Overcurrent > Detection 2 > Interrupts > Upper Limit Interrupt	Disabled Enabled	Disabled	Overcurrent upper limit exceeded output interrupt enable.
Extra > Overcurrent > Detection 2 > Interrupts > Lower Limit Interrupt	Disabled Enabled	Disabled	Overcurrent lower limit detection interrupt enable.
Extra > Overcurrent > Window Notification > Notification 0 > Output Enable	Disabled Enabled	Disabled	Overcurrent detection window notification 0 output enable.
Extra > Overcurrent > Window Notification > Notification 0 > Function Enable	Disabled Enabled	Disabled	Overcurrent detection window notification 0 function enable.
Extra > Overcurrent > Window Notification > Notification 0 > Mode	(overcurrent data < lower limit 0) or (overcurrent data > upper limit 0) lower limit 0 <= overcurrent data <= upper limit 0	(overcurrent data < lower limit 0) or (overcurrent data > upper limit 0)	Channel n overcurrent detection window notification 0 mode select.
Extra > Overcurrent > Window Notification > Notification 1 > Output Enable	Disabled Enabled	Disabled	Overcurrent detection window notification 1 output enable.
Extra > Overcurrent > Window Notification > Notification 1 > Function Enable	Disabled Enabled	Disabled	Overcurrent detection window notification 1 function enable.
Extra > Overcurrent > Window Notification > Notification 1 > Mode	(overcurrent data < lower limit 1) or (overcurrent data > upper limit 1) lower limit 1 <= overcurrent data <= upper limit 1	(overcurrent data < lower limit 1) or (overcurrent data > upper limit 1)	Channel n overcurrent detection window notification 1 mode select.
Extra > Overcurrent > Window Notification > Notification 2 > Output Enable	Disabled Enabled	Disabled	Overcurrent detection window notification 2 output enable.
Extra > Overcurrent > Window Notification > Notification 2 > Function Enable	Disabled Enabled	Disabled	Overcurrent detection window notification 2 function enable.
Extra > Overcurrent > Window Notification > Notification 2 > Mode	(overcurrent data < lower limit 2) or (overcurrent data > upper limit 2) lower limit 2 <= overcurrent data <= upper limit 2	(overcurrent data < lower limit 2) or (overcurrent data > upper limit 2)	Channel n overcurrent detection window notification 2 mode select.
Extra > Overcurrent > Window Notification > Notification 3 > Output Enable	Disabled Enabled	Disabled	Overcurrent detection window notification 3 output enable.
Extra > Overcurrent > Window Notification > Notification 3 > Function Enable	Disabled Enabled	Disabled	Overcurrent detection window notification 3 function enable.
Extra > Overcurrent > Window Notification > Notification 3 > Mode	Refer to the RZT Configuration tool for available options.	Notification 0	Channel n overcurrent detection window notification 3 mode select.
Extra > Short Circuit > Interrupts > Interrupt	Disabled Enabled	Disabled	Short circuit detection error interrupt enable.
Extra > Short Circuit > Detection	Disabled Enabled	Disabled	Short circuit detection enable.
Extra > Short Circuit > High Count Threshold	Short circuit detection high continuous detection count between 0x0 and 0x1FFF	0x0	Short circuit detection high continuous detection count.
Extra > Short Circuit > Low Count Threshold	Short circuit detection low continuous detection count between 0x0 and 0x1FFF	0x0	Short circuit detection low continuous detection count.
Name	Manual Entry	g_dsmif_channel0	Module name.

Clock Configuration

The DSMIF clock is configurable on the clocks tab.

Master mode supports the following output clock for RZ/T2M, RZ/T2ME and RZ/T2L:

• 25/20/12.5/10/6.25/5 MHz (PCLKH 200 MHz)
• 25/18.75/12.5/9.375/6.25/5 MHz (PCLKH 150 MHz)

Master mode supports the following output clock for RZ/T2H:

• 25/20/12.5/10/6.25/5 MHz (Core clock 400Mhz, Bus Clock 250 Mhz)
• 25/20.8/12.5/10.4/6.25/5 MHz (Core Clock 250 MHz, Bus Clock 250 Mhz)

Pin Configuration

The relationship between the I / O pin and the DSMIF unit for RZ/T2M, RZ/T2ME and RZ/T2L is as follows.

Item	Unit0(DSMIF0)	Unit1(DSMIF1)
Clock	MCLK0-2	MCLK3-5
Data	MDAT0-2	MDAT3-5

The relationship between the I / O pin and the DSMIF unit for RZ/T2H is as follows.

Item	Unitm(DSMIFn)
Clock	MCLKmn
Data	MDATmn

Note: m = 0 to 9 (unit), n = 0 to 2 (channel)

Usage Notes

In this document, the term "sampling" refers to the ability to sample data from the DSMIF clock and works as follows:

1. Clock Specification Sampling clock ofDSMIF is Select slave mode or master mode. In slave mode, the external input MCLKn is the sampling clock. In master mode, the clock obtained by dividing PCLKH is the sampling clock.
2. Channel Start and Channel Stop Sampling starts by starting the channel. Sampling is stopped by stopping the channel. There are two modes for starting the channel, synchronization control mode and individual control mode. Channel start and channel stop and mode selection are controlled by registers. Refer to the Table 39.4 "Channel start trigger and channel stop trigger" in Chapter 39.36 "Channel Start and Channel" Stop for the correspondence of the registers to be controlled.
3. Channel Synchronization To synchronize the channels, you need to synchronize the Sinc filter of each channel. To sync, follow the steps in Section 39.3.1. Start the flow.
   1. Set the same clock settings.
   2. Select the same trigger for division counter initialization trigger. Set the same value to Division counter initialization trigger select bits (DSCMCTCRCHn.DITSEL[1:0]).
   3. Select the same trigger for capture trigger A and B. (a) Set the same value to the Current Capture Trigger A Select bits (DSCMCTCRCHn.CTSELA[2:0]). (b) Set the same value to the Current Capture Trigger B Select bits (DSCMCTCRCHn.CTSELB[2:0]).
   4. Activate the channels simultaneously Write 1 to Channel n start trigger (DSCSTRTR.STRTRGn) at the same time.
4. Data Input Control By using the DSCMCRCHn.SEDGE bit, data receive can be selected to receive on the falling edge of MCLKn or the rising edge of MCLKn. Data input control receives clock and data from DSM.
5. Sinc Filter The differentiation stage is operated by decimation clock (the frequency is 1/M of MCLKn). M is the decimation ratio and is set in the DSCMFCRCHn.CMDEC[7:0] bits for current measurement or in the DSOCFCRCHn.OCDEC[7:0] bits for overcurrent detection. The filter result is stored in register every decimation clock. In the case of current data, an interrupt is output at the same time when the filter result is stored.
6. Available Settings of Sinc Filter Available Settings of Sinc Filter is refer to Chapter 39.3.10. Table 39.5 lists the available settings of the sinc filter and data shifting.
7. Current Measurement Data Processing Each channel of DSMIF has the data registers specified in Table 39.6. Capture trigger A is selected by DSCMCTCRCHn.CTSELA[2:0] and capture trigger B is selected by DSCMCTCRCHn.CTSELB[2:0]. The trigger capturing function allows the capture of the values for current at the time of capture trigger A and capture trigger B using the event link controller (ELC) to set the capture trigger A or capture trigger B.
8. Short-circuit Detection When the short-circuit detection enable (DSEDCRCHn.SDE) is valid, the short-circuit detection can operate. A dedicated 13-bit counter counts consecutive 0 or 1 input from dsmdata n (n = 0 to 2). When the number of consecutive 0 exceeds the value set in the DSSCTSRCHn.SCNTL[12:0] register or the number of consecutive 1 exceeds the value set in the DSSCTSRCHn.SCNTH[12:0] register, a short-circuit detection interrupt request is generated.
9. Overcurrent Sum Error Detection
   • When the overcurrent sum error upper limit detection enable (DSSECR.SEEH) is valid, the overcurrent sum error upper limit detection can operate.
   • When the overcurrent sum error lower limit detection enable (DSSECR.SEEL) is valid, the overcurrent sum error lower limit detection can operate.
   • An overcurrent upper limit sum error detection interrupt is requested when the sum of the values for each mode (see Table 39.7) is higher than the value of SCMPTBH.
   • An overcurrent lower limit sum error detection interrupt is requested when the sum of the values for each mode is lower than the value of SCMPTBL.

When Interrupts Are Not Enabled

If interrupts are not enabled, the R_DSMIF_StatusGet() API can be used to poll the DSMIF to determine when the scan has completed. The R_DSMIF_Read() API function is used to access the converted DSMIF result.

Notes when specifying a channel

In the channel specification of R_DSMIF_Read(), select channels 0 to 2 even when using Unit1.

Examples

Basic Example

This is a basic example of minimal use of the DSMIF in an application.

void dsmif_basic_example (void)
{
    fsp_err_t err = FSP_SUCCESS;


    /* Initializes the module. */
    err = R_DSMIF_Open(&g_dsmif0_ctrl, &g_dsmif0_cfg);


    /* Handle any errors. This function should be defined by the user. */
    handle_error(err);


    dsmif_status_t status;
    status.state = DSMIF_STATE_IN_OPERATION;
    while (DSMIF_STATE_IN_OPERATION == status.state)
    {
        R_DSMIF_StatusGet(&g_dsmif0_ctrl, &status);
    }



    /* Calculate the stable output time of the filter result. */
    set_time_unit0 = r_dsmif_setting_time_calc(&g_dsmif0_ctrl);

    /* In software trigger mode, start a scan by calling R_DSMIF_ScanStart(). In other modes, enable external
     * triggers by calling R_DSMIF_ScanStart(). */
    (void) R_DSMIF_ScanStart(&g_dsmif0_ctrl);



    /* Wait for the time from the start of the channel to the stable output of the filter result. */
    R_BSP_SoftwareDelay(set_time_unit0, BSP_DELAY_UNITS_MICROSECONDS);

    R_DSMIF_CfgSet(&g_dsmif0_ctrl, &g_dsmif0_cfg);


    /* Wait for conversion to complete. */
    status.state = DSMIF_STATE_IN_OPERATION;
    while (DSMIF_STATE_IN_OPERATION == status.state)
    {
        R_DSMIF_StatusGet(&g_dsmif0_ctrl, &status);
    }


    /* Read converted data. */
    uint32_t      data32;
    adc_channel_t dsmif_ch = ADC_CHANNEL_0;
    R_DSMIF_Read(&g_dsmif0_ctrl, dsmif_ch, &data32);

}

Data Structures
struct	dsmif_extended_cfg_t
struct	dsmif_instance_ctrl_t
struct	dsmif_error_status_t

Enumerations
enum	dsmif_sum_err_detect_channel_t
enum	dsmif_clock_ctrl_t
enum	dsmif_clock_edge_t
enum	dsmif_filter_order_t
enum	dsmif_data_shift_t
enum	dsmif_capture_trigger_t
enum	dsmif_counter_init_trigger_t
enum	dsmif_current_data_t
enum	dsmif_channel_mask_t
enum	dsmif_channel_overcurrent_status_t
enum	dsmif_channel_short_circuit_status_t
enum	dsmif_overcurrent_sum_status_t

---

Data Structure Documentation

dsmif_extended_cfg_t

struct dsmif_extended_cfg_t

DSMIF configuration extension. This extension is required and must be provided in dsmif_cfg_t::p_extend.

Data Fields
bool	isel	Overcurrent sum error lower limit detection interrupt enable bit.
bool	iseh	Overcurrent sum error upper limit detection interrupt enable bit.
dsmif_sum_err_detect_channel_t	sedm	Overcurrent sum error detect mode setting bit.
uint32_t	scmptbl	DSSELTR : Overcurrent Sum Error Detect Low Threshold Register.
uint32_t	scmptbh	DSSEHTR : Overcurrent Sum Error Detect High Threshold Register.
bool	seel	DSSECR : Overcurrent Sum Error lower limit detection enable.
bool	seeh	DSSECR : Overcurrent Sum Error upper limit detection enable.
dsmif_capture_trigger_t	cap_trig_a	DSCMCTCRCHn.CTSELA[2:0] : Current capture trigger A selection bit.
dsmif_capture_trigger_t	cap_trig_b	DSCMCTCRCHn.CTSELB[2:0] : Current capture trigger B selection bit.
dsmif_counter_init_trigger_t	cnt_init_trig	DSCMCTCRCHn.DITSEL[2:0] : Current measurement filter initialization trigger division counter for decimation.
dsmif_clock_edge_t	edge	DSCMCTCRCHn.DEDGE[2:0] : Current measurement filter initialization trigger for division counter for decimation edge.
dsmif_channel_cfg_t *	p_channel_cfgs[DSMIF_MAX_NUM_CHANNELS]	Configuration for each channel, set to NULL if unused.
dsmif_channel_mask_t	channel_mask	Channel bitmask.

dsmif_instance_ctrl_t

struct dsmif_instance_ctrl_t

DSMIF instance control block. DO NOT INITIALIZE.

dsmif_error_status_t

struct dsmif_error_status_t

DSMIF Error status.

Data Fields
dsmif_channel_overcurrent_status_t	channel_overcurrent_status	Channel Overcurrent state.
dsmif_channel_short_circuit_status_t	channel_short_circuit_status	Channel Short circuit state.
dsmif_overcurrent_sum_status_t	overcurrent_sum_status	Overcurrent Sum state.

Enumeration Type Documentation

dsmif_sum_err_detect_channel_t

enum dsmif_sum_err_detect_channel_t

Enumerator
DSMIF_SUM_ERR_DETECT_CHANNEL_0_2	Detects error of sum value of overcurrent data of CH0, CH1, CH2.
DSMIF_SUM_ERR_DETECT_CHANNEL_0_1	Detects error of sum value of overcurrent data of CH0, CH1.
DSMIF_SUM_ERR_DETECT_CHANNEL_0	Detects error of overcurrent data of CH0.
DSMIF_SUM_ERR_DETECT_CHANNEL_1	Detects error of overcurrent data of CH1.
DSMIF_SUM_ERR_DETECT_CHANNEL_2	Detects error of overcurrent data of CH2.

dsmif_clock_ctrl_t

enum dsmif_clock_ctrl_t

Enumerator
DSMIF_CLOCK_CTRL_SLAVE	MCLKn pin is input (slave operation)
DSMIF_CLOCK_CTRL_MASTER	MCLKn pin is output (master operation)

dsmif_clock_edge_t

enum dsmif_clock_edge_t

Enumerator
DSMIF_CLOCK_EDGE_NEGATIVE	Capture MDATn at the negative edge of MCLKn.
DSMIF_CLOCK_EDGE_POSITIVE	Capture MDATn at the positive edge of MCLKn.

dsmif_filter_order_t

enum dsmif_filter_order_t

Enumerator
DSMIF_FILTER_ORDER_3RD	Overcurrent detection filter order setting 3rd order.
DSMIF_FILTER_ORDER_1ST	Overcurrent detection filter order setting 1st order.
DSMIF_FILTER_ORDER_2ND	Overcurrent detection filter order setting 2nd order.

dsmif_data_shift_t

enum dsmif_data_shift_t

Enumerator
DSMIF_DATA_SHIFT_23_8	Data shift setting for overcurrent detection [23:8].
DSMIF_DATA_SHIFT_22_7	Data shift setting for overcurrent detection [22:7].
DSMIF_DATA_SHIFT_21_6	Data shift setting for overcurrent detection [21:6].
DSMIF_DATA_SHIFT_20_5	Data shift setting for overcurrent detection [20:5].
DSMIF_DATA_SHIFT_19_4	Data shift setting for overcurrent detection [19:4].
DSMIF_DATA_SHIFT_18_3	Data shift setting for overcurrent detection [18:3].
DSMIF_DATA_SHIFT_17_2	Data shift setting for overcurrent detection [17:2].
DSMIF_DATA_SHIFT_16_1	Data shift setting for overcurrent detection [16:1].
DSMIF_DATA_SHIFT_15_0	Data shift setting for overcurrent detection [15:0].
DSMIF_DATA_SHIFT_14_0	Data shift setting for overcurrent detection [14:0].
DSMIF_DATA_SHIFT_13_0	Data shift setting for overcurrent detection [13:0].
DSMIF_DATA_SHIFT_12_0	Data shift setting for overcurrent detection [12:0].
DSMIF_DATA_SHIFT_11_0	Data shift setting for overcurrent detection [11:0].
DSMIF_DATA_SHIFT_10_0	Data shift setting for overcurrent detection [10:0].
DSMIF_DATA_SHIFT_9_0	Data shift setting for overcurrent detection [9:0].
DSMIF_DATA_SHIFT_8_0	Data shift setting for overcurrent detection [8:0].
DSMIF_DATA_SHIFT_7_0	Data shift setting for overcurrent detection [7:0].
DSMIF_DATA_SHIFT_6_0	Data shift setting for overcurrent detection [6:0].
DSMIF_DATA_SHIFT_5_0	Data shift setting for overcurrent detection [5:0].
DSMIF_DATA_SHIFT_4_0	Data shift setting for overcurrent detection [4:0].

dsmif_capture_trigger_t

enum dsmif_capture_trigger_t

Enumerator
DSMIF_CAPTURE_TRIGGER_NOT	Do not capture.
DSMIF_CAPTURE_TRIGGER_0	Select current data capture trigger 0.
DSMIF_CAPTURE_TRIGGER_1	Select current data capture trigger 1.
DSMIF_CAPTURE_TRIGGER_2	Select current data capture trigger 2.
DSMIF_CAPTURE_TRIGGER_3	Select current data capture trigger 3.
DSMIF_CAPTURE_TRIGGER_4	Select current data capture trigger 4.
DSMIF_CAPTURE_TRIGGER_5	Select current data capture trigger 5.

dsmif_counter_init_trigger_t

enum dsmif_counter_init_trigger_t

Enumerator
DSMIF_COUNTER_INIT_TRIGGER_NOT	Do not initialize.
DSMIF_COUNTER_INIT_TRIGGER_0	Select decimation dividing counter initialization trigger 0.
DSMIF_COUNTER_INIT_TRIGGER_1	Select decimation dividing counter initialization trigger 1.
DSMIF_COUNTER_INIT_TRIGGER_2	Select decimation dividing counter initialization trigger 2.

dsmif_current_data_t

enum dsmif_current_data_t

DSMIF data register

Enumerator
DSMIF_CURRENT_DATA	DSCDRCHn : Current Data Register.
DSMIF_CURRENT_DATA_CAPTURE_A	DSCCDRACHn : Capture Current Data Register A.
DSMIF_CURRENT_DATA_CAPTURE_B	DSCCDRBCHn : Capture Current Data Register B.

dsmif_channel_mask_t

enum dsmif_channel_mask_t

For DSMIF Scan configuration e_dsmif_ch_mask::channel_mask. Use bitwise OR to combine these masks for desired channels and sensors.

Enumerator
DSMIF_CHANNEL_MASK_OFF	No channels selected.
DSMIF_CHANNEL_MASK_0	Channel 0 mask.
DSMIF_CHANNEL_MASK_1	Channel 1 mask.
DSMIF_CHANNEL_MASK_2	Channel 2 mask.
DSMIF_CHANNEL_MASK_3	Channel 3 mask.
DSMIF_CHANNEL_MASK_4	Channel 4 mask.
DSMIF_CHANNEL_MASK_5	Channel 5 mask.

dsmif_channel_overcurrent_status_t

enum dsmif_channel_overcurrent_status_t

DSMIF Channel Overcurrent detect status.

Enumerator
DSMIF_CHANNEL_OVERCURRENT_STATUS_CH0_LOWER_LIMIT_0	Channel 0 overcurrent lower limit detection 0 flag.
DSMIF_CHANNEL_OVERCURRENT_STATUS_CH1_LOWER_LIMIT_0	Channel 1 overcurrent lower limit detection 0 flag.
DSMIF_CHANNEL_OVERCURRENT_STATUS_CH2_LOWER_LIMIT_0	Channel 2 overcurrent lower limit detection 0 flag.
DSMIF_CHANNEL_OVERCURRENT_STATUS_CH0_UPPER_LIMIT_0	Channel 0 overcurrent upper limit exceeded 0 flag.
DSMIF_CHANNEL_OVERCURRENT_STATUS_CH1_UPPER_LIMIT_0	Channel 1 overcurrent upper limit exceeded 0 flag.
DSMIF_CHANNEL_OVERCURRENT_STATUS_CH2_UPPER_LIMIT_0	Channel 2 overcurrent upper limit exceeded 0 flag.

dsmif_channel_short_circuit_status_t

enum dsmif_channel_short_circuit_status_t

DSMIF Channel Short circuit detect status.

Enumerator
DSMIF_CHANNEL_SHORT_CIRCUIT_STATUS_CH0	Channel 0 short circuit detection flag.
DSMIF_CHANNEL_SHORT_CIRCUIT_STATUS_CH1	Channel 1 short circuit detection flag.
DSMIF_CHANNEL_SHORT_CIRCUIT_STATUS_CH2	Channel 2 short circuit detection flag.

dsmif_overcurrent_sum_status_t

enum dsmif_overcurrent_sum_status_t

DSMIF Overcurrent Sum detect status.

Enumerator
DSMIF_OVERCURRENT_SUM_STATUS_LOWER_LIMIT	Overcurrent sum error lower limit detection flag.
DSMIF_OVERCURRENT_SUM_STATUS_UPPER_LIMIT	Overcurrent sum error upper limit detection flag.

Function Documentation

R_DSMIF_Open()

fsp_err_t R_DSMIF_Open	(	adc_ctrl_t *	p_ctrl,
		adc_cfg_t const *const	p_cfg
	)

Applies power to the DSMIF and initializes the hardware based on the user configuration. As part of this initialization, set interrupts, set DSMIF error interrupt registers, etc.

Note

The DSMIF error interrupt is PERI_ERR0, which is an interrupt handler common to other modules, so IRQ interrupts are not allowed here.

Return values

FSP_SUCCESS	Configuration successful.
FSP_ERR_ASSERTION	An input pointer is NULL or an input parameter is invalid.
FSP_ERR_ALREADY_OPEN	Control block is already open.
FSP_ERR_IRQ_BSP_DISABLED	A required interrupt is disabled
FSP_ERR_IP_UNIT_NOT_PRESENT	The Unit requested in the p_cfg parameter is not available on this device.

R_DSMIF_ScanStart()

fsp_err_t R_DSMIF_ScanStart

(

adc_ctrl_t *

p_ctrl

)

Starts either synchronous control mode or individual control mode .

Note

After executing R_DSMIF_ScanStart, it is necessary to wait until the filter result is output stably. (Reference section 39.3.15.1 "Settling Time of Channel Activation")

Return values

FSP_SUCCESS	Scan started or hardware triggers enabled successfully.
FSP_ERR_ASSERTION	An input pointer was NULL.
FSP_ERR_NOT_OPEN	Instance control block is not open.

R_DSMIF_ScanStop()

fsp_err_t R_DSMIF_ScanStop

(

adc_ctrl_t *

p_ctrl

)

Stops any in-progress scan started by software.

Return values

FSP_SUCCESS	Scan stopped or hardware triggers disabled successfully.
FSP_ERR_ASSERTION	An input pointer was NULL.
FSP_ERR_NOT_OPEN	Instance control block is not open.
FSP_ERR_TIMEOUT	Timeout error.

R_DSMIF_CfgSet()

fsp_err_t R_DSMIF_CfgSet	(	adc_ctrl_t *	p_ctrl,
		adc_cfg_t const *const	p_cfg
	)

Configuration settings.(Overcurrent detection and Sum error detection).

Return values

FSP_SUCCESS	Configuration setting successfully.
FSP_ERR_ASSERTION	An input pointer was NULL.
FSP_ERR_NOT_OPEN	Instance control block is not open.

R_DSMIF_Read()

fsp_err_t R_DSMIF_Read	(	adc_ctrl_t *	p_ctrl,
		adc_channel_t const	reg_id,
		uint32_t *const	p_data
	)

Reads the most recent result from a channel.

Return values

FSP_SUCCESS	Result in p_data.
FSP_ERR_ASSERTION	An input pointer was NULL or an input parameter was invalid.
FSP_ERR_NOT_OPEN	Instance control block is not open.

R_DSMIF_StatusGet()

fsp_err_t R_DSMIF_StatusGet	(	adc_ctrl_t *	p_ctrl,
		adc_status_t *	p_status
	)

Returns the status of a scan started by software.

Return values

FSP_SUCCESS	No software scan is in progress.
FSP_ERR_ASSERTION	An input pointer was NULL.
FSP_ERR_NOT_OPEN	Instance control block is not open.

R_DSMIF_Close()

fsp_err_t R_DSMIF_Close

(

adc_ctrl_t *

p_ctrl

)

Stops any scan in progress, disables interrupts, and powers down the DSMIF peripheral.

Note

This function is delayed at least until the outage is complete, as required by the DSMIF outage procedure.

Return values

FSP_SUCCESS	Instance control block closed successfully.
FSP_ERR_ASSERTION	An input pointer was NULL.
FSP_ERR_NOT_OPEN	Instance control block is not open.

R_DSMIF_CallbackSet()

fsp_err_t R_DSMIF_CallbackSet	(	adc_ctrl_t *const	p_ctrl,
		void(*)(adc_callback_args_t *)	p_callback,
		void const *const	p_context,
		adc_callback_args_t *const	p_callback_memory
	)

Updates the user callback with the option to provide memory for the callback argument structure.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

R_DSMIF_ErrorStatusGet()

fsp_err_t R_DSMIF_ErrorStatusGet	(	adc_ctrl_t *	p_ctrl,
		dsmif_error_status_t *	p_error_status
	)

Returns the error status of a scan started by software.

Return values

FSP_SUCCESS	No software scan is in progress.
FSP_ERR_ASSERTION	An input pointer was NULL.
FSP_ERR_NOT_OPEN	Instance control block is not open.