The following build time configurations are defined in fsp_cfg/bsp/bsp_mcu_family_cfg.h:
| Configuration | Options | Default | Description |
| OFS0 register settings |
| OFS0 register settings > Independent WDT |
| Start Mode |
-
IWDT is stopped after a reset
-
IWDT is automatically activated after a reset (Autostart mode)
| IWDT is stopped after a reset | |
| Timeout Period |
-
128 cycles
-
512 cycles
-
1024 cycles
-
2048 cycles
| 2048 cycles | |
| Dedicated Clock Frequency Divisor |
| 128 | |
| Window End Position |
-
75%
-
50%
-
25%
-
0% (no window end position)
| 0% (no window end position) | |
| Window Start Position |
-
25%
-
50%
-
75%
-
100% (no window start position)
| 100% (no window start position) | |
| Reset Interrupt Request Select |
-
NMI request or interrupt request is enabled
-
Reset is enabled
| Reset is enabled | |
| Stop Control |
-
Counting continues
-
Stop counting when in Sleep, Snooze mode, or Software Standby
| Stop counting when in Sleep, Snooze mode, or Software Standby | |
| OFS0 register settings > WDT |
| Start Mode Select |
-
Automatically activate WDT after a reset (auto-start mode)
-
Stop WDT after a reset (register-start mode)
| Stop WDT after a reset (register-start mode) | |
| Timeout Period |
-
1024 cycles
-
4096 cycles
-
8192 cycles
-
16384 cycles
| 16384 cycles | |
| Clock Frequency Division Ratio |
| 128 | |
| Window End Position |
-
75%
-
50%
-
25%
-
0% (no window end position)
| 0% (no window end position) | |
| Window Start Position |
-
25%
-
50%
-
75%
-
100% (no window start position)
| 100% (no window start position) | |
| Reset Interrupt Request |
| Reset | |
| Stop Control |
-
Counting continues
-
Stop counting when entering Sleep mode
| Stop counting when entering Sleep mode | |
| OFS1 register settings |
| Internal Clock Supply Architecture Type |
| Type A | |
| Voltage Detection 0 Circuit Start |
-
Voltage monitor 0 reset is enabled after reset
-
Voltage monitor 0 reset is disabled after reset
| Voltage monitor 0 reset is disabled after reset | |
| Voltage Detection 0 Level |
-
3.84 V
-
2.82 V
-
2.51 V
-
1.90 V
-
1.70 V
| 1.90 V | |
| HOCO Oscillation Enable |
-
HOCO oscillation is enabled after reset
-
HOCO oscillation is disabled after reset
| HOCO oscillation is enabled after reset | HOCO must be enabled out of reset because the MCU starts up in low voltage mode and the HOCO must be operating in low voltage mode. |
| MPU |
| Enable or disable PC Region 0 |
| Disabled | |
| PC0 Start | Value must be an integer between 0 and 0x000FFFFC (ROM) or between 0x1FF00000 and 0x200FFFFC (RAM) | 0x000FFFFC | |
| PC0 End | Value must be an integer between 0x00000003 and 0x000FFFFF (ROM) or between 0x1FF00003 and 0x200FFFFF (RAM) | 0x000FFFFF | |
| Enable or disable PC Region 1 |
| Disabled | |
| PC1 Start | Value must be an integer between 0 and 0x000FFFFC (ROM) or between 0x1FF00000 and 0x200FFFFC (RAM) | 0x000FFFFC | |
| PC1 End | Value must be an integer between 0x00000003 and 0x000FFFFF (ROM) or between 0x1FF00003 and 0x200FFFFF (RAM) | 0x000FFFFF | |
| Enable or disable Memory Region 0 |
| Disabled | |
| Memory Region 0 Start | Value must be an integer between 0 and 0x000FFFFC | 0x000FFFFC | |
| Memory Region 0 End | Value must be an integer between 0x00000003 and 0x000FFFFF | 0x000FFFFF | |
| Enable or disable Memory Region 1 |
| Disabled | |
| Memory Region 1 Start | Value must be an integer between 0x1FF00000 and 0x200FFFFC | 0x200FFFFC | |
| Memory Region 1 End | Value must be an integer between 0x1FF00003 and 0x200FFFFF | 0x200FFFFF | |
| Enable or disable Memory Region 2 |
| Disabled | |
| Memory Region 2 Start | Value must be an integer between 0x400C0000 and 0x400DFFFC or between 0x40100000 and 0x407FFFFC | 0x407FFFFC | |
| Memory Region 2 End | Value must be an integer between 0x400C0003 and 0x400DFFFF or between 0x40100003 and 0x407FFFFF | 0x407FFFFF | |
| Enable or disable Memory Region 3 |
| Disabled | |
| Memory Region 3 Start | Value must be an integer between 0x400C0000 and 0x400DFFFC or between 0x40100000 and 0x407FFFFC | 0x400DFFFC | |
| Memory Region 3 End | Value must be an integer between 0x400C0003 and 0x400DFFFF or between 0x40100003 and 0x407FFFFF | 0x400DFFFF | |
| Enable inline BSP IRQ functions |
| Disabled | Using static inline functions will slightly increase code size, but will slightly decrease cycles taken in ISRs in return. |
| Use Low Voltage Mode | Not Supported | Not Supported | Use the low voltage mode. This limits the ICLK operating frequency to 4 MHz and requires all clock dividers to be at least 4 when oscillation stop detection is used. |
| Main Oscillator Wait Time |
-
2 cycles
-
1024 cycles
-
2048 cycles
-
4096 cycles
-
8192 cycles
-
16384 cycles
-
32768 cycles
-
65536 cycles
-
131072 cycles
-
262144 cycles
| 262144 cycles | Number of cycles to wait for the main oscillator clock to stabilize. |
| ID Code Mode |
-
Unlocked (Ignore ID)
-
Locked with All Erase support
-
Locked
| Unlocked (Ignore ID) | When set to 'Locked with All Erase support', the ID Code must be set in the debugger to read or write data to the MCU, but the All Erase command is still accepted regardless. When set to 'Locked', all erase/download/debug access is disabled unless the ID Code is provided. |
| ID Code (32 Hex Characters) | Value must be a 32 character long hex string | FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF | Set the ID Code for locking debug access. This setting is only used when the ID Code Mode is not set to Unlocked. |
| Fill Flash Gap |
| Do not fill gap | A section of code flash exists between the end of the vector table (near the start of flash) and the ROM registers (at address 0x400). Selecting 'Fill gap' will assume a compiler optimization for size and fill this area with a preselected set functions in order to reduce the amount of code flash used by FSP. If you would like to fill this area with your own code or data, select 'Do not fill gap' and manually place items in the section '.flash_gap'. |
