Detailed Description

Build Time Configurations for ra2e3_fsp

The following build time configurations are defined in fsp_cfg/bsp/bsp_mcu_family_cfg.h:

Configuration	Options	Default	Description
Enable inline BSP IRQ functions	Enabled Disabled	Disabled	Using static inline functions will slightly increase code size, but will slightly decrease cycles taken in ISRs in return.
Use Low Voltage Mode	Not Supported	Not Supported	Use the low voltage mode. This limits the ICLK operating frequency to 4 MHz and requires all clock dividers to be at least 4 when oscillation stop detection is used.
Main Oscillator Wait Time	2 cycles 1024 cycles 2048 cycles 4096 cycles 8192 cycles 16384 cycles 32768 cycles 65536 cycles 131072 cycles 262144 cycles	262144 cycles	Number of cycles to wait for the main oscillator clock to stabilize.

Groups	Modules
Analog	ADC (r_adc)
Connectivity	I2C Master (r_iic_master) I2C Master (r_sci_i2c) I2C Slave (r_iic_slave) SMCI (r_sci_smci) SPI (r_sci_spi) SPI (r_spi) UART (r_sci_uart)
Input	External IRQ (r_icu) Key Matrix (r_kint)
Monitoring	Clock Accuracy Circuit (r_cac) CRC (r_crc) Data Operation Circuit (r_doc) Independent Watchdog (r_iwdt) Low/Programmable Voltage Detection (r_lvd) Watchdog (r_wdt)
Power	Low Power Modes (r_lpm)
Storage	Flash (r_flash_lp)
System	Clock Generation Circuit (r_cgc) Event Link Controller (r_elc) I/O Port (r_ioport)
Timers	Port Output Enable for GPT (r_poeg) Realtime Clock (r_rtc) Three-Phase PWM (r_gpt_three_phase) Timer, General PWM (r_gpt) Timer, Low-Power (r_agt)
Transfer	Transfer (r_dtc)

#define BSP_ELC_PERIPHERAL_MASK

Positions of event link set registers (ELSRs) available on this MCU

Sources of event signals to be linked to other peripherals or the CPU

Events to be used with the IELSR register to link interrupt events to the NVIC

Possible peripherals to be linked to event signals