RA Flexible Software Package Documentation  Release v5.4.0

 

Functions

bsp_power_mode_t R_BSP_PowerModeSet (bsp_power_mode_t mode)
 

Detailed Description

Build Time Configurations for ra2l1_fsp

The following build time configurations are defined in fsp_cfg/bsp/bsp_mcu_family_cfg.h:

ConfigurationOptionsDefaultDescription
OFS0 register settings
OFS0 register settings > Independent WDT
Start Mode
  • IWDT is stopped after a reset
  • IWDT is automatically activated after a reset (Autostart mode)
IWDT is stopped after a reset
Timeout Period
  • 128 cycles
  • 512 cycles
  • 1024 cycles
  • 2048 cycles
2048 cycles
Dedicated Clock Frequency Divisor
  • 1
  • 16
  • 32
  • 64
  • 128
  • 256
128
Window End Position
  • 75%
  • 50%
  • 25%
  • 0% (no window end position)
0% (no window end position)
Window Start Position
  • 25%
  • 50%
  • 75%
  • 100% (no window start position)
100% (no window start position)
Reset Interrupt Request Select
  • NMI request or interrupt request is enabled
  • Reset is enabled
Reset is enabled
Stop Control
  • Counting continues
  • Stop counting when in Sleep, Snooze mode, or Software Standby
Stop counting when in Sleep, Snooze mode, or Software Standby
OFS0 register settings > WDT
Start Mode Select
  • Automatically activate WDT after a reset (auto-start mode)
  • Stop WDT after a reset (register-start mode)
Stop WDT after a reset (register-start mode)
Timeout Period
  • 1024 cycles
  • 4096 cycles
  • 8192 cycles
  • 16384 cycles
16384 cycles
Clock Frequency Division Ratio
  • 4
  • 64
  • 128
  • 512
  • 2048
  • 8192
128
Window End Position
  • 75%
  • 50%
  • 25%
  • 0% (no window end position)
0% (no window end position)
Window Start Position
  • 25%
  • 50%
  • 75%
  • 100% (no window start position)
100% (no window start position)
Reset Interrupt Request
  • NMI
  • Reset
Reset
Stop Control
  • Counting continues
  • Stop counting when entering Sleep mode
Stop counting when entering Sleep mode
OFS1 register settings
Internal Clock Supply Architecture Type
  • Type B
  • Type A
Type A
Voltage Detection 0 Circuit Start
  • Voltage monitor 0 reset is enabled after reset
  • Voltage monitor 0 reset is disabled after reset
Voltage monitor 0 reset is disabled after reset
Voltage Detection 0 Level
  • 3.84 V
  • 2.82 V
  • 2.51 V
  • 1.90 V
  • 1.70 V
1.90 V
HOCO Oscillation Enable
  • HOCO oscillation is enabled after reset
  • HOCO oscillation is disabled after reset
HOCO oscillation is enabled after reset HOCO must be enabled out of reset because the MCU starts up in low voltage mode and the HOCO must be operating in low voltage mode.
MPU
Enable or disable PC Region 0
  • Enabled
  • Disabled
Disabled
PC0 StartValue must be an integer between 0 and 0x000FFFFC (ROM) or between 0x1FF00000 and 0x200FFFFC (RAM)0x000FFFFC
PC0 EndValue must be an integer between 0x00000003 and 0x000FFFFF (ROM) or between 0x1FF00003 and 0x200FFFFF (RAM)0x000FFFFF
Enable or disable PC Region 1
  • Enabled
  • Disabled
Disabled
PC1 StartValue must be an integer between 0 and 0x000FFFFC (ROM) or between 0x1FF00000 and 0x200FFFFC (RAM)0x000FFFFC
PC1 EndValue must be an integer between 0x00000003 and 0x000FFFFF (ROM) or between 0x1FF00003 and 0x200FFFFF (RAM)0x000FFFFF
Enable or disable Memory Region 0
  • Enabled
  • Disabled
Disabled
Memory Region 0 StartValue must be an integer between 0 and 0x000FFFFC0x000FFFFC
Memory Region 0 EndValue must be an integer between 0x00000003 and 0x000FFFFF0x000FFFFF
Enable or disable Memory Region 1
  • Enabled
  • Disabled
Disabled
Memory Region 1 StartValue must be an integer between 0x1FF00000 and 0x200FFFFC0x200FFFFC
Memory Region 1 EndValue must be an integer between 0x1FF00003 and 0x200FFFFF0x200FFFFF
Enable or disable Memory Region 2
  • Enabled
  • Disabled
Disabled
Memory Region 2 StartValue must be an integer between 0x400C0000 and 0x400DFFFC or between 0x40100000 and 0x407FFFFC0x407FFFFC
Memory Region 2 EndValue must be an integer between 0x400C0003 and 0x400DFFFF or between 0x40100003 and 0x407FFFFF0x407FFFFF
Enable or disable Memory Region 3
  • Enabled
  • Disabled
Disabled
Memory Region 3 StartValue must be an integer between 0x400C0000 and 0x400DFFFC or between 0x40100000 and 0x407FFFFC0x400DFFFC
Memory Region 3 EndValue must be an integer between 0x400C0003 and 0x400DFFFF or between 0x40100003 and 0x407FFFFF0x400DFFFF
Power
DC-DC Regulator
  • Disabled
  • Enabled
  • Enabled at startup
Disabled To use the DCDC regulator an external inductor and capacitor must be connected as specified in chapter 40 of the RA2L1 manual. In addition the supply voltage must be above 2.4V and ICLK must be 2 MHz or higher.

When set to 'Enabled at startup' the BSP will switch to the DCDC regulator during startup using the voltage range specified below.
DC-DC Supply Range
  • 2.4V to 2.7V
  • 2.7V to 3.6V
  • 3.6V to 4.5V
  • 4.5V to 5.5V
2.7V to 3.6V Set this to the expected MCU supply voltage (Vcc) at startup when using the DCDC regulator.
Enable inline BSP IRQ functions
  • Enabled
  • Disabled
Disabled Using static inline functions will slightly increase code size, but will slightly decrease cycles taken in ISRs in return.
Use Low Voltage ModeNot Supportedconfig.bsp.low_voltage_mode.disabled Use the low voltage mode. This limits the ICLK operating frequency to 4 MHz and requires all clock dividers to be at least 4 when oscillation stop detection is used.
Main Oscillator Wait Time
  • 2 cycles
  • 1024 cycles
  • 2048 cycles
  • 4096 cycles
  • 8192 cycles
  • 16384 cycles
  • 32768 cycles
  • 65536 cycles
  • 131072 cycles
  • 262144 cycles
262144 cycles Number of cycles to wait for the main oscillator clock to stabilize.
ID Code Mode
  • Unlocked (Ignore ID)
  • Locked with All Erase support
  • Locked
Unlocked (Ignore ID) When set to 'Locked with All Erase support', the ID Code must be set in the debugger to read or write data to the MCU, but the All Erase command is still accepted regardless. When set to 'Locked', all erase/download/debug access is disabled unless the ID Code is provided.
ID Code (32 Hex Characters)Value must be a 32 character long hex stringFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF Set the ID Code for locking debug access. This setting is only used when the ID Code Mode is not set to Unlocked.
Fill Flash Gap
  • Do not fill gap
  • Fill gap
Do not fill gap A section of code flash exists between the end of the vector table (near the start of flash) and the ROM registers (at address 0x400). Selecting 'Fill gap' will assume a compiler optimization for size and fill this area with a preselected set functions in order to reduce the amount of code flash used by FSP. If you would like to fill this area with your own code or data, select 'Do not fill gap' and manually place items in the section '.flash_gap'.

Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file.

Macros

#define BSP_ELC_PERIPHERAL_MASK
 

Enumerations

enum  elc_event_t
 
enum  icu_event_t
 
enum  elc_peripheral_t
 
enum  bsp_power_mode_t
 

Macro Definition Documentation

◆ BSP_ELC_PERIPHERAL_MASK

#define BSP_ELC_PERIPHERAL_MASK

Positions of event link set registers (ELSRs) available on this MCU

Enumeration Type Documentation

◆ elc_event_t

Sources of event signals to be linked to other peripherals or the CPU

Note
This list is device specific.

◆ icu_event_t

Events to be used with the IELSR register to link interrupt events to the NVIC

Note
This list is device specific.

◆ elc_peripheral_t

Possible peripherals to be linked to event signals

Note
This list is device specific.

◆ bsp_power_mode_t

Voltage regulator mode

Enumerator
BSP_POWER_MODE_DCDC_2V4_TO_2V7 

DCDC mode; 2.4V to 2.7V supply.

BSP_POWER_MODE_DCDC_2V7_TO_3V6 

DCDC mode; 2.7V to 3.6V supply.

BSP_POWER_MODE_DCDC_3V6_TO_4V5 

DCDC mode; 3.6V to 4.5V supply.

BSP_POWER_MODE_DCDC_4V5_TO_5V5 

DCDC mode; 4.5V to 5.5V supply.

BSP_POWER_MODE_LDO 

LDO mode.

Function Documentation

◆ R_BSP_PowerModeSet()

bsp_power_mode_t R_BSP_PowerModeSet ( bsp_power_mode_t  mode)

Select either the LDO or DCDC regulator and/or update the MCU supply voltage range. Returns the previously selected mode.

Note
DCDC mode has the following limitations:
  • Supply voltage must be 2.4V or greater
  • Low- and Subosc-speed modes are not available
  • Software Standby is not available Ensure these limitations are respected before entering DCDC mode. If supply voltage may drop below 2.4V during operation, configure a LVD channel to interrupt or reset the MCU near this threshold to switch back to the LDO.
Switching to DCDC mode temporarily disables all interrupts and blocks for 22 microseconds; switching to LDO from DCDC temporarily disables all peripherals and interrupts and blocks for 60 microseconds.
If the supply voltage falls outside the range originally specified when starting the DCDC regulator, call this function again with the updated supply voltage.
Returns
The previously selected power mode.