RA Flexible Software Package Documentation  Release v5.7.0

 
Macros | Enumerations
RA4W1
BSP » MCU Board Support Package

Detailed Description

Build Time Configurations for ra4w1_fsp

The following build time configurations are defined in fsp_cfg/bsp/bsp_mcu_family_cfg.h:

ConfigurationOptionsDefaultDescription
OFS0 register settings
OFS0 register settings > Independent WDT
Start Mode
  • IWDT is stopped after a reset
  • IWDT is automatically activated after a reset (Autostart mode)
IWDT is stopped after a reset
Timeout Period
  • 128 cycles
  • 512 cycles
  • 1024 cycles
  • 2048 cycles
2048 cycles
Dedicated Clock Frequency Divisor
  • 1
  • 16
  • 32
  • 64
  • 128
  • 256
128
Window End Position
  • 75%
  • 50%
  • 25%
  • 0% (no window end position)
0% (no window end position)
Window Start Position
  • 25%
  • 50%
  • 75%
  • 100% (no window start position)
100% (no window start position)
Reset Interrupt Request Select
  • NMI request or interrupt request is enabled
  • Reset is enabled
Reset is enabled
Stop Control
  • Counting continues
  • Stop counting when in Sleep, Snooze mode, or Software Standby
Stop counting when in Sleep, Snooze mode, or Software Standby
OFS0 register settings > WDT
Start Mode Select
  • Automatically activate WDT after a reset (auto-start mode)
  • Stop WDT after a reset (register-start mode)
Stop WDT after a reset (register-start mode)
Timeout Period
  • 1024 cycles
  • 4096 cycles
  • 8192 cycles
  • 16384 cycles
16384 cycles
Clock Frequency Division Ratio
  • 4
  • 64
  • 128
  • 512
  • 2048
  • 8192
128
Window End Position
  • 75%
  • 50%
  • 25%
  • 0% (no window end position)
0% (no window end position)
Window Start Position
  • 25%
  • 50%
  • 75%
  • 100% (no window start position)
100% (no window start position)
Reset Interrupt Request
  • NMI
  • Reset
Reset
Stop Control
  • Counting continues
  • Stop counting when entering Sleep mode
Stop counting when entering Sleep mode
OFS1 register settings
Voltage Detection 0 Circuit Start
  • Voltage monitor 0 reset is enabled after reset
  • Voltage monitor 0 reset is disabled after reset
Voltage monitor 0 reset is disabled after reset
Voltage Detection 0 Level
  • 2.82 V
  • 2.51 V
  • 1.90 V
1.90 V
HOCO Oscillation EnableHOCO oscillation is enabled after resetconfig.bsp.fsp.OFS1.hoco_osc.disabled
MPU
Enable or disable PC Region 0
  • Enabled
  • Disabled
Disabled
PC0 StartValue must be an integer between 0 and 0x00FFFFFC (ROM) or between 0x1FF00000 and 0x200FFFFC (RAM)0x00FFFFFC
PC0 EndValue must be an integer between 0x00000003 and 0x00FFFFFF (ROM) or between 0x1FF00003 and 0x200FFFFF (RAM)0x00FFFFFF
Enable or disable PC Region 1
  • Enabled
  • Disabled
Disabled
PC1 StartValue must be an integer between 0 and 0x00FFFFFC (ROM) or between 0x1FF00000 and 0x200FFFFC (RAM)0x00FFFFFC
PC1 EndValue must be an integer between 0x00000003 and 0x00FFFFFF (ROM) or between 0x1FF00003 and 0x200FFFFF (RAM)0x00FFFFFF
Enable or disable Memory Region 0
  • Enabled
  • Disabled
Disabled
Memory Region 0 StartValue must be an integer between 0 and 0x00FFFFFC0x00FFFFFC
Memory Region 0 EndValue must be an integer between 0x00000003 and 0x00FFFFFF0x00FFFFFF
Enable or disable Memory Region 1
  • Enabled
  • Disabled
Disabled
Memory Region 1 StartValue must be an integer between 0x1FF00000 and 0x200FFFFC0x200FFFFC
Memory Region 1 EndValue must be an integer between 0x1FF00003 and 0x200FFFFF0x200FFFFF
Enable or disable Memory Region 2
  • Enabled
  • Disabled
Disabled
Memory Region 2 StartValue must be an integer between 0x400C0000 and 0x400DFFFC or between 0x40100000 and 0x407FFFFC0x407FFFFC
Memory Region 2 EndValue must be an integer between 0x400C0003 and 0x400DFFFF or between 0x40100003 and 0x407FFFFF0x407FFFFF
Enable or disable Memory Region 3
  • Enabled
  • Disabled
Disabled
Memory Region 3 StartValue must be an integer between 0x400C0000 and 0x400DFFFC or between 0x40100000 and 0x407FFFFC0x400DFFFC
Memory Region 3 EndValue must be an integer between 0x400C0003 and 0x400DFFFF or between 0x40100003 and 0x407FFFFF0x400DFFFF
Enable inline BSP IRQ functions
  • Enabled
  • Disabled
Enabled Using static inline functions will slightly increase code size, but will slightly decrease cycles taken in ISRs in return.
Use Low Voltage Mode
  • Enabled
  • Disabled
Disabled Use the low voltage mode. This limits the ICLK operating frequency to 4 MHz and requires all clock dividers to be at least 4.
Main Oscillator Wait Time
  • 2 cycles
  • 1024 cycles
  • 2048 cycles
  • 4096 cycles
  • 8192 cycles
  • 16384 cycles
  • 32768 cycles
  • 65536 cycles
  • 131072 cycles
  • 262144 cycles
262144 cycles Number of cycles to wait for the main oscillator clock to stabilize.
ID Code Mode
  • Unlocked (Ignore ID)
  • Locked with All Erase support
  • Locked
Unlocked (Ignore ID) When set to 'Locked with All Erase support', the ID Code must be set in the debugger to read or write data to the MCU, but the All Erase command is still accepted regardless. When set to 'Locked', all erase/download/debug access is disabled unless the ID Code is provided.
ID Code (32 Hex Characters)Value must be a 32 character long hex stringFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF Set the ID Code for locking debug access. This setting is only used when the ID Code Mode is not set to Unlocked.

Macros

#define BSP_ELC_PERIPHERAL_MASK
 

Enumerations

enum  elc_event_t
 
enum  elc_peripheral_t
 

Macro Definition Documentation

◆ BSP_ELC_PERIPHERAL_MASK

#define BSP_ELC_PERIPHERAL_MASK

Positions of event link set registers (ELSRs) available on this MCU

Enumeration Type Documentation

◆ elc_event_t

enum elc_event_t

Sources of event signals to be linked to other peripherals or the CPU

Note
This list is device specific.

◆ elc_peripheral_t

enum elc_peripheral_t

Possible peripherals to be linked to event signals

Note
This list is device specific.